Multi-signal wake-up chip plug circuit

Abstract

The invention discloses a multi-signal wake-up chip plug circuit which comprises a third resistor, a fourth resistor, a third MOS tube, a first connector and a second connector, one end of the third resistor is connected with the first connector, and the other end of the third resistor is connected with one end of the fourth resistor, a drain electrode of the third MOS tube and the second connector. And the other end of the fourth resistor, the source electrode of the third MOS tube and the grounding end are connected. And meanwhile, power supply and wake-up signals of the chip can be selectively limited based on the chip plugging state and the power supply signal amplitude of the chip so as to prevent the chip from being damaged and disordered in operational logic in the plugging process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip plugging, and in particular to a multi-signal wake-up chip plugging circuit. Background Art

[0002] During the chip insertion process, instantaneous current will be generated, which will cause the power signal to fluctuate and thus damage the chip. After the chip is plugged in, it will take a certain period of time for the power signal to gradually enter a stable state. When the chip starts working and processes and calculates the wake-up signal under the condition of obtaining an unstable power signal, it will cause confusion in the chip's operation logic. Therefore, a plug-in circuit for a multi-signal wake-up chip is proposed, which can prevent instantaneous current when the chip is initially plugged in, and can selectively limit the chip's power supply and wake-up signals based on the chip insertion state and the chip's power supply signal amplitude to prevent chip damage and operation logic confusion during the plug-in process. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a multi-signal wake-up chip plug-in circuit, including a third resistor R3, a fourth resistor R4, a third MOS tube Q3, a first connector P1, and a second connector P2, one end of the third resistor R3 is connected to the first connector P1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the drain of the third MOS tube Q3, and the second connector P2, and the other end of the fourth resistor R4, the source of the third MOS tube Q3 and the ground terminal are connected.

[0004] Furthermore, it also includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a twentieth resistor R20, a second operational amplifier U2, a second transistor Q2, a fifth MOS transistor Q5, a fourth connector P4, and a first diode D1, wherein one end of the ninth resistor R9 is connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the sixth resistor R6 and the emitter of the second transistor Q2, the base of the second transistor Q2 is connected to one end of the eighth resistor R8 and the cathode of the first diode D1, and the anode of the first diode D1 is connected to the first connector P1 is connected, the collector of the second triode Q2 is connected to one end of the seventh resistor R7 and the in-phase end of the second operational amplifier U2, the inverting end of the second operational amplifier U2 is connected to one end of the twentieth resistor R20, the output end of the second operational amplifier U2 is connected to the gate of the third MOS tube Q3 and the gate of the fifth MOS tube Q5, the drain of the fifth MOS tube Q5 is connected to the fourth connector P4, the other end of the sixth resistor R6, the other end of the seventh resistor R7, the other end of the eighth resistor R8, the other end of the twentieth resistor R20, the source of the fifth MOS tube Q5 and the ground are connected.

[0005] Furthermore, it also includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fourth operational amplifier U4, a fifth operational amplifier U5, and a seventh MOS tube Q7, wherein one end of the sixteenth resistor R16 is connected to the power supply, the other end of the sixteenth resistor R16 is connected to one end of the seventeenth resistor R17 and the inverting end of the fourth operational amplifier U4, the other end of the seventeenth resistor R17 is connected to one end of the eighteenth resistor R18 and the inverting end of the fifth operational amplifier U5, the in-phase end of the fourth operational amplifier U4 and the in-phase end of the fifth operational amplifier U5 are connected to the first connector P1, the output end of the fourth operational amplifier U4 is connected to the gate of the seventh MOS tube Q7, the output end of the fifth operational amplifier U5 is connected to the drain of the seventh MOS tube Q7, and the other end of the eighteenth resistor R18, the source of the seventh MOS tube Q7 and the ground end are connected.

[0006] Furthermore, the invention further comprises an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a twenty-first resistor R21, a third operational amplifier U3, a sixth MOS tube Q6, and a second capacitor C2, wherein one end of the eleventh resistor R11 is connected to the power supply, the other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the source of the sixth MOS tube Q6, the gate of the sixth MOS tube Q6 is connected to the output end of the fifth operational amplifier U5, and the drain of the sixth MOS tube Q6 is connected to the output end of the fifth operational amplifier U5. The pole is connected to one end of the fourteenth resistor R14, one end of the fifteenth resistor R15, and the in-phase end of the third operational amplifier U3, the inverting end of the third operational amplifier U3 is connected to one end of the thirteenth resistor R13 and one end of the second capacitor C2, the output end of the third operational amplifier U3 is connected to the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, one end of the twenty-first resistor R21, the other end of the twelfth resistor R12, the other end of the fifteenth resistor R15, the other end of the twenty-first resistor R21, the other end of the second capacitor C2 and the ground end are connected.

[0007] Furthermore, it also includes a first resistor R1, a second resistor R2, a fifth resistor R5, a first operational amplifier U1, a first MOS tube Q1, a fourth MOS tube Q4, a third connector P3, a fourth connector P4, and a first capacitor C1, wherein the drain of the first MOS tube Q1 is connected to the second connector P2, the gate of the first MOS tube Q1 is connected to one end of the fifth resistor R5, the output end of the first operational amplifier U1, and the gate of the fourth MOS tube Q4 are connected, the inverting end of the first operational amplifier U1 is connected to one end of the second resistor R2, the in-phase end of the first operational amplifier U1 is connected to one end of the first resistor R1 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the output end of the third operational amplifier U3, the drain of the fourth MOS tube Q4 is connected to the third connector P3, and the other end of the first resistor R1, the other end of the second resistor R2, the other end of the fifth resistor R5, the source of the first MOS tube Q1, the source of the fourth MOS tube Q4 and the ground are connected.

[0008] Furthermore, it also includes a twenty-third resistor R23, a fifth connector P5, a second diode D2, and a third diode D3, wherein the anode of the second diode D2 is connected to one end of the twenty-third resistor R23, the anode of the third diode D3, and the fifth connector P5, the cathode of the second diode D2 is connected to the fourth connector P4, the cathode of the third diode D3 is connected to the third connector P3, and the other end of the twenty-third resistor R23 is connected to the ground.

[0009] Furthermore, a tenth resistor R10 is included, one end of the tenth resistor R10 is connected to the gate of the fifth MOS transistor Q5, and the other end of the tenth resistor R10 is connected to the ground.

[0010] Furthermore, a twenty-second resistor R22 is included, one end of the twenty-second resistor R22 is connected to the gate of the seventh MOS transistor Q7, and the other end of the twenty-second resistor R22 is connected to the ground.

[0011] Furthermore, a nineteenth resistor R19 is included, one end of the nineteenth resistor R19 is connected to the gate of the sixth MOS transistor Q6, and the other end of the nineteenth resistor R19 is connected to the ground.

[0012] The beneficial effects of the present invention compared with the prior art are:

[0013] The present invention can prevent instantaneous current when the chip is initially plugged in, and can selectively limit the power supply and wake-up signals of the chip based on the chip plugging state and the power supply signal amplitude of the chip to prevent chip damage and operation logic confusion during the plugging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 , Figure 2 This is a schematic diagram of the integrated circuit structure provided by the present invention. DETAILED DESCRIPTION

[0016] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0017] The present invention discloses a multi-signal wake-up chip plug-in circuit, comprising a third resistor R3, a fourth resistor R4, a third MOS tube Q3, a first connector P1, and a second connector P2, wherein one end of the third resistor R3 is connected to the first connector P1, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the drain of the third MOS tube Q3, and the second connector P2, and the other end of the fourth resistor R4, the source of the third MOS tube Q3, and the ground terminal are connected.

[0018] Specifically, it also includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a twentieth resistor R20, a second operational amplifier U2, a second transistor Q2, a fifth MOS transistor Q5, a fourth connector P4, and a first diode D1. One end of the ninth resistor R9 is connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the sixth resistor R6 and the emitter of the second transistor Q2, the base of the second transistor Q2 is connected to one end of the eighth resistor R8 and the cathode of the first diode D1, and the anode of the first diode D1 is connected to the first connector P 1, the collector of the second triode Q2 is connected to one end of the seventh resistor R7 and the non-inverting end of the second operational amplifier U2, the inverting end of the second operational amplifier U2 is connected to one end of the twentieth resistor R20, the output end of the second operational amplifier U2 is connected to the gate of the third MOS tube Q3 and the gate of the fifth MOS tube Q5, the drain of the fifth MOS tube Q5 is connected to the fourth connector P4, the other end of the sixth resistor R6, the other end of the seventh resistor R7, the other end of the eighth resistor R8, the other end of the twentieth resistor R20, the source of the fifth MOS tube Q5 and the grounding end are connected.

[0019] Specifically, it also includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fourth operational amplifier U4, a fifth operational amplifier U5, and a seventh MOS tube Q7. One end of the sixteenth resistor R16 is connected to the power supply, the other end of the sixteenth resistor R16 is connected to one end of the seventeenth resistor R17 and the inverting end of the fourth operational amplifier U4, the other end of the seventeenth resistor R17 is connected to one end of the eighteenth resistor R18 and the inverting end of the fifth operational amplifier U5, the in-phase end of the fourth operational amplifier U4 and the in-phase end of the fifth operational amplifier U5 are connected to the first connector P1, the output end of the fourth operational amplifier U4 is connected to the gate of the seventh MOS tube Q7, the output end of the fifth operational amplifier U5 is connected to the drain of the seventh MOS tube Q7, and the other end of the eighteenth resistor R18, the source of the seventh MOS tube Q7 and the ground end are connected.

[0020] Specifically, it also includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a twenty-first resistor R21, a third operational amplifier U3, a sixth MOS tube Q6, and a second capacitor C2. One end of the eleventh resistor R11 is connected to the power supply, the other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the source of the sixth MOS tube Q6, the gate of the sixth MOS tube Q6 is connected to the output end of the fifth operational amplifier U5, and the drain of the sixth MOS tube Q6 is connected to the output end of the fifth operational amplifier U5. The pole is connected to one end of the fourteenth resistor R14, one end of the fifteenth resistor R15, and the in-phase end of the third operational amplifier U3, the inverting end of the third operational amplifier U3 is connected to one end of the thirteenth resistor R13 and one end of the second capacitor C2, the output end of the third operational amplifier U3 is connected to the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, one end of the twenty-first resistor R21, the other end of the twelfth resistor R12, the other end of the fifteenth resistor R15, the other end of the twenty-first resistor R21, the other end of the second capacitor C2 and the ground end are connected.

[0021] Specifically, it also includes a first resistor R1, a second resistor R2, a fifth resistor R5, a first operational amplifier U1, a first MOS tube Q1, a fourth MOS tube Q4, a third connector P3, a fourth connector P4, and a first capacitor C1. The drain of the first MOS tube Q1 is connected to the second connector P2, the gate of the first MOS tube Q1 is connected to one end of the fifth resistor R5, the output end of the first operational amplifier U1, and the gate of the fourth MOS tube Q4 are connected, the inverting end of the first operational amplifier U1 is connected to one end of the second resistor R2, the in-phase end of the first operational amplifier U1 is connected to one end of the first resistor R1 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the output end of the third operational amplifier U3, the drain of the fourth MOS tube Q4 is connected to the third connector P3, and the other end of the first resistor R1, the other end of the second resistor R2, the other end of the fifth resistor R5, the source of the first MOS tube Q1, the source of the fourth MOS tube Q4 and the ground are connected.

[0022] Specifically, it also includes a twenty-third resistor R23, a fifth connector P5, a second diode D2, and a third diode D3. The anode of the second diode D2 is connected to one end of the twenty-third resistor R23, the anode of the third diode D3, and the fifth connector P5. The cathode of the second diode D2 is connected to the fourth connector P4. The cathode of the third diode D3 is connected to the third connector P3. The other end of the twenty-third resistor R23 is connected to the ground.

[0023] Specifically, a tenth resistor R10 is also included, one end of the tenth resistor R10 is connected to the gate of the fifth MOS transistor Q5, and the other end of the tenth resistor R10 is connected to the ground end.

[0024] Specifically, a twenty-second resistor R22 is also included, one end of the twenty-second resistor R22 is connected to the gate of the seventh MOS transistor Q7, and the other end of the twenty-second resistor R22 is connected to the ground.

[0025] Specifically, a nineteenth resistor R19 is also included, one end of the nineteenth resistor R19 is connected to the gate of the sixth MOS transistor Q6, and the other end of the nineteenth resistor R19 is connected to the ground end.

[0026] When the chip is plugged in, the chip power supply signal is fed back to the first connector P1 on the plug-in circuit, the first connector P1 signal is fed back to the ground loop via the third resistor R3 and the fourth resistor R4, the fourth resistor R4 end signal is the power supply signal required by the chip, the fourth resistor R4 end signal is fed back to the chip power signal input end via the second connector P2, and the second connector P2 end signal is fed back to the drain of the third MOS tube Q3.

[0027] The power supply signal reaches the grounding loop via the ninth resistor R9 and the sixth resistor R6. The signal at the sixth resistor R6 reaches the grounding loop via the emitter of the second transistor Q2, the base of the second transistor Q2, and the eighth resistor R8. The base of the second transistor Q2 and the emitter of the second transistor Q2 are forward biased, and the second transistor Q2 is turned on. The signal at the sixth resistor R6 reaches the grounding loop via the emitter of the second transistor Q2, the collector of the second transistor Q2, and the seventh resistor R7. The signal at the seventh resistor R7 is fed back to the in-phase terminal of the second operational amplifier U2. The twentieth resistor R2 0 is the pull-down resistor at the inverting end of the second operational amplifier U2, the output of the second operational amplifier U2, and the output signal of the second operational amplifier U2 is fed back to the gate of the third MOS tube Q3. When the voltage difference between the gate of the third MOS tube Q3 and the source of the third MOS tube Q3 is higher than the conduction threshold, the third MOS tube Q3 is turned on, and the signal at the end of the fourth resistor R4 is looped through the drain of the third MOS tube Q3 and the source of the third MOS tube Q3 to the ground end. In this way, when the chip is not plugged in, the power signal feedback at the end of the second connector P2 is disconnected to prevent the chip from being burned when it is initially plugged in.

[0028] When the chip is in an unplugged state or a plugged state and the chip power supply signal is too low, the signal at the output end of the second operational amplifier U2 is synchronously fed back to the gate of the fifth MOS tube Q5, and the voltage difference between the gate of the fifth MOS tube Q5 and the source of the fifth MOS tube Q5 is higher than the conduction threshold, and the fifth MOS tube Q5 is turned on. The mainboard can feed back a wake-up signal to the wake-up signal input pin of the chip. When the pin receives the signal feedback, the chip is awakened, and the plug-in circuit is connected to the wake-up signal input pin of the chip through the fifth connector P5, so that the plug-in circuit synchronously obtains the wake-up signal, and the signal at the fifth connector P5 end passes through the twenty-third resistor R23 to the ground end loop. When the fifth MOS tube Q5 is turned on, the signal at the fifth connector P5 end passes through the second diode D2, the fourth connector P4, the drain of the fifth MOS tube Q5, and the source of the fifth MOS tube Q5 to the ground end loop, so as to prevent the chip from obtaining a wake-up signal when the amplitude of the power supply signal of the chip is too low after the chip is initially plugged in, causing confusion in the chip operation logic.

[0029] The power signal is looped to the ground terminal through the sixteenth resistor R16, the seventeenth resistor R17, and the eighteenth resistor R18. The signal amplitudes at the eighteenth resistor R18 and the seventeenth resistor R17 can be adjusted by adjusting the resistance values ​​of the sixteenth resistor R16, the seventeenth resistor R17, and the eighteenth resistor R18. The signal amplitude at the eighteenth resistor R18 is the lowest threshold signal of the power signal required for the chip to work, and the signal amplitude at the seventeenth resistor R17 is the highest threshold signal of the power signal required for the chip to work. The signal at the eighteenth resistor R18 is fed back to the fifth operational amplifier U5 for inversion. The signal at the end of the seventeenth resistor R17 is fed back to the inverting end of the fourth operational amplifier U4, the chip power supply signal is fed back to the plug-in circuit via the first connector P1, the signal at the first connector P1 is fed back to the grounding loop via the third resistor R3 and the fourth resistor R4, the signal at the fourth resistor R4 is fed back to the power signal input end of the chip via the second connector P2, and at the same time, the signal at the end of the first connector P1 is synchronously fed back to the in-phase end of the fifth operational amplifier U5 and the in-phase end of the fourth operational amplifier U4, the output end signal of the fourth operational amplifier U4 is fed back to the gate of the seventh MOS tube Q7, and the twentieth The second resistor R22 is used to discharge the parasitic capacitance of the gate of the seventh MOS tube Q7. The signal at the output end of the fifth operational amplifier U5 is fed back to the source of the seventh MOS tube Q7. The signal at the output end of the fifth operational amplifier U5 is a power supply permission signal. When the chip power supply signal amplitude is higher than the minimum threshold signal amplitude of the power supply signal required for the chip to work, the signal at the first connector P1 end passes through the first diode D1 and the eighth resistor R8 to the ground end loop, the second transistor Q2 is cut off, and the fifth operational amplifier U5 outputs. When the chip power supply signal amplitude is higher than the maximum threshold signal amplitude of the power supply signal required for the chip to work, the fourth operational amplifier U4 outputs, and the signal at the output end of the fourth operational amplifier U4 is fed back to the gate of the seventh MOS tube Q7. The voltage difference between the gate of the seventh MOS tube Q7 and the source of the seventh MOS tube Q7 is higher than the conduction threshold, and the seventh MOS tube Q7 is turned on. The signal at the output end of the fifth operational amplifier U5 passes through the drain of the seventh MOS tube Q7 and the source of the seventh MOS tube Q7 to the ground end loop, so that when the chip power supply signal is not within its working voltage threshold range after the initial plug-in, the chip power supply signal is disconnected to prevent the chip from being damaged by excessive high / low voltage.

[0030] The output terminal signal of the fifth operational amplifier U5 is fed back to the gate of the sixth MOS tube Q6. The nineteenth resistor R19 is used to discharge the parasitic capacitance of the gate of the sixth MOS tube Q6. When the fifth operational amplifier U5 is turned off, the power supply signal reaches the ground terminal loop through the eleventh resistor R11 and the twelfth resistor R12. The signal at the twelfth resistor R12 reaches the ground terminal loop through the drain of the sixth MOS tube Q6, the source of the sixth MOS tube Q6, and the fifteenth resistor R15. The signal at the fifteenth resistor R15 is fed back to the in-phase terminal of the third operational amplifier U3. The signal at the fifteenth resistor R15 reaches the ground terminal loop through the fourteenth resistor R14 and the twenty-first resistor R21. At the same time, the signal at the fifteenth resistor R15 is fed back to the in-phase terminal of the third operational amplifier U3, and the third operational amplifier U3 outputs. The output terminal signal of the third operational amplifier U3 reaches the ground terminal loop through the twenty-first resistor R21. The signal at the twenty-first resistor R21 reaches the ground terminal loop through the thirteenth resistor R1 3 is fed back to the inverting end of the third operational amplifier U3, and the potential of the second capacitor C2 rises at the same time. When the potential of the second capacitor C2 rises to a certain amplitude, the third operational amplifier U3 is cut off, and the potential of the second capacitor C2 drops. When the potential of the second capacitor C2 drops to a certain amplitude, the third operational amplifier U3 outputs, and the potential of the second capacitor C2 rises. At this time, the output end signal of the third operational amplifier U3 is a pulse signal. When the fifth operational amplifier U5 outputs, the output end signal of the fifth operational amplifier U5 is fed back to the gate of the sixth MOS tube Q6. The voltage difference between the gate of the sixth MOS tube Q6 and the source of the sixth MOS tube Q6 is higher than the conduction threshold, the sixth MOS tube Q6 is cut off, and the third operational amplifier U3 is cut off. In this way, when the chip is in any of the three states of not plugged in, the power supply signal of the chip after plugging is not within the range of its working voltage threshold, and the power supply signal is unstable, the output end of the third operational amplifier U3 can continuously feed back a pulse signal.

[0031] When the third operational amplifier U3 outputs, the output terminal signal of the third operational amplifier U3 is fed back to the positive plate of the first capacitor C1, the potential of the first capacitor C1 rises, and a potential difference is generated between the positive and negative plates of the first capacitor C1. The signal of the negative plate of the first capacitor C1 is fed back to the in-phase terminal of the first operational amplifier U1. The first resistor R1 is a pull-down resistor at the in-phase terminal of the first operational amplifier U1, and the second resistor R2 is a pull-down resistor at the inverting terminal of the first operational amplifier U1. The first operational amplifier U1 outputs, and the output terminal signal of the first operational amplifier U1 is fed back to the gate of the fourth MOS tube Q4 and the gate of the first MOS tube Q1. The voltage difference between the gate of the fourth MOS tube Q4 and the source of the fourth MOS tube Q4 is higher than the conduction threshold, and the fourth MOS tube Q4 is turned on. The chip wake-up signal pin input terminal signal is fed back to the plug-in circuit through the fifth connector P5, and the fifth connector P5 terminal signal is connected to the ground terminal loop via the twenty-third resistor R23. When the fourth MOS tube Q4 is turned on, the first operational amplifier U1 output terminal signal is fed back to the plug-in circuit via the fifth connector P5. The signal at the end of the fifth connector P5 is looped through the third diode D3, the third connector P3, the drain of the fourth MOS tube Q4, and the source of the fourth MOS tube Q4 to the ground end. At the same time, the voltage difference between the gate of the first MOS tube Q1 and the source of the first MOS tube Q1 is higher than the conduction threshold, and the first MOS tube Q1 is turned on. The signal at the end of the fourth resistor R4 is looped through the drain of the first MOS tube Q1 and the source of the first MOS tube Q1 to the ground end. When the positive plate of the first capacitor C1 stops rising, the first operational amplifier U1 is turned off, the first MOS tube Q1 is turned off, and the fourth MOS tube Q4 is turned off. When the power supply signal of the chip is unstable and causes its signal amplitude to fluctuate up and down, the first operational amplifier U1 outputs, thereby preventing instantaneous current from damaging the chip when the chip is initially plugged in. At the same time, based on the chip plugging state and the power supply signal amplitude of the chip, the power supply and wake-up signals of the chip are selectively limited to prevent the chip from being damaged and the operation logic from being confused during the plugging process.

[0032] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A multi-signal wake-up chip plug-in circuit, characterized in that: It includes a third resistor, a fourth resistor, a third MOS tube, a first connector, and a second connector. One end of the third resistor is connected to the first connector, the other end of the third resistor is connected to one end of the fourth resistor, the drain of the third MOS tube, and the second connector, and the other end of the fourth resistor, the source of the third MOS tube, and the ground terminal are connected.

2. The multi-signal wake-up chip plug-in circuit according to claim 1, characterized in that: It also includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a twentieth resistor, a second operational amplifier, a second triode, a fifth MOS tube, a fourth connector, and a first diode. One end of the ninth resistor is connected to a power supply, the other end of the ninth resistor is connected to one end of the sixth resistor and the emitter of the second triode, the base of the second triode is connected to one end of the eighth resistor and the cathode of the first diode, the anode of the first diode is connected to the first connector, the collector of the second triode is connected to one end of the seventh resistor and the in-phase end of the second operational amplifier, the inverting end of the second operational amplifier is connected to one end of the twentieth resistor, the output end of the second operational amplifier is connected to the gate of the third MOS tube and the gate of the fifth MOS tube, the drain of the fifth MOS tube is connected to the fourth connector, and the other end of the sixth resistor, the other end of the seventh resistor, the other end of the eighth resistor, the other end of the twentieth resistor, the source of the fifth MOS tube and the ground are connected.

3. The multi-signal wake-up chip plug-in circuit according to claim 1, characterized in that: It also includes a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a fourth operational amplifier, a fifth operational amplifier, and a seventh MOS tube. One end of the sixteenth resistor is connected to a power supply, the other end of the sixteenth resistor is connected to one end of the seventeenth resistor and an inverting end of the fourth operational amplifier, the other end of the seventeenth resistor is connected to one end of the eighteenth resistor and an inverting end of the fifth operational amplifier, the fourth operational amplifier in-phase end, the fifth operational amplifier in-phase end and the first connector are connected, the fourth operational amplifier output end is connected to the gate of the seventh MOS tube, the fifth operational amplifier output end is connected to the drain of the seventh MOS tube, and the other end of the eighteenth resistor, the source of the seventh MOS tube and the ground are connected.

4. The multi-signal wake-up chip plug-in circuit according to claim 3, characterized in that: The invention also includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a twenty-first resistor, a third operational amplifier, a sixth MOS tube, and a second capacitor. One end of the eleventh resistor is connected to a power supply, the other end of the eleventh resistor is connected to one end of the twelfth resistor and the source of the sixth MOS tube, the gate of the sixth MOS tube is connected to the output end of the fifth operational amplifier, the drain of the sixth MOS tube is connected to one end of the fourteenth resistor, one end of the fifteenth resistor, and the in-phase end of the third operational amplifier, the inverting end of the third operational amplifier is connected to one end of the thirteenth resistor and one end of the second capacitor, the output end of the third operational amplifier is connected to the other end of the thirteenth resistor, the other end of the fourteenth resistor, and one end of the twenty-first resistor, and the other end of the twelfth resistor, the other end of the fifteenth resistor, the other end of the twenty-first resistor, the other end of the second capacitor and the grounding end are connected.

5. The multi-signal wake-up chip plug-in circuit according to claim 4, characterized in that: It also includes a first resistor, a second resistor, a fifth resistor, a first operational amplifier, a first MOS tube, a fourth MOS tube, a third connector, a fourth connector, and a first capacitor. The drain of the first MOS tube is connected to the second connector, the gate of the first MOS tube is connected to one end of the fifth resistor, the output end of the first operational amplifier, and the gate of the fourth MOS tube, the inverting end of the first operational amplifier is connected to one end of the second resistor, the non-inverting end of the first operational amplifier is connected to one end of the first resistor and one end of the first capacitor, the other end of the first capacitor is connected to the output end of the third operational amplifier, the drain of the fourth MOS tube is connected to the third connector, and the other end of the first resistor, the other end of the second resistor, the other end of the fifth resistor, the source of the first MOS tube, the source of the fourth MOS tube, and the grounding end are connected.

6. The multi-signal wake-up chip plug-in circuit according to claim 5, characterized in that: It also includes a twenty-third resistor, a fifth connector, a second diode, and a third diode, wherein the anode of the second diode is connected to one end of the twenty-third resistor, the anode of the third diode, and the fifth connector, the cathode of the second diode is connected to the fourth connector, the cathode of the third diode is connected to the third connector, and the other end of the twenty-third resistor is connected to the ground.

7. The multi-signal wake-up chip plug-in circuit according to claim 2, characterized in that: A tenth resistor is also included, one end of the tenth resistor is connected to the gate of the fifth MOS tube, and the other end of the tenth resistor is connected to the ground end.

8. The multi-signal wake-up chip plug-in circuit according to claim 3, characterized in that: It also includes a twenty-second resistor, one end of which is connected to the gate of the seventh MOS tube, and the other end of which is connected to the ground.

9. The multi-signal wake-up chip plug-in circuit according to claim 4, characterized in that: It also includes a nineteenth resistor, one end of which is connected to the gate of the sixth MOS tube, and the other end of which is connected to the ground.

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