Raman spectrum acquisition and transmission circuit and transmission method

Abstract

The invention relates to a Raman spectrum acquisition and transmission circuit and a transmission method. The Raman spectrum acquisition and transmission circuit comprises a communication module, a spectrum acquisition module and a ZYNQ, the communication module is connected with the ZYNQ and is used for receiving the data information, transmitting the data information to the ZYNQ and sending the data information to a remote data center; the ZYNQ is connected with the spectrum acquisition module, is used for processing data information and driving the spectrum acquisition module to acquire, and is also used for processing a digital signal and transmitting the digital signal to a remote data center through the communication module; and the spectrum acquisition module is connected with the ZYNQ, and is used for receiving and acquiring an instruction, converting a spectrum signal into a digital signal and transmitting the digital signal to the ZYNQ. According to the circuit, spectrum data and geographical and time information can be synchronously acquired and sent to a server, so that the data security and traceability are improved; therefore, the method can be used for scenes with extremely high data quality requirements, the problem of communication protocol mismatching is avoided, and the high speed and stability of data transmission are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of Raman spectroscopy analysis, and in particular to a Raman spectroscopy acquisition and transmission circuit and a transmission method. Background Art

[0002] Raman spectroscopy is a technology that uses the light scattering properties of material molecules to identify different substances. When light hits a substance, most of it undergoes Rayleigh scattering, with the wavelength unchanged; while a small portion of the light undergoes Raman scattering, with the wavelength changing, forming a characteristic spectrum that can be used to identify substances, so it is widely used in substance identification and chemical analysis.

[0003] Existing Raman spectroscopy acquisition and transmission circuits face challenges in remote data transmission, mainly due to the lack of direct transmission capabilities and reliance on serial port communication and host computer transfer, which not only limits the transmission speed, but also may introduce data security risks, affecting the authenticity and traceability of the data, especially in application scenarios that require high data integrity, such as environmental monitoring and legal evidence collection.

[0004] In addition, the existing circuit cannot achieve remote control, which limits its application in industries that require real-time monitoring and rapid response, such as oil refining and chemical production, which also makes it impossible to achieve online monitoring of the production process. The existing solution for remote transmission of Raman spectrometers is to introduce a computer to transfer remote control commands, which increases the complexity of the system and may cause delays in the transmission of control commands, reducing the reliability and real-time performance of the system.

[0005] In terms of hardware, the chip solutions of existing circuits, whether single ARM, single FPGA or ARM+FPGA combination, have performance limitations. FPGA performs well in parallel computing and low-latency applications, but is not as good as ARM in general computing tasks. On the contrary, ARM is simpler and more efficient in Ethernet communication, but cannot meet high-real-time scenarios such as driving high-performance CMOS and AD converters in Raman acquisition circuits. The communication protocol between FPGA and ARM in the existing solution is also difficult to meet the needs of high-speed data transmission.

[0006] In terms of power supply, existing circuits usually use USB interfaces for power supply, lack dedicated power supply circuit design, and cannot provide stable and high-quality power supply, which is crucial for the stable operation of key components such as high-precision CMOS and AD converters. Summary of the invention

[0007] In view of one or more of the problems existing in the prior art, the first aspect of the present application provides a Raman spectrum acquisition and transmission circuit, including: a communication module, a spectrum acquisition module, and ZYNQ; wherein:

[0008] The communication module is connected to the ZYNQ and is used to receive data information from a remote data center and transmit it to the ZYNQ, and to send data information from the ZYNQ to the remote data center;

[0009] The ZYNQ is connected to the spectrum acquisition module, and is used to process the data information transmitted through the communication module, drive the spectrum acquisition module to collect data, and process the digital signal from the spectrum acquisition module and transmit it to the remote data center through the communication module;

[0010] The spectrum acquisition module is connected to the ZYNQ, and is used to receive instructions from the ZYNQ and perform acquisition, and convert the acquired spectrum signal into a digital signal and transmit it to the ZYNQ.

[0011] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the ZYNQ includes a PS and an FPGA, the PS includes an Ethernet module, an ARM, and a DDR control module, and the PS and the FPGA communicate using an AXI interface; wherein:

[0012] The Ethernet module is connected to the communication module and the ARM respectively, and is used to parse the data information from the remote data center and send the parsed data to the ARM, and is also used to send the data from the ARM to the remote data center through the communication module;

[0013] The ARM is connected to the FPGA and the DDR control module, and is used to process the data parsed by the Ethernet module, and send the processed instructions to the FPGA through the AXI interface, and is also used to read the data in the DDR control module and encapsulate it, and send the encapsulated data to the Ethernet module;

[0014] The FPGA is used to receive instructions from the ARM through the AXI interface to drive the spectrum acquisition module to perform acquisition work and spectrum signal conversion work, and can also write the acquisition information data into the DDR control module through the AXI interface in a DMA manner.

[0015] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the FPGA includes an instruction parsing module, a CMOS driver module, an AD driver module, a RAM and an AXIDMA module; wherein:

[0016] The instruction parsing module is connected to the ARM and the CMOS driving module, and is used to receive instructions from the ARM, parse the instructions, and transmit the parsing results to the CMOS driving module;

[0017] The CMOS driving module is connected to the spectrum acquisition module, and when the instruction parsing result is an acquisition start signal, it is used to drive the spectrum acquisition module to perform acquisition, and when the instruction parsing result is an integration time signal, it is used to save the integration time to the register of the CMOS driving module;

[0018] The AD driving module is connected to the spectrum acquisition module and the RAM, and is used to generate a driving signal to drive the spectrum acquisition module to perform analog-to-digital conversion, and write the converted digital signal into the RAM;

[0019] The RAM is connected to the AXIDMA module, and the AXIDMA module is connected to the PS via an AXI interface, and is used to write the digital signal stored in the RAM into the DDR control module in the PS via the AXI interface in a DMA manner.

[0020] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the spectrum acquisition module includes a CMOS, a signal conditioning circuit and an AD conversion circuit; wherein:

[0021] The CMOS is connected to the CMOS driving module and the signal conditioning circuit, and is used to perform spectrum acquisition according to the driving signal of the CMOS driving module, and output the spectrum signal to the signal conditioning circuit after photoelectric signal conversion;

[0022] The signal conditioning circuit is connected to the AD conversion circuit, and is used to filter and amplify the spectrum signal from the CMOS, and transmit it to the AD conversion circuit;

[0023] The AD conversion circuit is connected to the AD driving module, and is used for converting the spectrum signal from the signal conditioning circuit from an analog signal to a digital signal after receiving the driving signal from the AD driving module, and sending the digital signal to the AD driving module.

[0024] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the circuit further includes a GPS module, and the FPGA further includes a GPS control module, wherein:

[0025] The GPS control module is connected to the AD driving module, the GPS module and the RAM respectively, and is used to receive the GPS acquisition start signal sent by the AD driving module, and control the GPS module to capture the signal from the global positioning system satellite, and read the GNSS protocol data in the GPS module, and extract the longitude and latitude and time information therefrom, and store them in the RAM.

[0026] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the FPGA further includes a FIFO and a serial communication module; wherein:

[0027] The FIFO is connected to the AD driver module and is used to write the converted digital signal into the FIFO for cross-clock domain processing;

[0028] The serial communication module is connected to the host computer, the instruction parsing module and the FIFO, and is used to receive instruction information sent by the host computer and send it to the instruction parsing module for parsing, and is also used to read spectral data from the FIFO, send the data to the host computer through the serial communication circuit, and perform on-site display and processing of Raman spectra.

[0029] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the circuit further includes an anti-backflow circuit and CH340; wherein:

[0030] The CH340 is a USB to serial port chip, connected to the serial port communication module and the anti-backflow circuit, and is used to realize the conversion between the serial port communication protocol of the Raman acquisition transmission control circuit and the USB protocol of the host computer (computer);

[0031] The anti-backflow circuit is connected to the host computer and is used to prevent the USB-to-serial port chip from being burned by the backflow current.

[0032] According to a Raman spectrum transmission circuit provided by an embodiment of the present application, the circuit further includes a DDR3, which is connected to the DDR control module and is used to store data information transmitted from the DDR control module for reading by the DDR control module.

[0033] Preferably, the circuit further comprises an SD card circuit for storing programs and burning the programs into the circuit system when the circuit system is powered on.

[0034] According to a Raman spectrum transmission circuit provided in an embodiment of the present application, the workflow of the FPGA control program is as follows:

[0035] S1, the program starts running;

[0036] S2. The module outputs three signals, including the clock control signal scl, the write data signal sdata, and the write enable signal sload to complete the configuration of the analog-to-digital converter AD9826 in the AD conversion circuit.

[0037] S3, determine whether there is a signal sent by the host computer, if not, repeat S3; if yes, proceed to the next step;

[0038] S4, the instruction parsing module parses the data;

[0039] S5, determine the instruction type. If it is an integration time signal, save the integration time to the register in the CMOS driver module, then return to S3 and proceed downward; if it is an acquisition start signal, proceed to the next step;

[0040] S6, output CMOS chip drive clock, pull up CMOS chip acquisition control signal ST, and control the self-defined integral counter inside FPGA to start counting, and the program enters the integral state;

[0041] S7, judging whether the integral time has been reached by the integral counter, if not, returning to S6 and proceeding downward; if yes, proceeding to the next step;

[0042] S8, the program enters the transmission state, receives the synchronization signal Trig sent by CMOS, and customizes a Trig signal counter inside the FPGA to count the synchronization signal Trig;

[0043] S9, determine whether the count of the custom Trig signal counter reaches 89, if not, return to S8 and proceed to the next step; if yes, proceed to the next step;

[0044] S10, output two drive clocks cdsclk2 and adcclk to the analog-to-digital converter AD9826, driving the analog-to-digital converter AD9826 to start analog-to-digital conversion;

[0045] S11. Use a clock with the same frequency as adcclk, one of the AD9826 driving clocks, as a write clock to write the signal from the analog-to-digital converter AD9826 into the FIFO and RAM.

[0046] S12, determine whether the count of the custom synchronization signal Trig counter reaches 2136, if not, return to S10 and proceed to the next step; if yes, proceed to the next step;

[0047] S13, using the GPS control module to read the GPS data and write it into the RAM. After the RAM is full, the GPS control module sends an interrupt signal;

[0048] S14, using a clock with the same frequency as the transmission baud rate as a read clock, reading data from the FIFO, thereby completing cross-clock domain processing;

[0049] S15, using the serial communication module to send the data read from the FIFO;

[0050] S16, judging whether the FIFO is read from the FIFO and the FIFO is empty, if not, returning to S14 and proceeding downward; if yes, proceeding to the next step;

[0051] S17, determine whether to stop, if not, save the integration time to the register in the CMOS driver module, then return to S3 and proceed downward; if yes, proceed to the next step;

[0052] S18. The program ends.

[0053] Preferably, the workflow of the control program on the PS side is:

[0054] S1, program starts;

[0055] S2, interrupt initialization, DMA initialization, interrupt service program initialization, LWIP protocol stack and TCP / IP protocol initialization;

[0056] S3, perform three-way handshake with the server to establish a TCP connection;

[0057] S4, waiting for the interrupt signal of the GPS module. If there is no interrupt signal of the GPS module, proceed to S4 again. If there is an interrupt signal of the GPS module, proceed to the next step;

[0058] S5, start DMA data transmission;

[0059] S6, waiting for the DMA completion interrupt signal, if there is no DMA completion interrupt signal, then proceed to S6 again, if there is a DMA completion interrupt signal, then proceed to the next step;

[0060] S7, read the Raman spectrum raw data, time, and location information from the DDR and send it to the server via Ethernet;

[0061] S8, determine whether the Ethernet transmission is completed, if not, proceed to S8 again; if yes, proceed to the next step;

[0062] S9, determine whether to stop, if not, return to S4 and proceed to the next step; if yes, proceed to the next step;

[0063] S10, wave four times to the server to disconnect the TCP connection;

[0064] S11. The program ends.

[0065] A second aspect of the present application provides a Raman spectrum acquisition and transmission method, which is applied to the above circuit and includes:

[0066] The communication module receives data information from the remote data center and transmits it to ZYNQ;

[0067] ZYNQ processes the data information transmitted by the communication module and drives the spectrum acquisition module to collect data;

[0068] The spectrum acquisition module receives instructions from the ZYNQ and performs acquisition, and converts the acquired spectrum signal into a digital signal and transmits it to the ZYNQ;

[0069] The ZYNQ processes the digital signal from the spectrum acquisition module and sends the data to a remote data center through the communication module.

[0070] One or more of the above embodiments of the present application have at least the following beneficial effects:

[0071] Security and integrity of remote data transmission: The Raman spectrum acquisition and transmission circuit designed in this application integrates the ZYNQ chip and GPS module to achieve synchronous acquisition of data acquisition and geographic location and time information, and directly sends it to the server via Ethernet, eliminating the traditional step of transferring through the host computer, thereby improving the security, authenticity and traceability of the data. This innovation is suitable for application scenarios with extremely high requirements for data quality, such as environmental monitoring and law enforcement evidence collection, while avoiding the problem of communication protocol mismatch and ensuring high data transmission rate and stability.

[0072] High efficiency of remote data reception and analysis execution: The circuit design of this application has the function of remote data reception and analysis execution. Through the efficient processing capability of the ZYNQ chip, it realizes rapid response and execution of remote instructions, significantly improving real-time performance and reliability. Compared with the existing technology, this solution reduces the delay and single point failure risk of the computer as an intermediary, and provides a more stable and efficient remote control solution for online monitoring in industries such as petrochemicals, polymer synthesis, and food processing.

[0073] Optimization and implementation of the main control chip solution: This application uses ZYNQ as the main control chip, making full use of its advantages of integrated FPGA and ARM. Through the high-speed data transmission capability of the AXI bus, it optimizes the communication efficiency of the existing single ARM, single FPGA or ARM+FPGA solutions, solving the problem that they cannot take into account the advantages of both and the low communication efficiency. The PL part of ZYNQ is responsible for high-speed data acquisition and peripheral driving, while the PS part is responsible for data encapsulation and network transmission. This design gives full play to the strengths of each and improves the overall performance of the system.

[0074] Stability design of dedicated power supply circuit: The power supply system designed in this application is composed of BUCK step-down circuit and LDO voltage regulator circuit, which can provide input voltage up to 12V / 2A, ensuring stable power supply for each device in the system. The selected high-efficiency IC and high-quality inductor and capacitor components, combined with careful PCB layout, achieve high stability, low ripple and noise power output, meet the strict requirements of high-precision devices for power supply voltage, and provide a solid and reliable power supply guarantee for the entire Raman spectroscopy acquisition and transmission circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings:

[0076] Figure 1 is a schematic diagram of the structure of a Raman spectrum acquisition and transmission circuit provided according to an embodiment of the present application;

[0077] Figure 2 It is a power topology diagram of a Raman spectrum acquisition and transmission circuit provided in an embodiment of the present application;

[0078] Figure 3 It is a schematic diagram of the PL (FPGA) end program workflow of the Raman spectrum acquisition and transmission circuit provided in an embodiment of the present application;

[0079] Figure 4 It is a schematic diagram of the PS (ARM) end program workflow of the Raman spectrum acquisition and transmission circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] Embodiments of the present application will be described in detail below, examples of which are shown in the accompanying drawings, and the components of the embodiments of the present application generally described and shown in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the application claimed for protection, but merely represents selected embodiments of the present application.

[0081] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0082] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0083] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0084] The following will be combined Figure 1 and Figure 4 The technical solution of the present application is described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0085] See also Figure 1 The first aspect of the present application provides a Raman spectrum acquisition and transmission circuit, comprising: a communication module, a spectrum acquisition module, and ZYNQ; wherein:

[0086] The communication module is connected to ZYNQ. This module is responsible for data exchange with the remote data center. It receives data information from the remote data center and transmits this information to ZYNQ for further processing. At the same time, it is also responsible for sending the spectral data processed by ZYNQ back to the remote data center to ensure real-time transmission and reception of data.

[0087] Optionally, the communication module may be an Ethernet port.

[0088] As the control center of the entire circuit, ZYNQ is connected to the spectrum acquisition module. It receives data information from the communication module, analyzes the data information, and drives the spectrum acquisition module to collect data accordingly. In addition, ZYNQ is also responsible for processing the digital signal from the spectrum acquisition module and sending the processing results to the remote data center through the communication module.

[0089] The spectrum acquisition module is connected to ZYNQ and is used to receive instructions from ZYNQ and perform acquisition, as well as convert the acquired spectrum signals into digital signals and transmit them to ZYNQ for further processing and transmission.

[0090] The workflow of the entire circuit system is as follows: the remote data center sends data information to the communication module, the communication module passes the data information to ZYNQ, ZYNQ parses the instructions and drives the spectrum acquisition module to collect data. After the collected spectral signal is processed, it is sent back to the remote data center by ZYNQ through the communication module, completing the entire data collection and transmission process.

[0091] The Raman spectrum acquisition and transmission circuit designed in this application has a remote data transmission function, which solves the problem that the existing Raman spectrum acquisition circuit cannot guarantee the authenticity, credibility and traceability of data. It solves the problem that the existing Raman spectrum acquisition circuit is difficult to meet the needs of high-speed, stable and timely remote data transmission.

[0092] Compared with the existing method of first transmitting data to the host computer through serial communication and then using software to send data remotely through Ethernet, the Raman spectrum acquisition and transmission circuit designed in this application reduces the step of transferring by computer, avoids the additional potential risks of data tampering introduced by the computer as an intermediate link, and improves the security and credibility of data. Therefore, the Raman spectrum acquisition circuit designed in this patent is suitable for use scenarios with high requirements for data authenticity, credibility, and traceability, such as rapid detection of water pollution and on-site evidence collection and law enforcement of contraband.

[0093] In addition, the remote data transmission scheme proposed in this patent eliminates the serial communication with a slower communication rate in the existing remote transmission scheme, and improves the overall data transmission rate of the system. It avoids the problem of mismatch between the two communication protocols and improves the rate and stability of remote transmission. It can meet the needs of high-speed, stable and timely remote data transmission.

[0094] Furthermore, ZYNQ includes a processing system (PS) and a programmable logic part (PL, specifically a programmable logic array FPGA). The PS part integrates an Ethernet module, an ARM and a DDR control module. The FPGA is connected to the PS via an AXI interface; wherein:

[0095] The Ethernet module is not only connected to the external communication module to achieve data exchange with the remote data center, but also connected to ARM to ensure smooth data flow. The Ethernet module is responsible for receiving data sent by the remote data center, completing data link layer parsing work such as frame detection and synchronization, address recognition, and data error detection, and transmitting data to ARM. ARM is responsible for completing the protocol parsing work of the MAC layer, IP layer, and TCP layer to obtain user data. At the same time, the Ethernet module can also send the data processed by ARM to the remote data center through the communication module to complete the data transmission task.

[0096] ARM is connected to the Ethernet module, FPGA and DDR control module. ARM is responsible for processing the data parsed by the Ethernet module, further completing the protocol parsing work of the MAC layer, IP layer and TCP layer, parsing to obtain user data such as the acquisition start signal and the integration time configuration signal, and sending the acquisition start signal or the integration time configuration signal to the FPGA through the AXI interface, thereby starting the acquisition work of the spectrum acquisition module. In addition, ARM reads the data in the DDR memory, gradually encapsulates it into the protocols of the MAC layer, IP layer and TCP layer, and sends the data to the remote data center through the Ethernet module.

[0097] FPGA is used to receive instructions from ARM through the AXI interface, thereby driving the spectrum acquisition module to perform acquisition operations, and can also drive the spectrum acquisition module to convert and process spectrum signals. FPGA is also responsible for writing the collected information data to the DDR control module through the AXI bus to prepare for subsequent data storage and transmission.

[0098] The DDR control module is used to receive the collected information data written by the FPGA and store it securely in the DDR memory. This data can be read by the ARM processor for further data processing and packaging, and finally sent to the remote data center through the Ethernet module.

[0099] ZYNQ not only achieves efficient data processing and storage, but also ensures the flexibility and scalability of the system through its highly integrated architecture.

[0100] Compared with the existing remote control method that requires a computer as a "transfer station", the remote control terminal in the remote control solution designed by this application can directly send the control command to the Raman spectrum acquisition and transmission circuit with remote communication function without the need for computer transfer. This greatly simplifies the communication process and reduces the delay in transmission. At the same time, since the computer as a transfer link is removed, this solution reduces the risk of single point failure. Computer failure, shutdown or maintenance will no longer affect the implementation of remote control, thereby improving the reliability and stability of the entire system. With the increasing complexity of process flows in today's petrochemical, polymer synthesis, food processing and other fields, the real-time and reliability requirements of the monitoring systems therein are getting higher and higher. The remote control solution proposed by this patent and its supporting software and hardware have obvious advantages in real-time and reliability, and have broad application prospects.

[0101] Furthermore, the FPGA includes an instruction parsing module, a CMOS driver module, an AD driver module, a RAM and an AXIDMA module; wherein:

[0102] The instruction parsing module is connected to the ARM and CMOS driver modules through the AXI interface, and is used to receive instructions issued by the ARM, parse the instructions, and transmit the parsing results to the CMOS driver module to guide its subsequent actions;

[0103] Optionally, ARM may send the acquisition start instruction or the integration time configuration instruction to the instruction parsing module via the AXI interface.

[0104] The CMOS driver module is connected to the spectrum acquisition module, and the CMOS driver module takes action according to the results of the instruction parsing module. When the CMOS driver module receives the acquisition start signal, it activates the spectrum acquisition module and starts the spectrum data acquisition process. If an integration time signal is received, the CMOS driver module will save the time parameter to its own register to control the integration time during the acquisition process.

[0105] The AD driver module is connected to the spectrum acquisition module and RAM. During the spectrum acquisition process, the AD driver module generates a drive signal to trigger the spectrum acquisition module to perform analog-to-digital conversion and convert the analog signal into a digital signal. The converted digital signal is then sent to the RAM to prepare for the next step of data storage and processing.

[0106] AXIDMA refers to a DMA module with an AXI interface. RAM is connected to the AXIDMA module, and finally the AXIDMA module is connected to the PS through the AXI interface. RAM is responsible for temporarily storing the digital signals written by the AD driver module. Subsequently, the data information in the RAM is efficiently written to the PS through the AXI interface through DMA (direct memory access), realizing fast data storage and subsequent processing.

[0107] In the transmission circuit disclosed in this application, FPGA can not only quickly respond to ARM instructions, but also efficiently manage and process data from the spectrum acquisition module. This efficient data processing process ensures that the system can collect and store spectrum data in real time and accurately, providing a solid foundation for subsequent data analysis and application.

[0108] In addition, the flexibility and programmability of FPGA allow the system to be customized and optimized according to different application requirements, further improving the adaptability and performance of the system. This design not only improves the efficiency and accuracy of spectral data acquisition, but also ensures the stability and reliability of the circuit system through a highly integrated architecture.

[0109] Furthermore, the spectrum acquisition module includes CMOS, a signal conditioning circuit and an AD conversion circuit; wherein:

[0110] CMOS is used to capture the spectral information of incident light. It is connected to the CMOS driver module and the signal conditioning circuit, and performs the spectral acquisition task according to the driving signal provided by the CMOS driver module. The CMOS sensor converts the received optical signal into an electrical signal, namely a spectral signal, and outputs it to the signal conditioning circuit.

[0111] The signal conditioning circuit is located between the CMOS sensor and the AD conversion circuit. The signal conditioning circuit can filter and amplify the spectral signal output by the CMOS sensor. This step is crucial because it can improve the quality of the signal and reduce noise, thereby ensuring the accuracy and reliability of the signal. The spectral signal after signal conditioning is transmitted to the AD conversion circuit to prepare for analog-to-digital conversion.

[0112] The AD conversion circuit is connected to the AD driver module. The task of the AD conversion circuit is to convert the spectrum signal processed by the signal conditioning circuit from an analog signal to a digital signal. This conversion process is the basis for data storage and further analysis. The AD conversion circuit receives the driving signal from the AD driver module, triggers the analog-to-digital conversion process, and sends the converted digital signal to the AD driver module.

[0113] Furthermore, the circuit further includes a GPS module, and the FPGA further includes a GPS control module, wherein:

[0114] The GPS control module is connected to the AD drive module. When the AD control module controls the AD conversion circuit to complete the spectrum data acquisition and store the data in RAM, the AD drive module sends a GPS acquisition start signal to the GPS control module. The above synchronization measures ensure that each spectrum data has corresponding position coordinate data, ensuring the authenticity and traceability of the original spectrum data.

[0115] The GPS module is connected to the GPS control module. After the GPS control module receives the GPS acquisition start signal from the AD driver module, it controls the GPS module to capture the signal from the global positioning system satellite. The GPS module receives key time and geographic location data by communicating with satellites in the sky.

[0116] The GPS control module is connected to the RAM and is used to read and process the satellite signals received by the GPS module, convert these signals into data in the format of the Global Navigation Satellite System (GNSS), and store them in the RAM. These data can then be accessed by other parts of the circuit system for further analysis and processing.

[0117] Through this design, the transmission circuit system provided in the present application can not only realize efficient spectral data acquisition and processing, but also provide accurate time and geographic location information, greatly expanding the application scope and function of the circuit system. At the same time, the circuit system also sends the location and time information together with the original spectral data to the remote data center, which improves the integrity and traceability of the data.

[0118] Furthermore, the circuit also includes DDR3, which is connected to the DDR control module. The main function of DDR3 is to store data information from the DDR control module. These data may include information collected from devices such as CMOS and GPS modules, as well as intermediate data and result data generated during the operation of the system; DDR3 allows the DDR control module to read the stored data on demand. This reading capability ensures that the data can be accessed and analyzed by the subsequent processing unit in a timely manner.

[0119] Furthermore, the FPGA also includes a serial communication module and a FIFO (First In, First Out) queue; wherein:

[0120] The serial communication module is connected to the host computer, the instruction parsing module and the FIFO, and is used to receive the instruction information sent by the host computer and send it to the instruction parsing module for parsing. After the instruction information received by the serial communication module is parsed by the instruction parsing module, it can trigger the corresponding operation inside the FPGA, such as starting or stopping data acquisition, configuring acquisition parameters, etc. The serial communication module is also used to read the stored spectral data from the FIFO, and send the data to the host computer through the serial communication circuit. The spectral data received by the host computer can be displayed and preliminarily processed in real time on site, providing operators with an intuitive data view and fast data analysis capabilities. This not only improves the interactivity of the system, but also makes on-site decision-making and response faster and more accurate.

[0121] FIFO is connected to the AD driver module and can be used to temporarily store the digital signal converted by the AD conversion circuit to ensure the stability and integrity of the data during the cross-clock domain transmission process. The use of FIFO effectively avoids data loss or errors caused by clock domain asynchrony, and improves the data processing capability and reliability of the system. The introduction of FIFO allows the circuit system to process data at different clock frequencies, which is the key to achieving high-speed data acquisition and transmission. Through cross-clock domain processing, the system can smoothly process the high-speed data stream from the AD conversion circuit while maintaining the synchronization and accuracy of the data.

[0122] Furthermore, the transmission circuit provided by the present application also includes an anti-backflow circuit, CH340; wherein:

[0123] CH340 is a USB to serial port chip, connected to the serial port communication module and the anti-backflow circuit, and is used to achieve seamless conversion between the serial port communication protocol of the Raman acquisition transmission control circuit and the USB protocol of the host computer (computer). This conversion capability greatly enhances the compatibility of the system, allows the use of ordinary USB interfaces for data communication, and simplifies the connection between the system and the host computer;

[0124] In order to ensure the stable operation of CH340, an anti-reverse flow circuit is specially integrated in the system design. This circuit is connected to the host computer, and its main function is to form a protection in the circuit to prevent the reverse flow of current due to abnormal conditions of the USB interface, thereby avoiding burning the USB to serial port chip.

[0125] The combination of the anti-backflow circuit and the CH340 chip provides users with a safe and convenient way of data communication. Users do not need to worry about the risk of circuit damage and can focus on data analysis and processing.

[0126] Furthermore, the circuit also includes an SD card circuit for storing programs and burning the programs into the circuit system when the circuit system is powered on. When the circuit system is powered on, the SD card circuit will automatically detect and read the programs stored on the SD card, and then burn these programs into the system's memory or flash memory to achieve fast startup and deployment.

[0127] Furthermore, there is a protection circuit, such as a power supply circuit, outside the Raman spectrum collection and transmission circuit provided in the present application, and the power supply circuit is responsible for providing electrical energy to the entire system.

[0128] Figure 2 What is shown is the power topology diagram of the Raman acquisition and transmission circuit designed in this application. This system uses lithium batteries as power sources, and ensures that each component obtains a stable and appropriate voltage supply through a carefully designed power management circuit.

[0129] The following is a detailed workflow of circuit system power management and distribution:

[0130] The entire circuit system is powered by a lithium battery, which provides the necessary energy for the system to operate stably for a long time;

[0131] The output voltage of the lithium battery is stepped down through the BUCK step-down circuit to reduce the voltage to 5V to meet the working voltage requirements of major components such as ZYNQ, GPS module, operational amplifier in the signal conditioning circuit, CMOS sensor, AD conversion chip, etc.

[0132] The 5V voltage is stabilized to -5V through an LDO (Low Dropout Regulator) voltage regulator circuit to provide the required negative power supply voltage for the operational amplifier in the signal conditioning circuit;

[0133] The other 5V voltage is reduced to 3.3V through the LDO voltage regulator circuit to provide a stable power supply for components such as the anti-backflow circuit, DDR3 memory, Ethernet port, and SD card circuit;

[0134] The 5V voltage is also reduced to 1.8V through an LDO voltage regulator circuit to provide another required power supply voltage for the SD card circuit to ensure the stable operation of the SD card;

[0135] The 5V voltage output by the USB of the host computer is stabilized to 3.3V through LDO, which provides power for the USB-to-serial port chip CH340 to ensure the stable operation of the serial port communication module;

[0136] The power supply circuit designed in this application adopts an efficient and stable architecture, consisting of a BUCK step-down circuit and four LDO voltage regulator circuits. It can accept an input voltage of up to 12V / 2A to ensure that the power requirements of each device in the system are met and there is sufficient margin to maintain stable operation of the system.

[0137] Buck step-down circuit: Select high switching frequency, high efficiency, low quiescent current IC, with high saturation current, low internal resistance power inductor, and low equivalent series resistance, high saturation voltage filter capacitor. The PCB layout of the circuit is optimized for the buck topology to achieve high-efficiency power conversion.

[0138] LDO voltage regulator circuit: According to the specific power requirements of each device, select ICs with high load adjustment performance, high linear adjustment speed and high ripple suppression capability, as well as filter capacitors with low equivalent series resistance and high saturation voltage. These selected components ensure that the power supply circuit can provide a high stability, low ripple, low noise and high precision power supply voltage.

[0139] Power performance: The comprehensive design ensures that the power system can adapt to load changes and provide the required power supply voltage for the high-precision devices in the system to meet their strict requirements for power quality.

[0140] Through this power supply system design, the present application not only improves the stability and efficiency of the power supply, but also ensures the reliability of the entire circuit system and the maximization of device performance.

[0141] Furthermore, the present application provides a control program for the PL (FPGA) end in the Raman spectrum acquisition and transmission circuit, such as Figure 3 As shown, its workflow is:

[0142] S1, the program starts running;

[0143] S2. The module outputs three signals, including the clock control signal scl, the write data signal sdata, and the write enable signal sload to complete the configuration of the analog-to-digital converter AD9826 in the AD conversion circuit.

[0144] S3, determine whether there is a signal sent by the host computer, if not, repeat S3; if yes, proceed to the next step;

[0145] S4, the instruction parsing module parses the data;

[0146] S5, determine the instruction type. If it is an integration time signal, save the integration time to the register in the CMOS driver module, then return to S3 and proceed downward; if it is an acquisition start signal, proceed to the next step;

[0147] S6, output CMOS chip drive clock, pull up CMOS chip acquisition control signal ST, and control the self-defined integral counter inside FPGA to start counting, and the program enters the integral state;

[0148] S7, judging whether the integral time has been reached by the integral counter, if not, returning to S6 and proceeding downward; if yes, proceeding to the next step;

[0149] S8, the program enters the transmission state, receives the synchronization signal Trig sent by CMOS, and customizes a Trig signal counter inside the FPGA to count the synchronization signal Trig;

[0150] S9, determine whether the count of the custom Trig signal counter reaches 89, if not, return to S8 and proceed to the next step; if yes, proceed to the next step;

[0151] S10, output two drive clocks cdsclk2 and adcclk to the analog-to-digital converter AD9826, driving the analog-to-digital converter AD9826 to start analog-to-digital conversion;

[0152] S11. Use a clock with the same frequency as adcclk, one of the AD9826 driving clocks, as a write clock to write the signal from the analog-to-digital converter AD9826 into the FIFO and RAM.

[0153] S12, determine whether the count of the custom synchronization signal Trig counter reaches 2136, if not, return to S10 and proceed to the next step; if yes, proceed to the next step;

[0154] S13, using the GPS control module to read the GPS data and write it into the RAM. After the RAM is full, the GPS control module sends an interrupt signal;

[0155] S14, using a clock with the same frequency as the transmission baud rate as a read clock, reading data from the FIFO, thereby completing cross-clock domain processing;

[0156] S15, using the serial communication module to send the data read from the FIFO;

[0157] S16, judging whether the FIFO is read from the FIFO and the FIFO is empty, if not, returning to S14 and proceeding downward; if yes, proceeding to the next step;

[0158] S17, determine whether to stop, if not, save the integration time to the register in the CMOS driver module, then return to S3 and proceed downward; if yes, proceed to the next step;

[0159] S18. The program ends.

[0160] Furthermore, the present application provides a control program for the PS (ARM) terminal in the Raman spectrum acquisition and transmission circuit, such as Figure 3 As shown, its workflow is:

[0161] S1, program starts;

[0162] S2, interrupt initialization, DMA initialization, interrupt service program initialization, LWIP protocol stack and TCP / IP protocol initialization;

[0163] S3, perform three-way handshake with the server to establish a TCP connection;

[0164] S4, waiting for the interrupt signal of the GPS module. If there is no interrupt signal of the GPS module, proceed to S4 again. If there is an interrupt signal of the GPS module, proceed to the next step;

[0165] S5, start DMA data transmission;

[0166] S6, waiting for the DMA completion interrupt signal, if there is no DMA completion interrupt signal, then proceed to S6 again, if there is a DMA completion interrupt signal, then proceed to the next step;

[0167] S7, read the Raman spectrum raw data, time, and location information from the DDR and send it to the server via Ethernet;

[0168] S8, determine whether the Ethernet transmission is completed, if not, proceed to S8 again; if yes, proceed to the next step;

[0169] S9, determine whether to stop, if not, return to S4 and proceed to the next step; if yes, proceed to the next step;

[0170] S10, wave four times to the server to disconnect the TCP connection;

[0171] S11. The program ends.

[0172] This application adopts ZYNQ chip as the main control chip solution for Raman spectrum acquisition and transmission circuit and writes the corresponding control program. ZYNQ is a SOC chip that integrates FPGA and ARM, combining the advantages of FPGA's expertise in high-speed parallel computing and ARM's expertise in general computing tasks. At the same time, the FPGA and ARM use the AXI bus integrated inside ZNYQ for communication. The AXI bus protocol is an on-chip bus for high performance, high bandwidth, and low latency, which ensures high-speed data transmission between FPGA and ARM.

[0173] This application uses the PL (FPGA) part of ZYNQ to control high-performance CMOS for photoelectric conversion, control high-speed AD conversion circuits for analog-to-digital conversion, control GPS modules to receive satellite signals and parse out location, time and other information, and other tasks, giving full play to the advantages of FPGA in parallel computing and driving high-performance peripherals. This application uses the PS (ARM) part of ZYNQ to package data and perform tasks such as Ethernet data transmission, giving full play to the advantages of ARM in general computing and high integration. This patent uses the AXI bus inside ZYNQ to complete the communication between FPGA and ARM to cope with the transmission of a large amount of Raman spectral raw data between FPGA and ARM. The solution in this patent solves the shortcomings of existing single ARM, single FPGA or ARM+FPGA chip solutions that cannot take into account the advantages of ARM and FPGA and the low communication efficiency between the two.

[0174] The working process of the Raman spectrum acquisition and transmission circuit provided in this application is as follows:

[0175] The remote data center sends data information to the Ethernet port of the circuit system via Ethernet;

[0176] After receiving the data, the Ethernet communication module in the PS part of ZYNQ completes the data link layer parsing work such as frame detection and synchronization, address recognition, data error checking, and transmits the data to ARM;

[0177] ARM processes the data parsed by the Ethernet module, further completes the protocol parsing work of the MAC layer, IP layer, and TCP layer, parses to obtain user data such as the acquisition start signal and the integration time configuration signal, and sends the acquisition start signal or the integration time configuration signal to the instruction parsing module through the AXI interface;

[0178] If the instruction parsing module confirms that the received signal is the acquisition start signal, the CMOS driver module will output a drive signal to the CMOS to start the spectrum acquisition process; if the integration time signal is received, the CMOS driver module will save the time parameter to its own register to control the integration time during the acquisition process;

[0179] The spectral signal collected by CMOS is filtered and amplified by the signal conditioning circuit to improve the signal quality;

[0180] The AD driver module in the PL part of ZYNQ drives the AD conversion circuit to convert the conditioned analog spectrum signal into a digital signal and write it into RAM;

[0181] At the same time, the GPS control module reads the current time and geographic location data from the GPS module and stores this information in RAM;

[0182] The time, geographic location and spectral data in the RAM are written to the DDR3 via the AXI interface between the PL and the PS in the form of DMA and are managed by the DDR control module.

[0183] ARM reads the data in DDR3 through the DDR control module, performs necessary processing and encapsulation, and encapsulates the data into a format suitable for network transmission, including encapsulation of the MAC layer, IP layer, and TCP layer;

[0184] The encapsulated data is sent to the remote data center through the Ethernet module and Ethernet port to complete the remote transmission of data;

[0185] After the remote data center receives the data, it can perform further analysis and processing, such as spectral analysis, data storage, and report generation;

[0186] Based on the processing results of the remote data center, the system can receive feedback instructions and perform the next step, such as adjusting collection parameters, re-collecting, etc.

[0187] The entire workflow reflects the high degree of automation and intelligence of the circuit system. From the reception of remote instructions to the collection, processing, storage and remote transmission of data, the entire process is efficient and accurate, meeting the needs of modern spectral analysis for remote communication and data processing. Through this design, the circuit system not only improves the efficiency and accuracy of spectral data collection, but also greatly expands its application scenarios through remote communication capabilities, and is suitable for a variety of fields that require remote monitoring and real-time data analysis.

[0188] The Raman spectrum acquisition and transmission circuit provided in this application also retains a serial communication interface to achieve on-site operation and debugging. Its workflow is as follows:

[0189] The operator connects the host computer to the serial communication interface of the circuit system, and the host computer sends command information to the PL part of ZYNQ through the serial communication circuit. These commands may include acquisition start, integration time configuration, etc.

[0190] The serial communication module in the PL part of ZYNQ receives the command information sent by the host computer and sends this information to the command parsing module for parsing.

[0191] If the instruction parsing module confirms that the received signal is the acquisition start signal, the CMOS driver module will output the corresponding drive signal to start the CMOS to collect the spectrum; if the integration time signal is received, the CMOS driver module will save the time parameter to its own register to control the integration time during the acquisition process;

[0192] The spectral signal collected by CMOS is transmitted to the signal conditioning circuit for necessary filtering and amplification processing to optimize the signal quality.

[0193] The conditioned analog spectral signal is driven by the AD driver module to drive the AD conversion circuit to perform analog-to-digital conversion, thereby converting the analog signal into a digital signal;

[0194] The converted digital signal is written into the FIFO for cross-clock domain processing to ensure that data is transmitted safely and accurately between clock domains of different rates;

[0195] The serial communication module reads the processed spectral data from the FIFO and sends the data to the host computer through the serial communication circuit;

[0196] The spectral data received by the host computer can be displayed to the operator in real time and provide on-site data processing functions such as data visualization and preliminary analysis;

[0197] The operator can monitor the spectrum acquisition process in real time based on the data and analysis results displayed by the host computer, and send adjustment instructions through the serial communication interface as needed, such as changing the integration time, triggering re-acquisition, etc.

[0198] This method of on-site operation through a host computer and a serial communication interface provides an intuitive and flexible spectral acquisition control solution. It allows operators to interact directly with the system locally, quickly respond to on-site conditions, and achieve accurate spectral data acquisition and real-time processing, which is suitable for application scenarios that require fast on-site response and precise control.

[0199] A second aspect of the present application provides a Raman spectrum acquisition and transmission method, which can be applied to the above circuit, and the method includes:

[0200] The communication module receives data information from the remote data center and transmits it to ZYNQ;

[0201] ZYNQ processes the data information transmitted by the communication module and drives the spectrum acquisition module to collect data;

[0202] The spectrum acquisition module receives instructions from the ZYNQ and performs acquisition, and converts the acquired spectrum signal into a digital signal and transmits it to the ZYNQ;

[0203] The ZYNQ processes the digital signal from the spectrum acquisition module and passes it through the communication module.

[0204] It should be noted that the technical solutions in the various embodiments of the present application can be combined with each other, but the basis for the mutual combination is that it can be implemented by ordinary technicians in the field; when the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist, that is, it does not belong to the scope of protection of this application.

[0205] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A Raman spectrum collection and transmission circuit, characterized in that: include: Communication module, spectrum acquisition module, ZYNQ; Among them: The communication module is connected to the ZYNQ and is used to receive data information from a remote data center and transmit it to the ZYNQ, and to send data information from the ZYNQ to the remote data center; The ZYNQ is connected to the spectrum acquisition module, and is used to process the data information transmitted through the communication module, drive the spectrum acquisition module to collect data, and process the digital signal from the spectrum acquisition module and transmit it to the remote data center through the communication module; The spectrum acquisition module is connected to the ZYNQ, and is used to receive instructions from the ZYNQ and perform acquisition, and convert the acquired spectrum signal into a digital signal and transmit it to the ZYNQ.

2. The circuit according to claim 1, characterized in that The ZYNQ includes a PS and an FPGA, the PS includes an Ethernet module, an ARM, and a DDR control module, and the PS and the FPGA communicate with each other using an AXI interface; wherein: The Ethernet module is connected to the communication module and the ARM respectively, and is used to parse the data information from the remote data center and send the parsed data to the ARM, and is also used to send the data from the ARM to the remote data center through the communication module; The ARM is connected to the FPGA and the DDR control module, and is used to process the data parsed by the Ethernet module, and send the processed instructions to the FPGA through the AXI interface, and is also used to read the data in the DDR control module and encapsulate it, and send the encapsulated data to the Ethernet module; The FPGA is used to receive instructions from the ARM through the AXI interface to drive the spectrum acquisition module to perform acquisition work and spectrum signal conversion work, and can also write the acquisition information data into the DDR control module through the AXI interface in a DMA manner.

3. The circuit according to claim 2, characterized in that The FPGA includes an instruction parsing module, a CMOS driver module, an AD driver module, a RAM and an AXIDMA module; wherein: The instruction parsing module is connected to the ARM and the CMOS driving module, and is used to receive instructions from the ARM, parse the instructions, and transmit the parsing results to the CMOS driving module; The CMOS driving module is connected to the spectrum acquisition module, and when the instruction parsing result is an acquisition start signal, it is used to drive the spectrum acquisition module to perform acquisition, and when the instruction parsing result is an integration time signal, it is used to save the integration time to the register of the CMOS driving module; The AD driving module is connected to the spectrum acquisition module and the RAM, and is used to generate a driving signal to drive the spectrum acquisition module to perform analog-to-digital conversion, and write the converted data into the RAM; The RAM is connected to the AXIDMA module, and the AXIDMA module is connected to the PS via an AXI interface, and is used to write the digital signal stored in the RAM into the DDR control module in the PS via the AXI interface in a DMA manner.

4. The circuit according to claim 3, characterized in that The spectrum acquisition module includes CMOS, signal conditioning circuit and AD conversion circuit; wherein: The CMOS is connected to the CMOS driving module and the signal conditioning circuit, and is used to perform spectrum acquisition according to the driving signal of the CMOS driving module, and output the spectrum signal to the signal conditioning circuit after photoelectric signal conversion; The signal conditioning circuit is connected to the AD conversion circuit, and is used to filter and amplify the spectrum signal from the CMOS, and transmit it to the AD conversion circuit; The AD conversion circuit is connected to the AD driving module, and is used for converting the spectrum signal from the signal conditioning circuit from an analog signal to a digital signal after receiving the driving signal from the AD driving module, and sending the digital signal to the AD driving module.

5. The circuit according to claim 4, characterized in that The circuit further includes a GPS module, and the FPGA further includes a GPS control module, wherein: The GPS control module is connected to the AD driving module, the GPS module and the RAM respectively, and is used to receive the GPS acquisition start signal sent by the AD driving module, and control the GPS module to capture the signal from the global positioning system satellite, and read the GNSS protocol data in the GPS module, and extract the longitude and latitude and time information therefrom, and store them in the RAM.

6. The circuit according to claim 5, characterized in that The FPGA also includes a FIFO and a serial communication module; wherein: The FIFO is connected to the AD driver module and is used to write the converted digital signal into the FIFO for cross-clock domain processing; The serial communication module is connected to the host computer, the instruction parsing module and the FIFO, and is used to receive instruction information sent by the host computer and send it to the instruction parsing module for parsing, and is also used to read spectral data from the FIFO, send the data to the host computer through the serial communication circuit, and perform on-site display and processing of Raman spectra.

7. The circuit according to claim 6, characterized in that The circuit also includes an anti-backflow circuit and CH340; wherein: The CH340 is a USB to serial port chip, connected to the serial port communication module and the anti-backflow circuit, and is used to realize the conversion between the serial port communication protocol of the Raman acquisition transmission control circuit and the USB protocol of the host computer (computer); The anti-backflow circuit is connected to the host computer and is used to prevent the USB-to-serial port chip from being burned by the backflow current.

8. The circuit according to claim 2, characterized in that The circuit further comprises a DDR3, which is connected to the DDR control module and is used to store data information transmitted from the DDR control module for reading by the DDR control module; Preferably, the circuit further comprises an SD card circuit for storing programs and burning the programs into the circuit system when the circuit system is powered on.

9. The circuit according to claim 6, characterized in that The workflow of the FPGA control program is: S1, the program starts running; S2, the module outputs 3 signals, including the clock control signal scl, the write data signal sdata, and the write enable signal sload to complete the configuration of the analog-to-digital converter AD9826 in the AD conversion circuit; S3, determine whether there is a signal sent by the host computer, if not, repeat S3; if yes, proceed to the next step; S4, the instruction parsing module parses the data; S5, determine the instruction type. If it is an integration time signal, save the integration time to the register in the CMOS driver module, then return to S3 and proceed downward; if it is an acquisition start signal, proceed to the next step; S6, output CMOS chip drive clock, pull up CMOS chip acquisition control signal ST, and control the self-defined integral counter inside FPGA to start counting, and the program enters the integral state; S7, judging whether the integral time has been reached by the integral counter, if not, returning to S6 and proceeding downward; if yes, proceeding to the next step; S8, the program enters the transmission state, receives the synchronization signal Trig sent by CMOS, and customizes a Trig signal counter inside the FPGA to count the synchronization signal Trig; S9, determine whether the count of the custom Trig signal counter reaches 89, if not, return to S8 and proceed to the next step; if yes, proceed to the next step; S10, output two drive clocks cdsclk2 and adcclk to the analog-to-digital converter AD9826, driving the analog-to-digital converter AD9826 to start analog-to-digital conversion; S11, using a clock with the same frequency as one of the AD9826 driving clocks, adcclk, as a write clock, to write the signal from the analog-to-digital converter AD9826 into the FIFO and RAM; S12, determine whether the count of the custom synchronization signal Trig counter reaches 2136, if not, return to S10 and proceed to the next step; if yes, proceed to the next step; S13, using the GPS control module to read the GPS data and write it into the RAM. After the RAM is full, the GPS control module sends an interrupt signal; S14, using a clock with the same frequency as the transmission baud rate as a read clock, reading data from the FIFO, thereby completing cross-clock domain processing; S15, using the serial communication module to send the data read from the FIFO; S16, judging whether the FIFO is read from the FIFO and the FIFO is empty, if not, returning to S14 and proceeding downward; if yes, proceeding to the next step; S17, determine whether to stop, if not, save the integration time to the register in the CMOS driver module, then return to S3 and proceed downward; if yes, proceed to the next step; S18, the program ends; Preferably, the workflow of the control program on the PS side is: S1, program starts; S2, interrupt initialization, DMA initialization, interrupt service program initialization, LWIP protocol stack and TCP / IP protocol initialization; S3, perform three-way handshake with the server to establish a TCP connection; S4, waiting for the interrupt signal of the GPS module. If there is no interrupt signal of the GPS module, proceed to S4 again. If there is an interrupt signal of the GPS module, proceed to the next step; S5, start DMA data transmission; S6, waiting for the DMA completion interrupt signal, if there is no DMA completion interrupt signal, then proceed to S6 again, if there is a DMA completion interrupt signal, then proceed to the next step; S7, read the Raman spectrum raw data, time, and location information from the DDR and send it to the server via Ethernet; S8, determine whether the Ethernet transmission is completed, if not, proceed to S8 again; if yes, proceed to the next step; S9, determine whether to stop, if not, return to S4 and proceed to the next step; if yes, proceed to the next step; S10, wave four times to the server to disconnect the TCP connection; S11. The program ends.

10. A Raman spectrum collection and transmission method, characterized in that: The method is applied to the circuit according to any one of claims 1 to 9, and the method comprises: The communication module receives data information from the remote data center and transmits it to ZYNQ; ZYNQ processes the data information transmitted by the communication module and drives the spectrum acquisition module to collect data; The spectrum acquisition module receives instructions from the ZYNQ and performs acquisition, and converts the acquired spectrum signal into a digital signal and transmits it to the ZYNQ; The ZYNQ processes the digital signal from the spectrum acquisition module and sends the data to a remote data center through the communication module.

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