Manufacturing method of semiconductor device, semiconductor device and memory system

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor device, the semiconductor device and a memory system. The method comprises the following steps: forming an initial stack structure comprising dielectric layers and sacrificial layers which are alternately stacked; a plurality of first holes, at least one second hole and a plurality of third holes penetrating through the initial stacking structure are formed, the first holes and the second holes are arranged in a collinear mode in the first direction, the third holes are arranged in a collinear mode in the first direction, the first holes are located in the array area, and the third holes are located in the connecting area; the first direction is perpendicular to the stacking direction of the initial stacking structure; the initial stacking structure is etched through a plurality of first holes, at least one second hole and a plurality of third holes, so that the first holes are communicated with one another to form a first grid line gap structure, the third holes are communicated with one another to form a second grid line gap structure, and the initial stacking structure is reserved between the first grid line gap structure and the etched at least one second hole; and forming an isolation structure using the at least one second hole.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, and a memory system. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of planar memories to approach an upper limit.

[0003] To overcome the limitations of planar memory, the industry has developed a memory with a three-dimensional structure (e.g., 3D NAND memory) to increase storage density by arranging storage cells three-dimensionally on a substrate. Currently, how to optimize the gate line gap structure and its manufacturing method is one of the problems that need to be solved. Summary of the invention

[0004] The present application provides a method for manufacturing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] In the first aspect, the embodiment of the present application provides a method for manufacturing a semiconductor device. The manufacturing method includes: forming an initial stacking structure including alternating dielectric layers and sacrificial layers, the initial stacking structure having an array region and a connection region; forming a plurality of first holes, at least one second hole, and a plurality of third holes that penetrate the initial stacking structure, wherein the plurality of first holes and the at least one second hole are arranged in a collinear manner along a first direction, the plurality of third holes are arranged in a collinear manner along the first direction, the plurality of first holes are located in the array region, the plurality of third holes are located in the connection region, and the first direction is perpendicular to the stacking direction of the initial stacking structure; etching the initial stacking structure using the plurality of first holes, the at least one second hole, and the plurality of third holes, so that the plurality of first holes are connected to each other as a first gate line gap structure, the plurality of third holes are connected to each other as a second gate line gap structure, and the initial stacking structure is retained between the first gate line gap structure and the at least one second hole after etching; and forming an isolation structure using the at least one second hole.

[0006] In some embodiments, the manufacturing method further includes: using the first gate line gap structure to remove the sacrificial layer of the initial stacking structure located in the array region, and using the second gate line gap structure to remove a portion of the sacrificial layer of the initial stacking structure located in the connection region.

[0007] In some embodiments, forming an isolation structure using at least one second hole includes: using the at least one second hole after etching to replace a portion of the sacrificial layer exposed to the at least one second hole with a dielectric layer; and filling the at least one second hole with a dielectric material to form an isolation structure.

[0008] In some embodiments, the manufacturing method further includes: forming a gate layer in the gap formed after removing the sacrificial layer to form a stacked structure.

[0009] In some embodiments, first gate line gap structures adjacent to each other in the second direction form a storage block, the first gate line gap structure and the second gate line gap structure are arranged in a colinear manner, and the second direction is perpendicular to the first direction and the stacking direction.

[0010] In some embodiments, first gate line gap structures adjacent in the second direction form a storage block, the second gate line gap structure is located within the storage block, and in the second direction, the second gate line gap structure is spaced apart from the first gate line gap structure, and the second direction is perpendicular to the first direction and the stacking direction.

[0011] In some embodiments, an initial stacking structure is etched using multiple first holes, at least one second hole, and multiple third holes, so that the multiple first holes are connected to each other as a first gate line gap structure, and the multiple third holes are connected to each other as a second gate line gap structure, and retaining the initial stacking structure between the first gate line gap structure and at least one second hole after etching includes: retaining the initial stacking structure between the second gate line gap structure and at least one second hole after etching.

[0012] In some embodiments, a plurality of first holes are arranged at a first spacing distance, a plurality of third holes are arranged at a second spacing distance, the minimum spacing distance between the first hole and the second hole is greater than the first spacing distance and the second spacing distance, and the minimum spacing distance between the third hole and the second hole is greater than the first spacing distance and the second spacing distance.

[0013] In some embodiments, the manufacturing method also includes: forming a plurality of fourth holes in the array area that penetrate the initial stacking structure and are arranged in a colinear manner along a first direction, the plurality of fourth holes are located in the storage block, and in the second direction, the plurality of fourth holes are spaced apart from the first gate line gap structure; and etching the initial stacking structure using the plurality of fourth holes so that the plurality of fourth holes are connected to each other to form a third gate line gap structure.

[0014] In some embodiments, multiple fourth holes are divided into at least two groups; wherein, etching an initial stacking structure using multiple fourth holes so that the multiple fourth holes are connected to each other to form a third gate line gap structure includes: etching an initial stacking structure using multiple fourth holes so that each group of fourth holes are connected to each other to form a sub-gate line gap structure, and the initial stacking structure is retained between adjacent sub-gate line gap structures.

[0015] In some embodiments, the process further includes: forming a plurality of channel holes penetrating the initial stacking structure in the array region; wherein the plurality of channel holes, the plurality of first holes, at least one second hole, the plurality of third holes, and the plurality of fourth holes are formed in the same process.

[0016] In some embodiments, the connection area has a conductive area and an insulating area, the portion of the stacked structure located in the array area and the conductive area includes alternatingly stacked dielectric layers and gate layers, and the portion of the stacked structure located in the insulating area includes alternatingly stacked dielectric layers and sacrificial layers, and the manufacturing method further includes: forming a plurality of contact structures of different depths penetrating the stacked structure in the insulating area, wherein the contact structures are connected to the gate layer of the same layer.

[0017] In a second aspect, an embodiment of the present application provides a semiconductor device. The semiconductor device includes: a stacked structure having an array region and a connection region; a first gate line isolation structure that penetrates the stacked structure and extends in a first direction in the array region, the first direction being perpendicular to the stacking direction of the stacked structure; a second gate line isolation structure that penetrates the stacked structure and extends in the first direction in the connection region; and an isolation structure that penetrates the stacked structure and contacts the first gate line isolation structure; wherein the sidewalls of the first gate line isolation structure and the second gate line isolation structure are concave-convex structures.

[0018] In some embodiments, first gate line isolation structures adjacent to each other in the second direction form a storage block, the first gate line isolation structure and the second gate line isolation structure extend colinearly, and the second direction is perpendicular to the first direction and the stacking direction.

[0019] In some embodiments, the isolation structure contacts the second gate line isolation structure.

[0020] In some embodiments, first gate line isolation structures adjacent in the second direction form a storage block, the second gate line isolation structure is located within the storage block, and in the second direction, the second gate line isolation structure is spaced apart from the first gate line isolation structure, and the second direction is perpendicular to the first direction and the stacking direction.

[0021] In some embodiments, the semiconductor device also includes a third gate line isolation structure, which runs through the stacked structure, extends along a first direction in the array area, and is located in the storage block. In the second direction, the third gate line isolation structure is spaced apart from the first gate line isolation structure, and the sidewalls of the third gate line isolation structure are concave-convex structures.

[0022] In some embodiments, the third gate line isolation structure includes at least two sub-gate line isolation structures, the sub-gate line isolation structures extend along a first direction in the array region, and adjacent sub-gate line isolation structures are spaced apart from each other.

[0023] In some embodiments, the connection region has a conductive region and an insulating region, the stacked structure located in the array region and the conductive region includes alternating dielectric layers and gate layers, and the stacked structure located in the insulating region includes alternating dielectric layers and sacrificial layers.

[0024] In some embodiments, the semiconductor device further includes a plurality of contact structures, wherein the plurality of contact structures are located in the insulating region and respectively penetrate the stacked structure at different depths, and the contact structures are connected to a gate layer at the same layer.

[0025] In some embodiments, the semiconductor device further includes a plurality of channel structures penetrating the stacked structure in the array region.

[0026] In a third aspect, an embodiment of the present application provides a memory system, which includes: at least one three-dimensional memory, including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0027] According to at least one embodiment of the present application, the manufacturing method of the semiconductor device, the semiconductor device and the memory system provided by the present application use a plurality of first holes respectively formed in the array area and a plurality of third holes located in the connection area to form a first gate line gap structure and a second gate line gap structure, which can effectively solve the problem of tipping over, thereby improving the structural stability and yield. On the other hand, using at least one second hole co-linearly arranged with the plurality of first holes to form an isolation structure can provide etching isolation between the first gate line gap structure and the portion of the initial stacking structure located in the connection area, so as to meet the requirements of using the first gate line gap structure and the second gate line gap structure to perform different ranges of "gate replacement" in the array area and the connection area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0029] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0030] FIG. 2A to FIG. 7B is a schematic structural diagram of a semiconductor device during the manufacturing process according to the first embodiment of the present application;

[0031] Figures 8 to 10 is a schematic top view of a semiconductor device during the manufacturing process according to the second embodiment of the present application;

[0032] Figures 11 to 13 is a schematic top view of a semiconductor device during manufacturing according to a third embodiment of the present application;

[0033] Figures 14 to 16 is a schematic top view of a semiconductor device in a manufacturing process according to a fourth embodiment of the present application;

[0034] FIG. 17A to FIG. 21Bis a schematic structural diagram of a semiconductor device in a manufacturing process according to a fifth embodiment of the present application;

[0035] Fig. 22 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application; and

[0036] Fig.23A and Fig. 23B is a schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first hole discussed in this application may also be referred to as the second hole, and vice versa.

[0039] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0040] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0041] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0043] In addition, when "connect" or "couple" is used in the present application, it can indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0044] It should be noted that, in the following, the x-direction, y-direction, and z-direction in each figure show the spatial relationship of each component in the semiconductor device. For example, the z-direction is the stacking direction of the initial stacking structure (or stacking structure), and the x-direction and the y-direction are respectively the first direction and the second direction perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout this application to describe the spatial relationship of each component in the semiconductor device.

[0045] As the number of stacked layers of 3D NAND memory increases, the problem of gate line gap structure dumping becomes more serious, resulting in yield loss. On the other hand, since the range of "gate replacement" performed by using the gate line gap structure in the array area and the connection area of ​​the three-dimensional memory is different, optimizing the gate line gap structure and its manufacturing method has become one of the technical problems that technicians in this field focus on.

[0046] In view of this, an embodiment of the present application provides a method for manufacturing a semiconductor device. Figure 1 FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Figure 1 As shown, a method 1000 for manufacturing a semiconductor device (hereinafter referred to as manufacturing method 1000 ) includes steps S110 to S140 .

[0047] S110 , forming an initial stacking structure including alternately stacked dielectric layers and sacrificial layers, wherein the initial stacking structure has an array region and a connection region.

[0048] S120, forming a plurality of first holes, at least one second hole and a plurality of third holes penetrating the initial stacking structure, wherein the plurality of first holes and the at least one second hole are collinearly arranged along a first direction, the plurality of third holes are collinearly arranged along the first direction, the plurality of first holes are located in an array area, the plurality of third holes are located in a connection area, and the first direction is perpendicular to the stacking direction of the initial stacking structure.

[0049] S130, etching an initial stacking structure using a plurality of first holes, at least one second hole and a plurality of third holes, so that the plurality of first holes are connected to each other to form a first gate line gap structure, and the plurality of third holes are connected to each other to form a second gate line gap structure, and the initial stacking structure is retained between the first gate line gap structure and the at least one second hole after etching.

[0050] S140, forming an isolation structure using at least one second hole.

[0051] According to the manufacturing method of the semiconductor device provided by the embodiment of the present application, the first gate line gap structure and the second gate line gap structure are formed by using a plurality of first holes respectively formed in the array area and a plurality of third holes located in the connection area, which can effectively solve the problem of tipping over, thereby improving the structural stability and yield. On the other hand, the isolation structure is formed by using at least one second hole arranged in line with the plurality of first holes, which can provide etching isolation between the first gate line gap structure and the portion of the initial stacking structure located in the connection area, so as to meet the requirements of performing different ranges of "gate replacement" in the array area and the connection area using the first gate line gap structure and the second gate line gap structure respectively.

[0052] FIG. 2A to FIG. 7B 1 is a schematic diagram of the structure of the semiconductor device in the manufacturing process of the first embodiment of the present application. It should be noted that in order to clearly show the spatial relationship between the components in the semiconductor device, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A as well as Fig. 7A The dielectric layer 123 farthest from the substrate 121 is omitted from illustration. Hereinafter, the structure of the semiconductor device during the manufacturing process is referred to as an intermediate structure. For example, the semiconductor device may be a 3D NAND memory or a part of a 3D NAND memory.

[0053] Figure 2A It is a schematic top view of an intermediate structure after an initial stacking structure is formed and a plurality of first holes, a second hole, and a plurality of third holes are formed. Figure 2B It is along Figure 2A The schematic cross-sectional view is taken along line II'.

[0054] In step S110, Figure 2A and Figure 2BAs shown, the initial stacked structure 122 may be formed by a thin film deposition process of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof to form alternating stacked dielectric layers 123 and sacrificial layers 124. The dielectric layer 123 and the sacrificial layer 124 may extend laterally in a plane perpendicular to the z direction. For example, the dielectric layer 123 and the sacrificial layer 124 may extend laterally in the array area 101 and the connection area 102. The more stacked layers of the dielectric layer 123 and the sacrificial layer 124, the higher the integration of the memory cell, that is, the greater the unit storage density. For example, the materials of the dielectric layer 123 and the sacrificial layer 124 may be different from each other, so that the dielectric layer 123 and the sacrificial layer 124 have different etching selectivities relative to the same etchant. For example, the material of the dielectric layer 123 may be silicon oxide, and the material of the sacrificial layer 124 may be silicon nitride.

[0055] In some embodiments, the initial stacked structure 122 may be formed on one side of the substrate 121. For example, the material of the substrate 121 may include silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material. The substrate 121 may be used to support various components (e.g., the initial stacked structure 122) formed thereon.

[0056] In step S120, continue to refer to Figure 2A and Figure 2B , a plurality of first holes 131 (e.g., first holes 131_1 to 131_n), a second hole 132, and a plurality of third holes 133 (e.g., third holes 133_1 to 133_n) penetrating the initial stacking structure 122 may be formed by photolithography and etching (e.g., dry etching) processes. A plurality of first holes 131 are formed in the array region 101, and a plurality of third holes 133 are formed in the connection region 102. The plurality of first holes 131, the second holes 132, and the plurality of third holes 133 are arranged in a colinear manner along the x direction. For example, the plurality of first holes 131, the second holes 132, and the plurality of third holes 133 may be arranged in the above manner by patterning the mask.

[0057] In some embodiments, each of the plurality of first holes 131, the second hole 132, and each of the plurality of third holes 133 may have substantially the same shape and size. In some examples, on a plane perpendicular to the z direction, each of the plurality of first holes 131, the second hole 132, and each of the plurality of third holes 133 may be an ellipse with a minor axis parallel to the x direction. In other examples, on a plane perpendicular to the z direction, each of the plurality of first holes 131, the second hole 132, and each of the plurality of third holes 133 may be a perfect circle (not shown) or other appropriate shapes. For example, each of the plurality of first holes 131, the second hole 132, and each of the plurality of third holes 133 have the same size. It should be noted that the present application does not specifically limit the number of the plurality of first holes 131 and the number of the plurality of third holes 133. For example, the size and number of the plurality of first holes 131 and the plurality of third holes 133 may be determined according to the area size of the array area 101 and the connection area 102.

[0058] In some embodiments, the plurality of first holes 131 are arranged at a first spacing distance s1, the plurality of third holes 133 are arranged at a second spacing distance s2, the minimum spacing distance d1 between the first hole 131_1 and the second hole 132 is greater than the first spacing distance s1 and the second spacing distance s2, and the minimum spacing distance d2 between the third hole 133_1 and the second hole 132 is greater than the first spacing distance s1 and the second spacing distance s2. For example, the first spacing distance s1 and the second spacing distance s2 may be the same. For another example, the two minimum spacing distances d1 and d2 may be the same. The plurality of first holes 131, the second holes 132, and the plurality of third holes 133 have the above-mentioned non-uniform arrangement, which is helpful for the implementation of step S130 which will be described in detail below.

[0059] In some embodiments, the manufacturing method 1000 may further include the step of forming a plurality of channel holes 161 penetrating the initial stacking structure 122 in the array region 101. In the step of forming the plurality of channel holes 161, the plurality of channel holes 161 may be formed by photolithography and etching (e.g., dry etching) processes. For example, the plurality of channel holes 161, the plurality of first holes 131, the second holes 132, and the plurality of third holes 133 may be formed in the same photolithography and etching process by patterning the mask plate to improve manufacturing efficiency and save manufacturing costs. Optionally, in the process of forming the plurality of channel holes 161, the plurality of first holes 131, the second holes 132, and the plurality of third holes 133, a plurality of dummy channel holes 163 penetrating the initial stacking structure 122 may also be formed in the connection region 102. For example, the plurality of dummy channel holes 163 are formed on both sides of the plurality of third holes 133.

[0060] In some embodiments, a plurality of channel holes 161 may be used to form a plurality of channel structures 162 (see Figure 4A). For example, a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer (not shown) may be sequentially formed on the inner wall of the channel hole 161 by a thin film deposition process of PVD, CVD, ALD, or any combination thereof. For example, the materials of the charge blocking layer, the charge trapping layer, the tunneling layer, and the channel layer may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively. A plurality of channel structures 162 may be used to provide a memory cell array. Optionally, the dummy channel hole 163 may be filled with the same material as the channel hole 161, or filled with at least one insulating material, to form a dummy channel structure 164 (see Figure 4A ). For example, multiple dummy channel structures 164 may be used to provide mechanical support and / or load balancing.

[0061] Figure 3A It is a schematic top view of the intermediate structure after the first gate line gap structure and the second gate line gap structure are formed. Figure 3B It is along Figure 3A The schematic cross-sectional view is taken along line II'.

[0062] In step S130, if FIG. 2A to FIG. 3B As shown, the initial stacked structure 122 can be etched using a plurality of first holes 131, a second hole 132, and a plurality of third holes 133, so that the plurality of first holes 131 are connected to each other to form a first gate line slit structure 141, and the plurality of third holes 133 are connected to each other to form a second gate line slit structure 142, and the initial stacked structure 122 is retained between the first gate line slit structure 141 and the etched second hole 132, and between the second gate line slit structure 142 and the etched second hole 132. Both the first gate line slit structure 141 and the second gate line slit structure 142 can be grooves extending along the x-direction and have sidewalls with a concave-convex structure. It should be noted that the first gate line slit structure 141 and the second gate line slit structure 142 are in an unfilled state.

[0063] In some embodiments, a wet etching process can be used to allow the etchant to enter the multiple first holes 131, the second holes 132, and the multiple third holes 133, and to etch the initial stacked structure 122 (for example, the dielectric layer 123 and the sacrificial layer 124) of the peripheral portion of each of the multiple first holes 131, the second holes 132, and the multiple third holes 133. When the multiple first holes 131, the second holes 132 and the multiple third holes 133 have the non-uniform arrangement described above and have the same size, during the wet etching process, the size of each of the multiple first holes 131, the second holes 132 and the multiple third holes 133 is approximately uniformly expanded in the radial direction. When the radial size of each of the multiple first holes 131 is expanded to make the multiple first holes 131 connected to each other as the first gate line gap structure 141, and the radial size of each of the multiple third holes 133 is expanded to make the multiple third holes 133 connected to each other as the second gate line gap structure 142, since the two minimum spacing distances d1 and d2 are both greater than the first spacing distance s1 and the second spacing distance s2, the etched second hole 132 (or the second hole 132 after the radial size is expanded) will not be connected to the first gate line gap structure 141 and the second gate line gap structure 142, but the initial stacking structure 122 will be retained between the two. As an option, multiple first holes 133, second holes 132 and multiple third holes 133 are evenly arranged at equal intervals (not shown), and on a plane perpendicular to the z-direction, the size of the second hole 132 is smaller than the size of each of the multiple first holes 131 and each of the multiple third holes 133. During the wet etching process, since the radial size of the second hole 132 before etching is smaller than the radial size of each of the multiple first holes 131 and each of the multiple third holes 133, the etched second hole 132 (or the second hole 132 after the radial size is enlarged) will not be connected to the first gate line gap structure 141 and the second gate line gap structure 142, but the initial stacking structure 122 will be retained between the two.

[0064] In some related technologies, the first gate line gap structure and the second gate line gap may be long strip grooves extending continuously in the array area and the connection area along the x-direction. Compared with the related technology, in this embodiment, a plurality of first holes 131 and a plurality of third holes 133 are used to form the first gate line gap structure 141 and the second gate line gap structure 142, which can address the problem of excessive groove depth and easy collapse due to an increase in the number of stacked layers, thereby improving structural stability and yield.

[0065] Figure 4A It is a schematic top view of the intermediate structure after the sacrificial material is filled in the first gate line gap structure and the second gate line gap structure. Figure 5A It is a schematic cross-sectional view of the intermediate structure after the isolation structure is formed. Figure 4B and Figure 5B Along the Figure 4A and Figure 5A The schematic cross-sectional view is taken along line II'.

[0066] In step S140, if Figure 5A and Figure 5B As shown, the second hole 132 after etching can be used (see Figure 3A ) to form an isolation structure 151. The isolation structure 151 can be used to provide etching isolation between the first gate line gap structure 141 and the second gate line gap structure 142 located in the array area 102, thereby providing etching isolation between the initial stacked structure 122 and the portion located in the array area 102. For example, the material of the isolation structure 151 and the material of the dielectric layer 123 can be the same (for example, silicon oxide). The isolation structure 151 does not have a clear interface with the dielectric layer 123.

[0067] In some embodiments, the isolation structure 151 can be formed by the following method. First, Figure 4A and Figure 4B As shown, a sacrificial material 171 may be filled in the first gate line gap structure 141 and the second gate line gap structure 142. The sacrificial material 171 may be different from the material of the dielectric layer 123 and the sacrificial layer 124. For example, the sacrificial material 171 may include but is not limited to polysilicon or carbon. Then, as shown in FIG. Figure 5A and Figure 5B As shown, the second hole 132 (refer to Figure 4B ), the sacrificial layer 124 (reference Figure 4B ), and a dielectric layer 152 is formed in the gap formed by removing the portion of the sacrificial layer 124, and a dielectric material 153 is filled in the second hole 132, thereby forming an isolation structure 151. Exemplarily, the material of the dielectric layer 152 may be the same as the dielectric material 153 (for example, silicon oxide). The dielectric layer 152 and the dielectric material may be formed in the same thin film deposition process. When the first gate line gap structure 141 and the second gate line gap structure 142 are filled with the sacrificial material 171, the removal of the portion of the sacrificial layer 124 exposed to the second hole 132 may stop at the sacrificial material 171, which is beneficial to control the morphology of the isolation structure 151. It should be noted that Figure 5A The shape of the isolation structure 151 shown is only an example, and the present application does not specifically limit the shape of the isolation structure 151 on a plane perpendicular to the z-direction.

[0068] In some embodiments, the manufacturing method 1000 may further include a step of forming a gate layer. Fig. 6A and Figure 6B It is a schematic top view of the intermediate structure after the gate layer is formed. Figure 6B It is along Fig. 6AThe schematic cross-sectional view is taken along line II'.

[0069] In the step of forming the gate layer, first, as Figure 5A and Figure 5B As shown, an etching (e.g., wet etching) process may be used to remove the sacrificial material 171 filled in the first gate line gap structure 141, so that the first gate line gap structure 141 is in an unfilled state, and the sacrificial material 171 filled in the second gate line gap structure 142 is retained. Then, a wet etching process may be used, and the sacrificial layer 124 of the initial stacked structure 122 located in the array area 101 may be removed by using the first gate line gap structure 141. The isolation structure 151 may block the etching agent from etching the sacrificial layer 124 of the initial stacked structure 122 located in the connection area 102. Then, an etching (e.g., wet etching) process may be used to remove the sacrificial material 171 filled in the second gate line gap structure 142, so that the second gate line gap structure 142 is in an unfilled state. Then, a wet etching process may be used, and a portion of the sacrificial layer 124 of the initial stacked structure 122 located in the connection area 102 may be removed by using the second gate line gap structure 142. For example, compared with the sacrificial layer 124 removed from the array region 101 , the sacrificial layer 124 removed from the connection region 102 has a smaller size in the y direction.

[0070] Furthermore, if Fig. 6A and Figure 6B As shown, a thin film deposition process such as PVD, CVD, ALD or any combination thereof can be used to form a gate layer 125 in the gap formed by the sacrificial layer 124 removed from the array region 101 and the connection region 102. The material of the gate layer 125 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide or any other suitable conductive material. Optionally, a gate barrier layer, an adhesive layer and a metal layer (not shown) can be sequentially formed in the gap formed by the sacrificial layer 124 removed from the array region 101 and the connection region 102. Thus, the initial stacked structure 122 (refer to Figure 5A ) is transformed into a stacked structure 126. In the stacked structure 126, the gate layer 125 may extend laterally in the array region 101 and a portion of the connection region 102 (i.e., the conductive region 103), and the sacrificial layer 124 may extend laterally in another portion of the connection region 102 (i.e., the two insulating regions 104). As described above, the process of replacing the sacrificial layer 124 in the initial stacked structure 122 with the gate layer 125 may be referred to as "gate replacement".

[0071] Further, continue to refer to Fig. 6A and Figure 6B, an insulating material may be filled in the first gate line gap structure 141 and the second gate line gap structure 142 by a thin film deposition process using PVD, CVD, ALD or any combination thereof to form a first gate line isolation structure 143 and a second gate line isolation structure 143. Exemplarily, the insulating material may include silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material. Optionally, an insulating material and polysilicon may be sequentially formed in the first gate line gap structure 141 and the second gate line gap structure 142 to balance stress and save manufacturing costs.

[0072] It should be noted that although the above describes in detail the manufacturing method of first removing the sacrificial material 171 in the first gate line gap structure 141 and then removing the sacrificial material 171 in the second gate line gap structure 142, the present application does not specifically limit the order of removing the sacrificial material 171 from the first gate line gap structure 141 and the second gate line gap structure 142.

[0073] In some embodiments, the manufacturing method 1000 may further include a step of forming a plurality of contact structures. Fig. 7A and Figure 7B is a schematic top view of a semiconductor device after a plurality of contact structures are formed. Figure 7B It is along Fig. 7A A schematic cross-sectional view taken along line II-II' is shown.

[0074] In the step of forming a plurality of contact structures, such as Fig. 7A and Figure 7B As shown, a plurality of contact holes penetrating the stacked structure 126 at different depths can be formed in the insulating region 104 by using photolithography and etching (e.g., dry etching) processes. For example, the bottom of the contact hole can stop at its corresponding sacrificial layer 124. Optionally, a protective layer (not shown) can be formed on the sidewall of the contact hole. The contact hole is then used to remove a portion of the sacrificial layer 124 exposed at the bottom until the gate layer 125 of the same layer is exposed, and an epitaxial gap is formed. Optionally, the protective layer can prevent the sacrificial layer 124 adjacent to the sidewall of the contact hole from being removed. A first conductive portion 182 is then formed in the epitaxial gap, and a second conductive portion 183 is formed in the contact hole. The first conductive portion 182 and the second conductive portion 183 can be used to form a contact structure 181. The contact structure 181 can be connected (e.g., physically and electrically connected) to the gate layer 125 of the same layer.

[0075] In the first embodiment, the isolation structure can provide etching isolation between the first gate line gap structure and the initial stacking structure located in the connection area to meet the requirements of performing different ranges of "gate replacement" in the array area and the connection area using the first gate line gap structure and the second gate line gap structure respectively.

[0076] Figures 8 to 101 is a schematic top view of a semiconductor device in the manufacturing process according to the second embodiment of the present application. For the purpose of simplicity, the same contents as the first embodiment will not be repeated in the following embodiments.

[0077] Figure 8 is a schematic top view of the intermediate structure after forming a plurality of first holes, a second hole, a plurality of third holes, and a plurality of fourth holes. In step S120, as Figure 8 As shown, a plurality of first holes 231 (e.g., first holes 231_1 to 231_n), a second hole 232, and a plurality of third holes 233 (e.g., third holes 233_1 to 233_n) penetrating the initial stacked structure 222 may be formed by photolithography and etching (e.g., dry etching) processes. The plurality of first holes 231, the second hole 232, and the plurality of third holes 233 are arranged in a colinear manner along the x direction.

[0078] In some embodiments, the manufacturing method 1000 may further include the step of forming a plurality of fourth holes 234 (e.g., fourth holes 234_1 to 234_n) penetrating the initial stacked structure 222. The plurality of fourth holes 234 are arranged in a colinear manner along the x-direction in the array region 201. For example, the plurality of fourth holes 234 adjacent to each other may have substantially the same spacing distance in the x-direction. For example, by patterning the mask, the plurality of fourth holes 234, the plurality of first holes 231, the second hole 232, and the plurality of third holes 233 are formed in the same photolithography and etching process to improve manufacturing efficiency and save manufacturing costs.

[0079] Fig. 9 is a schematic top view of the intermediate structure after forming the first gate line gap structure, the second gate line gap structure and the third gate line gap structure. Figure 8 and Fig. 9 As shown, a wet etching process can be used, and the initial stacked structure 222 can be etched using a plurality of first holes 231, a second hole 232, and a plurality of third holes 233, so that the plurality of first holes 231 are connected to each other to form a first gate line gap structure 241, and the plurality of third holes 233 are connected to each other to form a second gate line gap structure 242, and the initial stacked structure 222 is retained between the first gate line gap structure 241 and the etched second hole 232, and between the second gate line gap structure 242 and the etched second hole 232. Two first gate line gap structures 241 adjacent in the y direction can form a storage block 205. For example, the storage block 205 can be the minimum erasable unit of the three-dimensional memory.

[0080] In some embodiments, during the wet etching process of forming the first gate line slit structure 241 and the second gate line slit structure 242, the initial stacking structure can be etched using the plurality of fourth holes 234 so that the plurality of fourth holes 234 are connected to each other to form a third gate line slit structure 245. For example, the third gate line slit structure 245 can be a groove extending along the x direction and having a sidewall with a concave-convex structure. The third gate line slit structure 245 is located in the storage block 205 and is used to provide mechanical support for the storage block 205. For example, the third gate line slit structure 245 can divide the storage block 206 into two finger storage areas 206. It should be noted that, depending on the number of the third gate line slit structures 245, the storage block 206 can be divided into a greater number of finger storage areas, which is not specifically limited in the present application.

[0081] In some embodiments, during the wet etching process, the etchant enters the plurality of fourth holes 234 and etches the initial stacked structure 222 at the peripheral portion of each of the plurality of fourth holes 234, so that the size of each of the plurality of fourth holes 234 is substantially uniformly enlarged in the radial direction until they are connected to each other to form a third gate line gap structure 245. The use of the plurality of fourth holes 245 to form the third gate line gap structure 245 can address the problem of excessive groove depth and easy collapse due to an increase in the number of stacked layers, thereby improving structural stability and yield.

[0082] Fig.10 is a schematic top view of the intermediate structure after forming the isolation structure, the gate layer, the first gate line isolation structure, the second gate line isolation structure and the third gate line isolation structure. Fig. 9 and Fig.10 As shown, the isolation structure 251 can be formed by using the etched second hole 232. In some embodiments, in the steps of forming the gate layer 225, the first gate line isolation structure 243, the second gate line isolation structure 244 and the third gate line isolation structure 246, the first gate line gap structure 241 and / or the third gate line gap structure 245 can be used to remove the sacrificial layer 224 of the initial stacking structure 222 located in the array area 101, and the second gate line gap structure 242 can be used to remove the sacrificial layer 224 of the initial stacking structure 222 located in the two conductive areas 204 in the connection area 102. Then, the gate layer 225 is formed in the gap formed after removing the sacrificial layer 224, so that the initial stacking structure 222 is converted into a stacking structure 226. Exemplarily, the third gate line isolation structure 246 can be formed in the process of forming the first gate line isolation structure 243 and the second gate line isolation structure 244, for example, by using the same thin film deposition process.

[0083] In the second embodiment, the isolation structure can not only provide etching isolation between the first gate line gap structure and the initial stacking structure located in the connection area, but also form an insulating boundary of the storage block together with the first gate line isolation structure and the second gate line isolation structure.

[0084] Figures 11 to 13 It is a schematic top view of a semiconductor device during the manufacturing process according to the third embodiment of the present application.

[0085] Fig.11 is a schematic top view of the intermediate structure after forming a plurality of first holes, two second holes, a plurality of third holes, and a plurality of fourth holes. In step S120, as Fig.11 As shown, unlike the second embodiment, the number of second holes arranged in a colinear manner with the plurality of first holes 331 and the plurality of third holes 333 is two, that is, the second holes 332_1 and 332_2. In some embodiments, the plurality of first holes 331 are arranged at intervals of a first spacing distance s1, the plurality of third holes 333 are arranged at intervals of a second spacing distance s2, the minimum spacing distance d1 between the first hole 331_1 and the second hole 332_1 is greater than the first spacing distance s1 and the second spacing distance s2, and the minimum spacing distance d2 between the third hole 333_1 and the second hole 332_2 is greater than the first spacing distance s1 and the second spacing distance s2. The two second holes 332_1 and 332_2 have a third spacing distance s3 in the x direction. For example, the first spacing distance s1, the second spacing distance s2, and the third spacing distance s3 may be the same. For another example, the two minimum spacing distances d1 and d2 may be the same.

[0086] Fig.12 is a schematic top view of the intermediate structure after forming the first gate line gap structure, the second gate line gap structure and the third gate line gap structure. Fig.11 and Fig.12 As shown, different from the second embodiment, in the process of etching the initial stacking structure 322 using a plurality of first holes 331, second holes 332_1 and 332_2 and a plurality of third holes 333, the plurality of first holes 331 are connected to each other to form a first gate line gap structure 341, the plurality of third holes 333 are connected to each other to form a second gate line gap structure 342, and the initial stacking structure 322 is retained between the first gate line gap structure 341 and the etched second hole (i.e., opening 332a) and between the second gate line gap structure 342 and the opening 332a, the two second holes 332_1 and 332_2 can be connected to each other to form an opening 332a after etching. As another option, the two second holes (not shown) after etching can retain the initial stacking structure 322 in the x direction. In other words, the size of the two second holes after etching is enlarged in the radial direction, but will not be connected to each other.

[0087] Fig.13is a schematic top view of the intermediate structure after forming the isolation structure, the gate layer, the first gate line isolation structure, the second gate line isolation structure and the third gate line isolation structure. Fig.12 and Fig.13 As shown, in the case where the two second holes 332_1 and 332_2 after etching are openings 332a that are connected to each other, the openings 332a can be used to form an isolation structure 351. For example, a portion of the sacrificial layer 324 exposed to the opening 332a is replaced with a dielectric layer (not shown), and a dielectric material (not shown) is filled in the opening 332a. The dielectric layer and the dielectric material can together constitute the isolation structure 351. As another option, in the case where the two second holes 332_1 and 332_2 after etching are not connected to each other, the two second holes with radially enlarged dimensions after etching can be used to form an isolation structure. For example, a portion of the sacrificial layer exposed to the two second holes is replaced with a dielectric layer, and a dielectric material is filled in the two second holes to form an isolation structure. For example, the replaced dielectric layer can extend laterally continuously, so that the isolation structure can be an integrated structure.

[0088] In some embodiments, the gate layer 325 , the first gate line isolation structure 343 , the second gate line isolation structure 344 , and the third gate line isolation structure 346 may be formed by the method described above.

[0089] It should be noted that the number of the second holes is not limited to the two described in the third embodiment, and the second holes may have a larger number, which is not specifically limited in the present application. For example, at least one second hole and a plurality of first holes and a plurality of third holes may be formed in the same photolithography and etching process by patterning the mask.

[0090] In the third embodiment, the number of the second holes can be adjusted according to actual design requirements, which is beneficial to increase the flexibility of patterning design.

[0091] Figures 14 to 16 It is a schematic top view of a semiconductor device during the manufacturing process according to the fourth embodiment of the present application.

[0092] Fig.14 is a schematic top view of the intermediate structure after forming a plurality of first holes, a second hole, a plurality of third holes, and a plurality of fourth holes. In step S120, as Fig.14 As shown, different from the second embodiment, the plurality of fourth holes 434 are divided into three groups, namely the first group 4341, the second group 4342 and the third group 4343. For example, in the x direction, the minimum spacing distance d3 between adjacent groups is greater than the fourth spacing distance s4 between adjacent fourth holes in the group.

[0093] Fig.15is a schematic top view of an intermediate structure after forming a plurality of first gate line gap structures, a second gate line gap structure, and a plurality of sub-gate line gap structures. Fig.14 and Fig.15 As shown, different from the second embodiment, in the process of etching the initial stacked structure 422 using the plurality of fourth holes 434 divided into three groups, the fourth holes corresponding to each other in the first group 4341, the second group 4342 and the third group 4343 can be connected to each other to form three sub-grid line gap structures 4451, 4452 and 4453. The initial stacked structure 422 is retained between adjacent sub-grid line gap structures (for example, sub-grid line gap structures 4451 and 4452, and sub-grid line gap structures 4452 and 4453).

[0094] Fig.16 is a schematic top view of the intermediate structure after forming the isolation structure, the gate layer, the first gate line isolation structure, the second gate line isolation structure and a plurality of sub-gate line isolation structures. Fig.15 and Fig.16 As shown, during the process of forming the first gate line isolation structure 443 and the second gate line isolation structure 444, for example, the same thin film deposition process can be used to form the three sub-gate line isolation structures 4461, 4462, and 4463. In some embodiments, the isolation structure 451, the gate layer 425, the first gate line isolation structure 443, and the second gate line isolation structure 444 can be formed using the method described above.

[0095] It should be noted that the number of groups into which the plurality of fourth holes are divided and the number of fourth holes in each group are not specifically limited in the present application.

[0096] In the fourth embodiment, a plurality of sub-gate line gap structures are formed by grouping a plurality of fourth holes, and then a third gate line gap structure for dividing the finger storage area is formed, which can further address the dumping problem and help to further improve the structural stability and yield.

[0097] FIG. 17A to FIG. 21B FIG. 1 is a schematic diagram of the structure of a semiconductor device in the manufacturing process according to the fifth embodiment of the present application. It should be noted that in order to clearly show the spatial relationship between the components in the semiconductor device, Fig.17A , Fig.18A , Fig.19A , Fig. 20A as well as Fig.21A The dielectric layer 523 farthest from the substrate 521 is omitted from illustration.

[0098] Fig.17A It is a schematic top view of an intermediate structure after an initial stacking structure is formed and a plurality of first holes, two second holes, and a plurality of third holes are formed. Fig. 17B It is along Fig.17AThe schematic cross-sectional view taken along line III-III' is shown. In step S120, as Fig.17A and Fig. 17B As shown, a plurality of first holes 531 (e.g., first holes 531_1 to 531_n), two second holes 532_1 and 532_2, and a plurality of third holes 533 (e.g., third holes 533_1 to 533_n) penetrating the initial stacking structure 522 may be formed by photolithography and etching (e.g., dry etching) processes. The plurality of first holes 531 are formed in the array region 501, and the plurality of third holes 533 are formed in the connection region 502. The plurality of first holes 531, the two second holes 532_1 and 532_2, and the plurality of third holes 533 are sequentially arranged along the x direction. The plurality of first holes 531 and the two second holes 532_1 and 532_2 are arranged in a collinear manner, and the plurality of third holes 553 are arranged non-collinearly with the plurality of first holes 531 and the two second holes 532_1 and 532_2. For example, multiple first holes 531 and two second holes 532_1 and 532_2 are collinearly arranged along a first virtual straight line parallel to the x direction, and multiple third holes 533 are collinearly arranged along a second virtual straight line parallel to the x direction, and the first virtual straight line and the second virtual straight line are spaced apart in the y direction.

[0099] In some embodiments, the plurality of first holes 531 are arranged at a first spacing distance s1, the plurality of third holes 533 are arranged at a second spacing distance s2, and the minimum spacing distance d1 between the first hole 531_1 and the second hole 532_1 is greater than the first spacing distance s1. For example, the first spacing distance s1 and the second spacing distance s2 may be the same.

[0100] In some embodiments, the plurality of fourth holes 534 (eg, fourth holes 534_1 ˜ 534_n) penetrating the initial stack structure 522 may be formed in the same photolithography and etching process as the plurality of first holes 531 , the two second holes 532_1 and 532_2 , and the plurality of third holes 533 .

[0101] Fig.18A It is a schematic top view of the intermediate structure after the first gate line gap structure and the second gate line gap structure are formed. Fig.18B It is along Fig.18A The schematic cross-sectional view taken along line III-III' is shown. In step S130, as FIG. 17A to FIG. 18BAs shown, the initial stacking structure 522 can be etched using a plurality of first holes 531, two second holes 532_1 and 532_2, and a plurality of third holes 533, so that the plurality of first holes 531 are connected to each other to form a first gate line gap structure 541, the plurality of third holes 533 are connected to each other to form a second gate line gap structure 542, and the initial stacking structure 522 is retained between the first gate line gap structure 541 and the etched second hole (i.e., the opening 532a). Two first gate line gap structures 541 adjacent to each other in the y direction can form a storage block 505. The second gate line gap structure 542 can be located in the storage block 505.

[0102] In some embodiments, during the wet etching process of forming the first gate line gap structure 541 and the second gate line gap structure 542 , the initial stacking structure 522 may be etched using the plurality of fourth holes 534 so that the plurality of fourth holes 534 are interconnected to form a third gate line gap structure 545 .

[0103] Fig.19A It is a schematic top view of the intermediate structure after the sacrificial material is filled in the first gate line gap structure and the second gate line gap structure. Fig. 20A It is a schematic cross-sectional view of the intermediate structure after the isolation structure is formed. Fig.19B and Fig. 20B Along the Fig.19A and Fig. 20A The schematic cross-sectional view taken along line III-III' is shown. In step S140, as Fig. 20A and Fig. 20B As shown, the opening 532a can be used to form an isolation structure 551. The isolation structure 551 is located at the end of the first gate line gap structure 541 close to the connection region 502. For example, the isolation structure 551 spans the array region 501 and the connection region 502.

[0104] In some embodiments, the isolation structure 551 can be formed by the method described below. First, as Fig.19A and Fig.19B As shown, a sacrificial material 571 may be filled in the first gate line gap structure 541 and the second gate line gap structure 542. Then, as shown in FIG. Fig. 20A and Fig. 20B As shown, a portion of the sacrificial layer 524 exposed to the opening 532 a may be removed, a dielectric layer 552 may be formed in a gap formed by removing the portion of the sacrificial layer 524 , and a dielectric material 553 may be filled in the opening 532 a , thereby forming an isolation structure 551 .

[0105] In some embodiments, the manufacturing method 1000 may further include a step of forming a gate layer. Fig.21A and Fig. 21B It is a schematic top view of the intermediate structure after the gate layer is formed. Fig. 21B It is along Fig.21A A schematic cross-sectional view taken along line III-III' is shown.

[0106] like FIG. 20A to FIG. 21B As shown, first, a wet etching process may be used to remove the sacrificial material 571 filled in the first gate line gap structure 541, so that the first gate line gap structure 541 is in an unfilled state, and the sacrificial material 571 in the second gate line gap structure 542 is retained. Then, a wet etching process may be used, and the sacrificial layer 524 of the initial stacking structure 522 located in the array area 501 may be removed by using the first gate line gap structure 541. The isolation structure 551 can block the etching agent from etching the portion of the initial stacking structure 522 located in the array area 502. Then, an etching (e.g., wet etching) process may be used to remove the sacrificial material 571 filled in the second gate line gap structure 542, so that the second gate line gap structure 542 is in an unfilled state. Then, a wet etching process may be used, and a portion of the sacrificial layer 524 of the initial stacking structure 522 located in the connection area 502 may be removed by using the second gate line gap structure 542. For example, compared with the sacrificial layer 524 removed from the array region 501 , the sacrificial layer 524 removed from the connection region 502 has a smaller size in the y direction.

[0107] Furthermore, a thin film deposition process such as PVD, CVD, ALD or any combination thereof may be used to form a gate layer 525 in the gap formed by the sacrificial layer 524 removed from the array region 501 and the connection region 502. Fig. 20B ) is transformed into a stacked structure 526. In the stacked structure 526, the gate layer 525 may extend laterally in the array region 501 and a portion of the connection region 502 (i.e., the conductive region 503), and the sacrificial layer 524 may extend laterally in another portion of the connection region 502 (i.e., the two insulating regions 504).

[0108] In some embodiments, the first gate line isolation structure 543 , the second gate line isolation structure 544 , and the third gate line isolation structure 546 may be formed by a same thin film deposition process.

[0109] In the fifth embodiment, the isolation structure can not only provide etching isolation between the first gate line gap structure and the initial stack structure located in the connection region, but also form an insulating boundary of the memory block together with the first gate line isolation structure.

[0110] The present application also provides a semiconductor device. For example, the semiconductor device may be a 3D NAND memory or a part of a 3D NAND memory, such as Fig. 7A and Figure 7B As shown, the semiconductor device 100 includes a stacked structure 126 , a first gate line isolation structure 143 , a second gate line isolation structure 144 and an isolation structure 151 .

[0111] The stacked structure 126 has an array region 101 and a connection region 102. For example, on a plane perpendicular to the z direction, the stacked structure 126 is divided into an array region 101 and a connection region 102 along the x direction. The first gate line isolation structure 143 runs through the stacked structure 126 and extends along the x direction in the array region 101. The second gate line isolation structure 144 runs through the stacked structure 126 and extends along the x direction in the connection region 102. For example, the first gate line isolation structure 143 and the second gate line isolation structure 144 may extend along the x direction. The sidewalls of the first gate line isolation structure 143 and the second gate line isolation structure 144 are concave-convex structures. The isolation structure 151 runs through the stacked structure 126 and contacts the first gate line isolation structure 143. For example, on a plane perpendicular to the z direction, the isolation structure 151 is located in the extension direction (i.e., the x direction) of the first gate line isolation structure 143.

[0112] In this embodiment, the first gate line isolation structure and the second gate line isolation structure with concave-convex sidewalls are conducive to improving structural stability, reducing the risk of tipping, and improving yield. The isolation structure is in contact with the first gate line isolation structure, which can ensure that the gate layer in the stacked structure has different extension ranges in the array area and the connection area.

[0113] In some embodiments, Fig. 7A and Figure 7B As shown, the connection area 102 has a conductive area 103 and an insulating area 104. For example, in the connection area 102, the two sides of the second gate line isolation structure 144 are conductive areas 103. The two regions of the conductive area 103 away from the second gate line isolation structure 144 are insulating areas 104. The portion of the stacked structure 126 located in the array area 101 and the conductive area 103 includes alternately stacked dielectric layers 123 and gate layers 125. The portion of the stacked structure 126 located in the insulating area 104 includes alternately stacked dielectric layers 123 and sacrificial layers 124.

[0114] In some embodiments, Fig. 7A and Figure 7B As shown, the semiconductor device 100 may further include a plurality of contact structures 181. The plurality of contact structures 181 are located in the insulating region 104 and respectively penetrate the stacked structure 126 at different depths. The contact structure 181 is connected (e.g., physically and electrically connected) to the gate layer 125 of the same layer. For example, the contact structure 181 may include a first conductive portion 182 and a second conductive portion 183. The first conductive portion 182 is disposed in the same layer as a sacrificial layer 124 in the stacked structure 126, and extends laterally in a plane perpendicular to the z-direction to contact the gate layer 125 of the same layer as the sacrificial layer 124. The second conductive portion 183 extends longitudinally along the z-direction to contact the first conductive portion 182.

[0115] In some embodiments, Fig. 7A and Figure 7B As shown, the semiconductor device 100 may further include a plurality of channel structures 162 penetrating the stacked structure 126 in the array region 101. For example, the channel structure 162 may include a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer (not shown) arranged sequentially from the outside to the inside. Optionally, the semiconductor device 100 may further include a plurality of dummy channel structures 164 penetrating the stacked structure 126 in the connection region 102. For example, the dummy channel structure 164 is located in the conductive region 103 on both sides of the second gate line isolation structure 144.

[0116] In some embodiments, Fig.10 As shown, the first gate line isolation structures 243 adjacent in the y direction form a storage block 205. For example, the storage block 205 may include an array area 201 and a connection area 202 arranged in the x direction. The first gate line isolation structure 243 and the second gate line isolation structure 244 extend in the same line. In this case, the isolation structure 251 contacts the second gate line isolation structure 244. The isolation structure 251, the first gate line isolation structure 243, and the second gate line isolation structure 244 together constitute the insulation boundary of the storage block 205.

[0117] In some embodiments, Fig.10 As shown, the semiconductor device may further include a third gate line isolation structure 246. The third gate line isolation structure 246 penetrates the stacked structure 226 and extends in the array area 201 along the x direction. In the y direction, the third gate line isolation structure 246 and the first gate line isolation structure 243 have a spacing distance. The third gate line isolation structure 246 can be used to divide the storage block 205 into two finger storage areas 206. The sidewall of the third gate line isolation structure 246 can be a concave-convex structure, which is conducive to improving the structural stability, reducing the risk of tipping, and improving the yield.

[0118] In some embodiments, Fig.16 As shown, the third gate line isolation structure 446 may include at least two (e.g., three) sub-gate line isolation structures 4461-4463. Each sub-gate line isolation structure 4461-4463 extends along the x-direction in the array region 401, and adjacent sub-gate line isolation structures (e.g., sub-gate line isolation structures 4461 and 4462, and sub-gate line isolation structures 4462 and 4463) have a spacing distance between them, which is beneficial to further improve the structural stability.

[0119] In some embodiments, Fig.21A and Fig. 21BAs shown, the first gate isolation structure 543 adjacent in the y direction forms a storage block 505. For example, the storage block 505 may include an array area 501 and a connection area 502 arranged in the x direction. The first gate isolation structure 543 and the second gate isolation structure 544 extend non-collinearly. The second gate isolation structure 544 is located in the storage block 505, and in the y direction, the second gate isolation structure 544 and the first gate isolation structure 543 have a spacing distance. In this case, the isolation structure 551 does not contact the second gate isolation structure 544. The isolation structure 551 and the first gate isolation structure 543 together constitute the insulating boundary of the storage block 505.

[0120] Since the contents and structures involved in the above description of the preparation method 1000 may be fully or partially applicable to the semiconductor device described herein, the contents related or similar thereto will not be described in detail.

[0121] Some embodiments of the present application also provide a memory system. Fig. 22 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application.

[0122] like Fig. 22 As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Fig. 22 As shown, the system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0123] The three-dimensional memory 14 may include a semiconductor device described in any embodiment of the present application, for example, Fig. 7A and Figure 7BThe semiconductor device 100 is shown. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate functions may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0124] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.23AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig. 22 The host 18 in the memory card connector 24 is coupled. Fig. 23B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig. 22 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0125] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming an initial stacking structure including alternately stacked dielectric layers and sacrificial layers, wherein the initial stacking structure has an array region and a connection region; forming a plurality of first holes, at least one second hole, and a plurality of third holes penetrating the initial stacking structure, wherein the plurality of first holes and the at least one second hole are collinearly arranged along a first direction, the plurality of third holes are collinearly arranged along the first direction, the plurality of first holes are located in the array region, the plurality of third holes are located in the connection region, and the first direction is perpendicular to the stacking direction of the initial stacking structure; Etching the initial stacked structure using the plurality of first holes, the at least one second hole, and the plurality of third holes so that the plurality of first holes are connected to each other to form a first gate line slit structure, the plurality of third holes are connected to each other to form a second gate line slit structure, and the initial stacked structure is retained between the first gate line slit structure and the at least one second hole after etching; and An isolation structure is formed using the at least one second hole.

2. The manufacturing method according to claim 1, wherein: Also includes: The sacrificial layer of the initial stacked structure located in the array region is removed by using the first gate line gap structure, and a portion of the sacrificial layer of the initial stacked structure located in the connection region is removed by using the second gate line gap structure.

3. The manufacturing method according to claim 1, wherein: Forming an isolation structure using the at least one second hole comprises: Using the at least one second hole after etching, replacing a portion of the sacrificial layer exposed to the at least one second hole with a dielectric layer; and A dielectric material is filled in the at least one second hole to form the isolation structure.

4. The manufacturing method according to claim 2, wherein: Also includes: A gate layer is formed in the gap formed after removing the sacrificial layer to form a stacked structure.

5. The manufacturing method according to claim 1, wherein: The first gate line gap structures adjacent to each other in a second direction form a storage block, the first gate line gap structures and the second gate line gap structures are arranged in a colinear manner, and the second direction is perpendicular to the first direction and the stacking direction.

6. The manufacturing method according to claim 1, wherein: The first gate line gap structures adjacent to each other in a second direction form a storage block, the second gate line gap structure is located in the storage block, and in the second direction, the second gate line gap structure is spaced apart from the first gate line gap structure, and the second direction is perpendicular to the first direction and the stacking direction.

7. The manufacturing method according to claim 5, wherein: Etching the initial stacked structure using the plurality of first holes, the at least one second hole, and the plurality of third holes so that the plurality of first holes are connected to each other to form a first gate line slit structure, the plurality of third holes are connected to each other to form a second gate line slit structure, and the initial stacked structure is retained between the first gate line slit structure and the at least one second hole after etching, comprising: The initial stacking structure is retained between the second gate line gap structure and the at least one second hole after etching.

8. The manufacturing method according to claim 7, wherein: The multiple first holes are arranged at a first spacing distance, the multiple third holes are arranged at a second spacing distance, the minimum spacing distance between the first holes and the second holes is greater than the first spacing distance and the second spacing distance, and the minimum spacing distance between the third holes and the second holes is greater than the first spacing distance and the second spacing distance.

9. The manufacturing method according to claim 5 or 6, wherein: Also includes: A plurality of fourth holes are formed in the array region, penetrating the initial stacking structure and arranged in a colinear manner along the first direction, the plurality of fourth holes are located in the storage block, and in the second direction, the plurality of fourth holes are spaced apart from the first gate line gap structure; as well as The initial stack structure is etched using the plurality of fourth holes, so that the plurality of fourth holes are connected to each other to form a third gate line gap structure.

10. The manufacturing method according to claim 9, wherein: The plurality of fourth holes are divided into at least two groups; Wherein, etching the initial stack structure by using the plurality of fourth holes so that the plurality of fourth holes are connected to each other to form a third gate line gap structure comprises: The initial stacking structure is etched by using the plurality of fourth holes, so that each group of fourth holes are connected to each other to form a sub-gate line gap structure, and the initial stacking structure is retained between adjacent sub-gate line gap structures.

11. The manufacturing method according to claim 9, wherein: Also includes: forming a plurality of channel holes penetrating the initial stacked structure in the array region; Wherein, the plurality of channel holes, the plurality of first holes, the at least one second hole, the plurality of third holes and the plurality of fourth holes are formed in the same process.

12. The manufacturing method according to claim 4, wherein: The connection region has a conductive region and an insulating region, the portion of the stacked structure located in the array region and the conductive region includes the alternately stacked dielectric layers and the gate layers, and the portion of the stacked structure located in the insulating region includes the alternately stacked dielectric layers and the sacrificial layers, and the method further includes: A plurality of contact structures penetrating the stacked structure at different depths are respectively formed in the insulating region, wherein the contact structures are connected to a gate layer in the same layer.

13. A semiconductor device, characterized in that: include: A stacked structure having an array region and a connection region; A first gate line isolation structure, which penetrates the stacked structure and extends in a first direction in the array region, wherein the first direction is perpendicular to a stacking direction of the stacked structure; A second gate line isolation structure, penetrating the stacked structure and extending along the first direction in the connection region; as well as an isolation structure, penetrating the stacked structure and contacting the first gate line isolation structure; Wherein, the sidewalls of the first gate line isolation structure and the second gate line isolation structure are concave-convex structures.

14. The semiconductor device according to claim 13, wherein: The first gate line isolation structures adjacent to each other in a second direction form a storage block, the first gate line isolation structure and the second gate line isolation structure extend colinearly, and the second direction is perpendicular to the first direction and the stacking direction.

15. The semiconductor device according to claim 14, wherein: The isolation structure contacts the second gate line isolation structure.

16. The semiconductor device according to claim 13, wherein: The first gate line isolation structures adjacent to each other in a second direction form a storage block, the second gate line isolation structure is located in the storage block, and in the second direction, the second gate line isolation structure is spaced apart from the first gate line isolation structure, and the second direction is perpendicular to the first direction and the stacking direction.

17. The semiconductor device according to claim 14 or 16, wherein: It also includes a third gate line isolation structure, which runs through the stacked structure, extends along the first direction in the array area, and is located in the storage block. In the second direction, the third gate line isolation structure is spaced apart from the first gate line isolation structure, and the sidewalls of the third gate line isolation structure are concave-convex structures.

18. The semiconductor device according to claim 17, wherein: The third gate line isolation structure includes at least two sub-gate line isolation structures, and the sub-gate line isolation structures extend along the first direction in the array region, and there is a spacing distance between adjacent sub-gate line isolation structures.

19. The semiconductor device according to claim 13, wherein: The connection area has a conductive area and an insulating area, the stacked structure located in the array area and the conductive area includes alternately stacked dielectric layers and gate layers, and the stacked structure located in the insulating area includes alternately stacked dielectric layers and sacrificial layers.

20. The semiconductor device according to claim 19, wherein It also includes a plurality of contact structures, which are located in the insulating region and penetrate the stacked structure at different depths respectively, and are connected to the gate layer of the same layer.

21. The semiconductor device according to claim 13, wherein Also included are a plurality of channel structures penetrating the stacked structure in the array region.

22. A memory system, characterized in that: include: A three-dimensional memory, comprising a semiconductor device according to any one of claims 13 to 21; as well as The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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