Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a laminated structure and a capacitor contact structure. The laminated structure comprises first dielectric layers and gate layers which are alternately stacked. The capacitor contact structure comprises a first conductive layer, a first insulating dielectric layer and a second conductive layer from outside to inside, and the first conductive layer extends in the laminated structure along the stacking direction and is connected with the corresponding gate layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a structure of a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Taking three-dimensional memory as an example, some semiconductor devices include a stacked structure. As the number of stacked layers in the stacked structure continues to increase, the depth of etching required for the contact holes (CT) extending to different word lines (WL) is getting deeper and deeper, and higher requirements are also put forward for the CT etching process and the process of etching the stop layer. In order to reduce the process difficulty and simplify the process steps, the SCT (self-align contact) architecture is proposed in the relevant technology. The SCT process uses the step (SS) cutting process to accurately stop the contact hole on each layer of WL, thereby realizing the merger of the SS process and the CT process.

[0003] It should be understood that the contents described in this background technology section are only used to help understand the technical solutions disclosed in this application, and do not necessarily belong to the prior art before the filing date of this application. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a storage system that can at least partially solve the above-mentioned problems or other problems existing in the related art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a stacked structure, including alternately stacked first dielectric layers and gate layers; and a capacitor contact structure, including, from the outside to the inside, a first conductive layer, a first insulating dielectric layer, and a second conductive layer, wherein the first conductive layer extends in the stacked structure along the stacking direction and is connected to the corresponding gate layer.

[0006] In one embodiment of the present application, the capacitor contact structure further includes a third conductive layer and a second insulating medium layer located between the second conductive layer and the third conductive layer.

[0007] In one embodiment of the present application, the first conductive layer includes a first part and a second part connected to each other, wherein the first part extends in the stacking structure along the stacking direction; and the second part extends in a plane perpendicular to the stacking direction and connects the first part and the corresponding gate layer.

[0008] In one embodiment of the present application, the capacitor contact structure further includes a sidewall barrier layer, and the sidewall barrier layer is located between the stacked structure and the first portion.

[0009] In one embodiment of the present application, in a plane perpendicular to the stacking direction, the projection of the second part covers the projection of the first part.

[0010] In one embodiment of the present application, in a plane perpendicular to the stacking direction, the projection of the first part is annular.

[0011] In one embodiment of the present application, the first insulating dielectric layer covers the surface of the first conductive layer; and the second conductive layer covers the surface of the first insulating dielectric layer, wherein the extension length of the first conductive layer in the stacking direction is greater than the extension length of the second conductive layer in the stacking direction.

[0012] In one embodiment of the present application, the third conductive layer includes a conductive material layer and an insulating filling layer surrounded by the conductive material layer.

[0013] In one embodiment of the present application, the second conductive layer includes at least one of a semiconductor material layer and a metal material layer; and / or the third conductive layer includes at least one of a semiconductor material layer and a metal material layer.

[0014] In one embodiment of the present application, the first conductive layer and the second conductive layer have the same thickness; and / or the second conductive layer and the third conductive layer have the same thickness.

[0015] In one embodiment of the present application, the second conductive layer and the third conductive layer include the same material.

[0016] In one embodiment of the present application, the stacked structure includes a storage area and a connection area adjacently distributed in a plane perpendicular to the stacking direction, wherein the gate layer extends from the storage area into the connection area, and the connection area also includes a second dielectric layer alternately stacked with the first dielectric layer, wherein the first conductive layer passes through a plurality of the second dielectric layers in the connection area along the stacking direction and is connected to the corresponding gate layer.

[0017] Another aspect of the present application provides a method for preparing a semiconductor device, the method comprising:

[0018] In one embodiment of the present application, a stacked structure is formed, the stacked structure including alternately stacked first dielectric layers and gate layers; and a capacitor contact structure is formed, wherein the capacitor contact structure includes, from the outside to the inside, a first conductive layer, a first insulating dielectric layer, and a second conductive layer, the first conductive layer extends in the stacked structure along the stacking direction and is connected to the corresponding gate layer.

[0019] In one embodiment of the present application, forming the stacked structure includes: alternately stacking the first dielectric layer and the second dielectric layer to form a stacked structure; removing a portion of the second dielectric layer to form a sacrificial gap; and forming the gate layer in the sacrificial gap.

[0020] In one embodiment of the present application, the stacking structure includes a predetermined storage area and a predetermined connection area adjacently distributed in a plane perpendicular to the stacking direction, and forming the sacrificial gap includes: forming a gate line gap that runs through the stacking structure along the stacking direction, wherein the gate line gap includes a first gap located in the predetermined storage area and a second gap located in the predetermined connection area; filling the first gap and removing a portion of the second dielectric layer based on the second gap to form a first gap; exposing the first gap and filling the second gap and the first gap; and based on the exposed first gap, continuing to remove a portion of the second dielectric layer to form a second gap, wherein the first gap and the second gap that are connected to each other are formed as the sacrificial gap.

[0021] In one embodiment of the present application, forming a capacitor contact structure includes: forming a first opening of a second dielectric layer extending along the stacking direction to a predetermined stacking height; forming a sidewall barrier layer on the sidewall of the first opening; removing a portion of the second dielectric layer in contact with the bottom of the first opening to form a second opening; and forming the first conductive layer, the first insulating dielectric layer and the second conductive layer in the first opening and the second opening in sequence.

[0022] In one embodiment of the present application, the method further includes: sequentially forming a second insulating dielectric layer and a third conductive layer on the surface of the second conductive layer.

[0023] In one embodiment of the present application, the second conductive layer is formed by using at least one of a semiconductor material and a metal material; and / or the third conductive layer is formed by using at least one of a semiconductor material and a metal material.

[0024] In one embodiment of the present application, forming the third conductive layer includes: forming a conductive material layer on the surface of the second insulating medium layer; and forming an insulating filling layer on the surface of the conductive material layer to fill the remaining space of the first opening.

[0025] Another aspect of the present application provides a storage system, which includes: a controller; and the semiconductor device provided in any one of the aspects of the present application, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0026] In one embodiment of the present application, the semiconductor device includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0027] According to the semiconductor device and its preparation method and storage system provided by at least one embodiment of the present application, there is no need to form a step and a word line contact located on the step in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and a plurality of capacitor contact structures arranged in the stacked structure, and the first conductive layer of the capacitor contact structure can realize electrical connection between the gate layer located at different stacking heights and the external circuit, thereby simplifying the preparation process and reducing the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0028] In addition, the capacitor contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first conductive layer and the second conductive layer. The first conductive layer, the second conductive layer and the first insulating dielectric layer form a capacitor structure, so the capacitor contact structure can not only realize the electrical connection between the gate layer at different stacking heights and the external circuit, but also use its own internal space to form the capacitor structure required by the semiconductor device. While improving the comprehensive performance of the semiconductor device, it effectively improves the unit storage density and reduces the price of the unit storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. In the drawings:

[0030] Figure 1 is a partial cross-sectional schematic diagram of a semiconductor device according to one embodiment of the present application;

[0031] Figure 2 yes Figure 1 A schematic top view of a cross section of the semiconductor device shown is taken along line BB';

[0032] Figure 3 yes Figure 2 The semiconductor device is shown as an enlarged schematic top view at A;

[0033] Figure 4 is a partial cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present application;

[0034] Figure 5 yes Figure 4 A schematic top view of a cross section of the semiconductor device shown along line DD';

[0035] Figure 6 yes Figure 4 The enlarged cross-sectional view of the semiconductor device at position C is shown;

[0036] Figure 7 is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0037] Figure 8A-Figure 10 They are respectively process schematic diagrams of a method for preparing a semiconductor device according to an embodiment of the present application; and

[0038] Fig.11 It is a schematic diagram of the storage system structure according to one embodiment of the present application.

[0039] Specific method

[0040] The present application will be described in detail below in conjunction with the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present application and are not used to limit the scope of the present application. Throughout the specification, the same reference numerals refer to the same elements.

[0041] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximation, not degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0042] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "including", "including", "having", "having" and / or "having" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or parts, but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. When describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0043] In addition, when the expressions “connected”, “covered” and / or “formed on” are used in the present application, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or inferred from the context.

[0044] Unless otherwise specified, all words (including technical terms and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. In addition, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] Figure 1 is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to an embodiment of the present application. Figure 2 yes Figure 1 The semiconductor device is shown in a schematic top view of a cross section taken along line BB′. Figure 3 yes Figure 2 The semiconductor device is shown as an enlarged schematic top view at A. Figure 4 is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to another embodiment of the present application. Figure 5 yes Figure 4 The semiconductor device is shown in a top view schematically showing a cross section taken along line DD′. Figure 6 yes Figure 4 The semiconductor device is shown as an enlarged cross-sectional schematic diagram at C.

[0047] like Figure 1-Figure 6 As shown, the semiconductor device 1000 may include: a stacked structure 200 and a capacitor contact structure 500. The stacked structure 200 includes a plurality of first dielectric layers 210 and a plurality of gate layers 230 that are alternately stacked. The capacitor contact structure 500 includes a first conductive layer 530, a first insulating dielectric layer 34, and a second conductive layer 540 from the outside to the inside. The first conductive layer 530 extends in the stacked structure 200 along the stacking direction (z direction) and is electrically connected to the corresponding gate layer.

[0048] According to the semiconductor device provided by at least one embodiment of the present application, there is no need to form a step and a word line contact located on the step in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and a plurality of capacitor contact structures arranged in the stacked structure, and the first conductive layer of the capacitor contact structure can realize electrical connection between the gate layer located at different stacking heights and the external circuit, thereby simplifying the preparation process and reducing the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0049] In addition, the capacitor contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first conductive layer and the second conductive layer. The first conductive layer, the second conductive layer and the first insulating dielectric layer form a capacitor structure, so the capacitor contact structure can not only realize the electrical connection between the gate layer at different stacking heights and the external circuit, but also use its own internal space to form the capacitor structure required by the semiconductor device. While improving the comprehensive performance of the semiconductor device, it effectively improves the unit storage density and reduces the price of the unit storage unit.

[0050] Specifically, the stacked structure 200 can be arranged on a substrate and includes a storage area 01 and a connection area 02 adjacently distributed in a plane parallel to the substrate (xy plane, in which the x direction, the y direction and the z direction are perpendicular to each other), wherein the storage area 01 includes a plurality of first dielectric layers 210 and a plurality of gate layers 230 stacked alternately; the connection area 02 includes a plurality of first dielectric layers 210 and a plurality of second dielectric layers 220 stacked alternately.

[0051] The gate layer 230 may include a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide. The first dielectric layer 210 may be used as an isolation stacking layer, including but not limited to insulating dielectric material layers such as silicon oxide layers. Among them, the first dielectric layer 210 and the second dielectric layer 220 are two different insulating dielectric material layers. For example, the second dielectric layer 220 may include but not limited to insulating dielectric material layers such as silicon nitride layers. In addition, multiple second dielectric layers 220 and multiple gate layers 230 may have the same stacking height. In addition, the number of layers of the stacked structure 200 is not limited to the number of layers shown in the figure, and can be set separately as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0052] In other words, the connection area 02 may include alternately stacked first dielectric layers 210 and composite layers, wherein each of the plurality of composite layers may include second dielectric layers 220 and gate layers 230 connected and distributed in an xy plane. Each of the plurality of capacitor contact structures 500 extends in the stacked structure 200 along the z direction in the connection area 02. The gate layer 230 extends from the storage area 01 into the connection area 02, and the first conductive layer 530 passes through the plurality of second dielectric layers 220 along the z direction and is electrically connected to the corresponding gate layer.

[0053] Taking three-dimensional memory as an example, semiconductor devices generally include a stacked structure formed by alternating gate layers and dielectric layers, wherein the word line contact located in the step area of ​​the stacked structure can realize the electrical connection between the gate layer and the external circuit. However, as the number of stacked layers increases, the formation of word line contacts in the step area requires multiple processes such as photolithography and etching to form the stepped morphology of the steps, which greatly increases the manufacturing cost of semiconductor devices; at the same time, the more steps there are, the larger the area of ​​the step area to be formed, which is not conducive to improving the integration of semiconductor devices. In addition, the more stacked layers there are, the more severe the warping of the wafer, and it will be more difficult to align the word line contact with the step surface in the step area, resulting in the degradation of the reliability of the semiconductor device or the low yield of the electrical test, and ultimately affecting the reliability and overall performance of the semiconductor device.

[0054] The semiconductor device provided in the embodiment of the present application does not need to form steps and word line contacts located on the steps. Electrical connection between gate layers located at different stacking heights and external circuits can be achieved by providing multiple capacitor contact structures in the second area of ​​the stacked structure. This can simplify the preparation process and reduce the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0055] In addition, the capacitor contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first conductive layer and the second conductive layer. The first conductive layer, the second conductive layer and the first insulating dielectric layer form a capacitor structure, so the capacitor contact structure can not only realize the electrical connection between the gate layer located at different stacking heights and the external circuit, but also use its own internal space to form a capacitor structure required for the semiconductor device. For example, the capacitor structure of the capacitor contact structure can be used for the CMOS charge pump (Complementary Metal Oxide Semiconductor charge pump, CMOS charge pump) circuit required for the peripheral circuit of the semiconductor device. Therefore, while improving the comprehensive performance of the semiconductor device, the unit storage density is effectively improved and the price of the unit storage unit is reduced.

[0056] In addition, reference Figure 1 and Figure 4 In one embodiment of the present application, the capacitor contact structure 500 further includes a third conductive layer 550 and a second insulating medium layer 45 located between the second conductive layer 540 and the third conductive layer 550 .

[0057] In other words, the capacitor contact structure 500 may include a plurality of capacitor structures, such as Figure 1 and Figure 4A capacitor contact structure 500 including two capacitor structures is shown respectively, wherein the first conductive layer 530, the first insulating medium layer 34 and the second conductive layer 540 can form a first capacitor structure; the second conductive layer 540, the second insulating medium layer 45 and the third conductive layer 550 can form a second capacitor structure.

[0058] Those skilled in the art will appreciate that the number of capacitor structures shown in the figure is only for the sake of illustration, and the present application is not limited thereto. The specific number of capacitor structures of the capacitor contact structure can be set according to actual needs. As an option, the multiple capacitor contact structures 500 may include the same number of capacitor structures; as another option, the multiple capacitor contact structures 500 may include different numbers of capacitor structures, and the specific number of capacitor structures included in the capacitor contact structure in the semiconductor device can be set according to actual needs.

[0059] In addition, with the increasing demand for the storage capacity of semiconductor devices, the above-mentioned storage stacking layers are gradually increasing. The stacking structure 200 may include a plurality of sub-stacked structures formed by a double stacking technology or a multi-stacked technology. A plurality of sub-stacked structures may be stacked in sequence in the stacking direction to form a stacking structure 200, wherein each sub-stacked structure may include a storage area and a connection area adjacently distributed in a plane perpendicular to the stacking direction. The storage area includes a first dielectric layer and a gate layer stacked on each other, and the connection area includes a first dielectric layer and a second dielectric layer stacked on each other. The number of layers of each sub-stacked structure may be the same or different. The content of a single stacked structure described in this article may be fully or partially applicable to a stacked structure formed by a plurality of sub-stacked structures, and therefore the content related or similar thereto will not be repeated.

[0060] Reference again Figure 4 and Figure 6 As an option, in one embodiment of the present application, the first conductive layer 530 includes a first portion 21 and a second portion 22 connected to each other, wherein the first portion 21 extends in the stacked structure 200 along a direction approximately in the z direction, and the second portion 22 extends in the xy plane and connects the first portion 21 and the corresponding gate layer.

[0061] In addition, the conductive material forming the first conductive layer 530 may include any one or a combination of conductive metal materials and doped semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., which is not limited in the present application.

[0062] In addition, in one embodiment of the present application, the capacitor contact structure 500 may further include a sidewall barrier layer 520, which is located between the stacked structure 200 and the first portion 530. The sidewall barrier layer 520 prevents the first portion 530 from forming a connection with the remaining gate layers in the stacked structure 200 except for the corresponding gate layer, thereby achieving electrical connection between the corresponding gate layer and the external circuit through the capacitor contact structure. In addition, as described above, the connection area 02 may include alternately stacked first dielectric layers 210 and composite layers, wherein each of the plurality of composite layers may include a second dielectric layer 220 and a gate layer 230 that are connected and distributed to each other in the xy plane. In the process of preparing the capacitor contact structure 500, under the protection of the sidewall barrier layer 520, by, for example, a dry etching process or a combination of dry and wet etching processes, only a portion of the second dielectric layer in the composite layer where the corresponding gate layer is located may be removed, without removing a portion of the second dielectric layer in the remaining composite layers at different stacking heights from the corresponding gate layer.

[0063] Reference again Figure 4-Figure 6 In one embodiment of the present application, in the xy plane, the projection of the second part covers the projection of the first part.

[0064] In other words, the stacked structure 200 includes a storage area 01 and a connection area 02, and the connection area 02 may include an insulating dielectric material stacking layer formed by a first dielectric layer 210 and a second dielectric layer 220 stacked on each other. The capacitor contact structure 500 is set in the connection area, and the first part 21 of the first conductive layer 530 extends in the insulating dielectric material stacking layer along the z direction and is connected to the second part 22 at the stacking height of the corresponding gate layer. By setting the projection of the second part 22 to the projection of the covered first part 21, the second part 22 can be extended along the xy direction and connected to the corresponding gate layer. While achieving electrical communication between the capacitor contact structure and the corresponding gate layer, short circuits between different gate layers can be prevented.

[0065] In addition, in the semiconductor device provided in at least one embodiment of the present application, in the xy plane, the projection of the first portion 21 of the first conductive layer 530 is ring-shaped.

[0066] The capacitor contact structure 500 can be accommodated in a pre-formed contact hole. As an option, the first conductive layer of the conventional contact structure can fill the contact hole including the sidewall barrier layer 520. However, in the semiconductor device provided by at least one embodiment of the present application, the projection of the first portion 21 of the first conductive layer 530 is annular. In other words, the first conductive layer 530 is located on the surface of the sidewall barrier layer 520 and the sidewall of the contact hole, the first portion 21 of the first conductive layer 530 is located on the surface of the sidewall barrier layer 520, and the second portion 22 of the first conductive layer 530 is located on the sidewall of the contact hole.

[0067] Considering that the material forming the first conductive layer 530 generally includes any one or combination of conductive metal materials and doped semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., therefore, setting the projection of the first portion 21 of the first conductive layer 530 to be annular can reduce the manufacturing cost of the semiconductor device and reduce the stress deformation of the stacked structure caused by the capacitor contact structure, and at the same time, most of the space can be left on the inner wall of the capacitor contact structure 500 to form a capacitor structure. For example, by using the internal space of the capacitor contact structure 500 itself to form the capacitor structure required by the semiconductor device, the unit storage density can be effectively improved and the price of the unit storage unit can be reduced while improving the comprehensive performance of the semiconductor device.

[0068] In addition, if Figure 1 and Figure 4 As shown, in one embodiment of the present application, the first insulating medium layer 34 may cover the surface of the first conductive layer 530; and the second conductive layer 540 may cover the surface of the first insulating medium layer 34, wherein the extension length of the first conductive layer 530 in the z direction is greater than the extension length of the second conductive layer 540 in the z direction.

[0069] In addition, if Figure 1 and Figure 3 As shown, in one embodiment of the present application, the third conductive layer 550 may include a conductive material layer 550 - 2 and an insulating filling layer 550 - 1 surrounded by the conductive material layer 550 - 2 .

[0070] In other words, the capacitor contact structure 500 may include a plurality of capacitor structures, such as Figure 1 A capacitor contact structure 500 including two capacitor structures is shown, wherein the first conductive layer 530, the first insulating dielectric layer 34 and the second conductive layer 540 can form a first capacitor structure; the second conductive layer 540, the second insulating dielectric layer 45 and the third conductive layer 550 can form a second capacitor structure. In a plurality of capacitor structures arranged in sequence from the outside to the inside, the innermost conductive layer can be a composite structure. The innermost conductive layer can include a conductive material layer and an insulating filling layer surrounded by the conductive material layer. Through the above arrangement, the manufacturing cost of the semiconductor device can be reduced and the stress deformation of the stacked structure caused by the capacitor contact structure can be reduced.

[0071] Optionally, in one embodiment of the present application, the second conductive layer 540 may include any one or a combination of a conductive metal material layer and a semiconductor material layer, wherein the material used to form the conductive metal material layer may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the material used to form the semiconductor material layer may be, for example, crystalline silicon or silicide, etc.

[0072] In addition, the third conductive layer 550 may include any one or a combination of a conductive metal material layer and a semiconductor material layer, wherein the material used to form the conductive metal material layer may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the material used to form the semiconductor material layer may be, for example, crystalline silicon or silicide, etc.

[0073] In addition, in order to simplify the manufacturing process and save the manufacturing cost, the same process and the same material may be used to form multiple conductive layers included in the capacitor contact structure 500, such as the second conductive layer, the third conductive layer, etc.

[0074] On this basis, optionally, the first conductive layer 530 and the second conductive layer 540 may have the same thickness. Alternatively, the second conductive layer 540 and the third conductive layer 550 may have the same thickness. Alternatively, the first conductive layer 530, the second conductive layer 540 and the third conductive layer 550 may all have the same thickness.

[0075] like Figure 1 and Figure 2 As shown, in one embodiment of the present application, the semiconductor device 1000 may further include a gate line gap structure 400. The gate line gap structure 400 may pass through the storage area 01 along the z direction and extend in the y direction. Alternatively, the gate line gap structure 400 may pass through the connection area 02 along the z direction and extend in the y direction.

[0076] In addition, the semiconductor device 1000 further includes a channel structure 300 extending along the z direction in the storage area 01 of the stacked structure 200. The channel structure 300 may include a semiconductor layer and a composite dielectric layer filled in the channel hole, for example, a functional layer and a channel layer sequentially formed on the inner wall of the channel hole. In addition, the channel structure 300 may further include a channel filling dielectric layer, which may be filled in the remaining space of the channel hole after the functional layer and the channel layer have been formed.

[0077] The functional layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed on the inner wall of the channel hole. As an alternative, the channel hole may have a cylindrical or columnar shape extending along the z direction in the stacked structure 200. Similar to the channel hole, the functional layer may also have a cylindrical or columnar shape extending along the z direction in the stacked structure 200.

[0078] The channel layer may be located on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes). The channel layer may also have a cylindrical or columnar shape extending along the z direction in the stacked structure 200. The channel layer may be made of semiconductor materials such as polycrystalline silicon or single crystal silicon, and may have conductive impurities. For example, the channel layer may be an N-type doped or P-type doped polycrystalline silicon layer.

[0079] In addition, the semiconductor device 1000 may further include a dummy channel structure (not shown). As an option, the channel structure 300 and the dummy channel structure may have partially the same internal structure. For example, when forming the functional layer, the channel layer, and the channel filling dielectric layer of the channel structure 300, the functional layer, the channel layer, and the channel filling dielectric layer may also be filled in the dummy channel hole of the dummy channel junction.

[0080] In addition, as another option, based on the fact that the dummy channel structure does not have a storage function, an insulating dielectric material layer such as a silicon oxide layer may be usually filled in the dummy channel hole of the dummy channel structure.

[0081] Figure 7 is a flow chart of a method 2000 for preparing a semiconductor device according to one embodiment of the present application. Figure 8A-Figure 10 They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to an embodiment of the present application.

[0082] like Figure 7 As shown, the method 2000 for preparing a semiconductor device may include:

[0083] S1, forming a stacked structure, wherein the stacked structure includes first dielectric layers and gate layers that are alternately stacked.

[0084] S2, forming a capacitor contact structure, wherein the capacitor contact structure includes, from outside to inside, a first conductive layer, a first insulating dielectric layer, and a second conductive layer, wherein the first conductive layer extends in the stacked structure along a stacking direction and is connected to a corresponding gate layer.

[0085] The following will be combined Figures 7 to 10 The specific process of each step of the above-mentioned preparation method 2000 in one embodiment of the present application is described in detail.

[0086] Step S1

[0087] Fig. 8A It is a schematic cross-sectional view of a structure formed after forming a stacked structure 200 ′ according to a preparation method of one embodiment of the present application. Figure 8B It is a schematic cross-sectional view of a structure formed after forming a conductive layer 530 according to a preparation method of one embodiment of the present application.

[0088] like Figure 7 and Fig. 8A As shown, step S1 forms a stacked structure, and the stacked structure includes alternately stacked first dielectric layers and gate layers, which may include, for example: alternately stacking first dielectric layers 210 and second dielectric layers 220 to form a stacked structure 200'; removing part of the second dielectric layer 220 to form a sacrificial gap (not shown); and forming a gate layer 230 in the sacrificial gap.

[0089] Specifically, in one embodiment of the present application, step S1 of forming the stacked structure may further include providing an initial substrate. The material for preparing the initial substrate may be any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the initial substrate may be single crystal silicon.

[0090] In one embodiment of the present application, the initial substrate may be, for example, a composite substrate for supporting a device structure thereon. The initial substrate may be formed by sequentially depositing a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0091] In one embodiment of the present application, the initial substrate may include a substrate sacrificial layer for subsequently forming a semiconductor connection layer connecting the channel structure. The substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0092] Part of the initial substrate may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0093] After forming the initial substrate, a stacked structure 200' may be formed on the initial substrate by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present application.

[0094] The stack structure 200' may include a plurality of pairs of first dielectric layers 210 and second dielectric layers 220 alternately stacked with each other. For example, the stack structure 200' may include 64 pairs, 128 pairs, or more than 128 pairs of first dielectric layers 210 and second dielectric layers 220.

[0095] In some embodiments, the first dielectric layer 210 and the second dielectric layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the first dielectric layer 210 and the second dielectric layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stacking layer, and the silicon nitride layer may be used as a sacrificial stacking layer. Subsequently, a portion of the sacrificial stacking layer may be etched away, and the etched portion of the sacrificial stacking layer may be replaced with a conductor layer including a conductive material to form a gate layer of the semiconductor device.

[0096] In addition, the stacked structure 200' may further include a cover layer, which is located at the highest position of the stacked structure 200'. The cover layer includes but is not limited to an insulating dielectric material layer such as a silicon oxide layer.

[0097] The preparation method of a single stacking structure is described above. In fact, as the storage demand of semiconductor devices continues to increase, the storage stack gradually increases. In order to break through the limitations of traditional process limits, a double stacking technology or a multi-stack technology can also be used to form a stacking structure by stacking multiple sub-stack structures stacked in sequence in the direction of the thickness of the stacking structure, wherein each sub-stack structure may include a plurality of first dielectric layers and second dielectric layers alternately stacked. The number of layers of each sub-stack structure may be the same or different. Since the content and structure involved in the preparation process of the single stacking structure described above may be fully or partially applicable to the stacking structure formed by multiple sub-stack structures described here, the content related or similar thereto will not be repeated. However, it can be understood by those skilled in the art that subsequent preparation processes can be performed on the basis of a multi-stack structure or a single stack structure.

[0098] In addition, in one embodiment of the present application, step S1 of forming a stacked structure may also include: forming a channel structure 300 and a dummy channel structure (not shown) in the stacked structure 200'; forming a gate line gap (not shown) in the stacked structure 200'; removing a portion of the second dielectric layer 220 through the gate line gap to form a gate layer 230; and forming a gate line gap structure 400, thereby forming the stacked structure 200.

[0099] In one embodiment of the present application, a first region 01' and a second region 02' that are adjacently distributed may be defined on the surface of the initial substrate. A stacked structure is subsequently formed on the surface of the initial substrate, and the stacked structure may include a storage region and a connection region that are adjacently distributed in a plane parallel to the initial substrate (a plane perpendicular to the stacking direction), wherein the storage region and the connection region may be formed in the first region 01' and the second region 02', respectively, and include stacked layers formed of different materials.

[0100] Specifically, in one embodiment of the present application, a channel structure 300 and a dummy channel structure may be formed in the stacked structure 200'. Forming a plurality of channel structures 300 extending along the z direction in the stacked structure 200' may include: forming a channel hole (not shown); and sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole.

[0101] The channel structure 300 may include a semiconductor layer and a composite dielectric layer filled in the channel hole. The functional layer 320 and the channel layer 330 may be formed on the inner wall of the channel hole by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0102] Specifically, the channel hole can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed. The channel hole can have a cylindrical or columnar shape extending along the z direction in the stacked structure 200'. As an option, the channel hole can extend into the initial substrate.

[0103] The functional layer 320 may include a blocking layer formed on an inner wall of the channel hole to block outflow of charges, a charge trapping layer formed on a surface of the blocking layer to store charges during operation of the semiconductor device, and a tunneling layer formed on a surface of the charge trapping layer.

[0104] In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure different from the ONO configuration. The channel layer 330 may be formed on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes).

[0105] However, those skilled in the art should understand that, without departing from the teachings of the present application, they may choose to form a functional layer on the sidewalls and bottom surface of the channel hole, or form a functional layer on the sidewalls of the channel hole according to different semiconductor device architectures, and the present application does not limit this.

[0106] For example, as an option, according to one embodiment of the present application, a functional layer 320 may be formed on the sidewalls and bottom surface of the channel hole, and a channel layer 330 may be formed on the surface of the tunneling layer of the functional layer 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0107] As another option, according to one embodiment of the present application, an epitaxial layer (not shown) may be first formed on the bottom surface of the channel hole, and a functional layer 320 may be formed on the sidewalls of the channel hole and the surface of the epitaxial layer. After removing the portion of the functional layer 320 located on the surface of the epitaxial layer, a channel layer 330 is formed on the surface of the tunneling layer of the remaining functional layer 320 and the surface of the epitaxial layer through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0108] In some embodiments, the channel layer 330 may be made of a semiconductor material such as polysilicon or monocrystalline silicon, and may have conductive impurities. For example, the channel layer may be an N-type doped or P-type doped polysilicon layer. Similar to the channel hole, the channel layer 330 may also have a cylindrical or columnar shape extending in the z-direction in the stacked structure 200'. As an option, the channel layer 330 may also extend into the initial substrate.

[0109] In addition, a channel plug may be formed at one end of the channel hole away from the initial substrate (which can be understood as the top of the channel structure 300). Specifically, after forming the functional layer 320 and the channel layer 330, the channel hole may be filled with a channel filling dielectric layer. The channel filling dielectric layer may include an oxidizing dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulating gaps may be formed in the channel filling dielectric layer by controlling the channel filling process to reduce structural stress. Then, a channel plug is formed in the portion of the channel filling dielectric layer located at the top of the channel hole. The material of the channel plug may be prepared from the same material as the channel layer 330, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer 330.

[0110] After forming the channel structure 300 , a dummy channel structure having a spacing from the channel structure 300 in the first direction (x direction) may be formed in the same manner as described above, and thus related or similar contents are not described in detail herein.

[0111] In addition, as an option, based on the virtual channel structure not having a storage function, generally, in a virtual channel hole (not shown) of the virtual channel structure, only an insulating dielectric material layer such as a silicon oxide layer can be filled by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Similarly, by controlling the channel filling process, a plurality of insulating gaps can be formed in the insulating dielectric material layer to reduce the structural stress of the virtual channel structure.

[0112] After forming the channel structure 300 and the dummy channel structure, multiple channel structures 300 may form a channel structure array, multiple dummy channel structures may form a dummy channel structure array, and each array may be arranged in multiple rows and columns in the first direction and the second direction (y direction). The first region 01' may include at least the channel structure array.

[0113] After forming the channel structure 300 and the dummy channel structure, a gate line gap can be formed through the stacked structure 200' in the z direction and extending in the y direction by, for example, a dry etching process or a combination of dry and wet etching processes. As an option, the gate line gap can pass through the stacked structure 200' in the z direction and extend into the initial substrate. The gate line gap can be used as a path for providing an etchant, and a wet etching or equivalent etching process is used to remove part of the second dielectric layer 220 in the stacked structure, thereby forming a gate layer.

[0114] The stacked structure provided in the embodiment of the present application includes a storage area 01 and a connection area 02 (see Figure 1 ), the storage area includes a channel structure and the connection area includes a contact structure. Therefore, the stacking structure 200' used to form a stacked structure also includes a predetermined storage area and a predetermined connection area correspondingly, and the predetermined storage area and the predetermined connection area of ​​the stacking structure are respectively formed in the first area 01' and the second area 02'.

[0115] In one embodiment of the present application, forming a sacrificial gap for accommodating the gate layer 230 may include: forming a gate line gap that penetrates the stacked structure 200' along the z direction, wherein the gate line gap includes a first gap (not shown) located in a predetermined storage area and a second gap (not shown) located in a predetermined connection area; filling the first gap and removing a portion of the second dielectric layer 230 based on the second gap to form a first gap (not shown); exposing the first gap and filling the second gap and the first gap; and based on the exposed first gap, continuing to remove a portion of the second dielectric layer to form a second gap (not shown), wherein the first gap and the second gap that are connected to each other are formed as a sacrificial gap.

[0116] Specifically, some of the plurality of gate line gaps extend in the y direction and extend along the y direction only in the storage area of ​​the stacked structure 200'. Optionally, some of the plurality of gate line gaps extend in the y direction and extend along the y direction at least in the storage area and the connection area of ​​the stacked structure 200'. The gate line gaps can be used to remove part of the second dielectric layer 220 in the stacked structure 200' in batches in subsequent steps.

[0117] In addition, after removing part of the second dielectric layer to form the gate layer, the connection area may include an insulating dielectric material stacking layer formed by the mutually stacked first dielectric layer and the retained second dielectric layer. By setting the contact structure in the insulating dielectric material stacking layer, the contact structure can be electrically connected to the corresponding gate layer, and short circuits between different gate layers can be prevented. Therefore, in order to achieve the above effect, the semiconductor device manufacturing method provided in the embodiment of the present application only removes part of the second dielectric layer, and the shape and size of the gate layer finally formed can be controlled by removing part of the second dielectric layer in batches.

[0118] As an option, in one embodiment of the present application, in the process of removing part of the second dielectric layer by a process such as wet etching, the process parameters such as the type of etchant in the gate line gap, the concentration of the etchant, the etching time and the etching speed can be adjusted, so that in the process of etching part of the second dielectric layer, both the part of the second dielectric layer located in the storage area and the part of the second dielectric layer located in the connection area and adjacent to the gate line gap can be fully etched without insufficient etching; and it can be ensured that the etching process can accurately retain part of the second dielectric layer in the connection area of ​​the stacked structure to improve over-etching.

[0119] As another option, in one embodiment of the present application, some of the plurality of gate line gaps may define a first gap and a second gap in the y direction, wherein the first gap may be located in the first region 01', and the second gap may be located in the second region 02'. In addition, some of the plurality of gate line gaps may only include the first gap located in the first region 01'.

[0120] The first gap may be filled with a first filling sacrificial layer (not shown) by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and a portion of the second dielectric layer 220 may be removed based on the unfilled second gap.

[0121] Optionally, the first filling sacrificial layer may be a polysilicon layer. The material of the first filling sacrificial layer is different from that of the second dielectric layer, so that the first filling sacrificial layer and the second dielectric layer 220 can have different etching rates for the same etchant, which is convenient for removing part of the second dielectric layer 220 by an etching process in the subsequent process. In addition, since the first filling sacrificial layer needs to be removed in the subsequent steps, a carbon layer, a polysilicon layer, etc. may be used as the first filling sacrificial layer, so as to prevent damage to the stacked structure 200' in the subsequent process step of removing the first filling sacrificial layer, and reduce the cost of manufacturing the semiconductor device.

[0122] Optionally, the entire gate line gap may be filled with a first filling sacrificial layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thereafter, a portion of the first filling sacrificial layer located in the second gap may be removed by, for example, a dry etching process or a combination of dry and wet etching processes to expose the second gap, and the remaining first filling sacrificial layer may be located only in the first gap.

[0123] By filling the remaining first filling sacrificial layer in the first gap, the second gap can be exposed. The exposed second gap can be used as a path for providing an etchant, and a part of the second dielectric layer located in the second region 02' can be removed by adopting, for example, a wet etching equivalent etching process to form a first gap. In this process, by adjusting the process parameters such as the type of etchant in the second gap, the concentration of the etchant, the etching time and the etching speed, in the process of etching part of the second dielectric layer, the part of the second dielectric layer located in the second region 02' and adjacent to the gate line gap can be fully etched without insufficient etching; and it can also ensure that the etching process can accurately retain part of the second dielectric layer of the stacked structure in the second region 02' to improve over-etching.

[0124] In addition, after forming the first void, a dry etching process or a combination of dry and wet etching processes may be used, or other manufacturing processes may be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, to remove the first filling sacrificial layer in the first gap, and through the exposed first gap, a wet etching or equivalent etching process may be used to remove the portion of the second dielectric layer located in the first region 01' to form a second void. This step may also include filling the formed first void with a second filling sacrificial layer (not shown). Optionally, a carbon layer may be used as the second filling sacrificial layer to fill the first void.

[0125] In some embodiments of the present application, after forming the second gap, the connected first gap and the second gap are formed as a sacrificial gap. The gate layer 230 may be formed in the sacrificial gap by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The gate layer 230 may include a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide.

[0126] In addition, before forming the gate layer 230, the method 2000 for preparing a semiconductor device according to an embodiment of the present application further includes forming an isolation dielectric layer on the inner wall of the sacrificial gap and on the inner side wall of the gate line gap by using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. As an option, the isolation dielectric layer can be a high dielectric constant dielectric layer. Further, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof can be used to form an adhesion layer between the first dielectric layer and the gate layer or between the isolation dielectric layer and the gate layer. For example, the adhesion layer can be a titanium nitride TiN layer.

[0127] In addition, if Figure 8B As shown, in some embodiments of the present application, after forming the gate layer 230, a gate line gap structure 400 can also be formed by filling the gate line gap. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof can be used to sequentially fill the gate line gap with a sidewall isolation layer and a dielectric filling layer to form the gate line gap structure 400. The dielectric filling layer can be made of insulating dielectric materials such as silicon oxide, silicon nitride and silicon oxynitride, or semiconductor materials such as polysilicon, which are not limited in the present application. After the gate line gap structure 400 and the gate layer 230 are formed in the stacked structure 200', the stacked structure 200' is formed into a stacked structure 200.

[0128] Step 2

[0129] Fig. 9 It is a schematic cross-sectional view of a structure formed after forming the first insulating dielectric layer 34 according to a preparation method of an embodiment of the present application. Fig.10 It is a schematic cross-sectional view of a structure formed after forming the second conductive layer 540 according to a preparation method of one embodiment of the present application.

[0130] like Figure 1 , Figure 4 , Figure 8B to Figure 10As shown, step S2 forms a capacitor contact structure, wherein the capacitor contact structure includes a first conductive layer, a first insulating dielectric layer and a second conductive layer from the outside to the inside, and the first conductive layer extends in the stacking direction in the stacked structure and is connected to the corresponding gate layer. It may, for example, include: forming a first opening (not shown) of the second dielectric layer extending along the z direction to a predetermined stacking height; forming a sidewall barrier layer 520 on the sidewall of the first opening; removing a portion of the second dielectric layer in contact with the bottom of the first opening to form a second opening (not shown); and forming a first conductive layer 530, a first insulating dielectric layer 34 and a second conductive layer 540 in the first opening and the second opening in sequence.

[0131] Specifically, Figure 1 , Figure 4 and Figure 8B As shown, a plurality of first openings extending along the z direction and having different depths can be formed in the stacked structure 200 by, for example, a dry etching process or a combination of dry and wet etching processes, or by performing other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing.

[0132] After the first opening is formed, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to form an initial barrier layer (not shown) on the surface of the stacked structure 200 away from the initial substrate, the sidewall and the bottom of the first opening. The initial barrier layer may be made of dielectric materials such as silicon oxide, silicon nitride and silicon oxynitride, or may be made of high dielectric constant dielectric materials such as aluminum oxide, which is not limited in the present application.

[0133] After the initial barrier layer is formed, the portion of the initial barrier layer located on the surface of the stacked structure 200 is removed, and the portion of the initial barrier layer located at the bottom of the first opening is removed to form a sidewall barrier layer 520. Under the protection of the sidewall barrier layer 520, a portion of the second dielectric layer 220 in contact with the bottom of the first opening and a portion of the second dielectric layer 220 adjacent to the contact portion are removed through the first opening by, for example, a dry etching process or a combination of dry and wet etching processes, to form a second opening. The second opening and the first opening constitute a contact hole of the capacitor contact structure 500.

[0134] Optionally, in order to reduce the process difficulty and simplify the process steps, the contact hole of the capacitor contact structure 500 can be formed in the process of forming the gate line gap. In this case, in the process of removing part of the second dielectric layer 220 to form the gate layer 230 described in the above step S1, a third filling sacrificial layer (not shown) can be used to fill the contact hole of the capacitor contact structure 500. The third filling sacrificial layer can be selected as a carbon layer, which is convenient for removal in the subsequent step after the gate layer 230 is formed.

[0135] After forming the sidewall barrier layer 520, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to fill a conductive material at least on the surface of the sidewall barrier layer 520 and in the second opening to form a first conductive layer 530.

[0136] As an option, the conductive material forming the first conductive layer 530 may include any one or a combination of conductive metal materials and doped semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the doped semiconductor material may be, for example, doped crystalline silicon or silicide, etc., which is not limited in the present application.

[0137] In addition, in one embodiment of the present application, the first conductive layer 530 does not completely fill the contact hole formed with the sidewall barrier layer 520. For example, part of the first conductive layer 530 fills the second opening, and part of the first conductive layer 530 is located on the surface of the sidewall barrier layer 520. In the remaining space of the contact hole, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof can be used to fill the initial first insulating dielectric layer 34'. Optionally, the material forming the initial first insulating dielectric layer 34' can be a dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0138] like Figure 1 , Figure 4 as well as Figure 8B-Figure 9 As shown, a portion of the initial first insulating dielectric layer 34' can be removed by, for example, a dry etching process or a combination of dry and wet etching processes, or other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, to form the first insulating dielectric layer 34. The first insulating dielectric layer 34 is located on the surface of the first conductive layer 530.

[0139] Alternatively, if Figure 1 , Figure 4 as well as Figure 9-10 As shown, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof can be used to form a second conductive layer 540 on the surface of the first insulating dielectric layer 34. The conductive material forming the second conductive layer 540 may include any one or a combination of conductive metal materials and semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the semiconductor material may be, for example, doped crystalline silicon or silicide, etc., which is not limited in this application. The second conductive layer 540 and the first conductive layer 530 are the first capacitor structure of the capacitor contact structure 500.

[0140] In addition, refer again Figure 1 , Figure 4 as well as Fig.10 According to an embodiment of the present application, the method 2000 for preparing a semiconductor device further includes: sequentially forming a second insulating dielectric layer 45 and a third conductive layer 550 on the surface of the second conductive layer 540 .

[0141] Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof is used to form a second insulating dielectric layer 45 on the surface of the second conductive layer 540. Optionally, the material forming the second insulating dielectric layer 45 may be a dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride.

[0142] After forming the second insulating dielectric layer 45 , a third conductive layer 550 may be formed on the surface of the second insulating dielectric layer 45 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0143] The conductive material forming the third conductive layer 550 may include any one or a combination of conductive metal materials and semiconductor materials, wherein the conductive metal material may be, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc., and the semiconductor material may be, for example, doped crystalline silicon or silicide, etc., which is not limited in this application. The second conductive layer 540 and the third conductive layer 550 are the second capacitor structure of the capacitor contact structure 500.

[0144] Referring to the above steps of forming a conductive layer (e.g., the second conductive layer 540 and the third conductive layer 550) and an insulating dielectric layer (e.g., the second insulating dielectric layer 45) in the contact hole of the capacitor contact structure 500, multiple capacitor structures can be formed in the contact hole according to actual needs.

[0145] According to the semiconductor device manufacturing method provided by at least one embodiment of the present application, there is no need to form a step and a word line contact located on the step in the semiconductor device. Specifically, the semiconductor device may include a stacked structure and a plurality of capacitor contact structures arranged in the stacked structure, and the first conductive layer of the capacitor contact structure can realize electrical connection between the gate layer located at different stacking heights and the external circuit, thereby simplifying the manufacturing process and reducing the production cost, while improving the unit storage density, reliability and overall performance of the semiconductor device.

[0146] In addition, the capacitor contact structure also includes a second conductive layer and a first insulating dielectric layer located between the first conductive layer and the second conductive layer. The first conductive layer, the second conductive layer and the first insulating dielectric layer form a capacitor structure, so the capacitor contact structure can not only realize the electrical connection between the gate layer at different stacking heights and the external circuit, but also use its own internal space to form the capacitor structure required by the semiconductor device. While improving the comprehensive performance of the semiconductor device, it effectively improves the unit storage density and reduces the price of the unit storage unit.

[0147] In addition, reference Figure 1 , Figure 3 and Fig.10 , forming the third conductive layer 550 may include: forming a conductive material layer 550-2 on the surface of the second insulating dielectric layer 45; and forming an insulating filling layer 550-1 on the surface of the conductive material layer 550-2 to fill the remaining space of the contact hole (or the first opening).

[0148] The finally formed capacitor contact structure 500 may include a plurality of capacitor structures, for example Figure 1 A capacitor contact structure 500 including two capacitor structures is shown, wherein the first conductive layer 530, the first insulating dielectric layer 34 and the second conductive layer 540 can form a first capacitor structure; the second conductive layer 540, the second insulating dielectric layer 45 and the third conductive layer 550 can form a second capacitor structure. In a plurality of capacitor structures arranged in sequence from the outside to the inside, the innermost conductive layer can be a composite structure. The innermost conductive layer can include a conductive material layer and an insulating filling layer surrounded by the conductive material layer. Through the above arrangement, the manufacturing cost of the semiconductor device can be reduced and the stress deformation of the stacked structure caused by the capacitor contact structure can be reduced.

[0149] Optionally, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to sequentially form a conductive material layer 550-2 and an insulating filling layer 550-1 on the surface of the second insulating dielectric layer 45, wherein the insulating filling layer 550-1 fills the remaining space of the contact hole (or the first opening).

[0150] Alternatively, the conductive material forming the third conductive layer 550 may be the same as the conductive material forming the second conductive layer 540 .

[0151] In addition, the material forming the insulating filling layer 550-1 may be a dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride. Optionally, the material of the insulating filling layer 550-1 is the same as the material of the second insulating dielectric layer 45; or the material of the insulating filling layer 550-1, the material of the first insulating dielectric layer 34, and the material of the second insulating dielectric layer 45 are all the same.

[0152] Optionally, in order to simplify the preparation process and save preparation costs, the same process and the same material may be used to form multiple conductive layers included in the capacitor contact structure 500, such as the second conductive layer, the third conductive layer, etc. On this basis, the first conductive layer 530 and the second conductive layer 540 may have the same thickness; or, the second conductive layer 540 and the third conductive layer 550 may have the same thickness; or, the first conductive layer 530, the second conductive layer 540 and the third conductive layer 550 may all have the same thickness.

[0153] Fig.11 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0154] like Fig.11 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0155] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0156] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0157] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0158] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0159] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A semiconductor device, characterized in that: include: A stacked structure comprising a first dielectric layer and a gate layer that are alternately stacked; as well as The capacitor contact structure includes, from outside to inside, a first conductive layer, a first insulating dielectric layer, and a second conductive layer. The first conductive layer extends in the stacked structure along the stacking direction and is connected to the corresponding gate layer.

2. The semiconductor device according to claim 1, wherein The capacitor contact structure further includes a third conductive layer and a second insulating medium layer located between the second conductive layer and the third conductive layer.

3. The semiconductor device according to claim 1, wherein The first conductive layer includes a first portion and a second portion connected to each other, wherein the first portion extends in the stacking structure along the stacking direction; and The second portion extends in a plane perpendicular to the stacking direction and connects the first portion and the corresponding gate layer.

4. The semiconductor device according to claim 3, wherein: The capacitor contact structure further includes a sidewall barrier layer, and the sidewall barrier layer is located between the stacked structure and the first portion.

5. The semiconductor device according to claim 3, wherein: In a plane perpendicular to the stacking direction, a projection of the second portion covers a projection of the first portion.

6. The semiconductor device according to claim 3, wherein: In a plane perpendicular to the stacking direction, a projection of the first portion is annular.

7. The semiconductor device according to claim 1, wherein The first insulating medium layer covers the surface of the first conductive layer; as well as The second conductive layer covers the surface of the first insulating medium layer, Wherein, an extension length of the first conductive layer in the stacking direction is greater than an extension length of the second conductive layer in the stacking direction.

8. The semiconductor device according to claim 2, wherein: The third conductive layer includes a conductive material layer and an insulating filling layer surrounded by the conductive material layer.

9. The semiconductor device according to claim 2, wherein: The second conductive layer includes at least one of a semiconductor material layer and a metal material layer; and / or The third conductive layer includes at least one of a semiconductor material layer and a metal material layer.

10. The semiconductor device according to claim 2, wherein: The first conductive layer and the second conductive layer have the same thickness; and / or The second conductive layer and the third conductive layer have the same thickness.

11. The semiconductor device according to claim 2, wherein: The second conductive layer and the third conductive layer include the same material.

12. The semiconductor device according to claim 1, wherein The stacked structure includes a storage area and a connection area adjacently distributed in a plane perpendicular to the stacking direction, wherein the gate layer extends from the storage area into the connection area, and the connection area also includes a second dielectric layer alternately stacked with the first dielectric layer, Wherein, the first conductive layer penetrates through a plurality of the second dielectric layers along the stacking direction in the connection region and is connected to the corresponding gate layer.

13. A method for preparing a semiconductor device, characterized in that: The method comprises: forming a stacked structure, the stacked structure comprising first dielectric layers and gate layers stacked alternately; and Forming a capacitive contact structure, The capacitor contact structure includes, from outside to inside, a first conductive layer, a first insulating dielectric layer, and a second conductive layer. The first conductive layer extends in the stacked structure along a stacking direction and is connected to a corresponding gate layer.

14. The method according to claim 13, wherein: Forming a laminate structure includes: Alternately stacking the first dielectric layer and the second dielectric layer to form a stacked structure; removing a portion of the second dielectric layer to form a sacrificial gap; and The gate layer is formed in the sacrificial gap.

15. The method according to claim 14, wherein: The stacking structure includes a predetermined storage area and a predetermined connection area adjacently distributed in a plane perpendicular to the stacking direction, and forming the sacrificial gap includes: Forming a gate line gap penetrating the stacked structure along the stacking direction, wherein the gate line gap includes a first gap located in the predetermined storage area and a second gap located in the predetermined connection area; Filling the first gap, and removing a portion of the second dielectric layer based on the second gap to form a first gap; exposing the first gap, and filling the second gap and the first void; and Based on the exposed first gap, continue to remove part of the second dielectric layer to form a second gap, The first gap and the second gap that are connected to each other are formed as the sacrificial gap.

16. The method according to claim 14, wherein: Forming a capacitive contact structure includes: forming a first opening of the second dielectric layer extending along the stacking direction to a predetermined stacking height; forming a sidewall barrier layer on the sidewall of the first opening; removing a portion of the second dielectric layer in contact with a bottom of the first opening to form a second opening; and The first conductive layer, the first insulating dielectric layer and the second conductive layer are sequentially formed in the first opening and the second opening.

17. The method according to claim 16, wherein: The method further comprises: A second insulating dielectric layer and a third conductive layer are sequentially formed on the surface of the second conductive layer.

18. The method according to claim 17, wherein: The second conductive layer is formed by using at least one of a semiconductor material and a metal material; and / or The third conductive layer is formed by using at least one of a semiconductor material and a metal material.

19. The method according to claim 17, wherein: Forming the third conductive layer includes: forming a conductive material layer on a surface of the second insulating dielectric layer; and An insulating filling layer is formed on the surface of the conductive material layer to fill the remaining space of the first opening.

20. A storage system, characterized in that: include: Controller; as well as The semiconductor device according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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