Silicon controlled rectifier device and manufacturing method thereof
By designing the structure of a single crystal substrate, heavily doped region, first doped region and mesa trench in a thyristor device, the problem of insufficient forward voltage resistance is solved, and higher forward resistance is achieved Voltage capacity and electric field dispersion effect.
Patent Information
- Application Number
- CN202411431074.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-01-14
AI Technical Summary
The forward voltage withstandability of existing thyristor devices is low, which is difficult to meet the actual application requirements. At the same time, the forward voltage withstandability is improved while ensuring parameters such as surge capacity, conduction voltage drop, IGT, dv/dt, IH, etc. ability.
The structural design of a single crystal substrate, a heavily doped region, a first doped region and a mesa trench is adopted, wherein the angle at which the mesa trench and the heavily doped region and the first doped region is an acute angle, and the first doped region is The doping concentration of the complex region gradually decreases along the edge direction, forming an electric field buffer to improve the forward voltage withstandability.
By dispersing the electric field strength and forming an electric field buffer zone, the forward voltage withstandability of the thyristor device is significantly improved, the electric field concentration is reduced, and the critical electric field strength is enhanced.
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Figure CN119317127A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a thyristor device and a method for manufacturing the same. Background Art
[0002] Silicon Controlled Rectifier (SCR) is a high-power semiconductor device with four layers (P1N1P2N2) and three PN junctions. SCR can control high-power circuits through low-power control signals to achieve efficient power management and regulation.
[0003] However, most thyristor devices in related technologies use a single-table structure, which has a high reverse withstand voltage capability but a low forward withstand voltage capability, which does not meet the actual application requirements. Therefore, how to improve the forward withstand voltage capability of thyristor devices while ensuring the surge capability, on-state voltage drop, IGT, dv / dt, IH and other parameters has become a problem that people in this field need to solve urgently. Summary of the invention
[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a thyristor device and a method for manufacturing the same.
[0005] In a first aspect, an embodiment of the present application provides a thyristor device, wherein the thyristor device comprises:
[0006] A single crystal substrate, the single crystal substrate comprising a first surface and a second surface opposite to each other;
[0007] A heavily doped region, the heavily doped region being located at a peripheral edge of the single crystal substrate;
[0008] a first doping region, wherein the first doping region is located on the second surface, and a doping concentration of the first doping region gradually decreases along a direction approaching an edge of the first doping region;
[0009] A mesa groove is located on the second surface of the single crystal substrate, and the mesa groove is arranged around the first doped region, wherein the angle between the edge of the intersection of the first doped region and the mesa groove and the edge of the mesa groove is an acute angle.
[0010] In a possible implementation, the thyristor device further includes a second doping region, a third doping region and a fourth doping region;
[0011] The second doped region is located on the first surface, and the second doped region is connected to the heavily doped region;
[0012] The third doping region is located on the first surface, the fourth doping region is located on a side of the first doping region away from the first surface, and the orthographic projection of the fourth doping region on the first surface is located within the orthographic projection of the first doping region on the first surface.
[0013] In one possible implementation, the doping type of the third doping region and the fourth doping region is the same as the doping type of the single crystal substrate, and the doping type of the first doping region and / or the second doping region is opposite to the doping type of the third doping region and / or the fourth doping region.
[0014] In a possible implementation, the fourth doping region includes a first sub-region and a second sub-region that are spaced apart from each other;
[0015] The thyristor device also includes a first electrode located on the first surface, and a second electrode and a third electrode located on the second surface and insulated from each other, wherein the orthographic projection of the second electrode on the first surface is within the orthographic projection of the first sub-region on the first surface, and the orthographic projection of the third electrode on the first surface is within the orthographic projection of the second sub-region on the first surface.
[0016] In a possible implementation manner, the thyristor device further includes a glass passivation layer, and the glass passivation layer is located in the mesa groove.
[0017] In a second aspect, an embodiment of the present application further provides a method for manufacturing a thyristor device, the method comprising:
[0018] Providing a single crystal substrate, the single crystal substrate comprising a first surface and a second surface opposite to each other;
[0019] Forming a silicon oxide layer on the first surface and the second surface respectively, wherein the silicon oxide layer at least partially exposes the edge of the single crystal substrate, and performing aluminum diffusion on the single crystal substrate based on the silicon oxide layer to introduce doping impurities that form a heavily doped region;
[0020] forming at least one annular masking layer on the second surface;
[0021] Performing a second doping type diffusion on the single crystal substrate to form a heavily doped region located at a peripheral edge of the single crystal substrate and a first doped region located at the second surface, wherein the heavily doped region and the first doped region respectively form doped region edges with a slope in the area covered by the masking layer, and the doping concentration of the first doped region gradually decreases along a direction close to the edge of the first doped region;
[0022] Based on the masking layer, a mesa groove is made to intersect with the edges of the heavily doped region and the first doped region respectively, wherein in the direction in which the radius of the masking layer gradually increases, the width of the mesa groove is smaller than the width of the masking layer, and the angle between the edge of the first doped region and the edge of the mesa groove is an acute angle.
[0023] In a possible implementation manner, the step of forming at least one annular masking layer on the second surface includes:
[0024] Performing field oxidation on the single crystal substrate to form an oxide layer on the surface of the single crystal substrate;
[0025] The front active region of the single crystal substrate is photolithographically processed, and the oxide layer is etched to form a ring-shaped masking layer on one side surface of the single crystal substrate.
[0026] In a possible implementation, the step of forming a mesa groove intersecting with an edge of the heavily doped region and an edge of the first doped region respectively based on the masking layer includes:
[0027] A photoresist layer is formed on a surface of one side of the single crystal substrate on which the masking layer is formed and on a side of the masking layer away from the single crystal substrate;
[0028] Expose and develop the photoresist to obtain a photoresist layer that exposes at least a portion of the masking layer;
[0029] The mask layer region exposed by the photoresist layer is etched to obtain a mesa groove intersecting with the edge of the heavily doped region and the edge of the first doped region respectively.
[0030] In a possible implementation, before the step of forming mesa grooves respectively intersecting the heavily doped region and the first doped region edge based on the masking layer, the method further includes:
[0031] A third doping region having the same doping type as the single crystal substrate is fabricated on the first surface, and a fourth doping region having the same doping type as the single crystal substrate is fabricated on a side of the first doping region away from the first surface.
[0032] In a possible implementation, the fourth doped region includes a first sub-region and a second sub-region, and after the step of forming a mesa groove intersecting the edge of the heavily doped region and the edge of the first doped region respectively based on the masking layer, the method further includes:
[0033] Applying glass powder in the mesa groove, and sintering the mesa groove coated with the glass powder to form a glass passivation layer;
[0034] A second electrode and a third electrode insulated from each other are formed on the second surface, wherein the orthographic projection of the second electrode on the first surface is located within the orthographic projection of the first sub-region on the first surface, and the orthographic projection of the third electrode on the first surface is located within the orthographic projection of the second sub-region on the first surface;
[0035] Metal deposition is performed on the single crystal substrate, and a first electrode is manufactured on the first surface.
[0036] Based on any one of the above aspects, the thyristor device and its manufacturing method provided in the embodiment of the present application include a heavily doped region, a first doped region and a mesa groove. The mesa groove intersects with the heavily doped region and the first doped region respectively, and the angle between the edge of the intersection of the first doped region and the mesa groove and the central axis of the mesa groove is an acute angle, that is, the edge of the mesa groove and the edge of the first doped region are at a positive bevel angle. When the thyristor device is forward biased, the positive bevel structure is conducive to dispersing the electric field strength and reducing the electric field concentration, thereby improving the forward withstand voltage capability. In addition, the doping concentration of the first doped region gradually decreases in the direction close to the edge of the first doped region, that is, the doping concentration at the junction of the first doped region and the mesa groove is different from the doping concentration at the position with the same junction depth. In this way, when the thyristor device is forward biased, an electric field buffer zone can be formed to increase the critical electric field strength and improve the forward withstand voltage capability. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0038] Figure 1 A schematic diagram of the structure of a thyristor device in the prior art;
[0039] Figure 2 A possible structural diagram of the thyristor device provided in this embodiment Figure 1 ;
[0040] Figure 3 A possible structural diagram of the thyristor device provided in this embodiment Figure 2 ;
[0041] Figure 4 A possible structural diagram of the thyristor device provided in this embodiment Figure 3 ;
[0042] Figure 5A schematic flow chart of a method for manufacturing a thyristor device provided in this embodiment;
[0043] Figure 6 for Figure 5 The corresponding process diagram;
[0044] Figure 7 Another schematic flow chart of the method for manufacturing the thyristor device provided in this embodiment. DETAILED DESCRIPTION
[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0048] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0049] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0050] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0051] In some related methods, by increasing the width and depth of the front trench corrosion terminal, the forward voltage withstand capability of the thyristor can be improved to a certain extent without expanding the chip area. However, due to the reduction in the size of the active area, it may lead to problems such as increased on-state voltage drop of the thyristor device, reduced surge capability, and significantly increased cost. In addition, due to the limitation of the process level, the groove depth and groove width cannot exceed the limit value.
[0052] In other related methods, the forward withstand voltage capability is increased by adding SIPOS passivation film, which can also improve the forward withstand voltage capability of thyristors to a certain extent. However, this method may cause the problem of large leakage current at high temperature, and is easily restricted by other factors such as trench size and concentration. The forward withstand voltage capability cannot be further improved, and the forward and reverse withstand voltage consistency cannot be maintained.
[0053] In other related methods, the forward voltage withstand capability is improved by changing the temperature and time of the phosphorus main expansion. However, since the phosphorus main expansion conditions are strongly related to the thyristor's IGT, IH, dv / dt and other parameters, the thyristor's triggering parameters may exceed the control value.
[0054] After analyzing the manufacturing process and structure of the thyristor device, the inventors found that the thyristor device in the related art includes a mesa groove 140, a heavily doped region 120, and a first doped region 130, wherein the edge of the first doped region 130 is substantially parallel to the edge of the mesa groove 140. Figure 1 The negative bevel angle θ shown 1 , which means that the electric field distribution of the first doped region 130 is not uniform enough. When forward biased, the electric field strength in some areas may be too high, thereby reducing the forward withstand voltage capability of the thyristor device. In addition, the inventors also found that the heavily doped region 120 and the first doped region 130 are usually realized by a single boron diffusion, and the boron concentration at the intersection edge of the first doped region 130 and the mesa groove 140 is no different from other positions with the same junction depth. This means that during forward withstand voltage, the electric field is mainly concentrated at the intersection edge of the first doped region 130 and the mesa groove 140, which is not conducive to the forward withstand voltage capability.
[0055] To solve the above problems, please refer to Figure 2The embodiment of the present application provides a thyristor device 10, including a single crystal substrate 110, a heavily doped region 120, a first doped region 130 and a mesa groove 140. The single crystal substrate 110 includes a first surface 110A and a second surface 110B opposite to each other, and the single crystal substrate 110 may include an N-type single crystal substrate or a P-type single crystal substrate. By way of example, the single crystal substrate 110 is an N-type single crystal substrate, and its thickness may be 200 μm-250 μm, and its resistivity may be 30 Ω·cm-40 Ω·cm.
[0056] The heavily doped region 120 is located on the first surface 110A and the peripheral edge of the single crystal substrate 110, the first doped region 130 is located on the second surface 110B, the mesa groove 140 is located on the second surface 110B of the single crystal substrate 110, and the mesa groove 140 is arranged around the first doped region 130. It should be noted that the doping type of the heavily doped region 120 and the first doped region 130 is different from the doping type of the single crystal substrate 110, and the edges of the heavily doped region 120 and the first doped region 130 form a first PN junction and a second PN junction with the single crystal substrate 110, respectively.
[0057] In the above structure, the mesa groove 140 intersects the heavily doped region 120 and the first doped region 130 respectively, and the angle θ between the edge of the intersection of the first doped region 130 and the mesa groove 140 and the edge of the mesa groove 140 is 2 The first doping region 130 has an acute angle, that is, the edge of the mesa groove 140 and the edge of the first doping region 130 form a positive bevel angle. When the thyristor device 10 is forward biased, the positive bevel angle structure is conducive to dispersing the electric field strength and reducing the electric field concentration, thereby improving the forward withstand voltage capability. In addition, the doping concentration of the first doping region 130 gradually decreases along the direction close to the edge of the first doping region 130, that is, the doping concentration at the junction of the first doping region 130 and the mesa groove 140 is different from the doping concentration at the position with the same junction depth. In this way, when the thyristor device 10 is forward biased, an electric field buffer zone can be formed to increase the critical electric field strength and improve the forward withstand voltage capability.
[0058] For some possible embodiments, please refer to Figure 3The thyristor device 10 further includes a second doping region 150, a third doping region 160, and a fourth doping region 170. The second doping region 150 is located on the first surface 110A, and the second doping region 150 is connected to the heavily doped region 120. The third doping region 160 is located on the first surface 110A, and the second doping region 150 surrounds the third doping region 160. The fourth doping region 170 is located on a side of the first doping region 130 away from the heavily doped region 120, and the orthographic projection of the fourth doping region 170 on the first surface 110A is located within the orthographic projection of the first doping region 130 on the first surface 110A. The doping type of the third doping region 160 and the fourth doping region 170 is the same as the doping type of the single crystal substrate 110, and opposite to the doping type of the first doping region 130 and / or the second doping region 150, wherein the single crystal substrate 110, the first doping region 130 and the fourth doping region 170 can form a double-layer structure of PNP or NPN, so that the thyristor device 10 is turned on when forward biased and blocked when reverse biased. Exemplarily, the single crystal substrate 110 may include an N-type single crystal substrate, the first doping region 130 and the second doping region 150 may be P-type doped, and the third doping region 160 and the fourth doping region 170 may be N-type doped.
[0059] For further information, please refer to Figure 4 The fourth doped region 170 includes a first sub-region 171 and a second sub-region 172 that are spaced apart. The thyristor device 10 also includes a first electrode T1 located on the first surface 110A, and an oxide layer 190, a second electrode T2, and a third electrode G located on the second surface 110B. The second electrode T2 and the third electrode G may be insulated from each other by the oxide layer 190. The orthographic projection of the second electrode T2 on the first surface 110A is located within the orthographic projection of the first sub-region 171 on the first surface 110A. The orthographic projection of the third electrode G on the first surface 110A is located within the orthographic projection of the second sub-region 172 on the first surface 110A. The first electrode T1 may be an anode, the second electrode T2 may be a cathode, and the third electrode G may be a gate.
[0060] Furthermore, the thyristor device 10 also includes a glass passivation layer 180 located in the mesa groove 140. The glass passivation layer 180 can not only effectively improve the surface defects of the side walls of the mesa groove 140, but also prevent external contaminants (such as moisture, dust and chemical impurities, etc.) from invading the interior of the device through the side walls of the mesa groove 140, thereby reducing the impact of the environment on the device performance.
[0061] Based on the same inventive concept, the present application also provides a method for manufacturing a thyristor device. For details, please refer to Figure 5 and Figure 6 , Figure 5 A schematic diagram of a process for manufacturing a thyristor device provided in this application, Figure 6 for Figure 5 The corresponding process is drawn, and the following will be combined Figure 5 and Figure 6 The method is described in detail.
[0062] Step S110: providing a single crystal substrate.
[0063] In this step, an N-type single crystal substrate or a P-type single crystal substrate can be selected, and the single crystal substrate 110 includes a first surface 110A and a second surface 110B opposite to each other. For example, an N-type single crystal substrate with a thickness of 200 μm-250 μm and a resistivity of 30 Ω·cm-40 Ω·cm can be selected.
[0064] Step S120: forming a silicon oxide layer on the first surface and the second surface respectively, the silicon oxide layer at least partially exposing the edge of the single crystal substrate, and performing aluminum diffusion on the single crystal substrate based on the silicon oxide layer to introduce doping impurities to form a heavily doped region.
[0065] In this step, the single crystal substrate 110 can be placed in SC-1 cleaning solution for cleaning to remove organic matter, particles and other contaminants on the surface of the single crystal substrate 110 to ensure the effectiveness of subsequent processes and good performance of the device. Next, the single crystal substrate 110 can be field oxidized to form a silicon oxide layer 210 on the first surface 110A and the second surface 110B, respectively, and the silicon oxide layer 210 is photolithographically processed so that the etched silicon oxide layer 210 at least partially exposes the edge of the single crystal substrate 110. After forming a specific pattern, aluminum is diffused on the single crystal substrate 110 based on the silicon oxide layer 210 to introduce doping impurities that form the heavily doped region 120, and preliminarily define the area where the heavily doped region 120 is located. For example, the introduced doping impurities can make the heavily doped region 120 P-type doped.
[0066] Step S130: forming at least one annular masking layer on the second surface.
[0067] In this step, the silicon oxide layer 210 may be removed first, and then the single crystal substrate 110 may be subjected to field oxidation to form an oxide layer on the surface of the single crystal substrate 110. Next, the single crystal substrate 110 may be subjected to front active region photolithography, and the oxide layer may be etched to form a ring-shaped masking layer 220 on one side of the single crystal substrate 110.
[0068] Step S140: performing a second doping type diffusion on the single crystal substrate to form a heavily doped region located on the first surface and the peripheral edge of the single crystal substrate, and a first doped region located on the second surface.
[0069] In this step, boron can be implanted and diffused into the single crystal substrate 110 to form a first doping region 130 located on the second surface 110B and a second doping region 150 located on the first surface 110A, and the doping impurities introduced in step 120 are diffused to a preset position to form a heavily doped region 120 located on the peripheral edge of the single crystal substrate 110, wherein the second doping region 150 intersects with the heavily doped region 120. During the diffusion process, due to the presence of the masking layer 220, the diffusion concentration of the dopant in the area where the masking layer 220 is located is low and the diffusion rate is slow, so that the heavily doped region 120 and the first doping region 130 respectively form a doping region edge with a slope in the area covered by the masking layer 220, and different levels of doping are achieved, that is, the doping concentration of the first doping region 130 gradually decreases along the direction close to the edge of the first doping region 130, and the size of the first doping region 130 gradually decreases in the direction perpendicular to the first surface 110A.
[0070] After this step, a third doping region 160 with the same doping type as the single crystal substrate 110 can be made on the first surface 110A, and a fourth doping region 170 with the same doping type as the single crystal substrate 110 can be made on the side of the first doping region 130 away from the first surface 110A, wherein the fourth doping region 170 includes a first sub-region 171 and a second sub-region 172.
[0071] Specifically, a photoresist layer may be formed on the first surface 110A and the second surface 110B, and then the cathode position may be defined, and the photoresist layer may be photolithographically exposed to expose a portion of the first surface 110A and the second surface 110B. Then, phosphorus diffusion may be performed on the single crystal substrate 110 to form a third doping region 160 on the first surface 110A and a fourth doping region 170 on the second surface 110B.
[0072] Step S150: forming at least one mesa trench intersecting with edges of the heavily doped region and the first doped region respectively based on the masking layer.
[0073] In this step, a photoresist layer can be firstly formed on the surface of one side of the single crystal substrate 110 where the masking layer is formed and on the side of the masking layer away from the single crystal substrate 110. Then, the photoresist is exposed and developed to obtain a photoresist layer that exposes at least part of the masking layer. Finally, the masking layer area exposed by the photoresist layer is etched to obtain a mesa groove 140 that intersects with the edge of the heavily doped region 120 and the edge of the first doped region 130 respectively. Among them, in the direction in which the radius of the masking layer gradually increases, the width of the mesa groove 140 is smaller than the width of the masking layer, and in the direction perpendicular to the first surface 110A, the width of the mesa groove 140 gradually increases, so that the angle θ between the edge of the first doped region 130 and the edge of the mesa groove 140 is 2It is an acute angle, that is, the edge of the mesa trench 140 and the edge of the first doped region 130 are at a positive bevel angle. When the thyristor device 10 is forward biased, the positive bevel angle structure is beneficial to disperse the electric field strength and reduce the electric field concentration, thereby improving the forward withstand voltage capability.
[0074] In this embodiment, after making an annular masking layer on the second surface 110B, the second doping type diffusion is performed on the single crystal substrate 110 to achieve different levels of doping, that is, the doping concentration of the first doping region 130 gradually decreases along the direction close to the edge of the first doping region 130, so that the doping concentration at the junction of the first doping region 130 and the subsequently made mesa groove 140 is different from the doping concentration at the position with the same junction depth. In this way, when the thyristor device 10 is forward biased, an electric field buffer zone can be formed to increase the critical electric field strength and the forward withstand voltage capability. Next, the mesa groove 140 is made based on the masking layer, so that the angle θ between the edge of the first doping region 130 and the edge of the mesa groove 140 is 2 It is an acute angle, that is, the edge of the mesa trench 140 and the edge of the first doped region 130 are at a positive bevel angle. When the thyristor device 10 is forward biased, the positive bevel angle structure is beneficial to disperse the electric field strength and reduce the electric field concentration, thereby improving the forward withstand voltage capability.
[0075] For further information, please refer to Figure 7 In addition to step S150, the method for manufacturing a thyristor provided by the present invention may further include the following steps.
[0076] Step S160: coating glass powder in the mesa groove, and sintering the mesa groove coated with the glass powder to form a glass passivation layer.
[0077] In this step, the single crystal substrate 110 may be spot cleaned, and then glass powder may be coated in the mesa groove 140 , and the mesa groove 140 coated with the glass powder may be sintered to form a glass passivation layer 180 .
[0078] Step S170: forming a second electrode and a third electrode insulated from each other on the second surface.
[0079] In this step, the second electrode T2 may be a cathode, the third electrode G may be a gate, and the orthographic projections of the second electrode T2 and the third electrode G on the first surface 110A are located within the orthographic projection of the fourth doping region 170 on the first surface 110A.
[0080] Step S180: performing metal deposition on the single crystal substrate to form a first electrode T1 on the first surface.
[0081] In this step, metal deposition may be performed on the first surface 110A to form a nickel-titanium-silver alloy layer, and the nickel-titanium-silver alloy layer may be ground to obtain a first electrode T1 , wherein the first electrode T1 may be an anode.
[0082] Step S190: when the single crystal substrate includes a plurality of mesa grooves, cutting the single crystal substrate including the plurality of mesa grooves to obtain a thyristor device including one mesa groove.
[0083] In this step, the thyristor device 10 including multiple mesa grooves 140 can be parameter tested first, and after the products with unqualified parameters are eliminated, the single crystal substrate 110 including multiple mesa grooves 140 can be cut to obtain a thyristor device 10 including one mesa groove 140.
[0084] In summary, the embodiment of the present application provides a thyristor device and a method for manufacturing the same, including a heavily doped region, a first doped region and a mesa groove. The mesa groove intersects with the heavily doped region and the first doped region respectively, and the angle between the edge of the intersection of the first doped region and the mesa groove and the central axis of the mesa groove is an acute angle, that is, the edge of the mesa groove and the edge of the first doped region are at a positive bevel angle. When the thyristor device is forward biased, the positive bevel structure is conducive to dispersing the electric field strength and reducing the electric field concentration, thereby improving the forward withstand voltage capability. In addition, the doping concentration of the first doped region gradually decreases in the direction close to the edge of the first doped region, that is, the doping concentration at the junction of the first doped region and the mesa groove is different from the doping concentration at the position with the same junction depth. In this way, when the thyristor device is forward biased, an electric field buffer zone can be formed to increase the critical electric field strength and improve the forward withstand voltage capability.
[0085] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A thyristor device, characterized in that: include: A single crystal substrate, the single crystal substrate comprising a first surface and a second surface opposite to each other; A heavily doped region, wherein the heavily doped region is located at a peripheral edge of the single crystal substrate; a first doping region, wherein the first doping region is located on the second surface, and a doping concentration of the first doping region gradually decreases along a direction approaching an edge of the first doping region; A mesa groove is located on the second surface of the single crystal substrate, and the mesa groove is arranged around the first doped region, wherein the angle between the edge of the intersection of the first doped region and the mesa groove and the edge of the mesa groove is an acute angle.
2. The thyristor device according to claim 1, characterized in that: The thyristor device further includes a second doping region, a third doping region and a fourth doping region; The second doped region is located on the first surface, and the second doped region is connected to the heavily doped region; The third doping region is located on the first surface, the fourth doping region is located on a side of the first doping region away from the first surface, and the orthographic projection of the fourth doping region on the first surface is located within the orthographic projection of the first doping region on the first surface.
3. The thyristor device according to claim 2, characterized in that: The doping type of the third doping region and the fourth doping region is the same as the doping type of the single crystal substrate, and the doping type of the first doping region and / or the second doping region is opposite to the doping type of the third doping region and / or the fourth doping region.
4. The thyristor device according to claim 3, characterized in that: The fourth doping region includes a first sub-region and a second sub-region distributed at intervals; The thyristor device also includes a first electrode located on the first surface, and a second electrode and a third electrode located on the second surface and insulated from each other, wherein the orthographic projection of the second electrode on the first surface is within the orthographic projection of the first sub-region on the first surface, and the orthographic projection of the third electrode on the first surface is within the orthographic projection of the second sub-region on the first surface.
5. The thyristor device according to claim 1, characterized in that: The thyristor device further includes a glass passivation layer, and the glass passivation layer is located in the mesa groove.
6. A method for manufacturing a thyristor device, characterized in that: The method comprises: Providing a single crystal substrate, the single crystal substrate comprising a first surface and a second surface opposite to each other; Forming a silicon oxide layer on the first surface and the second surface respectively, wherein the silicon oxide layer at least partially exposes the edge of the single crystal substrate, and performing aluminum diffusion on the single crystal substrate based on the silicon oxide layer to introduce doping impurities that form a heavily doped region; forming at least one annular masking layer on the second surface; Performing a second doping type diffusion on the single crystal substrate to form a heavily doped region located at a peripheral edge of the single crystal substrate and a first doped region located at the second surface, wherein the heavily doped region and the first doped region respectively form doped region edges with a slope in the area covered by the masking layer, and the doping concentration of the first doped region gradually decreases along a direction close to the edge of the first doped region; Based on the masking layer, a mesa groove is made to intersect with the edges of the heavily doped region and the first doped region respectively, wherein in the direction in which the radius of the masking layer gradually increases, the width of the mesa groove is smaller than the width of the masking layer, and the angle between the edge of the first doped region and the edge of the mesa groove is an acute angle.
7. The method for manufacturing a thyristor device according to claim 6, characterized in that: The step of forming at least one annular masking layer on the second surface comprises: Performing field oxidation on the single crystal substrate to form an oxide layer on the surface of the single crystal substrate; The front active region of the single crystal substrate is photolithographically processed, and the oxide layer is etched to form a ring-shaped masking layer on one side surface of the single crystal substrate.
8. The method for manufacturing a thyristor device according to claim 6, characterized in that: The step of making mesa grooves respectively intersecting with the edge of the heavily doped region and the edge of the first doped region based on the masking layer comprises: A photoresist layer is formed on a surface of one side of the single crystal substrate on which the masking layer is formed and on a side of the masking layer away from the single crystal substrate; Expose and develop the photoresist to obtain a photoresist layer that exposes at least a portion of the masking layer; The mask layer region exposed by the photoresist layer is etched to obtain a mesa groove intersecting with the edge of the heavily doped region and the edge of the first doped region respectively.
9. The method for manufacturing a thyristor device according to claim 6, characterized in that: Before the step of making mesa grooves respectively intersecting the heavily doped region and the first doped region edge based on the masking layer, the method further includes: A third doping region having the same doping type as the single crystal substrate is fabricated on the first surface, and a fourth doping region having the same doping type as the single crystal substrate is fabricated on a side of the first doping region away from the first surface.
10. The method for manufacturing a thyristor device according to claim 9, characterized in that: The fourth doped region includes a first sub-region and a second sub-region. After the step of forming a mesa groove intersecting with an edge of the heavily doped region and an edge of the first doped region based on the masking layer, the method further includes: Applying glass powder in the mesa groove, and sintering the mesa groove coated with the glass powder to form a glass passivation layer; A second electrode and a third electrode insulated from each other are formed on the second surface, wherein the orthographic projection of the second electrode on the first surface is located within the orthographic projection of the first sub-region on the first surface, and the orthographic projection of the third electrode on the first surface is located within the orthographic projection of the second sub-region on the first surface; Metal deposition is performed on the single crystal substrate, and a first electrode is manufactured on the first surface.