Two-dimensional semiconductor transistor and preparation method thereof

Abstract

The invention relates to the field of electronic devices, in particular to a two-dimensional semiconductor transistor and a preparation method thereof. The two-dimensional semiconductor transistor comprises a substrate and a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer which are sequentially arranged on the substrate, the semi-metal layer is made of bismuth or antimony, and the metal covering layer is made of aluminum, silver or copper. According to the invention, by designing and preferably selecting a proper metal type of the covering layer, the alloying reaction between the metal material of the covering layer and the semi-metal material is avoided or delayed on the basis of ensuring the excellent performance of the device, so that the device after heat treatment can still keep a semi-metal Bi / Sb-two-dimensional semiconductor contact interface; the method reduces the damage of the alloying reaction to the ohmic contact between the two-dimensional semiconductor and the electrode, improves the thermal stability of the contact of the two-dimensional semiconductor device, enables more technological processes comprising a heat treatment step to be used for producing the two-dimensional semiconductor device, and enlarges the application range of the two-dimensional semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices, and in particular to a two-dimensional semiconductor transistor and a preparation method thereof. Background Art

[0002] Two-dimensional semiconductor materials (such as molybdenum disulfide and tungsten disulfide) have great potential in the field of integrated circuits. The contact of two-dimensional semiconductor materials is an important factor affecting the performance of devices such as two-dimensional semiconductor transistors. Due to the matching interface band structure, semimetals (bismuth Bi and antimony Sb) can form good ohmic contacts with two-dimensional semiconductors. Patent application CN115064588A proposes to deposit semimetal Sb or an alloy containing semimetal Sb on a two-dimensional semiconductor layer to form an ohmic contact structure. Semimetal Sb, as a contact electrode, has a strong van der Waals interaction and band hybridization with the two-dimensional semiconductor, realizing barrier-free carrier transmission at the contact interface; Sb has a high melting point and stability, which can enhance the reliability and stability of the device.

[0003] However, since semimetals (Bi and Sb) have low electrical conductivity and are easily oxidized, a gold (Au) capping layer with higher electrical conductivity is usually added to the semimetal material to form a two-dimensional semiconductor-semimetal-gold stacking junction as the contact of the two-dimensional semiconductor transistor device. Many previous studies have found that the thermal stability of the two-dimensional semiconductor-semimetal-gold stacking structure is poor, and the contact performance of the device will decrease after heat treatment. X-ray diffraction experiments have found that the two-dimensional semiconductor-Bi-Au and two-dimensional semiconductor-Sb-Au stacking structures can undergo alloying reactions at temperatures below the melting point of the semimetal (bismuth melting point: 271.5°C, antimony melting point: 630.6°C) to generate Au2Bi and AuSb2, turning the semimetal Bi / Sb-two-dimensional semiconductor contact interface into Au2Bi / AuSb2-two-dimensional semiconductor contact interface, thereby destroying the ohmic contact between the semimetal and the two-dimensional semiconductor. Two-dimensional semiconductor devices usually need to go through many process flows including heat treatment steps, so it is necessary to solve the problem of poor thermal stability of two-dimensional semiconductor devices caused by the easy alloying reaction of gold (Au) covering layer materials with semi-metal (Bi and Sb) materials. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a two-dimensional semiconductor transistor and a method for preparing the same, aiming to solve the problem of poor thermal stability of two-dimensional semiconductor devices caused by the existing gold covering layer material being easily alloyed with semi-metal (Bi and Sb) materials.

[0005] The technical solution of the present invention is as follows:

[0006] According to a first aspect of the present invention, a two-dimensional semiconductor transistor is provided, which comprises a substrate and a two-dimensional semiconductor layer, a semi-metal layer, and a metal covering layer sequentially arranged on the substrate, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver, or copper.

[0007] Optionally, the thickness of the semi-metal layer is 10nm-100nm, and the thickness of the metal covering layer is 5nm-100nm.

[0008] Optionally, the two-dimensional semiconductor transistor comprises a conductive metal layer, and the conductive metal layer is arranged on a side of the metal cover layer away from the semi-metal layer.

[0009] Optionally, the material of the conductive metal layer is aluminum, silver or copper, and the material of the conductive metal layer is different from that of the metal covering layer.

[0010] Optionally, the thickness of the conductive metal layer is 5nm-100nm.

[0011] A second aspect of the present invention provides a method for preparing a two-dimensional semiconductor transistor, comprising:

[0012] providing a substrate having a two-dimensional semiconductor layer;

[0013] A semi-metal layer and a metal covering layer are sequentially deposited on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver or copper, to obtain the two-dimensional semiconductor transistor.

[0014] Optionally, after the step of sequentially depositing a semi-metal layer and a metal covering layer on the two-dimensional semiconductor layer, the method further includes the step of depositing a conductive metal layer on a side of the metal covering layer away from the semi-metal layer.

[0015] Optionally, the semi-metal layer and the metal covering layer are deposited by electron beam vacuum coating technology, wherein the vacuum degree is less than or equal to 1×10 -4 Pa.

[0016] Optionally, the method for preparing the two-dimensional semiconductor transistor further includes:

[0017] Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, a photoresist is coated on the two-dimensional semiconductor layer, and a preset patterning process is performed on the two-dimensional semiconductor layer by a photolithography process;

[0018] After the steps of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

[0019] Beneficial effect: The present invention avoids or delays the alloying reaction between the covering layer metal material and the semi-metal material while ensuring the excellent performance of the device by designing and selecting a suitable covering layer metal type, so that the device can still maintain the semi-metallic Bi / Sb-two-dimensional semiconductor contact interface after heat treatment, reduces the damage of the alloying reaction to the ohmic contact between the two-dimensional semiconductor and the electrode, improves the thermal stability of the contact of the two-dimensional semiconductor device, and enables more process flows including heat treatment steps to be used for the production of two-dimensional semiconductor devices, thereby expanding the application range of two-dimensional semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic structural diagram of a two-dimensional semiconductor transistor provided by the present invention.

[0021] Figure 2 A schematic flow chart of a method for preparing a two-dimensional semiconductor transistor provided by the present invention.

[0022] Figure 3 A schematic diagram of a process flow for preparing a two-dimensional semiconductor transistor provided by the present invention.

[0023] Figure 4 This is the XRD image of the Bi / Au contact structure of the MoS2 transistor in Comparative Example 1 after thermal annealing at 150°C.

[0024] Figure 5 Output characteristic curves of the MoS2 transistors in Example 1 and Comparative Example 1 before and after thermal annealing at 150°C.

[0025] Figure 6 This is the XRD image of the Sb / Al contact structure of the MoS2 transistor in Example 2 after thermal annealing at 200°C.

[0026] Figure 7 This is the XRD image of the Sb / Au contact structure of the MoS2 transistor in Comparative Example 2 after thermal annealing at 100°C. DETAILED DESCRIPTION

[0027] The present invention provides a two-dimensional semiconductor transistor and a method for manufacturing the same. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] According to one embodiment of the present invention, a two-dimensional semiconductor transistor is provided, which includes a substrate and a two-dimensional semiconductor layer, a semi-metal layer, and a metal covering layer sequentially arranged on the substrate, the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver, or copper.

[0029] In order to solve the technical problem that the devices of the two-dimensional semiconductor-semimetal (Bi / Sb)-gold stacking structure in the prior art have poor thermal stability, the embodiments of the present invention design and select suitable types of covering layer metals to replace gold in the prior art with aluminum, silver or copper, wherein aluminum, silver or copper has high electrical conductivity, good electrical conductivity, and is not easy to form alloys with semimetals (Bi / Sb). Therefore, on the basis of ensuring the excellent performance of the device, the alloying reaction between the covering layer metal material and the semimetal material is avoided, so that after heat treatment, the device can still maintain the semimetal Bi / Sb-two-dimensional semiconductor contact interface, reduce the damage of the alloying reaction to the ohmic contact between the two-dimensional semiconductor and the electrode, improve the thermal stability of the contact of the two-dimensional semiconductor device, and enable more process flows including heat treatment steps to be used for the production of two-dimensional semiconductor devices, thereby expanding the application range of two-dimensional semiconductor devices.

[0030] According to a preferred embodiment of the present invention, the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum.

[0031] In this embodiment, the material of the metal covering layer is aluminum, which can naturally form a thin and dense oxide layer in the air, thereby reducing the parasitic resistance of the device and preventing the oxidation of the semi-metal layer.

[0032] According to one embodiment of the present invention, the material of the two-dimensional semiconductor layer can be selected from two-dimensional materials commonly used in the prior art, preferably two-dimensional materials such as MoS2, WSe2, WS2, etc., but not limited thereto.

[0033] According to one embodiment of the present invention, the thickness of the semi-metal layer is 10nm-100nm, for example, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc. Within this thickness range, the thickness of the device can be reduced while maintaining good contact between the semi-metal and the two-dimensional material interface, which is conducive to forming a low contact resistance and improving the integration.

[0034] According to one embodiment of the present invention, the thickness of the metal covering layer is 5nm-100nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc. Within this thickness range, the metal covering layer can well reduce the parasitic resistance and prevent the oxidation of the semi-metal layer, which is beneficial to improving the on-state current, oxidation resistance and integration of the device.

[0035] According to one embodiment of the present invention, the two-dimensional semiconductor transistor includes a conductive metal layer, which is arranged on a side of the metal cover layer away from the semi-metal layer. The conductive metal layer is made of a conductive metal material with high conductivity, which may be aluminum, silver or copper, preferably aluminum, and the material of the conductive metal layer is different from that of the metal cover layer.

[0036] In the embodiment of the present invention, a conductive metal layer is disposed on the metal covering layer. The conductive metal layer can further reduce the parasitic resistance of the device and prevent oxidation of the semi-metal layer in contact with the two-dimensional material, which is beneficial to improving the on-state current and stability of the device.

[0037] According to one embodiment of the present invention, the thickness of the conductive metal layer is 5nm-100nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc. Within this thickness range, the parasitic resistance of the device can be effectively reduced, the semi-metal layer can be prevented from being oxidized, and the thickness of the device can be reduced, which is beneficial to improving the on-state current, stability and integration of the device.

[0038] According to one embodiment of the present invention, after the two-dimensional semiconductor transistor is subjected to heat treatment, a semi-metal material-two-dimensional semiconductor material contact interface is maintained between the semi-metal layer and the two-dimensional semiconductor layer.

[0039] In the two-dimensional semiconductor transistor in an embodiment of the present invention, the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver or copper. After heat treatment, the material of the semi-metal layer and the material of the metal covering layer will not undergo alloying reaction, thereby being able to maintain the semi-metal material-two-dimensional semiconductor material contact interface, and forming a good ohmic contact between the semi-metal layer and the two-dimensional semiconductor layer, thereby improving the thermal stability of existing two-dimensional semiconductor devices.

[0040] According to one embodiment of the present invention, a method for preparing a two-dimensional semiconductor transistor is provided, comprising:

[0041] providing a substrate having a two-dimensional semiconductor layer;

[0042] A semi-metal layer and a metal covering layer are sequentially deposited on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver or copper, to obtain the two-dimensional semiconductor transistor.

[0043] In the present invention, the two-dimensional semiconductor layer can be obtained by transferring to a substrate or growing directly on the surface of a substrate. The transfer or direct growth of two-dimensional semiconductor materials are both conventional techniques in the art and are not limited here. For example, the transfer of two-dimensional semiconductor materials can use a mechanical stripping method to strip and transfer two-dimensional semiconductor materials (MoS2, WSe2, WS2) on a substrate; or use a mechanical transfer method to transfer a single layer of two-dimensional semiconductor material grown by chemical vapor deposition (CVD) on a substrate.

[0044] According to one embodiment of the present invention, the deposition of the semi-metal layer and the metal covering layer may adopt a coating technology commonly used in the art, such as thermal evaporation coating technology, magnetron sputtering coating technology, electron beam vacuum coating technology, etc.

[0045] According to a preferred embodiment of the present invention, the semi-metal layer and the metal cover layer are deposited by electron beam vacuum coating technology, wherein the vacuum degree is less than or equal to 1×10 -4 Pa.

[0046] According to one embodiment of the present invention, after the step of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the step further includes: depositing a conductive metal layer on a side of the metal capping layer away from the semi-metal layer.

[0047] According to one embodiment of the present invention, a method for preparing a two-dimensional semiconductor transistor is provided, comprising:

[0048] providing a substrate having a two-dimensional semiconductor layer;

[0049] A semi-metal layer, a metal covering layer and a conductive metal layer are sequentially deposited on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver or copper, to obtain the two-dimensional semiconductor transistor.

[0050] According to one embodiment of the present invention, the method for preparing the two-dimensional semiconductor transistor further includes:

[0051] Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, a photoresist is coated on the two-dimensional semiconductor layer, and a preset patterning process is performed on the two-dimensional semiconductor layer by a photolithography process;

[0052] After the steps of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

[0053] In the present invention, photoresist and photolithography can be used to prepare photolithography patterns at specific locations of a substrate having a two-dimensional semiconductor layer according to specific needs. The specific shape of the photolithography pattern can be set according to actual needs, and the specific shape is not limited here. After the steps of sequentially depositing a semi-metal layer and a covering layer on the two-dimensional semiconductor layer, it is necessary to remove the photoresist on the two-dimensional semiconductor layer to form a preset graphical semi-metal layer and covering layer. Using photoresist and photolithography (such as optical lithography, electron beam lithography and other technologies) to pattern the two-dimensional semiconductor layer, and subsequently removing the photoresist are all conventional techniques in the art and are not limited here.

[0054] Combination Figure 1 , Figure 2 and Figure 3 As shown, the present invention provides a two-dimensional semiconductor transistor and a method for manufacturing the same, comprising:

[0055] A substrate having a two-dimensional semiconductor layer is provided, and the two-dimensional semiconductor layer is patterned by using a photoresist and a photolithography process. Then, a semi-metal material is deposited on the two-dimensional semiconductor layer to form a semi-metal layer, and a covering layer material is deposited on the semi-metal layer to form a metal covering layer. Finally, the photoresist is removed to obtain the two-dimensional semiconductor transistor of the present invention.

[0056] The present invention will be further described below by means of specific examples.

[0057] Example 1

[0058] This embodiment provides a method for preparing a MoS2 transistor having a Bi / Al contact interface, which is as follows:

[0059] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. MoS2 was prepared on the substrate by mechanical stripping. On the substrate with the MoS2 layer, a photoresist with a thickness of about 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and the film was dried and fixed. The preset electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Under a vacuum degree of 1.5 Pa, a Bi film (20 nm thick) and an Al film (30 nm thick) were sequentially deposited to form a semi-metal layer and a metal capping layer, respectively. The photoresist was removed by a lift-off process to obtain a MoS2 transistor with a Bi / Al contact interface.

[0060] Comparative Example 1

[0061] The preparation method is the same as that of Example 1, except that a Bi film (with a thickness of 20 nm) and an Au film (with a thickness of 30 nm) are sequentially deposited to replace the Bi film and the Al film in Example 1 to form a semi-metallic layer and a metal covering layer, thereby obtaining a MoS2 transistor with a Bi / Au contact interface.

[0062] The MoS2 transistor with the Bi / Al contact interface prepared in Example 1 is subjected to thermal annealing treatment, and the semi-metallic Bi and Al covering layers do not undergo alloying reaction, indicating that the semi-metallic material-two-dimensional semiconductor material contact interface can be maintained between the semi-metallic layer and the two-dimensional semiconductor layer to form a good ohmic contact.

[0063] The MoS2 transistor with Bi / Au contact interface prepared in Comparative Example 1 was subjected to thermal annealing at 150°C. Figure 4 This is the XRD image of the Bi / Au contact structure of the MoS2 transistor in Comparative Example 1 after thermal annealing at 150°C. Figure 4 It can be seen that the semi-metal Bi and the Au covering layer undergo an alloying reaction to generate Au2Bi, which transforms the semi-metal Bi-two-dimensional semiconductor contact interface into an Au2Bi-two-dimensional semiconductor contact interface, thereby destroying the ohmic contact between the semi-metal and the two-dimensional semiconductor.

[0064] In addition, the MoS2 transistors prepared in Example 1 and Comparative Example 1 were annealed before and after the thermal annealing treatment using a Prospectus Fs-Pro semiconductor parameter analyzer at a base pressure of 10 -6 The electrical performance of the device is tested in Torr's closed probe station. The voltage range between the source and drain is -0.5V to 0.5V, and the gate voltage is 60V.

[0065] Figure 5 The output characteristic curves of the MoS2 transistors in Example 1 and Comparative Example 1 before and after thermal annealing at 150°C. Figure 5 It shows that the current of the MoS2 transistor with Bi(20nm) / Au(30nm) contact interface in Comparative Example 1 decreases by about 59% after annealing, while the current of the MoS2 transistor with Bi(20nm) / Al(30nm) contact interface in Example 1 increases by about 5% after annealing, which indicates that the thermal stability of the device is significantly improved.

[0066] Example 2

[0067] This embodiment provides a method for preparing a MoS2 transistor having a Sb / Al contact interface, which is as follows:

[0068] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. MoS2 was prepared on the substrate by mechanical stripping. On the substrate with the MoS2 layer, a photoresist with a thickness of about 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and the film was dried and fixed. The preset electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Under a vacuum degree of 1.5 Pa, Sb film (thickness of 20 nm) and Al film (thickness of 30 nm) were deposited in sequence to form a semi-metal layer and a metal capping layer, respectively. The photoresist was removed by a lift-off process to obtain a MoS2 transistor with a Sb / Al contact interface.

[0069] Comparative Example 2

[0070] The preparation method is the same as that of Example 2, except that Sb film (thickness is 20 nm) and Au film (thickness is 30 nm) are deposited in sequence instead of the Sb film and Al film in Example 2 to form a semi-metallic layer and a metal covering layer, thereby obtaining a MoS2 transistor with a Sb / Au contact interface.

[0071] The MoS2 transistor with Sb / Al contact interface prepared in Example 2 was subjected to thermal annealing at 200°C. Figure 6 is an XRD image of the Sb / Al contact structure of the MoS2 transistor in Example 2 after thermal annealing at 200°C. Figure 6 It can be seen that the semi-metallic Sb and Al capping layers will not undergo alloying reaction, indicating that the semi-metallic material-two-dimensional semiconductor material contact interface can be maintained between the semi-metallic layer and the two-dimensional semiconductor layer to form a good ohmic contact.

[0072] The MoS2 transistor with Sb / Au contact interface prepared in Comparative Example 2 was subjected to thermal annealing, and it was found that alloying reaction occurred at 100°C. Figure 7 This is the XRD image of the Sb / Au contact structure of the MoS2 transistor in Comparative Example 2 after thermal annealing at 100°C. Figure 7 It can be seen that the semi-metal Sb and the Au covering layer undergo an alloying reaction to generate AuSb2, which transforms the semi-metal Sb-two-dimensional semiconductor contact interface into an AuSb2-two-dimensional semiconductor contact interface, thereby destroying the ohmic contact between the semi-metal and the two-dimensional semiconductor.

[0073] Example 3

[0074] This embodiment provides a method for preparing a MoS2 transistor having a Bi / Al / Ag contact interface, which is as follows:

[0075] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. MoS2 was prepared on the substrate by mechanical stripping. On the substrate with the MoS2 layer, a photoresist with a thickness of about 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and the film was dried and fixed. The preset electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Under a vacuum degree of 1.5 Pa, a Bi film (20 nm thick), an Al film (30 nm thick), and an Ag film (30 nm thick) are sequentially deposited to form a semi-metal layer, a metal capping layer, and a conductive metal layer, respectively. The photoresist is removed by a lift-off process to obtain a MoS2 transistor with a Bi / Al / Ag contact interface.

[0076] In summary, the present invention deposits aluminum, silver or copper as a covering layer on the semi-metal bismuth or antimony in the two-dimensional semiconductor transistor. In this way, while ensuring the excellent performance of the device, the alloying reaction between the metal material of the covering layer and the semi-metal material is avoided, so that after heat treatment, the device can still maintain the semi-metal material-two-dimensional semiconductor material contact interface, reduce the damage of the alloying reaction to the ohmic contact between the two-dimensional semiconductor and the electrode, and improve the thermal stability of the contact of the two-dimensional semiconductor device.

[0077] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A two-dimensional semiconductor transistor, characterized in that: It comprises a substrate and a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer arranged in sequence on the substrate. The material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver or copper.

2. The two-dimensional semiconductor transistor according to claim 1, characterized in that: The thickness of the semi-metal layer is 10nm-100nm, and the thickness of the metal covering layer is 5nm-100nm.

3. The two-dimensional semiconductor transistor according to claim 1, characterized in that: The two-dimensional semiconductor transistor comprises a conductive metal layer, wherein the conductive metal layer is arranged on a side of the metal cover layer away from the semi-metal layer.

4. The two-dimensional semiconductor transistor according to claim 3, characterized in that: The material of the conductive metal layer is aluminum, silver or copper, and the material of the conductive metal layer is different from that of the metal covering layer.

5. The two-dimensional semiconductor transistor according to claim 3, characterized in that: The thickness of the conductive metal layer is 5nm-100nm.

6. A method for preparing a two-dimensional semiconductor transistor, characterized in that: include: providing a substrate having a two-dimensional semiconductor layer; A semi-metal layer and a metal covering layer are sequentially deposited on the two-dimensional semiconductor layer, wherein the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is aluminum, silver or copper, to obtain the two-dimensional semiconductor transistor.

7. The method for preparing a two-dimensional semiconductor transistor according to claim 6, characterized in that: After the step of sequentially depositing a semi-metal layer and a metal covering layer on the two-dimensional semiconductor layer, the method further includes the step of depositing a conductive metal layer on a side of the metal covering layer away from the semi-metal layer.

8. The method for preparing a two-dimensional semiconductor transistor according to claim 6, characterized in that: The semi-metal layer and the metal cover layer are deposited by electron beam vacuum coating technology, wherein the vacuum degree is less than or equal to 1×10 -4 Pa.

9. The method for preparing a two-dimensional semiconductor transistor according to claim 6, characterized in that: The preparation method further comprises: Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, a photoresist is coated on the two-dimensional semiconductor layer, and a preset patterning process is performed on the two-dimensional semiconductor layer by a photolithography process; After the steps of sequentially depositing a semi-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

Images