Transistor, manufacturing method and device, electronic equipment and medium

Abstract

The embodiment of the invention provides a transistor, a manufacturing method and device, electronic equipment and a medium, a gate trench is arranged on a first surface of the transistor, an auxiliary trench is arranged on a second surface of the transistor, the auxiliary trench is arranged at a position corresponding to the gate trench, and a first floating region is formed between the auxiliary trench and the gate trench. According to the embodiment of the invention, the floating region is formed through the auxiliary groove, and the current path in the transistor can be optimized, so that the electric field concentration effect is improved, the reliability of the power device is improved, and the application of the power device under higher electric field voltage is prevented from being limited.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor preparation, and in particular to a transistor and a preparation method, device, electronic equipment and medium. Background Art

[0002] In the related art, a trench gate may be provided during the preparation of an IGBT (Insulated Gate Bipolar Transistor) or a MOS (Metal-Oxide Semiconductor Field Effect Transistor) to improve the performance and efficiency of the device.

[0003] However, in actual applications, due to the bending phenomenon directly below the gate trench, the electric field concentration effect is prone to occur at this location, which makes electric field breakdown prone, and the electric field concentration effect limits the application of power devices under higher electric field voltages. Summary of the invention

[0004] In view of the above problems, a transistor and a manufacturing method, a device, an electronic device and a medium are proposed to overcome the above problems or at least partially solve the above problems, including:

[0005] A transistor, the transistor comprising a first surface and a second surface opposite to the first surface, the first surface being provided with a gate trench, the second surface being provided with an auxiliary trench, the auxiliary trench being provided at a position corresponding to the gate trench;

[0006] A first floating region is formed between the auxiliary trench and the gate trench.

[0007] Optionally, a second floating region is formed between the gate trench and the auxiliary trench.

[0008] Optionally, the auxiliary trench is filled with insulating material and / or metal material, and the thermal conductivity of the insulating material and / or metal material is greater than the thermal conductivity of the wafer material of the transistor.

[0009] Optionally, the thermal expansion coefficient of the insulating material and / or metal material is the same as the thermal expansion coefficient of the wafer material of the transistor, or the difference between the thermal expansion coefficient of the insulating material and / or metal material and the thermal expansion coefficient of the wafer material of the transistor is less than a preset difference.

[0010] Optionally, the width of the auxiliary trench is the same as the width of the gate trench.

[0011] Optionally, the depth of the auxiliary trench is determined according to the wafer thickness of the transistor, the depth of the gate trench, the depth of the first floating region, and the depth of the second floating region.

[0012] Optionally, the transistor is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.

[0013] Optionally, the method comprises: etching a gate trench on the first surface, and etching an auxiliary trench at a position corresponding to the gate trench on the second surface;

[0014] A first floating region is formed between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench.

[0015] Optionally, the method further includes: forming a second floating region between the gate trench and the auxiliary trench by performing plasma implantation inside the gate trench.

[0016] Optionally, after forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes: filling the auxiliary trench with an insulating material and / or a metal material.

[0017] Optionally, etching the second surface to obtain the auxiliary groove comprises: coating the second surface with a photoresist to obtain a photoresist coating, and etching the auxiliary groove on the basis of the photoresist coating;

[0018] After forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes:

[0019] The photoresist coating is removed.

[0020] Optionally, after forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation inside the auxiliary trench, the method further includes: activating the implanted plasma.

[0021] A transistor manufacturing device, comprising:

[0022] A trench etching control module, configured to etch a gate trench on the first surface, and to etch an auxiliary trench at a position corresponding to the gate trench on the second surface;

[0023] The ion implantation control module is used to form a first floating region between the auxiliary trench and the gate trench by performing plasma implantation inside the auxiliary trench.

[0024] An electronic device comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method described above when executed by the processor.

[0025] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0026] The embodiments of the present invention have the following advantages:

[0027] In an embodiment of the present invention, a gate trench is provided on the first side of the transistor, an auxiliary trench is provided on the second side of the transistor, and the auxiliary trench is provided at a position corresponding to the gate trench, and a first floating region is formed between the auxiliary trench and the gate trench, thereby achieving the formation of the floating region through the auxiliary trench, and then optimizing the current path in the transistor, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0029] Figure 1 is a schematic diagram of a transistor in a related art;

[0030] Figure 2 is a schematic diagram of a transistor with an auxiliary trench provided in some embodiments of the present invention;

[0031] Figure 3 is a flowchart of steps of a method for manufacturing a transistor provided by some embodiments of the present invention;

[0032] Figure 4 is a flowchart of steps of another method for manufacturing a transistor provided by some embodiments of the present invention;

[0033] Figure 5 It is a schematic diagram of the structure of a transistor manufacturing device provided in some embodiments of the present invention. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] In the related technology, a floating region is formed by performing ion implantation directly below the gate trench, thereby preventing current from breaking through the trench, thereby protecting the trench, and keeping the electric field concentration effect away from the trench gate. At the same time, the electric field concentration effect is mitigated to a certain extent. However, the depth of ion implantation is limited to a certain extent by the capability of the implantation equipment and cannot reach any depth without restriction, so the floating region has a certain position limitation.

[0036] like Figure 1 By using the trench gate technology to etch multiple trenches 1 on the front side of the transistor, ion implantation can be performed directly below the trench gate to form multiple floating regions 2 to prevent current from breaking through the trenches and protect the trenches. During the use of the transistor, the current path 5 flows from the collector to the emitter, that is, the current flows from Figure 1 Flow downward toward the groove.

[0037] However, since the depth of ion implantation is limited to a certain extent by the capability of implantation equipment and cannot reach any depth without restriction, the floating region 1 has a certain position restriction.

[0038] Therefore, in an embodiment of the present invention, it is proposed to optimize the back structure and manufacturing process of the transistor, perform trench processing and ion implantation on the back of the wafer, and then fill the back trench with insulating material with high thermal conductivity, so as to optimize the current path in the transistor and improve the electric field concentration effect, while optimizing the heat transfer inside the chip and reducing the chip junction temperature.

[0039] The present invention will be further described below in conjunction with the accompanying drawings:

[0040] Reference Figure 2 , showing a schematic diagram of a transistor provided in some embodiments of the present invention, wherein the transistor is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.

[0041] Among them, the insulated gate bipolar transistor is a high-performance power semiconductor device, which is widely used in power electronics, transportation, industrial automation and other fields. The metal-oxide semiconductor field-effect transistor is a field-effect transistor widely used in analog circuits and digital circuits, and should also be widely used in electronics, transportation, industrial automation and other fields, such as silicon carbide metal oxide semiconductor field-effect transistor (SIC-MOS).

[0042] In some embodiments of the present invention, the transistor has a first surface and a second surface opposite to the first surface, the first surface is provided with a gate trench, the second surface is provided with an auxiliary trench, and the auxiliary trench is provided at a position corresponding to the gate trench.

[0043] When using a wafer to make transistors, technicians in this field can choose to use trench gate technology on the first side and the second side opposite to the first side of the wafer to etch gate trenches and auxiliary trenches according to actual conditions, and use them as the first side and second side of the completed transistor.

[0044] Among them, the trench gate technology is to coat a layer of photoresist on the surface of the wafer, obtain a patterned photoresist coating through development and curing, and then obtain the grooves of the wafer through dry or wet etching.

[0045] In some examples, the first side may be a front side and the second side may be a back side.

[0046] A wafer refers to the chip used to make transistors. Its original materials can be silicon, silicon carbide (SiC) and gallium nitride (GaN), etc. Taking silicon-based wafers as an example, high-purity polysilicon is dissolved and doped with silicon crystal seeds, which are then slowly pulled out to form cylindrical single crystal silicon. After grinding, polishing and slicing, the silicon crystal rods are formed into silicon wafers, that is, wafers. Generally, domestic wafer production lines are mainly 8-inch and 12-inch.

[0047] In some embodiments of the present invention, the width of the auxiliary trench is the same as the width of the gate trench.

[0048] like Figure 2 As shown, a plurality of gate trenches 1 can be etched on the first side of the wafer and a plurality of auxiliary trenches 4 can be etched on the second side by using the trench gate technology, and during the etching process, the width of the auxiliary trenches is made the same as the width of the gate trenches and the positions are made corresponding, so as to constrain the current path 5 of the transistor during use, thereby optimizing the current path in the transistor to improve the electric field concentration effect.

[0049] After completing the auxiliary trench etching of the wafer, the implantation equipment can perform B (Boron) or AL (Aluminum) ion implantation at the bottom of the auxiliary trench 4 to form the first floating region 3 .

[0050] In some embodiments of the present invention, a first floating region is formed between the auxiliary trench and the gate trench, and a second floating region is formed between the gate trench and the auxiliary trench.

[0051] like Figure 2 After the gate trench of the wafer is etched, the photoresist still exists on the surface of the first side of the wafer, which will block the ion implantation, while the bottom of the gate trench is successfully implanted because there is no shielding, so as to form the second floating region 2.

[0052] After the ion implantation of the second floating region 2 is completed, the first surface processing can be performed, such as removing the photoresist on the surface of the first surface of the wafer, growing gate oxide, filling the trenches, and performing a thinning process on the second surface of the wafer.

[0053] After the filling is completed, a planarization process can be performed to obtain a trench filling structure flush with the first surface of the wafer, and then the photoresist coating on the surface of the first surface of the wafer is removed to perform ion activation on the injected ions.

[0054] After the processing of the first side of the wafer is completed, the second side of the wafer can be cleaned to remove dirt and residue, and then a layer of photoresist is coated on the second side of the wafer to determine the corresponding width and position of the auxiliary grooves and the gate grooves to be etched. After development and curing, a patterned photoresist coating is obtained, and then dry or wet etching is performed to obtain the auxiliary grooves on the second side of the wafer.

[0055] Among them, gate oxide growth refers to the process of growing a layer of silicon oxide (SiO2) on a silicon wafer through certain process technology during the manufacturing process. Groove filling refers to filling the etched groove with insulating material; wherein the filling material is an insulating material with high thermal conductivity and a thermal expansion coefficient close to that of the wafer material; such as AlN (Aluminum nitride), BeO (Beryllium oxide), etc. It is also possible to fill a layer of insulating material first, and then fill the remaining grooves with metal materials with better thermal conductivity, such as Cu (Cuprum), Al (Aluminium), etc. Those skilled in the art can select suitable insulating materials to fill the grooves according to actual needs, and the present invention does not limit this.

[0056] In the embodiment of the present invention, not only is a gate trench provided on the first side of the transistor, but a second floating region is formed through the gate trench; and an auxiliary trench is provided on the second side of the transistor, and a first floating region is formed through the auxiliary trench. By providing two floating regions, the current path in the transistor can be further optimized, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages.

[0057] In some embodiments of the present invention, the depth of the auxiliary trench is determined according to the wafer thickness of the transistor, the depth of the gate trench, the depth of the first floating region, and the depth of the second floating region.

[0058] As some examples, the depth of the auxiliary trench is the etching depth of the auxiliary trench; the wafer thickness is the final thickness of the wafer, or it can be understood as the final thickness that the transistor needs to reach after the wafer passes all the manufacturing processes; the depth of the gate trench is the etching depth of the gate trench; the depth of the first floating area is the reserved injection depth of the first floating area; and the depth of the second floating area is the injection depth of the second floating area.

[0059] As some examples, the reserved injection depth of the first floating area may be consistent with or inconsistent with the injection depth of the second floating area. Those skilled in the art may define the reserved injection depth of the first floating area according to actual needs, and the present invention does not limit this.

[0060] In practical applications, the etching depth of the auxiliary trench needs to be defined according to the wafer thickness, the etching depth of the gate trench, the reserved injection depth of the first floating area, the injection depth of the second floating area, and the depth of each area interval. For example, the actual selected calculation method can be:

[0061] The etching depth of the auxiliary trench = the final thickness of the wafer - the etching depth of the gate trench - the reserved implantation depth of the first floating region - the implantation depth of the second floating region - the depth of the intervals between the regions.

[0062] Among them, the depth of each area interval is: the interval depth between the gate trench and the second floating area, the interval depth between the second floating area and the reserved first floating area, and the interval depth between the reserved first floating area and the auxiliary trench. The interval depth of each area will affect the current path. In theory, the smaller the better.

[0063] As some examples, the spacing depth between the second floating region and the reserved first floating region can be selected to be 0-2um, the spacing depth between the gate trench and the second floating region and the spacing depth between the reserved first floating region and the auxiliary trench can be selected to be 0.2-2um (a certain thickness is reserved this time to serve as an insulating layer buffer to prevent the filled conductive polysilicon and metal from being electrified and breaking down during use).

[0064] In some embodiments of the present invention, the auxiliary trench is filled with insulating material and / or metal material, and the thermal conductivity of the insulating material and / or metal material is greater than the thermal conductivity of the wafer material of the transistor.

[0065] In actual applications, transistors generate heat when in use. The transistors will be mounted on a frame, such as a DBC (Direct Bonded Copper, ceramic substrate) frame, and the heat will be dissipated by the transistor through the frame; however, the heat dissipation capacity inside the transistor depends on the thermal conductivity of the filling material (insulating material and / or metal material) in the transistor. When the thermal conductivity of the insulating material and / or metal material filled in the auxiliary groove is greater than the thermal conductivity of the wafer material itself when the transistor is manufactured, the heat can be better transferred from the filled insulating material and / or metal material, which will optimize the internal heat transfer of the transistor to the DBC frame, thereby reducing the internal junction temperature of the transistor.

[0066] The wafer material is generally silicon, i.e. Si, with a thermal conductivity of 1.5W / cm*K; or: SiC (silicon carbide) has a thermal conductivity of 2.7 / cm*K; the thermal conductivities of common insulating materials and filling metal materials are: ALN (aluminum nitride) has a thermal conductivity of 3.2 / cm*K, BeO (beryllium oxide) has a thermal conductivity of 2.19 / cm*K, diamond has a thermal conductivity of 20 / cm*K, Ag (silver) has a thermal conductivity of 4.29 / cm*K, Cu (copper) has a thermal conductivity of 3.98 / cm*K, and AL (aluminum) is 2.47 / cm*K.

[0067] Those skilled in the art may select insulating materials and / or metal materials with a thermal conductivity greater than that of the wafer material of the transistor as the filling material for the trench according to actual needs, and the present invention does not impose any limitation on this.

[0068] After the filling is completed, a planarization process is performed to obtain an auxiliary trench filling structure that is flush with the surface of the second side of the wafer, and then the subsequent transistor processes are continued, such as second-side injection and metal processes, etc., to finally complete the entire transistor process and obtain a transistor wafer that meets the specifications.

[0069] In some embodiments of the present invention, the thermal expansion coefficient of the insulating material and / or metal material is the same as the thermal expansion coefficient of the wafer material of the transistor, or the difference between the thermal expansion coefficient of the insulating material and / or metal material and the thermal expansion coefficient of the wafer material of the transistor is less than a preset difference.

[0070] As some examples, the back side groove can be filled by deposition methods such as CVD (Chemical Vapor Deposition) or PCD (plasma enhanced chemical vapor deposition), wherein the insulating material is a material with high thermal conductivity and a thermal expansion coefficient close to that of the wafer material; such as AlN (Aluminum nitride), BeO (Beryllium oxide), etc.

[0071] As some examples, a layer of insulating material may be first filled in the groove, and the remaining groove may be filled with a metal material having better thermal conductivity and a thermal expansion coefficient close to that of the wafer material, such as Cu (Cuprum), Al (Aluminum), etc. Those skilled in the art may select a suitable insulating material and / or metal material to fill the groove according to actual needs, and the present invention is not limited thereto.

[0072] Among them, the expansion coefficient is a physical quantity that characterizes the thermal expansion properties of an object, that is, a physical quantity that characterizes the degree of increase in the length, area, and volume of an object when heated.

[0073] As some examples, the preset difference may be greater than or equal to 0 and less than or equal to 1; for example, if the thermal expansion coefficient of the insulating material is 1 and the thermal expansion coefficient of the wafer material of the transistor is 1, it means that the thermal expansion coefficient of the insulating material is the same as the thermal expansion coefficient of the wafer material of the transistor; if the thermal expansion coefficient of the insulating material is 3 and the thermal expansion coefficient of the wafer material of the transistor is 1, the difference is 2, which is not less than the preset difference, then it is not used as the insulating material for filling.

[0074] As some examples, the preset difference can be greater than or equal to 0, and less than or equal to 1; for example, if the thermal expansion coefficient of the metal material is 1, and the thermal expansion coefficient of the wafer material of the transistor is 1, it means that the thermal expansion coefficient of the metal material is the same as the thermal expansion coefficient of the wafer material of the transistor; if the thermal expansion coefficient of the metal material is 3, and the thermal expansion coefficient of the wafer material of the transistor is 1, and the difference is 2, which is not less than the preset difference, then it is not used as the metal material for filling.

[0075] In an embodiment of the present invention, a gate trench is provided on the first side of the transistor, an auxiliary trench is provided on the second side of the transistor, and the auxiliary trench is provided at a position corresponding to the gate trench, and a first floating region is formed between the auxiliary trench and the gate trench, thereby achieving the formation of the floating region through the auxiliary trench, and then optimizing the current path in the transistor, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages.

[0076] Reference Figure 3 , showing a step flow chart of a transistor manufacturing method provided in some embodiments of the present invention, wherein the transistor is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.

[0077] Among them, the insulated gate bipolar transistor is a high-performance power semiconductor device, which is widely used in power electronics, transportation, industrial automation and other fields. The metal-oxide semiconductor field-effect transistor is a field-effect transistor widely used in analog circuits and digital circuits, and should also be widely used in electronics, transportation, industrial automation and other fields, such as silicon carbide metal oxide semiconductor field-effect transistor (SIC-MOS).

[0078] Specifically, the following steps may be included:

[0079] Step 301: etching a gate trench on the first surface, and etching an auxiliary trench at a position corresponding to the gate trench on the second surface.

[0080] When using a wafer to make transistors, technicians in this field can choose to use trench gate technology on the first side and the second side opposite to the first side of the wafer to etch gate trenches and auxiliary trenches according to actual conditions, and use them as the first side and second side of the completed transistor.

[0081] Among them, the trench gate technology is to coat a layer of photoresist on the surface of the wafer, obtain a patterned photoresist coating through development and curing, and then obtain the grooves of the wafer through dry or wet etching.

[0082] In some examples, the first side may be a front side and the second side may be a back side.

[0083] A wafer refers to the chip used to make transistors. Its original materials can be silicon, silicon carbide (SiC) and gallium nitride (GaN), etc. Taking silicon-based wafers as an example, high-purity polysilicon is dissolved and doped with silicon crystal seeds, which are then slowly pulled out to form cylindrical single crystal silicon. After grinding, polishing and slicing, the silicon crystal rods are formed into silicon wafers, that is, wafers. Generally, domestic wafer production lines are mainly 8-inch and 12-inch.

[0084] like Figure 2 As shown, a plurality of gate trenches 1 can be etched on the first side of the wafer and a plurality of auxiliary trenches 4 can be etched on the second side by using the trench gate technology, and during the etching process, the width of the auxiliary trenches is made the same as the width of the gate trenches and the positions are made corresponding, so as to constrain the current path 5 of the transistor during use, thereby optimizing the current path in the transistor to improve the electric field concentration effect.

[0085] In some embodiments of the present invention, it also includes:

[0086] A second floating region is formed between the gate trench and the auxiliary trench by performing plasma implantation in the gate trench.

[0087] like Figure 2 After the gate trench of the wafer is etched, the photoresist still exists on the surface of the first side of the wafer, which will block the ion implantation, while the bottom of the gate trench is successfully implanted because there is no shielding, so as to form the second floating region 2.

[0088] After the ion implantation of the second floating region 2 is completed, the first surface processing can be performed, such as removing the photoresist on the surface of the first surface of the wafer, growing gate oxide, filling the trenches, and performing a thinning process on the second surface of the wafer.

[0089] After the filling is completed, a planarization process can be performed to obtain a trench filling structure flush with the surface of the wafer, and then the photoresist coating on the surface of the first surface of the wafer is removed to activate the injected ions.

[0090] After the processing of the first side of the wafer is completed, the second side of the wafer can be cleaned to remove dirt and residue, and then a layer of photoresist is coated on the second side of the wafer to determine the corresponding width and position of the auxiliary grooves and the gate grooves to be etched. After development and curing, a patterned photoresist coating is obtained, and then dry or wet etching is performed to obtain the auxiliary grooves on the second side of the wafer.

[0091] Among them, gate oxide growth refers to the process of growing a layer of silicon oxide (SiO2) on a silicon wafer through certain process technologies during the manufacturing process. Trench filling refers to filling insulating materials and / or metal materials in etched trenches.

[0092] The insulating material is a material with high thermal conductivity and a thermal expansion coefficient close to that of the wafer material, such as AlN (Aluminum nitride), BeO (Beryllium oxide), and the like.

[0093] As some examples, a layer of insulating material may be first filled in the groove, and the remaining groove may be filled with a metal material having better thermal conductivity and a thermal expansion coefficient close to that of the wafer material, such as Cu (Cuprum), Al (Aluminum), etc. Those skilled in the art may select a suitable insulating material and / or metal material to fill the groove according to actual needs, and the present invention is not limited thereto.

[0094] Among them, the expansion coefficient is a physical quantity that characterizes the thermal expansion properties of an object, that is, a physical quantity that characterizes the degree of increase in the length, area, and volume of an object when heated.

[0095] Step 302 : forming a first floating region between the auxiliary trench and the gate trench by performing plasma implantation inside the auxiliary trench.

[0096] After completing the auxiliary trench etching of the wafer, the implantation equipment can perform B (Boron) or AL (Aluminum) ion implantation at the bottom of the auxiliary trench 4 to form the first floating region 3 .

[0097] In the embodiment of the present invention, not only is a gate trench provided on the first side of the transistor, but a second floating region is formed through the gate trench; and an auxiliary trench is provided on the second side of the transistor, and a first floating region is formed through the auxiliary trench. By providing two floating regions, the current path in the transistor can be further optimized, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages.

[0098] In some embodiments of the present invention, after forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation inside the auxiliary trench, the method further includes: filling the auxiliary trench with insulating material and / or metal material.

[0099] In some examples, the thermal conductivity of the insulating material and / or the metal material filled in the auxiliary trench is greater than the thermal conductivity of the wafer material of the transistor.

[0100] In actual applications, transistors generate heat when in use. The transistors will be mounted on a frame, such as a DBC (Direct Bonded Copper, ceramic substrate) frame, and the heat will be dissipated by the transistor through the frame; however, the heat dissipation capacity inside the transistor depends on the thermal conductivity of the filling material (insulating material and / or metal material) in the transistor. When the thermal conductivity of the insulating material and / or metal material filled in the auxiliary groove is greater than the thermal conductivity of the wafer material itself when the transistor is manufactured, the heat can be better transferred from the filled insulating material and / or metal material, which will optimize the internal heat transfer of the transistor to the DBC frame, thereby reducing the internal junction temperature of the transistor.

[0101] The wafer material is generally silicon, i.e. Si, with a thermal conductivity of 1.5W / cm*K; or: SiC (silicon carbide) has a thermal conductivity of 2.7 / cm*K; the thermal conductivities of common insulating materials and filling metal materials are: ALN (aluminum nitride) has a thermal conductivity of 3.2 / cm*K, BeO (beryllium oxide) has a thermal conductivity of 2.19 / cm*K, diamond has a thermal conductivity of 20 / cm*K, Ag (silver) has a thermal conductivity of 4.29 / cm*K, Cu (copper) has a thermal conductivity of 3.98 / cm*K, and AL (aluminum) is 2.47 / cm*K.

[0102] Those skilled in the art may select insulating materials and / or metal materials with a thermal conductivity greater than that of the wafer material of the transistor as the filling material for the trench according to actual needs, and the present invention does not impose any limitation on this.

[0103] After the filling is completed, a planarization process is performed to obtain an auxiliary trench filling structure that is flush with the surface of the second side of the wafer, and then the subsequent transistor processes are continued, such as second-side injection and metal processes, etc., to finally complete the entire transistor process and obtain a transistor wafer that meets the specifications.

[0104] In some examples, the thermal expansion coefficient of the insulating material and / or metal material is the same as the thermal expansion coefficient of the wafer material of the transistor, or the difference between the thermal expansion coefficient of the insulating material and / or metal material and the thermal expansion coefficient of the wafer material of the transistor is less than a preset difference.

[0105] As some examples, the back side groove can be filled by deposition methods such as CVD (Chemical Vapor Deposition) or PCD (plasma enhanced chemical vapor deposition), wherein the insulating material is a material with high thermal conductivity and a thermal expansion coefficient close to that of the wafer material; such as AlN (Aluminum nitride), BeO (Beryllium oxide), etc.

[0106] As some examples, a layer of insulating material may be first filled in the groove, and the remaining groove may be filled with a metal material having better thermal conductivity and a thermal expansion coefficient close to that of the wafer material, such as Cu (Cuprum), Al (Aluminum), etc. Those skilled in the art may select a suitable insulating material and / or metal material to fill the groove according to actual needs, and the present invention is not limited thereto.

[0107] Among them, the expansion coefficient is a physical quantity that characterizes the thermal expansion properties of an object, that is, a physical quantity that characterizes the degree of increase in the length, area, and volume of an object when heated.

[0108] As some examples, the preset difference may be greater than or equal to 0 and less than or equal to 1; for example, if the thermal expansion coefficient of the insulating material is 1 and the thermal expansion coefficient of the wafer material of the transistor is 1, it means that the thermal expansion coefficient of the insulating material is the same as the thermal expansion coefficient of the wafer material of the transistor; if the thermal expansion coefficient of the insulating material is 3 and the thermal expansion coefficient of the wafer material of the transistor is 1, the difference is 2, which is not less than the preset difference, then it is not used as the insulating material for filling.

[0109] As some examples, the preset difference can be greater than or equal to 0, and less than or equal to 1; for example, if the thermal expansion coefficient of the metal material is 1, and the thermal expansion coefficient of the wafer material of the transistor is 1, it means that the thermal expansion coefficient of the metal material is the same as the thermal expansion coefficient of the wafer material of the transistor; if the thermal expansion coefficient of the metal material is 3, and the thermal expansion coefficient of the wafer material of the transistor is 1, and the difference is 2, which is not less than the preset difference, then it is not used as the metal material for filling.

[0110] In some embodiments of the present invention, etching the second surface to obtain the auxiliary groove comprises: coating the second surface with a photoresist to obtain a photoresist coating, and etching the auxiliary groove on the basis of the photoresist coating;

[0111] After forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes:

[0112] The photoresist coating is removed.

[0113] In some examples, before etching to obtain the auxiliary groove, the process also includes: determining the depth of the auxiliary groove; specifically, the depth of the auxiliary groove is determined based on the wafer thickness of the transistor, the depth of the gate groove, the depth of the first floating region, and the depth of the second floating region.

[0114] Among them, the depth of the auxiliary groove is the etching depth of the auxiliary groove; the wafer thickness is the final thickness of the wafer, or it can be understood as the final thickness that the transistor needs to reach after the wafer passes all the manufacturing processes; the depth of the gate trench is the etching depth of the gate trench; the depth of the first floating area is the reserved injection depth of the first floating area; the depth of the second floating area is the injection depth of the second floating area.

[0115] In some examples, the reserved injection depth of the first floating region may be consistent with or inconsistent with the injection depth of the second floating region. Those skilled in the art may define the reserved injection depth of the first floating region according to actual needs, and the present invention does not limit this.

[0116] In practical applications, the etching depth of the auxiliary trench needs to be defined according to the wafer thickness, the etching depth of the gate trench, the reserved injection depth of the first floating area, the injection depth of the second floating area, and the depth of each area interval. For example, the actual selected calculation method can be:

[0117] The etching depth of the auxiliary trench = the final thickness of the wafer - the etching depth of the gate trench - the reserved implantation depth of the first floating region - the implantation depth of the second floating region - the depth of the intervals between the regions.

[0118] Among them, the depth of each area interval is: the interval depth between the gate trench and the second floating area, the interval depth between the second floating area and the reserved first floating area, and the interval depth between the reserved first floating area and the auxiliary trench. The interval depth of each area will affect the current path. In theory, the smaller the better.

[0119] In some examples, the spacing depth between the second floating region and the reserved first floating region can be selected to be 0-2um, the spacing depth between the gate trench and the second floating region, and the spacing depth between the reserved first floating region and the auxiliary trench can be selected to be 0.2-2um (a certain thickness is reserved this time to serve as an insulating layer buffer to prevent the filled conductive polysilicon and metal from being electrified and breaking down during use).

[0120] In practical applications, after the first floating region is formed between the auxiliary trench and the gate trench, the photoresist coating on the surface of the second surface may be removed and a planarization process may be performed.

[0121] In some embodiments of the present invention, after forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes: activating the implanted plasma.

[0122] As some examples, the injected plasma may be activated by an annealing process, such as laser anneal (LSA), silicide, rapid thermal processing (RTP), furnace annealing, and the like.

[0123] In an embodiment of the present invention, a gate groove is obtained by etching on the first surface, and an auxiliary groove is obtained at a position corresponding to the gate groove in the second surface; and plasma implantation is performed inside the auxiliary groove to form a first floating region between the auxiliary groove and the gate groove, thereby realizing the formation of the floating region through the auxiliary groove, and then optimizing the current path in the transistor, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages.

[0124] Reference Figure 4 , showing a step flow chart of another transistor manufacturing method provided in some embodiments of the present invention, wherein the transistor is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.

[0125] Among them, the insulated gate bipolar transistor is a high-performance power semiconductor device, which is widely used in power electronics, transportation, industrial automation and other fields. The metal-oxide semiconductor field-effect transistor is a field-effect transistor widely used in analog circuits and digital circuits, and should also be widely used in electronics, transportation, industrial automation and other fields, such as silicon carbide metal oxide semiconductor field-effect transistor (SIC-MOS).

[0126] Step 401 , etching a gate trench on a first surface of the transistor, and performing plasma implantation inside the gate trench to obtain a second floating region.

[0127] When using a wafer to make transistors, technicians in this field can choose to use trench gate technology on the first side and the second side opposite to the first side of the wafer to etch gate trenches and auxiliary trenches according to actual conditions, and use them as the first side and second side of the completed transistor.

[0128] Among them, the trench gate technology is to coat a layer of photoresist on the surface of the wafer, obtain a patterned photoresist coating through development and curing, and then obtain the grooves of the wafer through dry or wet etching.

[0129] In some examples, the first side may be a front side and the second side may be a back side.

[0130] A wafer refers to the chip used to make transistors. Its original materials can be silicon, silicon carbide (SiC) and gallium nitride (GaN), etc. Taking silicon-based wafers as an example, high-purity polysilicon is dissolved and doped with silicon crystal seeds, which are then slowly pulled out to form cylindrical single crystal silicon. After grinding, polishing and slicing, the silicon crystal rods are formed into silicon wafers, that is, wafers. Generally, domestic wafer production lines are mainly 8-inch and 12-inch.

[0131] like Figure 2 As shown, multiple gate trenches 1 can be etched on the first side of the wafer using trench gate technology. After the gate trench etching of the wafer is completed, the photoresist still exists on the surface of the first side of the wafer, which will block the ion implantation, while the bottom of the gate trench is successfully implanted because there is no obstruction to form a second floating area 2.

[0132] After the ion implantation of the second floating region 2 is completed, the first surface processing can be performed, such as removing the photoresist on the surface of the first surface of the wafer, growing gate oxide, filling the trenches, and performing a thinning process on the second surface of the wafer.

[0133] After the filling is completed, a planarization process can be performed to obtain a trench filling structure flush with the first surface of the wafer, and then the photoresist coating on the surface of the first surface of the wafer is removed.

[0134] Step 402, coating a photoresist on the second surface of the transistor to obtain a photoresist coating, and etching on the basis of the photoresist coating to obtain an auxiliary trench.

[0135] After the processing of the first side of the wafer is completed, the second side of the wafer can be cleaned to remove dirt and residue, and then a layer of photoresist is coated on the second side of the wafer to determine the corresponding width and position of the auxiliary grooves and the gate grooves to be etched. After development and curing, a patterned photoresist coating is obtained, and then dry or wet etching is performed to obtain the auxiliary grooves on the second side of the wafer.

[0136] In some examples, before etching to obtain the auxiliary groove, the process also includes: determining the depth of the auxiliary groove; specifically, the depth of the auxiliary groove is determined based on the wafer thickness of the transistor, the depth of the gate groove, the depth of the first floating region, and the depth of the second floating region.

[0137] Among them, the depth of the auxiliary groove is the etching depth of the auxiliary groove; the wafer thickness is the final thickness of the wafer, or it can be understood as the final thickness that the transistor needs to reach after the wafer passes all the manufacturing processes; the depth of the gate trench is the etching depth of the gate trench; the depth of the first floating area is the reserved injection depth of the first floating area; the depth of the second floating area is the injection depth of the second floating area.

[0138] In some examples, the reserved injection depth of the first floating region may be consistent with or inconsistent with the injection depth of the second floating region. Those skilled in the art may define the reserved injection depth of the first floating region according to actual needs, and the present invention does not limit this.

[0139] In practical applications, the etching depth of the auxiliary trench needs to be defined according to the wafer thickness, the etching depth of the gate trench, the reserved injection depth of the first floating area, the injection depth of the second floating area, and the depth of each area interval. For example, the actual selected calculation method can be:

[0140] The etching depth of the auxiliary trench = the final thickness of the wafer - the etching depth of the gate trench - the reserved implantation depth of the first floating region - the implantation depth of the second floating region - the depth of the intervals between the regions.

[0141] Among them, the depth of each area interval is: the interval depth between the gate trench and the second floating area, the interval depth between the second floating area and the reserved first floating area, and the interval depth between the reserved first floating area and the auxiliary trench. The interval depth of each area will affect the current path. In theory, the smaller the better.

[0142] In some examples, the spacing depth between the second floating region and the reserved first floating region can be selected to be 0-2um, the spacing depth between the gate trench and the second floating region, and the spacing depth between the reserved first floating region and the auxiliary trench can be selected to be 0.2-2um (a certain thickness is reserved this time to serve as an insulating layer buffer to prevent the filled conductive polysilicon and metal from being electrified and breaking down during use).

[0143] Step 403 , performing plasma implantation inside the auxiliary trench to form a first floating region between the auxiliary trench and the gate trench.

[0144] After completing the auxiliary trench etching of the wafer, the implantation equipment can perform B (Boron) or AL (Aluminum) ion implantation at the bottom of the auxiliary trench 4 to form a first floating region 3 between the auxiliary trench and the gate trench.

[0145] As some examples, the injected plasma may be activated by an annealing process, such as laser anneal (LSA), silicide, rapid thermal processing (RTP), furnace annealing, and the like.

[0146] In some embodiments of the present invention, not only is a gate trench provided on the first side of the transistor, but a second floating region is formed through the gate trench; and an auxiliary trench is provided on the second side of the transistor, and a first floating region is formed through the auxiliary trench. By providing two floating regions, the current path in the transistor can be further optimized, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages.

[0147] Step 404: filling the auxiliary trench with insulating material and / or metal material.

[0148] In some examples, the thermal conductivity of the insulating material filled in the auxiliary trench is greater than the thermal conductivity of the wafer material of the transistor.

[0149] In actual applications, transistors generate heat when in use. The transistors will be mounted on a frame, such as a DBC (Direct Bonded Copper, ceramic substrate) frame, and the heat will be dissipated by the transistor through the frame; however, the heat dissipation capacity inside the transistor depends on the thermal conductivity of the filling material (insulating material and / or metal material) in the transistor. When the thermal conductivity of the insulating material and / or metal material filled in the auxiliary groove is greater than the thermal conductivity of the wafer material itself when the transistor is manufactured, the heat can be better transferred from the filled insulating material and / or metal material, which will optimize the internal heat transfer of the transistor to the DBC frame, thereby reducing the internal junction temperature of the transistor.

[0150] The wafer material is generally silicon, i.e. Si, with a thermal conductivity of 1.5W / cm*K; or: SiC (silicon carbide) has a thermal conductivity of 2.7 / cm*K; the thermal conductivities of common insulating materials and filling metal materials are: ALN (aluminum nitride) has a thermal conductivity of 3.2 / cm*K, BeO (beryllium oxide) has a thermal conductivity of 2.19 / cm*K, diamond has a thermal conductivity of 20 / cm*K, Ag (silver) has a thermal conductivity of 4.29 / cm*K, Cu (copper) has a thermal conductivity of 3.98 / cm*K, and AL (aluminum) is 2.47 / cm*K.

[0151] Those skilled in the art may select insulating materials and / or metal materials with a thermal conductivity greater than that of the wafer material of the transistor as the filling material for the trench according to actual needs, and the present invention does not impose any limitation on this.

[0152] After the filling is completed, a planarization process is performed to obtain an auxiliary trench filling structure that is flush with the surface of the second side of the wafer, and then the subsequent transistor processes are continued, such as second-side injection and metal processes, etc., to finally complete the entire transistor process and obtain a transistor wafer that meets the specifications.

[0153] In some examples, the thermal expansion coefficient of the insulating material and / or metal material is the same as the thermal expansion coefficient of the wafer material of the transistor, or the difference between the thermal expansion coefficient of the insulating material and / or metal material and the thermal expansion coefficient of the wafer material of the transistor is less than a preset difference.

[0154] As some examples, the back side groove can be filled by deposition methods such as CVD (Chemical Vapor Deposition) or PCD (plasma enhanced chemical vapor deposition), wherein the insulating material is a material with high thermal conductivity and a thermal expansion coefficient close to that of the wafer material; such as AlN (Aluminum nitride), BeO (Beryllium oxide), etc.

[0155] As some examples, a layer of insulating material may be first filled in the groove, and the remaining groove may be filled with a metal material having better thermal conductivity and a thermal expansion coefficient close to that of the wafer material, such as Cu (Cuprum), Al (Aluminum), etc. Those skilled in the art may select a suitable insulating material and / or metal material to fill the groove according to actual needs, and the present invention is not limited thereto.

[0156] Among them, the expansion coefficient is a physical quantity that characterizes the thermal expansion properties of an object, that is, a physical quantity that characterizes the degree of increase in the length, area, and volume of an object when heated.

[0157] As some examples, the preset difference may be greater than or equal to 0 and less than or equal to 1; for example, if the thermal expansion coefficient of the insulating material is 1 and the thermal expansion coefficient of the wafer material of the transistor is 1, it means that the thermal expansion coefficient of the insulating material is the same as the thermal expansion coefficient of the wafer material of the transistor; if the thermal expansion coefficient of the insulating material is 3 and the thermal expansion coefficient of the wafer material of the transistor is 1, the difference is 2, which is not less than the preset difference, then it is not used as the insulating material for filling.

[0158] As some examples, the preset difference can be greater than or equal to 0, and less than or equal to 1; for example, if the thermal expansion coefficient of the metal material is 1, and the thermal expansion coefficient of the wafer material of the transistor is 1, it means that the thermal expansion coefficient of the metal material is the same as the thermal expansion coefficient of the wafer material of the transistor; if the thermal expansion coefficient of the metal material is 3, and the thermal expansion coefficient of the wafer material of the transistor is 1, and the difference is 2, which is not less than the preset difference, then it is not used as the metal material for filling.

[0159] In an embodiment of the present invention, a gate groove is obtained by etching on the first side of the transistor, and plasma is implanted inside the gate groove to obtain a second floating region; then, a photoresist is coated on the second side of the transistor to obtain a photoresist coating, and on the basis of the photoresist coating, an auxiliary groove is etched; then, plasma is implanted inside the auxiliary groove to form a first floating region between the auxiliary groove and the gate groove; finally, insulating material and / or metal material is filled in the auxiliary groove, and the injected plasma is activated to realize the formation of a floating region through the auxiliary groove, thereby optimizing the current path in the transistor, thereby improving the electric field concentration effect, enhancing the reliability of the power device, and avoiding limiting the application of the power device under higher electric field voltages.

[0160] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0161] Reference Figure 5 , shows a schematic structural diagram of a transistor manufacturing device provided by some embodiments of the present invention, which may specifically include the following modules:

[0162] A trench etching control module 501 is used for etching a gate trench on the first surface, and etching an auxiliary trench at a position corresponding to the gate trench on the second surface;

[0163] The ion implantation control module 502 is used to form a first floating region between the auxiliary trench and the gate trench by performing plasma implantation inside the auxiliary trench.

[0164] In some embodiments of the present invention, the device further comprises:

[0165] The ion implantation control submodule forms a second floating region between the gate trench and the auxiliary trench by performing ion implantation inside the gate trench.

[0166] The insulating material filling module is used to fill the auxiliary trench with insulating material and / or metal material after forming the first floating region between the auxiliary trench and the gate trench.

[0167] In some embodiments of the present invention, the trench etching control module 501 includes:

[0168] An auxiliary groove etching submodule, used for coating the second surface with photoresist to obtain a photoresist coating, and etching the auxiliary groove on the basis of the photoresist coating;

[0169] In some embodiments of the present invention, the device further comprises:

[0170] The photoresist removal module is used to remove the photoresist coating.

[0171] In some embodiments of the present invention, the device further comprises:

[0172] The ion activation module is used to activate the implanted plasma.

[0173] Some embodiments of the present invention further provide another transistor manufacturing device, wherein the device is used for:

[0174] A gate trench is obtained by etching on the first surface of the transistor, and plasma implantation is performed inside the gate trench to obtain a second floating region.

[0175] A photoresist is coated on the second surface of the transistor to obtain a photoresist coating layer, and on the basis of the photoresist coating layer, an auxiliary groove is obtained by etching.

[0176] Plasma implantation is performed inside the auxiliary trench to form a first floating region between the auxiliary trench and the gate trench.

[0177] The auxiliary trench is filled with an insulating material and / or a metal material.

[0178] Some embodiments of the present invention further provide an electronic device, comprising a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the above method is implemented when the computer program is executed by the processor.

[0179] Some embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, and the computer program implements the above method when executed by a processor.

[0180] Some embodiments of the present invention further provide a computer program product, including a computer program, which implements the above method when executed by a processor.

[0181] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0182] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0183] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0184] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0185] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0186] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0188] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0189] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the above elements.

[0190] The above is a detailed introduction to a transistor and a manufacturing method, device, electronic device and medium provided. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a general technician in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A transistor, characterized in that: The transistor comprises a first surface and a second surface opposite to the first surface, the first surface is provided with a gate trench, the second surface is provided with an auxiliary trench, and the auxiliary trench is provided at a position corresponding to the gate trench; A first floating region is formed between the auxiliary trench and the gate trench.

2. The transistor according to claim 1, characterized in that A second floating region is formed between the gate trench and the auxiliary trench.

3. The transistor according to claim 1 or 2, characterized in that: The auxiliary trench is filled with insulating material and / or metal material, and the thermal conductivity of the insulating material and / or metal material is greater than the thermal conductivity of the wafer material of the transistor.

4. The transistor according to claim 3, characterized in that The thermal expansion coefficient of the insulating material and / or metal material is the same as the thermal expansion coefficient of the wafer material of the transistor, or the difference between the thermal expansion coefficient of the insulating material and / or metal material and the thermal expansion coefficient of the wafer material of the transistor is less than a preset difference.

5. The transistor according to claim 1 or 2, characterized in that: The width of the auxiliary trench is the same as the width of the gate trench.

6. The transistor according to claim 2, characterized in that The depth of the auxiliary trench is determined according to the wafer thickness of the transistor, the depth of the gate trench, the depth of the first floating region, and the depth of the second floating region.

7. The transistor according to claim 1 or 2, characterized in that: The transistor is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.

8. A method for manufacturing a transistor according to any one of claims 1 to 7, characterized in that: include: Etching a gate trench on the first surface, and etching an auxiliary trench at a position corresponding to the gate trench on the second surface; A first floating region is formed between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench.

9. The method according to claim 8, characterized in that Also includes: A second floating region is formed between the gate trench and the auxiliary trench by performing plasma implantation in the gate trench.

10. The method according to claim 8 or 9, characterized in that: After forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes: filling the auxiliary trench with an insulating material and / or a metal material.

11. The method according to claim 8 or 9, characterized in that: The etching on the second surface to obtain the auxiliary groove comprises: coating the second surface with a photoresist to obtain a photoresist coating, and etching on the basis of the photoresist coating to obtain the auxiliary groove; After forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes: The photoresist coating is removed.

12. The method according to claim 8 or 9, characterized in that: After forming the first floating region between the auxiliary trench and the gate trench by performing plasma implantation in the auxiliary trench, the method further includes: activating the implanted plasma.

13. A manufacturing device for a transistor according to any one of claims 1 to 7, characterized in that: include: A trench etching control module, configured to etch a gate trench on the first surface, and to etch an auxiliary trench at a position corresponding to the gate trench on the second surface; The ion implantation control module is used to form a first floating region between the auxiliary trench and the gate trench by performing plasma implantation inside the auxiliary trench.

14. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method according to any one of claims 8 to 12 when executed by the processor.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 8 to 12 is implemented.

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