Preparation method of solar cell

Abstract

The invention provides a preparation method of a solar cell. The preparation method comprises the following steps: growing a tunneling layer on one surface of a silicon substrate; growing a doped silicon layer on the basis of the tunneling layer; performing selective treatment on the doped silicon layer; selectively etching the doped silicon layer by using fluorine-containing gas, and forming a local passivation contact structure on the surface; an electrode is formed on the locally passivated contact structure. Fluorine-containing gas dry etching is adopted to replace wet etching commonly used in the prior art to prepare the local passivation contact structure, the selection ratio of fluorine-containing gas to silicon oxide and amorphous silicon is more than 100, and the amorphous silicon layer below can be effectively protected only by a very thin silicon oxide layer. Compared with wet etching in the prior art in which a thicker and more compact silicon oxide layer is needed, the process time and the process cost of fluorine-containing gas dry etching are obviously reduced.

Description

Technical Field

[0001] The invention relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell. Background Art

[0002] With the continuous development of photovoltaic technology, crystalline silicon solar cell technology has become increasingly mature, and its conversion efficiency is approaching the theoretical limit. At present, the main factor affecting the open circuit voltage and conversion efficiency of crystalline silicon solar cells is the carrier recombination in the contact area between the metal electrode and the crystalline silicon surface.

[0003] In order to reduce the carrier recombination in the contact area between the metal electrode and the crystalline silicon surface of the solar cell, a local passivation contact structure, namely a Poly finger structure, can be made in the contact area between the crystalline silicon surface and the metal electrode.

[0004] At present, the main poly finger technology preparation schemes in the industry generally include photolithography, laser method, wax printing method, etc. The photolithography method uses photolithography to cover the polysilicon layer in the contact area, and uses wet etching to remove the remaining polysilicon layer to form a poly finger structure; the laser method uses laser to directly remove the polysilicon layer outside the contact area; the wax printing method prepares a graphic wax film on the surface of the entire polysilicon layer, and uses wet etching to remove the remaining polysilicon layer to form a poly finger structure. The above methods will completely remove the non-contact polysilicon and the tunneling layer below. They are powerless to meet the requirement of retaining a certain thickness of thin polysilicon for passivation, and cannot control the degree of reaction; in addition, the above methods also have the problem of complex process. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a method for preparing a solar cell which uses dry gas etching to form a local passivation contact structure and reduce costs and increase efficiency.

[0006] Technical solution: A method for preparing a solar cell, comprising the following steps:

[0007] S1 grows a tunneling layer on one side of the silicon substrate;

[0008] S2 grows a doped silicon layer based on the tunneling layer;

[0009] S3 selectively processes the doped silicon layer;

[0010] S4 uses fluorine-containing gas to selectively etch the doped silicon layer to form a local passivation contact structure on the surface;

[0011] S5: forming an electrode on the local passivation contact structure.

[0012] Specifically, the tunneling layer is one or more of silicon oxynitride, silicon carbide, silicon nitride, titanium nitride, aluminum oxide, and silicon oxide.

[0013] Specifically, the local passivation contact structure includes an electrode contact portion and a non-electrode contact portion, and the thickness of the doped silicon layer of the electrode contact portion is greater than the thickness of the doped silicon layer of the non-electrode contact portion.

[0014] Specifically, the doped silicon layer is a doped amorphous silicon layer or a doped polycrystalline silicon layer, and the type of doping elements is the same as that of the silicon substrate.

[0015] Preferably, the doped silicon layer includes a plurality of silicon layers stacked in sequence in the thickness direction and a plurality of silicon oxide interface layers between the silicon layers, the silicon layer is a doped amorphous silicon layer or a doped polycrystalline silicon layer, and the silicon layer and the silicon oxide interface layer are doped with the same element type as the silicon substrate. The thickness of the silicon oxide interface layer is less than the thickness of any silicon layer.

[0016] Specifically, selective treatment includes:

[0017] selectively printing a mask on the surface of the doped polysilicon layer, wherein the shape of the mask matches the shape of the electrode contact portion;

[0018] The surface of the doped amorphous silicon layer is selectively oxidized, and the shape of the oxidized area matches the shape of the electrode contact portion.

[0019] Specifically, the selective treatment of the doped amorphous silicon layer is to perform laser heat treatment on the region to be oxidized to form a silicon oxide layer in the region.

[0020] Specifically, the selective treatment of the doped polysilicon layer is to print an organic mask on a target area on the surface of the doped polysilicon layer, and the shape of the mask matches the shape of the electrode contact portion.

[0021] Specifically, the preparation method also includes removing and cleaning the organic mask: the removal of the organic mask adopts an alkaline etchant, and the alkaline etchant includes one or more of NaOH, KOH or organic alkaline reagents; the cleaning of the organic mask includes deionized water cleaning and cleaning with a mixture of alkaline reagents and oxidants, and the alkaline reagents include one or more of NaOH, KOH or organic alkaline reagents, and the oxidants include one or more of hydrogen peroxide and ozone.

[0022] Specifically, the fluorine-containing gas includes F 2 +N 2 、XeF 2 , ClF, CIF 3 IF 5 BrF 5 or BrF 3 One or more of .

[0023] Beneficial effect: Compared with the prior art, the present invention has the remarkable effect of using fluorine-containing gas dry etching instead of wet etching commonly used in the prior art to prepare a local passivation contact structure, and at the same time, the fluorine-containing gas has a selectivity of more than 100 for silicon oxide and amorphous silicon, and only a very thin silicon oxide layer is needed to effectively protect the underlying amorphous silicon layer. Compared with the prior art wet etching which requires a thicker and denser silicon oxide layer, the process time and process cost of fluorine-containing gas dry etching are significantly reduced, and the prepared solar cell has a higher photoelectric conversion efficiency than the same type of products obtained by the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of a solar cell prepared according to an embodiment of the present invention.

[0025] Figure 2 It is a schematic diagram of the silicon wafer structure of an embodiment of the present invention.

[0026] Figure 3 It is a schematic diagram of the structure of the silicon wafer after oxidation treatment of the present invention.

[0027] Figure 4 It is a schematic diagram of the silicon wafer structure after printing the organic mask of the present invention.

[0028] Figure 5 It is a schematic diagram of the structure of a silicon wafer after dry etching with fluorine-containing gas according to the present invention. DETAILED DESCRIPTION

[0029] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The experimental methods used in the following examples are conventional methods unless otherwise specified; the reagents, materials, etc. used in the following examples are all commercially available unless otherwise specified.

[0030] The present invention provides a method for preparing a solar cell, comprising the following steps:

[0031] Step 1: growing a tunneling layer on one side of a silicon substrate.

[0032] The substrate can be an n-type semiconductor substrate or a p-type semiconductor substrate. The material of the substrate can be single crystal silicon or polycrystalline silicon. The front and back of the substrate are consistent with the front and back of the solar cell, the front side is the side facing the sunlight, and the back side is the backlight side.

[0033] The tunneling layer can produce a tunneling effect, allowing majority carriers to pass through while blocking minority carriers. The material of the tunneling layer can include various materials that majority carriers can tunnel through, such as oxides, nitrides, semiconductors, and conductive polymers. The material of the tunneling layer can be one or more of silicon oxynitride, silicon carbide, silicon nitride, titanium nitride, aluminum oxide, and silicon oxide. The material of the tunneling layer is preferably silicon oxide, which has good passivation properties. The thickness of the tunneling layer is controlled to be 0.5 to 5 nm.

[0034] The substrate is firstly subjected to dedamaging and polishing treatment, and single-sided or double-sided polishing is performed using an alkaline reagent containing additives, and then a tunneling layer is deposited on the back side of the substrate using an LPCVD device.

[0035] Step 2: growing a doped silicon layer on the basis of the tunneling layer.

[0036] The doped silicon layer is a doped amorphous silicon layer or a doped polysilicon layer, and the doping element type is the same as the doping element type of the silicon substrate. The doped amorphous silicon layer can be formed by in-situ deposition, the doped polysilicon layer can be formed by annealing and converting the doped amorphous silicon layer, or it can be formed by diffusion and annealing of a deposited intrinsic amorphous silicon layer.

[0037] Preferably, the doped silicon layer includes a plurality of silicon layers stacked in sequence in the thickness direction and an interface layer sandwiched between the plurality of silicon layers, the silicon layer is a doped amorphous silicon layer or a doped polycrystalline silicon layer, the interface layer is a silicon oxide layer, and the silicon oxide layer is thinner than any silicon layer. Each of the silicon layers and the interface layer contains the same doping element as the silicon substrate. The interface layer is used as a stop layer for selectively etching the doped silicon layer, and even a very thin interface layer can have an excellent blocking effect on the etchant, so that a doped silicon layer structure with different heights, i.e., a Poly finger structure, is obtained on the surface of the silicon substrate.

[0038] Please refer to Figure 2 As shown, above the tunneling layer 4 are a first doped silicon layer 91 , an interface layer 92 , and a second doped silicon layer 93 .

[0039] After the tunnel layer is deposited, the doped silicon layer is deposited on the surface of the tunnel layer using LPCVD equipment.

[0040] Step 3: Selectively process the doped silicon layer.

[0041] When the doped silicon layer is a doped amorphous silicon layer, the selective treatment of the doped silicon layer is: laser heat treatment is performed on the target portion of the doped amorphous silicon layer. The laser used is any one of infrared laser, green laser, and ultraviolet laser. The laser wavelength is 190nm to 1064nm. The atmosphere of the laser heat treatment contains water vapor or an oxygen-containing atmosphere, such as oxygen, ozone, N 2O, the flow rate of water vapor is 1-500sccm. At this time, water vapor can provide an oxygen source, so that an oxide layer is generated on the surface of the target part of the doped amorphous silicon layer treated by laser heat treatment, and the pattern of the oxide area corresponds to the contact pattern of the electrode and the doped silicon layer. In the subsequent fluorine-containing gas dry etching process, the oxide layer can protect the doped amorphous silicon layer area from being damaged.

[0042] Please refer to Figure 3 As shown, an oxide layer 10 is formed on a target portion of the surface of the doped amorphous silicon layer to protect the doped amorphous silicon layer from being damaged during the etching process.

[0043] When the doped silicon layer is a doped polysilicon layer, the selective treatment of the doped silicon layer is: printing an organic mask on the doped polysilicon, the printed pattern of the organic mask corresponds to the contact pattern of the electrode and the doped silicon layer, the ratio of the printing width to the designed electrode width is 1:1 to 5, which is convenient for alignment and positioning during subsequent electrode printing, and the printing height of the organic mask is 1 to 10 μm.

[0044] Please refer to Figure 4 As shown, an organic mask 11 is formed on a target portion of the surface of the doped polysilicon layer to protect the doped polysilicon layer from being damaged during the etching process.

[0045] After etching is completed, the organic mask needs to be removed and cleaned. The organic mask is removed using an alkaline etchant, the etching temperature is 25℃~80℃, and the etching time is 1min~5min; wherein, the alkaline etchant includes one or more of NaOH, KOH or organic alkaline reagents. Under this etching parameter, the organic mask can be removed quickly and efficiently, so that the organic mask is completely or partially dissolved in the alkaline solution, and the non-dissolved part floats in the solution in strips or floccules, and is collected by the filter through overflow cleaning. Cleaning includes deionized water cleaning and alkaline solution + hydrogen peroxide / ozone cleaning. Deionized water cleaning is used to rinse the residual alkaline solution on the surface of the silicon wafer; alkaline solution + hydrogen peroxide / ozone cleaning is to remove the residual organic matter or organic groups on the surface of the silicon wafer, and the organic matter is decomposed by the oxidation of hydrogen peroxide or ozone. The cleaning temperature is 25℃~80℃, and the cleaning time is 1min~5min; wherein, the alkaline solution includes one or more of NaOH, KOH or organic alkaline reagents, and the concentration of the alkaline solution is 1%~3%.

[0046] Step 4: Use fluorine-containing gas to selectively etch the doped silicon layer to form a local passivation contact structure on the surface.

[0047] The present invention adopts fluorine-containing gas dry etching, and the fluorine-containing gas includes F 2 +N 2 、XeF 2 , CIF, CIF 3 IF 5 BrF 5BrF 3 One or more of the above. Fluorine-containing gases have a selectivity of at least 100 to silicon oxide and silicon, so even a thin layer of silicon oxide can provide good protection for the underlying doped silicon layer. The protective effect of silicon oxide in the dry etching process is much greater than that in the wet etching process. Wet etching usually uses strong alkaline solutions such as NaOH, KOH or TMAH to corrode the silicon layer, and these strong alkaline solutions are also corrosive to silicon oxide. For example, SiO 2 The etching rate in 44% KOH solution at 85°C is 1.4 nm / min, which requires thicker and denser SiO 2 The layer is used to protect the underlying amorphous silicon / polysilicon layer during wet etching, which undoubtedly increases process time and production cost. However, using fluorine-containing gas for dry etching can effectively reduce the thickness of the SiO layer. 2 The doped silicon layer of the present invention includes a plurality of silicon layers stacked in sequence in the thickness direction and SiO2 sandwiched between the plurality of silicon layers. 2 The interface layer, even the outer layer of SiO 2 The interface layer is etched by fluorine-containing gas, and the inner SiO 2 The interface layer can also provide a barrier to fluorine-containing gases.

[0048] Please refer to Figure 5 As shown, after dry etching with fluorine-containing gas, a local passivation contact structure is formed in the non-electrode contact area on the surface of the doped silicon layer.

[0049] Step 5: forming an electrode on the local passivation contact structure.

[0050] After printing the electrode on the local passivation contact structure, on the one hand, the electrode is in direct contact with the thick doped silicon layer area instead of the silicon substrate, which can reduce the carrier recombination between the semiconductor and the electrode and reduce the contact resistance; on the other hand, the thin doped silicon layer area is set at the non-electrode contact position, which can reduce the strong absorption of sunlight by the doped silicon layer and solve the contradiction between passivation and light absorption.

[0051] Example 1

[0052] The solar cell is prepared by the above preparation method, comprising the following steps:

[0053] 1. Texturing: Select N-type single crystal silicon wafer as the silicon substrate and perform double-sided texturing. The thickness of the N-type single crystal silicon wafer is 175μm and the resistivity is 0.8Ω / □;

[0054] 2. Boron diffusion: Use a low-pressure and high-temperature diffusion furnace to diffuse boron on the front side of the N-type single crystal silicon wafer. The diffusion temperature is 1000°C and the diffusion time is 60 minutes. After diffusion, the square resistance of the P+ doped layer is 85Ω / □, the junction depth is 0.35μm, and the thickness of the BSG layer is 150nm.

[0055] 3. Remove the BSG layer: remove the BSG layer on the back and sides of the silicon wafer;

[0056] 4. Backside etching and polishing: remove the PN junction formed by parasitic diffusion on the back side of the silicon wafer to prevent edge leakage;

[0057] 5. Growth of tunnel oxide layer: Use LPCVD equipment to deposit SiO on the back of N-type single crystal silicon wafer 2 Tunneling oxide layer, the oxide layer thickness is 0.5~5nm;

[0058] 6. Growth of phosphorus-doped amorphous silicon layer: On the basis of the tunnel oxide layer, continue to deposit a phosphorus-doped amorphous silicon layer with a thickness of 180nm;

[0059] 7. Laser heat treatment: Laser heat treatment is performed on the target area of ​​the doped amorphous silicon layer to form a layer of silicon oxide on the surface. The laser used is an infrared laser with a wavelength of 1064nm. The laser heat treatment area matches the electrode design pattern;

[0060] 8. Fluorine-containing gas dry etching: Use F 2 and N 2 The mixed gas is used to etch the surface, and the doped amorphous silicon on the front and side surfaces and the doped amorphous silicon on the back without organic mask protection are removed or thinned. The doped amorphous silicon without mask protection is etched to a thickness of 10 to 20 nm.

[0061] 9. High temperature annealing: High temperature annealing converts doped amorphous silicon into doped polysilicon;

[0062] 10. Remove the front BSG and back PSG: Use HF or a mixture of HF and HCl to remove the front BSG and back PSG of the silicon wafer;

[0063] 11. Silicon wafer coating: Aluminum oxide and silicon nitride layers are coated on the front and back of the silicon wafer;

[0064] 12. Electrode printing: Screen printing and sintering are performed on the front and back of the silicon wafer. Ag electrode is printed on the front and Ag / Al electrode is printed on the back.

[0065] Please refer to Figure 1As shown, a solar cell is produced through the above steps, which comprises a passivation anti-reflection layer 1, a doping layer 2, a silicon substrate 3, a tunneling layer 4, and a doped polysilicon layer 7 in order from the front side to the back side of the silicon wafer in thickness direction, a front electrode 5 is printed on the front side of the silicon wafer, and a back electrode 6 is printed on the back side of the silicon wafer, and directly contacts the thick doped polysilicon layer 7 through a local passivation contact structure, and the remaining area on the back side of the silicon wafer is a thin doped polysilicon layer 8.

[0066] The fill factor of the solar cell prepared in this embodiment is 82.5%, the photoelectric conversion efficiency is 24.55%, the open circuit voltage is 714.6mV, and the short circuit current is 41.6mA / cm 2 .

[0067] Example 2

[0068] The solar cell is prepared by the above preparation method, comprising the following steps:

[0069] 1. Texturing: Select N-type single crystal silicon wafer as the silicon substrate and perform double-sided texturing. The thickness of the N-type single crystal silicon wafer is 155μm and the resistivity is 2.1Ω / □;

[0070] 2. Boron diffusion: Use a low-pressure and high-temperature diffusion furnace to diffuse boron on the front side of the N-type single crystal silicon wafer. The diffusion temperature is 900°C and the diffusion time is 60 minutes. After diffusion, the square resistance of the P+ doped layer is 120Ω / □, the junction depth is 0.35μm, and the thickness of the BSG layer is 120nm.

[0071] 3. Remove the BSG layer: remove the BSG layer on the back and sides of the silicon wafer;

[0072] 4. Backside etching and polishing: remove the PN junction formed by parasitic diffusion on the back side of the silicon wafer to prevent edge leakage;

[0073] 5. Growth of tunnel oxide layer: Use LPCVD equipment to deposit SiO on the back of N-type single crystal silicon wafer 2 Tunneling oxide layer, the oxide layer thickness is 0.5nm;

[0074] 6. Growth of phosphorus-doped amorphous silicon layer and interface layer: On the basis of the tunneling oxide layer, a phosphorus-doped amorphous silicon layer is continuously deposited with a thickness of 30 nm; a silicon oxide interface layer is deposited on the phosphorus-doped amorphous silicon layer with a thickness of 0.2 nm, and a phosphorus-doped amorphous silicon layer is continuously deposited on the interface layer with a thickness of 65 nm;

[0075] 7. Laser heat treatment: Laser heat treatment is performed on the target area of ​​the doped amorphous silicon layer to form a layer of silicon oxide on the surface. The laser used is a green laser with a wavelength of 532nm. The laser heat treatment area matches the electrode design pattern;

[0076] 8. Fluorine-containing gas dry etching: using XeF2 and N 2 The mixed gas is used for surface etching. The doped amorphous silicon on the front and side surfaces and the doped amorphous silicon on the back surface that has not been subjected to laser heat treatment are thinned. The interface layer is the etching stop layer. The etching pressure is 0.2 Torr.

[0077] 9. High temperature annealing: High temperature annealing converts doped amorphous silicon into doped polysilicon;

[0078] 10. Remove the front BSG and back PSG: Use HF or a mixture of HF and HCl to remove the front BSG and back PSG of the silicon wafer;

[0079] 11. Silicon wafer coating: Aluminum oxide and silicon nitride layers are coated on the front and back of the silicon wafer;

[0080] 12. Electrode printing: Screen printing and sintering are performed on the front and back of the silicon wafer. Ag electrode is printed on the front and Ag / Al electrode is printed on the back.

[0081] The fill factor of the solar cell prepared in this embodiment is 82.7%, the photoelectric conversion efficiency is 24.70%, the open circuit voltage is 714.8mV, and the short circuit current is 41.8mA / cm 2 .

[0082] Example 3

[0083] The solar cell is prepared by the above preparation method, comprising the following steps:

[0084] 1. Texturing: Select N-type single crystal silicon wafer as the silicon substrate and perform double-sided texturing. The thickness of the N-type single crystal silicon wafer is 140μm and the resistivity is 1.2Ω / □;

[0085] 2. Boron diffusion: Use a low-pressure and high-temperature diffusion furnace to diffuse boron on the front side of the N-type single crystal silicon wafer. The diffusion temperature is 950°C and the diffusion time is 40 minutes. After diffusion, the square resistance of the P+ doped layer is 100Ω / □, the junction depth is 0.15μm, and the thickness of the BSG layer is 90nm.

[0086] 3. Remove the BSG layer: remove the BSG layer on the back and sides of the silicon wafer;

[0087] 4. Backside etching and polishing: remove the PN junction formed by parasitic diffusion on the back side of the silicon wafer to prevent edge leakage;

[0088] 5. Growth of tunnel oxide layer: Use LPCVD equipment to deposit SiO on the back of N-type single crystal silicon wafer 2 Tunneling oxide layer, the oxide layer thickness is 1.2nm;

[0089] 6. Growth of phosphorus-doped amorphous silicon layer and interface layer: On the basis of the tunneling oxide layer, a first phosphorus-doped amorphous silicon layer is continuously deposited with a thickness of 30 nm; a first silicon oxide interface layer is deposited on the first phosphorus-doped amorphous silicon layer with a thickness of 0.3 nm, and a second phosphorus-doped amorphous silicon layer is continuously deposited on the first interface layer with a thickness of 35 nm; a second silicon oxide interface layer is deposited on the second phosphorus-doped amorphous silicon layer with a thickness of 0.2 nm, and a third phosphorus-doped amorphous silicon layer is continuously deposited on the second interface layer with a thickness of 60 nm;

[0090] 7. Printing organic mask: Printing an organic mask on the back grid line area and then drying it. The organic mask pattern corresponds to the metal electrode pattern to be printed. The width of the grid line area is 260 μm.

[0091] 8. Fluorine-containing gas dry etching: using BrF 2 and N 2 The mixed gas is used for surface etching, and the doped amorphous silicon on the front and side surfaces and the doped amorphous silicon on the back without organic mask protection are removed or thinned. The second interface layer is an etching stop layer, and the etching pressure is 1.0 Torr;

[0092] 9. Remove the organic mask: Use KOH solution to remove the organic mask in the back gate line area;

[0093] 10. High temperature annealing: High temperature annealing converts doped amorphous silicon into doped polysilicon;

[0094] 11. Remove the front BSG and back PSG: Use HF or a mixture of HF and HCl to remove the front BSG and back PSG of the silicon wafer;

[0095] 12. Silicon wafer coating: Aluminum oxide and silicon nitride layers are coated on the front and back of the silicon wafer;

[0096] 13. Electrode printing: Screen printing and sintering are performed on the front and back of the silicon wafer. Ag electrode is printed on the front and Ag / Al electrode is printed on the back.

[0097] The fill factor of the solar cell prepared in this embodiment is 82.3%, the photoelectric conversion efficiency is 24.72%, the open circuit voltage is 715.5mV, and the short circuit current is 42.0mA / cm 2 .

[0098] Comparative Example:

[0099] A solar cell is prepared by conventional methods, which is basically the same as the solar cell structure of the above embodiment, except that the solar cell has a passivation contact structure of a tunneling layer and a doped silicon layer only under the electrode contact, and there is no doped silicon layer on the non-electrode contact area, which is passivated by a passivation layer containing silicon nitride deposited above. The preparation method of the above solar cell is as follows:

[0100] 1. Texturing: Select N-type single crystal silicon wafer as the silicon substrate and perform double-sided texturing. The thickness of the N-type single crystal silicon wafer is 175μm and the resistivity is 0.8Ω / □;

[0101] 2. Boron diffusion: Use a low-pressure and high-temperature diffusion furnace to diffuse boron on the front side of the N-type single crystal silicon wafer. The diffusion temperature is 1000°C and the diffusion time is 60 minutes. After diffusion, the square resistance of the P+ doped layer is 85Ω / □, the junction depth is 0.35μm, and the thickness of the BSG layer is 150nm.

[0102] 3. Remove the BSG layer: remove the BSG layer on the back and sides of the silicon wafer;

[0103] 4. Backside etching and polishing: remove the PN junction formed by parasitic diffusion on the back side of the silicon wafer to prevent edge leakage;

[0104] 5. Growth of tunnel oxide layer: Use LPCVD equipment to deposit SiO on the back of N-type single crystal silicon wafer 2 Tunneling oxide layer, the oxide layer thickness is 0.5~5nm;

[0105] 6. Growth of phosphorus-doped amorphous silicon layer: On the basis of the tunnel oxide layer, continue to deposit a phosphorus-doped amorphous silicon layer with a thickness of 180nm;

[0106] 7. Laser removal of the phosphorus-doped amorphous silicon layer in the non-contact area;

[0107] 8. Wet etching and cleaning: Use a solution containing NaOH to etch the surface, and plate doped amorphous silicon on the front and sides;

[0108] 9. High temperature annealing: High temperature annealing converts doped amorphous silicon into doped polysilicon;

[0109] 10. Remove BSG on the front and PSG on the back: Use HF or a mixture of HF and HCl to remove BSG on the front and PSG on the back of the silicon wafer;

[0110] 11. Silicon wafer coating: Aluminum oxide and silicon nitride layers are coated on the front and back of the silicon wafer;

[0111] 12. Electrode printing: Screen printing and sintering are performed on the front and back of the silicon wafer. Ag electrode is printed on the front and Ag / Al electrode is printed on the back.

[0112] The fill factor of the solar cell prepared in this comparative example is 82.1%, the photoelectric conversion efficiency is 24.34%, the open circuit voltage is 713.5mV, and the short circuit current is 41.2mA / cm 2The performance of the solar cell prepared in Example 1 was compared with that of the solar cell prepared in the comparative example. Under the same preparation parameters, the solar cell using the fluorine-containing gas dry etching process was superior to the solar cell using the wet etching process in all parameters.

Claims

1. A method for preparing a solar cell, characterized in that: The following steps are involved: S1 grows a tunneling layer on one side of the silicon substrate; S2 grows a doped silicon layer based on the tunneling layer; S3 selectively processes the doped silicon layer; S4 uses fluorine-containing gas to selectively etch the doped silicon layer to form a local passivation contact structure on the surface; S5: forming an electrode on the local passivation contact structure.

2. The preparation method according to claim 1, characterized in that: The tunneling layer includes one or more of silicon oxynitride, silicon carbide, silicon nitride, titanium nitride, aluminum oxide, and silicon oxide.

3. The preparation method according to claim 1, characterized in that: The local passivation contact structure comprises an electrode contact portion and a non-electrode contact portion, and the thickness of the doped silicon layer of the electrode contact portion is greater than the thickness of the doped silicon layer of the non-electrode contact portion.

4. The preparation method according to claim 3, characterized in that: The doped silicon layer is a doped amorphous silicon layer or a doped polycrystalline silicon layer, and the type of doped elements is the same as that of the silicon substrate.

5. The preparation method according to claim 3, characterized in that: The doped silicon layer includes a plurality of silicon layers stacked in sequence in the thickness direction and a plurality of silicon oxide interface layers located between the silicon layers. The silicon layer is a doped amorphous silicon layer or a doped polycrystalline silicon layer. The types of doping elements of the silicon layer and the silicon oxide interface layer are the same as those of the silicon substrate. The thickness of the silicon oxide interface layer is less than the thickness of any silicon layer.

6. The preparation method according to claim 4 or 5, characterized in that: The selective treatment includes: Selectively printing a mask on the surface of the doped polysilicon layer, wherein the shape of the mask matches the shape of the electrode contact portion; The surface of the doped amorphous silicon layer is selectively oxidized, and the shape of the oxidized region matches the shape of the electrode contact portion.

7. The preparation method according to claim 6, characterized in that: The selective treatment of the doped amorphous silicon layer is to perform laser heat treatment on the region to be oxidized to form a silicon oxide layer in the region.

8. The preparation method according to claim 7, characterized in that: The selective treatment of the doped polysilicon layer is to print an organic mask on the target area on the surface of the doped polysilicon layer, and the shape of the mask matches the shape of the electrode contact part.

9. The preparation method according to claim 8, characterized in that: The preparation method also includes removing and cleaning the organic mask: the removal of the organic mask adopts an alkaline etchant, and the alkaline etchant includes one or more of NaOH, KOH or organic alkaline reagents; the cleaning of the organic mask includes deionized water cleaning and cleaning with a mixed solution of an alkaline reagent and an oxidant, and the alkaline reagent includes one or more of NaOH, KOH or organic alkaline reagents, and the oxidant includes one or more of hydrogen peroxide and ozone.

10. The preparation method according to claim 1, characterized in that: The fluorine-containing gas includes one or more of F2+N2, XeF2, ClF, CIF3, IF5, BrF5 or BrF3.

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