Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention provides a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a silicon substrate, the silicon substrate is provided with a first surface and a second surface which are oppositely arranged, and the first surface is provided with first areas and second areas which are alternately arranged; the tunneling oxide layer, the doped polycrystalline silicon layer and the SiNx mask layer are located in the first region and are sequentially stacked in the direction away from the silicon substrate; the silicon oxide layer and the antireflection layer are located in the second area and are sequentially stacked in the direction away from the silicon substrate; the intrinsic amorphous silicon layer, the doped microcrystalline silicon layer and the transparent conductive oxide layer are located on the second surface and sequentially stacked in the direction away from the silicon substrate; and the doping type of the doped microcrystalline silicon layer is opposite to that of the doped polycrystalline silicon layer. According to the technical scheme of the invention, through the specific structures of the first surface and the second surface, the double-sided rate and the photoelectric conversion efficiency of the cell can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] With the large-scale development of clean energy, the proportion of photovoltaics in terminal energy consumption continues to increase. In the future, photovoltaics will rely on its advantages such as mature application methods, wide distribution of resources, and continuous technological optimization, and is expected to become the clean energy power generation method with the largest installed capacity.

[0003] At present, the mainstream photovoltaic crystalline silicon is PERC (emitter and back passivation cell), TopCon (tunnel oxide passivation contact cell), HJT (heterojunction cell), IBC (interdigitated back contact cell), etc. At this stage, PERC, as the mainstream cell in the p-type stage, has relatively low conversion efficiency, and its production capacity is accelerating; TopCon, as a transitional technology, its efficiency cannot reach the ceiling of crystalline silicon cells; HJT equipment has a large initial investment cost, and uses ITO (precious metal indium) and high-consumption silver paste, resulting in high cost and difficulty in large-scale mass production; IBC cells have complex processes and low yields, resulting in high costs, and their low bifaciality has always been difficult to apply to centralized photovoltaic projects.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] The present invention provides a solar cell and a method for preparing the same, and a photovoltaic module, aiming to solve the above technical problems. The solar cell of the present invention can effectively improve the bifaciality and photoelectric conversion efficiency of the cell through the specific structure of the first surface and the second surface.

[0006] In a first aspect, an embodiment of the present application provides a solar cell, comprising: A silicon substrate, the silicon substrate having a first surface and a second surface arranged opposite to each other, the first surface having first regions and second regions arranged alternately; The tunnel oxide layer, the doped polysilicon layer and the SiN layer are located in the first region and are sequentially stacked in a direction away from the silicon substrate. x mask layer; A silicon oxide layer and an anti-reflection layer located in the second region and stacked in sequence in a direction away from the silicon substrate; an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer located on the second surface and stacked in sequence in a direction away from the silicon substrate; the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polycrystalline silicon layer; Located in the SiN xa first electrode on the mask layer; A second electrode is located on the transparent conductive oxide layer.

[0007] Optionally, the width of the doped polysilicon layer and the SiN x The widths of the mask layers are the same, and the width of the doped polysilicon layer is 40-50 μm.

[0008] Optionally, the doping concentration of the doped polysilicon layer is 1E20-2E20 / cm 3 .

[0009] Optionally, the thickness of the tunnel oxide layer is 1.3-2.0 nm, the thickness of the doped polysilicon layer is 90-120 nm, and the thickness of the SiN x The thickness of the mask layer is 60-70 nm; and / or The thickness of the silicon oxide layer is 1.3-2.0 nm, and the thickness of the anti-reflection layer is 60-70 nm.

[0010] Optionally, the intrinsic amorphous silicon layer has a thickness of 5-7 nm, the doped microcrystalline silicon layer has a thickness of 20-25 nm, and the transparent conductive oxide layer has a thickness of 45-60 nm.

[0011] In a second aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising: Providing a silicon substrate, wherein the silicon substrate has a first surface and a second surface arranged opposite to each other, and the first surface has first regions and second regions arranged alternately; In the first region, a tunnel oxide layer, a doped polysilicon layer and a SiN layer are sequentially stacked in a direction away from the silicon substrate. x mask layer; forming a silicon oxide layer and an anti-reflection layer stacked in sequence in a direction away from the silicon substrate in the second region; forming an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer in sequence on the second surface; the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polycrystalline silicon layer; In the SiN x A first electrode is formed on the mask layer, and a second electrode is formed on the transparent conductive oxide layer.

[0012] Optionally, the tunnel oxide layer, the doped polysilicon layer and the SiN layer are sequentially stacked in a direction away from the silicon substrate. x Mask layer, including: An initial tunneling oxide layer, an initial doped polysilicon layer, an initial SiN x mask layer; The first laser etching process is used to sequentially remove the initial SiN x The mask layer, the initial doped polysilicon layer and the initial tunneling oxide layer retain the initial SiN x A mask layer, an initial doped polysilicon layer and an initial tunneling oxide layer are formed to form the SiN x A mask layer, the doped polysilicon layer and the tunneling oxide layer. Optionally, forming the initial doped polysilicon layer includes: forming an initial intrinsic polysilicon layer on the initial tunneling oxide layer; The initial intrinsic polysilicon layer is doped to form the initial doped polysilicon layer.

[0013] Optionally, forming a silicon oxide layer and an anti-reflection layer stacked in sequence in a direction away from the silicon substrate in the second region includes: In the embodiment of the present invention, the tunnel oxide layer, the doped polysilicon layer and the SiN x An initial silicon oxide layer and an initial anti-reflection layer are sequentially formed on the first surface of the mask layer; A second laser etching process is used to remove the initial silicon oxide layer and the initial anti-reflection layer located in the first region, exposing the SiN x The mask layer retains the initial silicon oxide layer and the initial anti-reflection layer located in the second region to form a silicon oxide layer and an anti-reflection layer.

[0014] Optionally, in the second laser etching process, the laser wavelength is 520-540 nm, the etching time is 0.7-0.8 s, and the laser power is 30-40 W.

[0015] In a third aspect, an embodiment of the present application provides a photovoltaic module, including the solar cell described in any one of the above embodiments.

[0016] The above technical solution adopted in the embodiment of the present application may have the following advantages: In the solar cell, a tunnel oxide layer, a doped polysilicon layer, a SiN x The mask layer and the first electrode are provided with a silicon oxide layer and an anti-reflection layer stacked in sequence in the second region of the first surface; the solar cell is provided with a doped polysilicon layer only in the first region, and no doped polysilicon layer is provided in the second region, which helps to reduce parasitic absorption loss; the second surface of the solar cell is provided with an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer stacked in sequence to improve the passivation effect, thereby improving the cell conversion efficiency. The solar cell of the embodiment of the present application can effectively improve the bifaciality and photoelectric conversion efficiency of the cell through the specific structure of the first surface and the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0018] Figure 1 is a flow chart of a method for preparing a solar cell provided in an embodiment of the present application; Figure 2 In the embodiment of the present application, an initial tunneling oxide layer, an initial doped polysilicon layer and an initial SiN x Product schematic diagram of the mask layer; Figure 3 In the embodiment of the present application, a tunnel oxide layer, a doped polysilicon layer and a SiN x Product schematic diagram of the mask layer; Figure 4 is a schematic diagram of a product for forming an initial silicon oxide layer and an initial anti-reflection layer in an embodiment of the present application; Figure 5 It is a schematic diagram of a product in which a silicon oxide layer, an anti-reflection layer, an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer and a transparent conductive oxide layer are formed in an embodiment of the present application; Figure 6 is a schematic diagram of a product for forming a photosensitive mask layer in an embodiment of the present application; Figure 7 It is a product schematic diagram of forming the first electrode and the second electrode in an embodiment of the present application.

[0019] Description of reference numerals: 10. silicon substrate; 11. first region; 12. second region; 21a, initial tunnel oxide layer; 21b, tunnel oxide layer; 22a, initial doped polysilicon layer; 22b, doped polysilicon layer; 23a, initial SiN x Mask layer; 23b, SiN x Mask layer; 24a, initial silicon oxide layer; 24b, silicon oxide layer; 25a, initial anti-reflection layer; 25b, anti-reflection layer; 26, photosensitive mask layer; 31. Intrinsic amorphous silicon layer; 32. Doped microcrystalline silicon layer; 33. Transparent conductive oxide layer; 41. First electrode; 42. Second electrode. DETAILED DESCRIPTION

[0020] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0021] like Figure 7 As shown, an embodiment of the present application provides a solar cell, comprising: A silicon substrate 10, wherein the silicon substrate 10 has a first surface and a second surface that are opposite to each other, and the first surface has first regions 11 and second regions 12 that are alternately arranged; The tunnel oxide layer 21b, the doped polysilicon layer 22b and the SiN layer 21b are located in the first region 11 and are sequentially stacked in a direction away from the silicon substrate 10. x Mask layer 23b; A silicon oxide layer 24b and an anti-reflection layer 25b located in the second region 12 and stacked in sequence in a direction away from the silicon substrate 10; An intrinsic amorphous silicon layer 31, a doped microcrystalline silicon layer 32, and a transparent conductive oxide layer 33 are located on the second surface and sequentially stacked in a direction away from the silicon substrate 10; the doping type of the doped microcrystalline silicon layer 32 is opposite to the doping type of the doped polycrystalline silicon layer 22b; Located in SiN x A first electrode 41 on the mask layer 23b; The second electrode 42 is located on the transparent conductive oxide layer 33 .

[0022] The silicon substrate may be an N-type silicon substrate or a P-type silicon substrate, and the doped polysilicon layer may be an N-type doped polysilicon layer or a P-type doped polysilicon layer. The doping type of the silicon substrate may be the same as or opposite to the doping type of the doped polysilicon layer. When the doping type of the silicon substrate is the same as the doping type of the doped polysilicon layer, the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polysilicon layer, and a PN junction is formed between the substrate and the doped microcrystalline silicon layer; when the doping type of the silicon substrate is opposite to the doping type of the doped polysilicon layer, the doping type of the doped microcrystalline silicon layer is the same as the doping type of the substrate, and a PN junction is formed between the substrate and the doped polysilicon layer. The N-type doping element may include one or more of phosphorus, arsenic, and antimony; the P-type doping element may include one or more of boron, gallium, and indium.

[0023] The first electrode and the second electrode may both be metal electrodes, and the material of the metal electrode includes but is not limited to one of Au, Ag, Al, and Cu.

[0024] In some embodiments, the width of the doped polysilicon layer and the SiN x The width of the mask layer is the same, and the width of the doped polysilicon layer is 40-50 μm.

[0025] The doped polysilicon layer is located in the first area, and there is no doped polysilicon layer in the second area. When the doped polysilicon layer is wider, more areas of the battery surface will be blocked, reducing the surface active area exposed to light, resulting in lower photoelectric conversion efficiency; when the doped polysilicon layer is narrower, it will increase resistance and affect electrical performance. When the width of the doped polysilicon layer is 40-50μm, the battery can have good photoelectric conversion efficiency and lower resistance, which helps to improve the overall performance of the solar cell. Specifically, the width of the doped polysilicon layer can be 40μm, 45μm or 50μm.

[0026] In some embodiments, the doping concentration of the doped polysilicon layer is 1E20-2E20 / cm 3 .

[0027] When the doping concentration of the doped polysilicon layer is 1E20-2E20 / cm 3 When the conductivity of the doped polysilicon layer is increased, the conductivity can be reasonably controlled, which can not only improve the charge collection efficiency and reduce the loss of charge during the transmission process, but also optimize the contact resistance. Specifically, the doping concentration of the doped polysilicon layer can be 1E20 / cm 3 , 1.2E20 / cm 3 , 1.5E20 / cm 3 , 1.8E20 / cm 3 or 2E20 / cm 3 In some embodiments, the thickness of the tunnel oxide layer is 1.3-2.0 nm, the thickness of the doped polysilicon layer is 90-120 nm, and the thickness of the SiN x The thickness of the mask layer is 60-70 nm; and / or The thickness of the silicon oxide layer is 1.3-2.0 nm, and the thickness of the anti-reflection layer is 60-70 nm.

[0028] The tunneling oxide layer is an ultra-thin passivation layer that allows majority electrons to tunnel into the doped polysilicon layer while blocking the recombination of minority holes, thereby allowing electrons to be laterally transmitted in the polysilicon layer and collected by the electrodes, greatly reducing the metal contact recombination current, increasing the open circuit voltage and short circuit current of the battery, and thus improving battery efficiency. When the thickness of the tunneling oxide layer is 1.3-2.0nm, it can not only ensure effective tunneling and passivation effects, but also avoid problems such as discontinuous or uneven film layers caused by the tunneling oxide layer being too thin. Specifically, the thickness of the tunneling oxide layer can be 1.3nm, 1.5nm, 1.7nm or 2.0nm.

[0029] The doped polysilicon layer acts as a charge carrier collection layer, which can improve the fill factor and open circuit voltage of the battery. If the thickness of the doped polysilicon layer is too small, it is not enough to form effective electron collection, and if the thickness is too large, it will increase resistance and parasitic absorption; when the thickness of the doped polysilicon layer is 90-120nm, it allows to provide sufficient lateral electron transmission paths while maintaining low contact resistance, so that electrons can be effectively collected by the electrode. Specifically, the thickness of the doped polysilicon layer can be 90nm, 100nm or 120nm.

[0030] The tunnel oxide layer is combined with the doped polysilicon layer to form a passivation contact structure, which reduces surface recombination on the first side and improves the overall efficiency of the battery.

[0031] S N x The mask layer is a protective layer for the passivation contact structure, used to protect the tunneling oxide layer and doped polysilicon layer. x When the thickness of the mask layer is 60-70nm, it can ensure that SiN x The layer provides protection while avoiding the SiN x The mask layer is too thick, which increases parasitic absorption or reduces the optical transmittance of the cell. x The thickness of the mask layer may be 60 nm, 65 nm or 70 nm.

[0032] Tunneling oxide layer, doped polysilicon layer and SiN x The thickness of the mask layer works synergistically to further enhance the passivation effect, improve charge transport, and provide good optical properties and structural protection, thereby improving the performance and reliability of the battery.

[0033] When the thickness of the silicon oxide layer is 1.3-2.0 nm, it can provide effective surface passivation, reduce dangling bonds on the silicon wafer surface, reduce the surface recombination rate, and increase the open circuit voltage of the battery. Specifically, the thickness of the silicon oxide layer can be 1.3 nm, 1.5 nm, 1.7 nm or 2.0 nm.

[0034] When the thickness of the anti-reflection layer is 60-70nm, it can effectively reduce the reflection of light on the surface of the battery, increase the transmittance of light, and improve the short-circuit current of the battery. The material of the anti-reflection layer may include one or more of silicon nitride, aluminum oxide, and titanium oxide. Specifically, the thickness of the anti-reflection layer may be 60nm, 65nm, or 70nm.

[0035] The synergistic effect of the thickness of the silicon oxide layer and the anti-reflection layer can reduce the surface recombination of charges while improving the utilization of light, thereby improving the overall photoelectric conversion efficiency of the battery.

[0036] In some embodiments, the intrinsic amorphous silicon layer has a thickness of 5-7 nm, the doped microcrystalline silicon layer has a thickness of 20-25 nm, and the transparent conductive oxide layer has a thickness of 45-60 nm.

[0037] The doped microcrystalline silicon layer can collect and transport charge carriers; when the thickness of the doped microcrystalline silicon layer is 20-25 nm, it can not only ensure good conductivity and effective charge collection, but also avoid excessive parasitic absorption. Specifically, the thickness of the doped microcrystalline silicon layer can be 20 nm, 23 nm or 25 nm.

[0038] The non-doped intrinsic amorphous silicon layer is arranged between the silicon substrate and the doped microcrystalline silicon layer, which can improve the passivation effect, reduce the dangling bonds on the silicon wafer surface, and reduce the surface recombination rate. When the thickness of the intrinsic amorphous silicon layer is 5-7nm, it can not only make the second surface of the silicon substrate have a good passivation effect, but also reduce the parasitic absorption of light by the material, and improve the performance of the battery. Specifically, the thickness of the intrinsic amorphous silicon layer can be 5nm, 6nm or 7nm.

[0039] The transparent conductive oxide layer can collect and transmit the current generated by photogenerated carriers, allowing sunlight to pass through, reducing light reflection and absorption losses, and improving the photoelectric conversion efficiency of the battery. When the thickness of the transparent conductive oxide layer is 45-60nm, the conductivity and transparency can be balanced to ensure the high photoelectric conversion efficiency of the battery. Among them, the material of the transparent conductive oxide layer can include one or more of indium tin oxide (ITO), aluminum zinc oxide (AZO), and fluorine-doped tin oxide (FTO). Specifically, the thickness of the transparent conductive oxide layer can be 45nm, 50nm, 55nm or 60nm.

[0040] The thicknesses of the intrinsic amorphous silicon layer, the doped microcrystalline silicon layer and the transparent conductive oxide layer work together to reduce surface recombination, achieve selective charge transfer, and improve light utilization, which helps to improve the photoelectric conversion efficiency of the battery and optimize the electrical performance of the battery.

[0041] like Figures 1 to 7 As shown, the embodiment of the present application also provides a method for preparing a solar cell, comprising: S100: providing a silicon substrate 10, wherein the silicon substrate 10 has a first surface and a second surface arranged opposite to each other, and the first surface has first regions 11 and second regions 12 arranged alternately; S200: forming a tunnel oxide layer 21b, a doped polysilicon layer 22b and a SiN layer in the first region 11 and stacking them in sequence in a direction away from the silicon substrate 10 x Mask layer 23b; S300: forming a silicon oxide layer 24b and an anti-reflection layer 25b stacked in sequence in a direction away from the silicon substrate 10 in the second region 12; S400: forming an intrinsic amorphous silicon layer 31, a doped microcrystalline silicon layer 32, and a transparent conductive oxide layer 33 on the second surface in sequence; the doping type of the doped microcrystalline silicon layer 32 is opposite to the doping type of the doped polycrystalline silicon layer 22b; S500: In SiN x A first electrode 41 is formed on the mask layer 23 b , and a second electrode 42 is formed on the transparent conductive oxide layer 33 .

[0042] The provided silicon substrate can be textured, and the velvet pyramid size is 3-5μm. This velvet structure can increase the roughness of the silicon substrate surface, help improve the pull-off force between the metal electrode and the silicon substrate, and ensure the mechanical stability of the battery during long-term operation.

[0043] like Figure 2 and Figure 3 As shown, in some embodiments, in step S200, a tunneling oxide layer 21b, a doped polysilicon layer 22b and a SiN layer are sequentially stacked in a direction away from the silicon substrate 10 in the first region 11. x The mask layer 23b includes: S210: forming an initial tunneling oxide layer 21a, an initial doped polysilicon layer 22a, an initial SiN x Mask layer 23a; S220: Using a first laser etching process, the initial SiN x The mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a retain the initial SiN x The mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a are used to form SiN x Mask layer 23b, doped polysilicon layer 22b and tunnel oxide layer 21b.

[0044] In step S210 , an initial tunneling oxide layer and an initial doped polysilicon layer may be formed on the first surface by using a LPCVD (low pressure chemical vapor deposition) method.

[0045] In some embodiments, in the first laser etching process, the laser wavelength is 450-550nm, and the laser power is 35-45W; specifically, the laser wavelength is 450nm, 500nm or 550nm, and the laser power is 35W, 40W or 45W.

[0046] In some embodiments, in step S210, forming the initial doped polysilicon layer 22a includes: S211: forming an initial intrinsic polysilicon layer on the initial tunneling oxide layer 21a; S212: performing a doping process on the initial intrinsic polysilicon layer to form an initial doped polysilicon layer 22a.

[0047] In step S212, the doping treatment may be a P-type doping element diffusion process to form a P-type initial doped polysilicon layer; the doping treatment may also be an N-type doping element diffusion process to form an N-type initial doped polysilicon layer.

[0048] In an optional embodiment, when the initial tunneling oxide layer and the initial intrinsic polysilicon layer are formed on the first surface of the silicon substrate, the initial tunneling oxide layer and the initial intrinsic polysilicon layer are formed on the second surface and the side surface of the silicon substrate, and only the initial intrinsic polysilicon layer on the first surface is doped to form an initial doped polysilicon layer; when the SiN x After the mask layer, doped polysilicon layer and tunnel oxide layer, a chemical etching process is used to remove the initial tunnel oxide layer and the initial intrinsic polysilicon layer located on the second surface and side of the silicon substrate. The etching solution in the chemical etching process can be SC1 cleaning solution (including potassium hydroxide and isopropyl alcohol) or SC2 cleaning solution (including sodium hydroxide, hydrogen peroxide and water).

[0049] like Figure 4 and Figure 5 As shown, in some embodiments, in step S300, a silicon oxide layer 24b and an anti-reflection layer 25b are sequentially stacked in a direction away from the silicon substrate 10 in the second region 12, including: S310: In the tunnel oxide layer 21b, the doped polysilicon layer 22b and the SiN x An initial silicon oxide layer 24a and an initial anti-reflection layer 25a are sequentially formed on the first surface of the mask layer 23b; S320: Using a second laser etching process, remove the initial silicon oxide layer 24a and the initial anti-reflection layer 25a located in the first region 11, exposing the SiN x The mask layer 23b retains the initial silicon oxide layer 24a and the initial anti-reflection layer 25a located in the second region 12 to form a silicon oxide layer 24b and an anti-reflection layer 25b.

[0050] In the formation of SiN x After the mask layer, the doped polysilicon layer and the tunnel oxide layer, and before the silicon oxide layer is formed, the second area of ​​the first surface is subjected to a texturing treatment, the size of the texturing pyramid is 2-3 μm, and the laser damage is processed.

[0051] After forming the silicon oxide layer and the anti-reflection layer, the silicon substrate with the silicon oxide layer and the anti-reflection layer can also be annealed to repair the damage caused to the silicon substrate by the second laser etching process; wherein the annealing temperature is 600-700° C. and the annealing time is 30-45 minutes.

[0052] In some embodiments, in the second laser etching process, the laser wavelength is 520-540 nm, the etching time is 0.7-0.8 s, and the laser power is 30-40 W. With the above parameters, the initial silicon oxide layer and the initial anti-reflection layer in the first region can be removed, but the SiN x The mask layer is not removed to avoid over-etching or under-etching. Specifically, in the second laser etching process, the laser wavelength may be 520nm, 532nm or 540nm, the etching time may be 0.7s, 0.75s or 0.8s, and the laser power may be 30W, 35W or 40W.

[0053] In step S400 , a PECVD (Plasma Enhanced Chemical Vapor Deposition) method may be used to sequentially form a stacked intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the second surface.

[0054] In step S400 , a transparent conductive oxide layer may be formed on the doped microcrystalline silicon layer by using a PVD (physical vapor deposition) method.

[0055] Before forming the intrinsic amorphous silicon layer on the second surface, the second surface may be polished and surface treated to enhance the passivation effect of the second surface so that the reflectivity of the second surface is 38-40%.

[0056] like Figure 6 and Figure 7 As shown, in step S500, an electroplating method is used to deposit SiN x The first electrode 41 is formed on the mask layer 23b. Before forming the first electrode 41, a photosensitive mask layer 26 may be disposed on the anti-reflection layer. The photosensitive mask layer 26 covers the anti-reflection layer 25b, exposing the SiN x The mask layer 23b can effectively prevent the electrode material from contaminating the anti-reflection layer when forming the first electrode; after the first electrode is formed, the photosensitive mask layer is removed.

[0057] like Figure 7 As shown, in step S500 , the second electrode 42 is formed on the transparent conductive oxide layer 33 by screen printing.

[0058] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.

[0059] Example 1 The solar cell of embodiment 1 comprises: A silicon substrate 10 (N-type silicon substrate), the silicon substrate 10 having a first surface and a second surface arranged opposite to each other, the first surface having first regions 11 and second regions 12 arranged alternately; The tunnel oxide layer 21 b, the doped polysilicon layer 22 b (N-type doped polysilicon layer) and the SiN x Mask layer 23b; A silicon oxide layer 24b and an anti-reflection layer 25b located in the second region 12 and stacked in sequence in a direction away from the silicon substrate 10; An intrinsic amorphous silicon layer 31, a doped microcrystalline silicon layer 32 (P-type doped microcrystalline silicon layer), and a transparent conductive oxide layer 33 are located on the second surface and are sequentially stacked in a direction away from the silicon substrate 10; Located in SiN x A first electrode 41 on the mask layer 23b; The second electrode 42 is located on the transparent conductive oxide layer 33 .

[0060] The method for preparing a solar cell of embodiment 1 comprises: S100a: providing a silicon substrate 10, wherein the silicon substrate 10 has a first surface and a second surface arranged opposite to each other, and the first surface has first regions 11 and second regions 12 arranged alternately; S210a: using LPCVD method, sequentially forming an initial tunneling oxide layer 21a and an initial intrinsic polysilicon layer on the first surface; S220a: performing doping treatment on the initial intrinsic polysilicon layer to form an initial doped polysilicon layer 22a; S230a: forming an initial SiN layer on the initial doped polysilicon layer 22a x Mask layer 23a; S240a: Using the first laser etching process, the initial SiN x The mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a retain the initial SiN x The mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a are used to form SiN x The mask layer 23b (width 45 μm, thickness 65 nm), the doped polysilicon layer 22b (width 45 μm, thickness 100 nm, doping concentration 1.5E20 / cm 3 ) and a tunnel oxide layer 21b (with a thickness of 1.3 nm); wherein in the first laser etching process, the laser wavelength is 500 nm and the laser power is 40 W); S310a: In the tunnel oxide layer 21b, the doped polysilicon layer 22b and the SiN x An initial silicon oxide layer 24a and an initial anti-reflection layer 25a are sequentially formed on the first surface of the mask layer 23b; S320a: Using a second laser etching process, remove the initial silicon oxide layer 24a and the initial anti-reflection layer 25a located in the first region 11, exposing the SiN x The mask layer 23b retains the initial silicon oxide layer 24a and the initial anti-reflection layer 25a located in the second region 12 to form a silicon oxide layer 24b (with a thickness of 1.6nm) and an anti-reflection layer 25b (with a thickness of 70nm); wherein, in the second laser etching process, the laser wavelength is 532nm, the etching time is 0.75s, and the laser power is 35W); S400a: using a PECVD method, sequentially forming an intrinsic amorphous silicon layer 31 (with a thickness of 5 nm) and a doped microcrystalline silicon layer 32 (with a thickness of 22 nm) on the second surface; using a PVD method, forming a transparent conductive oxide layer 33 (with a thickness of 50 nm) on the doped microcrystalline silicon layer 32; the doping type of the doped microcrystalline silicon layer 32 is opposite to the doping type of the doped polycrystalline silicon layer 22b; S500a: Using electroplating method, on SiN x A first electrode 41 is formed on the mask layer 23 b ; and a second electrode 42 is formed on the transparent conductive oxide layer 33 by screen printing.

[0061] Example 2 The solar cell of Example 2 is prepared by referring to the preparation method of Example 1, except that the doped polycrystalline silicon layer is a P-type doped polycrystalline silicon layer, and the doped microcrystalline silicon layer is an N-type doped microcrystalline silicon layer.

[0062] Example 3 The solar cell of Example 3 is prepared by referring to the preparation method of Example 1, except that the silicon substrate is a P-type silicon substrate.

[0063] Example 4 The solar cell of Example 4 is prepared by referring to the preparation method of Example 2, except that the silicon substrate is a P-type silicon substrate.

[0064] Example 5 The solar cell of Example 5 was prepared by referring to the preparation method of Example 1, except that: S N x The width of the mask layer is 50μm, SiN x The thickness of the mask layer is 60nm; The width of the doped polysilicon layer is 50 μm, the thickness of the doped polysilicon layer is 110 nm, and the doping concentration of the doped polysilicon layer is 1.2E20 / cm 3 ; The thickness of the tunnel oxide layer is 1.5 nm; The thickness of the silicon oxide layer is 1.8 nm, and the thickness of the anti-reflection layer is 65 nm; The thickness of the intrinsic amorphous silicon layer is 6 nm, the thickness of the doped microcrystalline silicon layer is 25 nm, and the thickness of the transparent conductive oxide layer is 55 nm.

[0065] Example 6 The solar cell of Example 6 was prepared by referring to the preparation method of Example 1, except that: S N x The width of the mask layer is 40μm, SiN x The thickness of the mask layer is 68nm; The width of the doped polysilicon layer is 40 μm, the thickness of the doped polysilicon layer is 100 nm, and the doping concentration of the doped polysilicon layer is 1.8E20 / cm 3 ; The thickness of the tunnel oxide layer is 2.0 nm; The thickness of the silicon oxide layer is 1.5 nm, and the thickness of the anti-reflection layer is 65 nm; The thickness of the intrinsic amorphous silicon layer is 7 nm, the thickness of the doped microcrystalline silicon layer is 23 nm, and the thickness of the transparent conductive oxide layer is 55 nm.

[0066] In order to more clearly illustrate the technical effects of the embodiments of the present application, the present application also points out the solar cells of Comparative Example 1 and Comparative Example 2.

[0067] Comparative Example 1 Comparative Example 1 is a TOPCon solar cell, comprising: A silicon substrate (N-type silicon substrate), wherein the N-type silicon substrate has a first surface and a second surface that are oppositely disposed; A P-type emitter, an anti-reflection layer, and a first electrode are located on the first surface and are stacked in sequence in a direction away from the silicon substrate; A tunneling oxide layer, an N-type doped polysilicon layer, an anti-reflection layer, and a second electrode are located on the second surface and are stacked in sequence in a direction away from the silicon substrate.

[0068] Comparative Example 2 Comparative Example 2 is a silicon heterojunction solar cell, comprising: A silicon substrate (N-type silicon substrate), wherein the N-type silicon substrate has a first surface and a second surface that are oppositely disposed; An intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a transparent conductive oxide layer, and a first electrode are located on the first surface and are stacked in sequence in a direction away from the silicon substrate; An intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a transparent conductive oxide layer, and a second electrode are located on the second surface and are stacked in sequence in a direction away from the silicon substrate.

[0069] The device performance of the solar cells of Examples 1 to 6 and Comparative Examples 1 to 2 of the present application was tested below to obtain the short-circuit current density Jsc, open-circuit voltage Voc, fill factor FF, and photoelectric conversion efficiency PCE of the corresponding battery devices. The test results are shown in Table 1.

[0070] Table 1

[0071] It can be seen from the data in Table 1 that compared with Comparative Example 1 and Comparative Example 2, the short-circuit current density, fill factor and photoelectric conversion efficiency of the solar cell devices of Examples 1 to 6 of the present application are significantly improved. This is because the passivation materials of the solar cells of Examples 1 to 6 of the present application have lower parasitic absorption, which greatly improves the current density, and the photoelectric conversion efficiency also has certain advantages over conventional HJT.

[0072] In summary, the solar cell in the embodiment of the present application is provided with a tunnel oxide layer, a doped polysilicon layer, a SiN x The mask layer and the first electrode are provided with a silicon oxide layer and an anti-reflection layer stacked in sequence in the second region of the first surface; the solar cell is provided with a doped polysilicon layer only in the first region, and no doped polysilicon layer is provided in the second region, which helps to reduce parasitic absorption loss; the second surface of the solar cell is provided with an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer stacked in sequence to improve the passivation effect, thereby improving the cell conversion efficiency. The solar cell of the embodiment of the present application can effectively improve the bifaciality and photoelectric conversion efficiency of the cell through the specific structure of the first surface and the second surface.

[0073] An embodiment of the present application provides a photovoltaic module (not shown), comprising the solar cell described in any one of the above embodiments.

[0074] The embodiment of the present application can provide a photovoltaic system, including the photovoltaic components in the above embodiment. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid and then connected to the mains network to realize solar power supply.

[0075] It should be noted that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0076] It should be noted that the terms "first", "second", "front", "back", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0078] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0079] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, the silicon substrate having a first surface and a second surface arranged opposite to each other, the first surface having first regions and second regions arranged alternately; The tunnel oxide layer, the doped polysilicon layer and the SiN layer are located in the first region and are sequentially stacked in a direction away from the silicon substrate. x mask layer; A silicon oxide layer and an anti-reflection layer located in the second region and stacked in sequence in a direction away from the silicon substrate; an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer located on the second surface and stacked in sequence in a direction away from the silicon substrate; the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polycrystalline silicon layer; Located in the SiN x a first electrode on the mask layer; A second electrode is located on the transparent conductive oxide layer.

2. The solar cell according to claim 1, characterized in that The width of the doped polysilicon layer and the SiN x The widths of the mask layers are the same, and the width of the doped polysilicon layer is 40-50 μm.

3. The solar cell according to claim 1, characterized in that The doping concentration of the doped polysilicon layer is 1E20-2E20 / cm 3 .

4. The solar cell according to any one of claims 1 to 3, characterized in that: The thickness of the tunnel oxide layer is 1.3-2.0 nm, the thickness of the doped polysilicon layer is 90-120 nm, and the thickness of the SiN x The thickness of the mask layer is 60-70 nm; and / or The thickness of the silicon oxide layer is 1.3-2.0 nm, and the thickness of the anti-reflection layer is 60-70 nm.

5. The solar cell according to any one of claims 1 to 3, characterized in that: The thickness of the intrinsic amorphous silicon layer is 5-7 nm, the thickness of the doped microcrystalline silicon layer is 20-25 nm, and the thickness of the transparent conductive oxide layer is 45-60 nm.

6. A method for preparing a solar cell, characterized in that: include: Providing a silicon substrate, wherein the silicon substrate has a first surface and a second surface arranged opposite to each other, and the first surface has first regions and second regions arranged alternately; In the first region, a tunnel oxide layer, a doped polysilicon layer and a SiN layer are sequentially stacked in a direction away from the silicon substrate. x mask layer; forming a silicon oxide layer and an anti-reflection layer stacked in sequence in a direction away from the silicon substrate in the second region; forming an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer in sequence on the second surface; the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polycrystalline silicon layer; In the SiN x A first electrode is formed on the mask layer, and a second electrode is formed on the transparent conductive oxide layer.

7. The method for preparing a solar cell according to claim 6, characterized in that: The tunnel oxide layer, the doped polysilicon layer and the SiN layer are sequentially stacked in a direction away from the silicon substrate in the first region. x Mask layer, including: An initial tunneling oxide layer, an initial doped polysilicon layer, an initial SiN x mask layer; The first laser etching process is used to sequentially remove the initial SiN x The mask layer, the initial doped polysilicon layer and the initial tunneling oxide layer retain the initial SiN x A mask layer, an initial doped polysilicon layer and an initial tunneling oxide layer are formed to form the SiN x A mask layer, the doped polysilicon layer and the tunneling oxide layer.

8. The method for preparing a solar cell according to claim 7, characterized in that: Forming the initial doped polysilicon layer comprises: forming an initial intrinsic polysilicon layer on the initial tunneling oxide layer; The initial intrinsic polysilicon layer is doped to form the initial doped polysilicon layer.

9. The method for preparing a solar cell according to claim 6, characterized in that: The step of forming a silicon oxide layer and an anti-reflection layer stacked in sequence in a direction away from the silicon substrate in the second region comprises: In the embodiment of the present invention, the tunnel oxide layer, the doped polysilicon layer and the SiN x An initial silicon oxide layer and an initial anti-reflection layer are sequentially formed on the first surface of the mask layer; A second laser etching process is used to remove the initial silicon oxide layer and the initial anti-reflection layer located in the first region, exposing the SiN x The mask layer retains the initial silicon oxide layer and the initial anti-reflection layer located in the second region to form a silicon oxide layer and an anti-reflection layer.

10. The method for preparing a solar cell according to claim 9, characterized in that: In the second laser etching process, the laser wavelength is 520-540nm, the etching time is 0.7-0.8s, and the laser power is 30-40W.

11. A photovoltaic module, characterized in that: The invention comprises the solar cell according to any one of claims 1 to 5.

Images