Time synchronization method for controller and electronic rearview mirror system

Abstract

The invention relates to the technical field of time synchronization for controllers, and discloses a time synchronization method for a controller and an electronic rearview mirror system. According to the application, message communication is directly carried out between a reference chip and a target chip, both parties respectively and accurately record the message receiving and transmitting time of each communication, and time synchronization parameters are calculated based on the message receiving and transmitting time, including the clock skew of the target chip and the clock frequency multiple of the target chip relative to the reference chip; the clock of the target chip is adjusted by using the parameters so as to ensure that the target chip and the reference chip keep high time synchronization, and compared with a traditional time synchronization method depending on a network environment, the clock skew and the clock frequency multiple are determined through message receiving and sending time of mutual message communication, so that the time synchronization accuracy is improved. The influence of a network environment and computing power resources on time synchronization is reduced, and the time synchronization difficulty is reduced, so that high-precision, low-delay and high-stability time synchronization is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of time synchronization for controllers, and in particular to a time synchronization method for controllers and an electronic rearview mirror system. Background Art

[0002] With the rapid advancement of intelligent assisted driving technology, the complexity of the vehicle's electrical and electronic (E / E) architecture has increased significantly. In particular, the electronic rearview mirror system (Camera Monitor System, CMS) as a key component has put forward extremely strict requirements on the response time from camera capture to screen display. Among them, the controller of the electronic rearview mirror system, as the core hub, needs to efficiently process massive data from widely distributed sensors and other controllers. The complexity of the system is not only reflected in the integrated processing of data, but also deeply reflected in the high-precision collaborative work between the microcontroller unit (MCU) and multiple system-level chips (SOC, System on Chip). For example, MCU is responsible for basic functions such as power management and CAN (Controller Area Network) communication, while SOC is responsible for core tasks such as camera control and screen display. Since the SOC chip system involves driver mounting, initialization, and the start of multiple processes one by one, these links consume time and directly affect the overall response speed of the CMS system. At the same time, the operation of the SOC system is highly dependent on a variety of driver modules, including but not limited to drivers for cameras, displays, and multiple communication protocols, as well as drivers for specific peripherals. The coordination and efficiency of these modules directly affect system performance. Therefore, in order to ensure stable operation of the system, the electronic rearview mirror controller requires high-precision time synchronization between multiple SOCs and MCUs.

[0003] However, most of the existing time synchronization methods such as the Network Time Protocol (NTP) and the Precision Time Protocol (PTP) are more suitable for time synchronization in a network environment. At the same time, the method of synchronizing time by line chips through real-time clock chips is inevitable to have error accumulation because each system runs independently and the time accuracy depends on the quality of the real-time chip and the accuracy of the crystal oscillator. As the execution time of multi-system collaborative tasks, errors above the second level are inevitable. For the automotive electronic rearview mirror system with limited resources and extremely high real-time requirements, the above methods are difficult to implement time synchronization and it is difficult to ensure synchronization accuracy. Summary of the invention

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] In view of the above-mentioned shortcomings of the prior art, the present application provides a time synchronization method for a controller and an electronic rearview mirror system to reduce the difficulty of implementing time synchronization, thereby ensuring synchronization accuracy.

[0006] The present application provides a time synchronization method for a controller, comprising: setting a reference chip and a target chip in an original chip of an electronic rearview mirror controller; performing message communication between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication respectively through the reference chip and the target chip; performing calculations based on the message sending and receiving time to obtain time synchronization parameters corresponding to the target chip, wherein the time synchronization parameters include a clock deviation and a clock frequency multiple; and adjusting the chip clock corresponding to the target chip through the time synchronization parameters so that the target chip maintains time synchronization with the reference chip.

[0007] In one embodiment of the present application, a reference chip and a target chip are set in the original chip of the electronic rearview mirror controller, including: the original chip includes a microcontroller unit and a system-level chip; the microcontroller unit is set as the reference chip, and the system-level chip is used as the target chip; if the number of the system-level chips is multiple, then in response to the first chip, the first chip is deleted from the target chip, and the first chip is used as a new reference chip, wherein the first chip is the target chip that completes time synchronization.

[0008] In one embodiment of the present application, the method also includes: if the number of the target chips is multiple, time synchronization is performed on the second chip through the reference chip, wherein the second chip is any target chip; in response to the second chip completing the time synchronization, an end message is sent to the reference chip through the second chip, wherein the end message includes the time synchronization result corresponding to the target chip; in response to the reference chip receiving the end message, time synchronization is performed on the third chip through the reference chip, wherein the third chip is any target chip and is different from the first chip.

[0009] In one embodiment of the present application, message communication is performed between the reference chip and the target chip, so that the message sending and receiving time corresponding to each message communication is recorded respectively by the reference chip and the target chip, including: sending a rearview mirror video stream to the reference chip by the target chip, wherein the rearview mirror video stream includes a plurality of image frames arranged according to frame sequence numbers, and adjacent image frames are separated by a preset time interval; sending a request message to the target chip by the reference chip, and at the same time, recording the frame sequence number received by the reference chip to obtain a first sending sequence number corresponding to the request message; receiving a request message by the target chip, and at the same time, recording the frame sequence number sent by the target chip to obtain a first receiving sequence number corresponding to the request message; sending a rearview mirror video stream to the reference chip by the target chip, wherein the rearview mirror video stream includes a plurality of image frames arranged according to frame sequence numbers, and adjacent image frames are separated by a preset time interval; sending a request message to the target chip by the reference chip, and at the same time, recording the frame sequence number sent by the target chip to obtain a first receiving sequence number corresponding to the request message; The chip sends a feedback message, and at the same time, records the frame sequence number sent by the target chip to obtain a first sending sequence number corresponding to the feedback message; receives the feedback message through the reference chip, and at the same time, records the frame sequence number received by the reference chip to obtain a second receiving sequence number corresponding to the feedback message; sends the first sending sequence number and the second receiving sequence number as a reply message to the target chip through the reference chip, and at the same time, records the frame sequence number received by the reference chip to obtain a third sending sequence number corresponding to the reply message; receives the reply message through the target chip, and at the same time, records the frame sequence number sent by the target chip to obtain a third receiving sequence number corresponding to the reply message; sends the third sending sequence number as a subsequent message to the target chip through the reference chip.

[0010] In one embodiment of the present application, a calculation is performed based on the message receiving and sending time to obtain a time synchronization parameter corresponding to the target chip, including: obtaining a clock frequency multiple corresponding to the target chip by calculating by the target chip according to the preset time interval, the sequence number difference between the first receiving sequence number and the third receiving sequence number, and the sequence number difference between the first sending sequence number and the third sending sequence number; obtaining a communication delay corresponding to the target chip by calculating by the target chip according to the clock frequency multiple, the preset time interval, the sequence number difference between the first sending sequence number and the second receiving sequence number, and the sequence number difference between the first receiving sequence number and the second sending sequence number; obtaining a clock deviation corresponding to the target chip by calculating by the target chip according to the communication delay, the preset time interval, and the sequence number difference between the first sending sequence number and the first receiving sequence number.

[0011] In one embodiment of the present application, message communication is performed between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication respectively through the reference chip and the target chip, including: sending a request message to the target chip through the reference chip, and recording a first sending time corresponding to the request message; the target chip records a first receiving time corresponding to the request message in response to receiving the request message; sending a feedback message to the reference chip through the target chip, and recording a second sending time corresponding to the feedback message; the reference chip records a second receiving time corresponding to the feedback message in response to receiving the feedback message; sending the first sending time and the second receiving time as a reply message to the target chip through the reference chip, and recording a third sending time corresponding to the reply message; the target chip records a third receiving time corresponding to the reply message in response to receiving the reply message; and sending the third sending time as a subsequent message to the target chip through the reference chip.

[0012] In one embodiment of the present application, a calculation is performed based on the message sending and receiving time to obtain a time synchronization parameter corresponding to the target chip, including: obtaining a clock frequency multiple corresponding to the target chip by calculating through the target chip based on the first sending time, the first receiving time, the third sending time, and the third receiving time; obtaining a communication delay corresponding to the target chip by calculating through the target chip based on the clock frequency multiple, the first sending time, the first receiving time, the second sending time and the second receiving time; obtaining a clock deviation corresponding to the target chip by calculating through the target chip based on the communication delay, the first sending time and the first receiving time.

[0013] In one embodiment of the present application, the target chip determines the clock frequency multiple by the following formula: Wherein, R is the clock frequency multiple, T_SOC_re_3 is the third receiving time, T_SOC_re_1 is the first receiving time, T_MCU_se_3 is the third sending time, and T_MCU_se_1 is the first sending time.

[0014] In one embodiment of the present application, the target chip determines the clock deviation by the following formula: Where Delay is the communication delay, T_MCU_re_2 is the second receiving time, T_SOC_se_2 is the second sending time, and Offset is the clock deviation.

[0015] The present application provides an electronic rearview mirror system, comprising: a reference chip, used for performing message communication with a target chip, and recording the message sending and receiving time corresponding to each message communication; the target chip, used for performing message communication with the reference chip, and recording the message sending and receiving time corresponding to each message communication; calculating according to the message sending and receiving time to obtain time synchronization parameters corresponding to the target chip, wherein the time synchronization parameters include clock deviation and clock frequency multiples; adjusting the chip clock corresponding to the target chip by using the time synchronization parameters, so that the target chip maintains time synchronization with the reference chip.

[0016] Beneficial effects of this application:

[0017] By directly communicating messages between the reference chip and the target chip, both parties accurately record the message sending and receiving time of each communication, and calculate the time synchronization parameters based on the message sending and receiving time, including the clock deviation of the target chip and its clock frequency multiple relative to the reference chip. These parameters are used to adjust the clock of the target chip to ensure that it maintains a high degree of time synchronization with the reference chip. In this way, compared with the traditional time synchronization method that relies on the network environment, the clock deviation and clock frequency multiple are determined by the message sending and receiving time of the mutual message communication, which reduces the impact of the network environment and computing resources on time synchronization, reduces the difficulty of time synchronization, and thus achieves high-precision, low-latency, and high-stability time synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of a time synchronization method for a controller in an embodiment of the present application;

[0019] Figure 2 is a structural schematic diagram of an electronic rearview mirror system in an embodiment of the present application;

[0020] Figure 3 is a flow chart of another method for time synchronization of a controller in an embodiment of the present application;

[0021] Figure 4 Schematic diagram of the structure of an electronic rearview mirror controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and sub-samples in the embodiments can be combined with each other without conflict.

[0023] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0025] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0026] Unless otherwise stated, the term "plurality" means two or more.

[0027] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0028] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0029] Combination Figure 1 As shown, the embodiment of the present disclosure provides a time synchronization method for a controller, comprising:

[0030] Step S101, setting a reference chip and a target chip in an original chip of an electronic rearview mirror controller;

[0031] Step S102, performing message communication between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication through the reference chip and the target chip respectively;

[0032] Step S103, calculating according to the message sending and receiving time to obtain the time synchronization parameter corresponding to the target chip;

[0033] Among them, the time synchronization parameters include clock deviation and clock frequency multiple;

[0034] Step S104: adjusting the chip clock corresponding to the target chip by using the time synchronization parameter so that the target chip maintains time synchronization with the reference chip.

[0035] The time synchronization method for the controller provided by the embodiment of the present disclosure is adopted. By directly communicating messages between the reference chip and the target chip, both parties accurately record the message sending and receiving time of each communication, and calculate the time synchronization parameters based on the message sending and receiving time, including the clock deviation of the target chip and its clock frequency multiple relative to the reference chip. These parameters are used to adjust the clock of the target chip to ensure that it maintains a high degree of time synchronization with the reference chip. In this way, compared with the traditional time synchronization method that relies on the network environment, the clock deviation and clock frequency multiple are determined by the message sending and receiving time of the mutual message communication, which reduces the impact of the network environment and computing resources on time synchronization, reduces the difficulty of time synchronization, and thus achieves high-precision, low-latency, and high-stability time synchronization.

[0036] Optionally, setting a reference chip and a target chip in an original chip of the electronic rearview mirror controller includes: the original chip includes a microcontroller unit and a system-level chip; setting the microcontroller unit as the reference chip, and using the system-level chip as the target chip.

[0037] In some embodiments, the microcontroller unit achieves accurate time synchronization with the cockpit domain controller (CDC) through CanTSyc, wherein the microcontroller unit, as the receiving end, obtains the accurate clock information message sent by the CDC in real time through the highly reliable CAN bus interface. These messages not only contain the current high-precision timestamp, but also ensure the integrity and timeliness of data transmission. The microcontroller unit parses the contents of these messages in real time and updates the parsed time information to its system clock, thereby serving as the time reference source of the electronic rearview mirror controller itself.

[0038] In some embodiments, a periodic synchronization calibration mechanism is established between the reference chip and the target chip. In each time synchronization period, each target chip is detected to compensate for possible clock deviation or frequency drift.

[0039] Combination Figure 2 As shown, the present disclosure implements and provides an electronic rearview mirror system, including a micro control unit and multiple system-level chips.

[0040] As the control center of the system and the initiator of time synchronization, the microcontroller unit is responsible for the overall time management and synchronization control.

[0041] The microcontroller unit and the system-level chip are connected through the SPI (Serial Peripheral Interface) bus, forming a one-master-multiple-slave communication architecture. The SPI bus includes four signal lines: SCLK (Serial Clock), MOSI (Master Out Slave In), MISO (Master In Slave Out) and CS / NSS (Chip Select / Not Slave Select), which are used for clock synchronization, data transmission, data reception and slave device selection respectively. SPI communication, with its high-speed and full-duplex characteristics, ensures the fast transmission and accuracy of data between MCU and SOC.

[0042] Optionally, the method further includes: if there are multiple system-level chips, in response to the first chip, deleting the first chip from the target chips and using the first chip as a new reference chip, wherein the first chip is the target chip that completes time synchronization.

[0043] In some embodiments, after any system-on-chip completes time synchronization, the system-on-chip is used as a new reference chip to synchronize with other unsynchronized system-on-chips, thereby improving time synchronization efficiency.

[0044] Optionally, message communication is performed between the reference chip and the target chip to record the message sending and receiving time corresponding to each message communication through the reference chip and the target chip respectively, including: sending a request message to the target chip through the reference chip, and recording a first sending time corresponding to the request message; the target chip records a first receiving time corresponding to the request message in response to receiving the request message; sending a feedback message to the reference chip through the target chip, and recording a second sending time corresponding to the feedback message; the reference chip records a second receiving time corresponding to the feedback message in response to receiving the feedback message; sending the first sending time and the second receiving time as a reply message to the target chip through the reference chip, and recording a third sending time corresponding to the reply message; the target chip records a third receiving time corresponding to the reply message in response to receiving the reply message; and sending the third sending time as a subsequent message to the target chip through the reference chip.

[0045] Optionally, the method also includes: if there are multiple target chips, time synchronization is performed on the second chip through the reference chip, wherein the second chip is any target chip; in response to the second chip completing the time synchronization, an end message is sent to the reference chip through the second chip, wherein the end message includes the time synchronization result corresponding to the target chip; in response to the reference chip receiving the end message, time synchronization is performed on the third chip through the reference chip, wherein the third chip is any target chip and is different from the first chip.

[0046] Combination Figure 3 As shown, the embodiment of the present disclosure provides a time synchronization method for a controller, comprising:

[0047] Step S301, selecting a target chip by using an SPI chip select signal through a reference chip, and establishing a communication link between the reference chip and the target chip;

[0048] Step S302, sending a request message to the target chip through the reference chip;

[0049] The reference chip sends a request message to the target chip through the SPI communication link. The request message does not carry actual data and is used to notify the target chip to perform time synchronization. It is the start mark of time synchronization.

[0050] Step S303, recording a first sending time corresponding to the request message through a reference chip;

[0051] The first sending time is the time reference starting point of the reference chip;

[0052] Step S304, recording a first receiving time corresponding to the request message in response to receiving the request message by the target chip;

[0053] Step S305, sending a feedback message to the reference chip through the target chip;

[0054] The feedback message does not carry actual data, but is used to notify the reference chip that the request message has been received;

[0055] Step S306, recording the second sending time corresponding to the feedback message through the target chip;

[0056] Step S307, recording a second receiving time corresponding to the feedback message in response to receiving the feedback message through the reference chip;

[0057] Step S308, sending a reply message to the target chip through the reference chip after a preset stable time;

[0058] The reply message carries a first sending time and a second receiving time;

[0059] In order to accurately measure the clock frequency relationship between the reference chip and the target chip, the reference chip is preset with a stabilization time, which is used to eliminate the influence of system noise and short-term fluctuations on the measurement results;

[0060] Step S309, recording the third sending time corresponding to the reply message through the reference chip;

[0061] Step S310, recording, by the target chip in response to receiving the reply message, a third receiving time corresponding to the reply message;

[0062] Step S311, sending a subsequent message to the target chip via the reference chip;

[0063] Wherein, the subsequent message carries a third sending time;

[0064] Among them, the target chip has obtained the sending and receiving time data of each of the three communication processes;

[0065] Step S312, the target chip calculates according to the message receiving and sending time to obtain the clock deviation and the clock frequency multiple;

[0066] Step S313, sending an end message to the reference chip via the target chip;

[0067] The end message carries the time synchronization result corresponding to the target chip.

[0068] The time synchronization method for the controller provided by the embodiment of the present disclosure is adopted. By directly communicating messages between the reference chip and the target chip, both parties accurately record the message sending and receiving time of each communication, and calculate the time synchronization parameters based on the message sending and receiving time, including the clock deviation of the target chip and its clock frequency multiple relative to the reference chip. These parameters are used to adjust the clock of the target chip to ensure that it maintains a high degree of time synchronization with the reference chip. In this way, compared with the traditional time synchronization method that relies on the network environment, the clock deviation and clock frequency multiple are determined by the message sending and receiving time of the mutual message communication, which reduces the impact of the network environment and computing resources on time synchronization, reduces the difficulty of time synchronization, and thus achieves high-precision, low-latency, and high-stability time synchronization.

[0069] In some embodiments, after completing time synchronization with any target chip, the reference chip automatically uses the next-order system-level chip as the new target chip according to a preset synchronization sequence or a dynamically monitored system-level chip status, and switches the SPI communication link to the new target chip to continue the time synchronization work.

[0070] In some embodiments, the reference chip records the time synchronization result of each target chip by maintaining a synchronization status table or a flag bit, and records synchronization anomalies or synchronization errors in time synchronization to ensure reliability and stability during the time synchronization process.

[0071] Optionally, calculations are performed based on the message sending and receiving times to obtain time synchronization parameters corresponding to the target chip, including: calculating through the target chip based on a first sending time, a first receiving time, a third sending time, and a third receiving time to obtain a clock frequency multiple corresponding to the target chip; calculating through the target chip based on the clock frequency multiples, the first sending time, the first receiving time, the second sending time, and the second receiving time to obtain a communication delay corresponding to the target chip; calculating through the target chip based on the communication delay, the first sending time, and the first receiving time to obtain a clock deviation corresponding to the target chip.

[0072] In some embodiments, the target chip determines the clock frequency multiple by the following formula:

[0073]

[0074] In formula (1), R is a clock frequency multiple, T_SOC_re_3 is the third receiving time, T_SOC_re_1 is the first receiving time, T_MCU_se_3 is the third sending time, and T_MCU_se_1 is the first sending time.

[0075] In some embodiments, the target chip determines the clock deviation by the following formula:

[0076]

[0077] In formula (2), Delay is the communication delay, T_MCU_re_2 is the second receiving time, T_SOC_se_2 is the second sending time, and Offset is the clock deviation.

[0078] In some embodiments, based on the calculated clock deviation and clock frequency multiple, the target chip adjusts the start time and frequency of its system clock through an internally preset clock management module to match the time state of the MCU to ensure time synchronization between the reference chip and the target chip.

[0079] Optionally, message communication is performed between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication respectively through the reference chip and the target chip, including: sending a rearview mirror video stream to the reference chip through the target chip, wherein the rearview mirror video stream includes a plurality of image frames arranged according to frame sequence numbers, and adjacent image frames are separated by a preset time interval; sending a request message to the target chip through the reference chip, and at the same time, recording the frame sequence number received by the reference chip to obtain a first sending sequence number corresponding to the request message; receiving the request message through the target chip, and at the same time, recording the frame sequence number sent by the target chip to obtain a first receiving sequence number corresponding to the request message; sending a request message to the reference chip through the target chip, and at the same time, recording the frame sequence number sent by the target chip to obtain a first receiving sequence number corresponding to the request message. The chip sends a feedback message and records the frame sequence number sent by the target chip to obtain a first sending sequence number corresponding to the feedback message; the feedback message is received through the reference chip and records the frame sequence number received by the reference chip to obtain a second receiving sequence number corresponding to the feedback message; the first sending sequence number and the second receiving sequence number are sent to the target chip as a reply message through the reference chip and records the frame sequence number received by the reference chip to obtain a third sending sequence number corresponding to the reply message; the reply message is received through the target chip and records the frame sequence number sent by the target chip to obtain a third receiving sequence number corresponding to the reply message; the third sending sequence number is sent to the target chip as a subsequent message through the reference chip.

[0080] Optionally, calculation is performed based on the message receiving and sending time to obtain the time synchronization parameters corresponding to the target chip, including: obtaining the clock frequency multiple corresponding to the target chip by calculating through the target chip according to a preset time interval, the sequence number difference between the first receiving sequence number and the third receiving sequence number, and the sequence number difference between the first sending sequence number and the third sending sequence number; obtaining the communication delay corresponding to the target chip by calculating through the target chip according to the clock frequency multiple, the preset time interval, the sequence number difference between the first sending sequence number and the second receiving sequence number, and the sequence number difference between the first receiving sequence number and the second sending sequence number; obtaining the clock deviation corresponding to the target chip by calculating through the target chip according to the communication delay, the preset time interval, and the sequence number difference between the first sending sequence number and the first receiving sequence number.

[0081] In some embodiments, the sequence number difference between any two sequence numbers is multiplied by a preset time interval to obtain the time difference between message sending and receiving times, and then calculation is performed based on the time difference to obtain the clock deviation and the clock frequency multiple.

[0082] Combination Figure 4 As shown, an embodiment of the present disclosure provides an electronic rearview mirror system, including a reference chip 401 and a target chip 402, wherein the reference chip 401 includes a microprocessing unit, and the target chip 402 includes a system-level chip.

[0083] The reference chip 401 is used to perform message communication with the target chip and record the message sending and receiving time corresponding to each message communication.

[0084] The target chip 402 is used to communicate messages with the reference chip and record the message sending and receiving time corresponding to each message communication; the time synchronization parameters corresponding to the target chip are calculated according to the message sending and receiving time, wherein the time synchronization parameters include clock deviation and clock frequency multiples; the chip clock corresponding to the target chip is adjusted through the time synchronization parameters so that the target chip maintains time synchronization with the reference chip.

[0085] The electronic rearview mirror controller provided by the embodiment of the present disclosure is used to directly communicate messages between the reference chip and the target chip. Both parties accurately record the message sending and receiving time of each communication, and calculate the time synchronization parameters based on the message sending and receiving time, including the clock deviation of the target chip and its clock frequency multiple relative to the reference chip. These parameters are used to adjust the clock of the target chip to ensure that it maintains a high degree of time synchronization with the reference chip. In this way, compared with the traditional time synchronization method that relies on the network environment, the clock deviation and clock frequency multiple are determined by the message sending and receiving time of the mutual message communication, which reduces the impact of the network environment and computing resources on time synchronization, reduces the difficulty of time synchronization, and thus achieves high-precision, low-latency, and high-stability time synchronization.

[0086] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation can be changed. Parts and sub-samples of some embodiments may be included in or replace parts and sub-samples of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of a stated sub-sample, whole, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other sub-samples, wholes, steps, operations, elements, components and / or groups of these. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0087] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. Technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. Technicians can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0088] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some sub-samples can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0089] The flowchart and block diagram in the accompanying drawings show the possible architecture, functions and operations of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A time synchronization method for a controller, characterized in that: include: Setting a reference chip and a target chip in an original chip of an electronic rearview mirror controller; Performing message communication between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication respectively through the reference chip and the target chip; Calculating according to the message receiving and sending time to obtain the time synchronization parameters corresponding to the target chip, wherein the time synchronization parameters include clock deviation and clock frequency multiple; The chip clock corresponding to the target chip is adjusted by the time synchronization parameter so that the target chip and the reference chip maintain time synchronization.

2. The method according to claim 1, characterized in that Setting the reference chip and target chip in the original chip of the electronic rearview mirror controller includes: The original chip includes a micro control unit and a system-level chip; Setting the microcontroller unit as a reference chip and the system-on-chip as a target chip; If there are multiple system-level chips, in response to a first chip, the first chip is deleted from the target chips and used as a new reference chip, wherein the first chip is a target chip that completes time synchronization.

3. The method according to claim 1, characterized in that The method further comprises: If there are multiple target chips, time synchronization is performed on a second chip through the reference chip, wherein the second chip is any target chip; In response to the second chip completing time synchronization, sending an end message to the reference chip through the second chip, wherein the end message includes a time synchronization result corresponding to the target chip; In response to the reference chip receiving the end message, time synchronization is performed on a third chip through the reference chip, wherein the third chip is any target chip and is different from the first chip.

4. The method according to any one of claims 1 to 3, characterized in that: Performing message communication between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication respectively through the reference chip and the target chip, comprises: Sending a rearview mirror video stream to the reference chip through the target chip, wherein the rearview mirror video stream includes a plurality of image frames arranged according to frame sequence numbers, and adjacent image frames are separated by a preset time interval; Sending a request message to the target chip through the reference chip, and recording the frame sequence number received by the reference chip to obtain a first sending sequence number corresponding to the request message; Receiving a request message through the target chip, and recording a frame sequence number sent by the target chip to obtain a first receiving sequence number corresponding to the request message; Sending a feedback message to the reference chip through the target chip, and recording the frame sequence number sent by the target chip to obtain a first sending sequence number corresponding to the feedback message; receiving the feedback message through the reference chip, and recording the frame sequence number received by the reference chip to obtain a second receiving sequence number corresponding to the feedback message; Sending the first sending sequence number and the second receiving sequence number as a reply message to the target chip through the reference chip, and recording the frame sequence number received by the reference chip to obtain a third sending sequence number corresponding to the reply message; receiving the reply message through the target chip, and recording the frame sequence number sent by the target chip to obtain a third receiving sequence number corresponding to the reply message; The third sending sequence number is sent as a subsequent message to the target chip through the reference chip.

5. The method according to claim 4, characterized in that Calculating according to the message receiving and sending time to obtain the time synchronization parameter corresponding to the target chip includes: Obtaining a clock frequency multiple corresponding to the target chip by calculating, by the target chip, according to the preset time interval, the sequence number difference between the first receiving sequence number and the third receiving sequence number, and the sequence number difference between the first sending sequence number and the third sending sequence number; The target chip calculates, according to the clock frequency multiple, the preset time interval, the sequence number difference between the first sending sequence number and the second receiving sequence number, and the sequence number difference between the first receiving sequence number and the second sending sequence number, to obtain a communication delay corresponding to the target chip; The target chip performs calculation according to the communication delay, the preset time interval, and the sequence number difference between the first sending sequence number and the first receiving sequence number to obtain a clock deviation corresponding to the target chip.

6. The method according to any one of claims 1 to 3, characterized in that: Performing message communication between the reference chip and the target chip, so as to record the message sending and receiving time corresponding to each message communication respectively through the reference chip and the target chip, comprises: Sending a request message to the target chip through the reference chip, and recording a first sending time corresponding to the request message; In response to receiving the request message, the target chip records a first receiving time corresponding to the request message; Sending a feedback message to the reference chip through the target chip, and recording a second sending time corresponding to the feedback message; In response to receiving the feedback message, the reference chip records a second receiving time corresponding to the feedback message; Sending the first sending time and the second receiving time as a reply message to the target chip through the reference chip, and recording a third sending time corresponding to the reply message; In response to receiving the reply message, the target chip records a third receiving time corresponding to the reply message; The third sending time is sent as a subsequent message to the target chip through the reference chip.

7. The method according to claim 6, characterized in that Calculating according to the message receiving and sending time to obtain the time synchronization parameter corresponding to the target chip includes: Obtaining a clock frequency multiple corresponding to the target chip by calculating, by the target chip, according to the first sending time, the first receiving time, the third sending time, and the third receiving time; Obtaining a communication delay corresponding to the target chip by calculating, by the target chip, according to the clock frequency multiple, the first sending time, the first receiving time, the second sending time and the second receiving time; The target chip performs calculation according to the communication delay, the first sending time and the first receiving time to obtain a clock deviation corresponding to the target chip.

8. The method according to claim 7, characterized in that The target chip determines the clock frequency multiple by the following formula: Wherein, R is the clock frequency multiple, T_SOC_re_3 is the third receiving time, T_SOC_re_1 is the first receiving time, T_MCU_se_3 is the third sending time, and T_MCU_se_1 is the first sending time.

9. The method according to claim 7, characterized in that: The target chip determines the clock deviation by the following formula: Where Delay is the communication delay, T_MCU_re_2 is the second receiving time, T_SOC_se_2 is the second sending time, and Offset is the clock deviation.

10. An electronic rearview mirror system, characterized in that: include: The reference chip is used to communicate messages with the target chip and record the message sending and receiving time corresponding to each message communication; The target chip is used to perform message communication with the reference chip and record the message sending and receiving time corresponding to each message communication; Calculate according to the message sending and receiving time to obtain the time synchronization parameter corresponding to the target chip, where: The time synchronization parameters include clock deviation and clock frequency multiples; the chip clock corresponding to the target chip is adjusted by the time synchronization parameters so that the target chip maintains time synchronization with the reference chip.

Images