GMII interface receiving system and method supporting multiple rates

Abstract

The invention discloses a GMII interface receiving system and method supporting multiple rates, and the system comprises a data distribution module which enables a first receiving data signal to serve as a high four-bit 100M receiving data signal and to be transmitted to a data FIFO module when an operation result is 1; when the operation result is 0, the first receiving data signal serves as a low four-bit 100M receiving data signal and is transmitted to the data FIFO module; the second selection module is used for selecting a 1000M received data signal as an output data signal when the rate is 1000Mbps, and selecting a 100M received data signal as an output data signal when the rate is 100Mbps; and the fourth selection module is used for selecting the received data effective signal as the output data effective signal when the rate is 1000Mbps, and selecting the read enable signal as the output data effective signal when the rate is 100Mbps. And the data transmission flexibility and compatibility are ensured.

Description

Technical Field

[0001] The present application generally relates to the field of communication technology, and specifically to a GMII interface receiving system and method supporting multiple rates. Background Art

[0002] The GMII (Gigabit Media Independent Interface) interface is a commonly used Ethernet physical layer interface. Copper Ethernet refers to the technology of transmitting Ethernet signals over copper wires (such as twisted pair cables), which is widely used in home, office and enterprise networks. In modern network devices (such as switches, routers and network cards), the GMII interface is a common design choice, allowing devices to connect to copper Ethernet to ensure high-speed data transmission.

[0003] However, if you need to process a custom network protocol, this method is not flexible enough and cannot meet the requirements. When using FPGA (Field Programmable Gate Array) chips for Ethernet protocol development, the GMII interface can often only use a fixed 1000Mbps or 100Mbps rate for reception, which has limitations and poor versatility. Therefore, we propose a GMII interface receiving system and method that supports multiple rates to solve the above problems. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a GMII interface receiving system and method supporting multiple rates that improves data transmission flexibility and compatibility.

[0005] In a first aspect, the present application provides a GMII interface receiving system supporting multiple rates, comprising: A data splicing module, a data distribution module, a data FIFO module, a calculation module, a first selection module, a second selection module, a third selection module and a fourth selection module connected in communication; The data splicing module is used to combine the first received data signal and the second received data signal to obtain a 1000M received data signal; The second selection module is used to select the 1000M received data signal as the output data signal when the rate is 1000Mbps; The fourth selection module is used to select the received data valid signal as the output data valid signal when the rate is 1000Mbps; The operation module is used to perform an AND operation on the byte data valid signal and the received data valid signal to obtain an operation result; the operation result is 1 or 0; The data distribution module is used to obtain the first received data signal and the operation result; when the operation result is 1, the first received data signal is used as the upper four-bit 100M received data signal and is transmitted to the data FIFO module; when the operation result is 0, the first received data signal is used as the lower four-bit 100M received data signal and is transmitted to the data FIFO module; The first selection module is used to obtain the byte data valid signal, and when the byte data valid signal is 0, output 1 and send a write enable signal to the data FIFO module; The third selection module is used to send a read enable signal to the data FIFO module when the data FIFO module is in a data reading state; The data FIFO module is used to form a 100M received data signal based on the write enable signal using the upper four-bit 100M received data signal and the lower four-bit 100M received data signal, and send the 100M received data signal to the second selection module based on the read enable signal; The data splicing module is used to combine the first received data signal and the second received data signal to obtain a 1000M received data signal; The second selection module is further configured to select the 100M received data signal as the output data signal when the rate is 100Mbps; The fourth selection module is further used to select the read enable signal as the output data valid signal when the rate is 100 Mbps.

[0006] According to the technical solution provided in the embodiment of the present application, it also includes: a data frame control unit communicatively connected to the data FIFO module; The data frame control unit is used to cache the length of the received data frame to the length FIFO module when the rate is 100Mbps; and in an idle state, detect whether there is data in the length FIFO module, and if so, jump to the length reading state; The data frame control unit is further used to read the received data frame length stored in the length FIFO module in the length reading state, and jump to the data reading state; at 100Mbps, only the lower 4 bits of each 8-bit data of the received data frame are valid data, and the fourth bits of two consecutive data are spliced ​​into an 8-bit data and stored in the data FIFO, so the number of data actually stored in the FIFO is half of the received data frame length value, and half of the received data frame length is called the valid data number; The data frame control unit is also used to read the data in the data FIFO module in the data reading state and record the number of reads; when the number of reads is the number of valid data, jump to the idle state.

[0007] According to the technical solution provided in the embodiment of the present application, the data frame control unit includes: a length counter, the length counter is used to store the length of the received data frame; The length counter is used to start recording the number of data read in the received data frame when the received data valid signal is 1; when the received data valid signal is 0, stop recording the number of data read in the received data frame after a delay of two clock cycles.

[0008] According to the technical solution provided in the embodiment of the present application, the byte data valid signal is the least significant bit valid signal of the length counter.

[0009] According to the technical solution provided in the embodiment of the present application, the second selection module has: A first input port, used to obtain the 1000M receiving data signal; A second input port is used to obtain the 100M receiving data signal; The first selection port is used to obtain the rate; when the rate is 1000Mbps, the 1000M received data signal is selected as the output data signal; when the rate is 100Mbps, the 100M received data signal is selected as the output data signal; The first output port is used to output the output data signal.

[0010] According to the technical solution provided in the embodiment of the present application, the data allocation module has: A third input port, used to obtain a first received data signal; The second selection port is used to obtain the operation result; when the operation result is 1, the first received data signal is used as the upper four-bit 100M received data signal; when the operation result is 0, the first received data signal is used as the lower four-bit 100M received data signal; The second output port is used to transmit the upper four-bit 100M received data signal to the data FIFO module; The third output port is used to transmit the lower four bits of the 100M received data signal to the data FIFO module.

[0011] According to the technical solution provided in the embodiment of the present application, the first received data signal is the lower four-bit received data signal of the eight-bit received data signal, and the second received data signal is the upper four-bit received data signal of the eight-bit received data signal.

[0012] According to the technical solution provided in the embodiment of the present application, when the rate is 1000Mbps, the data frame length of the 1000M received data signal is equal to the data frame length of the output data signal; when the rate is 100Mbps, the data frame length of the 100M received data signal is twice the data frame length of the output data signal.

[0013] In a second aspect, the present application provides a GMII interface receiving method supporting multiple rates. Based on the above-mentioned GMII interface receiving system supporting multiple rates, the method comprises the following steps: The first received data signal and the second received data signal are combined to obtain a 1000M received data signal; and when the rate is 1000Mbps, the 1000M received data signal is selected as the output data signal, and the received data valid signal is selected as the output data valid signal; Performing AND operation on the byte data valid signal and the received data valid signal to obtain an operation result; the operation result is 1 or 0; Acquire a first received data signal and the operation result; when the operation result is 1, use the first received data signal as the upper four-bit 100M received data signal and transmit it to the data FIFO module; when the operation result is 0, use the first received data signal as the lower four-bit 100M received data signal and transmit it to the data FIFO module; Obtain the byte data valid signal, and when the byte data valid signal is 0, output 1 and send a write enable signal to the data FIFO module; When the data FIFO module is in a data reading state, sending a read enable signal to the data FIFO module; Based on the write enable signal, a 100M receive data signal is formed by using the upper four bits of the 100M receive data signal and the lower four bits of the 100M receive data signal and stored in the data FIFO module, and based on the read enable signal, the 100M receive data signal is sent to the second selection module; When the rate is 100 Mbps, the 100M received data signal is selected as the output data signal, and the read enable signal is selected as the output data valid signal.

[0014] According to the technical solution provided in the embodiment of the present application, the following steps are also included: When the rate is 100Mbps, the received data frame length is cached in the length FIFO module; in the idle state, whether there is data in the length FIFO module is detected, if so, jump to the length reading state; In the length reading state, the received data frame length of the length FIFO module is read, and the module jumps to the data reading state; at 100Mbps, only the lower 4 bits of each 8-bit data in the received data frame are valid data, and the fourth bits of two consecutive data are concatenated into an 8-bit data and stored in the data FIFO. Therefore, the number of data actually stored in the FIFO is half of the received data frame length value, and half of the received data frame length is called the number of valid data; In the data reading state, the data in the data FIFO module is read and the number of reads is recorded; when the number of reads is the number of valid data, the system jumps to the idle state.

[0015] It can be seen from the above technical solution that the present application has at least the following beneficial effects: The present application discloses a GMII interface receiving system supporting multiple rates, comprising: a data splicing module, a data allocation module, a data FIFO module, an operation module, a first selection module, a second selection module, a third selection module and a fourth selection module connected in communication; the operation module performs AND operation processing on a byte data valid signal and a received data valid signal to obtain an operation result; wherein the operation result is 1 or 0; the data allocation module obtains a first received data signal and an operation result; when the operation result is 1, the first received data signal is used as a high four-bit 100M received data signal and is transmitted to the data FIFO module; when the operation result is 0, the first received data signal is used as a low four-bit 100M received data signal and is transmitted to the data FIFO module; the first selection module obtains a byte data valid signal, and when the byte data valid signal is 0, outputs 1 and sends a write enable signal to the data FIFO module; the third selection module is used to When the IFO module is in the data reading state, a read enable signal is sent to the data FIFO module; based on the write enable signal, the data FIFO module uses the upper four-bit 100M received data signal and the lower four-bit 100M received data signal to form a 100M received data signal, and based on the read enable signal, sends the 100M received data signal to the second selection module; the data splicing module combines the first received data signal and the second received data signal to obtain a 1000M received data signal; the second selection module is used to select the 1000M received data signal as the output data signal when the rate is 1000Mbps, and to select the 100M received data signal as the output data signal when the rate is 100Mbps; at the same time, the fourth selection module is used to select the received data valid signal as the output data valid signal when the rate is 1000Mbps, and to select the read enable signal as the output data valid signal when the rate is 100Mbps.

[0016] The data splicing module, data allocation module, data FIFO module, operation module and multiple selection modules designed and used in conjunction with each other enable the GMII interface receiving system to support multiple network rates and ensure data transmission flexibility and compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings.

[0018] Figure 1 A schematic diagram of the structure of a GMII interface receiving system that supports multiple rates.

[0019] Figure 2 This is an example diagram of the data receiving process.

[0020] Figure 3 This is an example diagram of FIFO reading and writing.

[0021] Figure 4 This is an example diagram of a data frame control unit.

[0022] Figure 5 This is an example diagram of a selector.

[0023] Figure 6 This is an example diagram of an allocator.

[0024] Numbers in the figure: 100, data splicing module; 200, data allocation module; 300, data FIFO module; 400, operation module; 500, first selection module; 600, second selection module; 700, third selection module; 800, fourth selection module. DETAILED DESCRIPTION

[0025] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] In order to make the GMII interface receiving system supporting multiple rates provided by the embodiment of the present application clearer and easier to understand, the system is introduced below in conjunction with the accompanying drawings. Figure 1 As shown, the figure is a schematic diagram of the structure of a GMII interface receiving system supporting multiple rates provided in an embodiment of the present application, and the system includes: The data splicing module 100, the data distribution module 200, the data FIFO module 300, the operation module 400, the first selection module 500, the second selection module 600, the third selection module 700 and the fourth selection module 800 are communicatively connected; The data splicing module 100 is used to combine the first received data signal and the second received data signal to obtain a 1000M received data signal; here, the first received data signal is the lower four bits of the eight-bit received data signal, and the second received data signal is the upper four bits of the eight-bit received data signal. Among them, the type of the data splicing module 100 is, for example, a splicer. A splicer is a circuit or module used to merge multiple data sources or signals into a single data stream for transmission, storage or processing. The data input to the input port of the splicer can be parallel data or serial data, and the output port of the splicer is used to output the merged data stream.

[0028] The second selection module 600 is used to select the 1000M received data signal as the output data signal when the rate is 1000Mbps; here, the type of the second selection module 600 is, for example, a selector. The selector is used to select an output signal from multiple input signals. The number of ports of the selector depends on the number of bits of the selector.

[0029] like Figure 5 As shown, the second selection module 600 has: The first input port is used to obtain the 1000M receiving data signal; the first input port is Figure 5 Data input port 1.

[0030] The second input port is used to obtain the 100M receiving data signal; the second input port is Figure 5 Data input port 2.

[0031] The first selection port is used to obtain the rate; when the rate is 1000Mbps, the 1000M received data signal is selected as the output data signal; when the rate is 100Mbps, the 100M received data signal is selected as the output data signal; the first selection port is Figure 5 The control signal port in.

[0032] The first output port is used to output the output data signal. The first output port is Figure 5 The data output port in .

[0033] It should be noted that the port designs and functions of the first selection module 500 , the second selection module 600 , the third selection module 700 and the fourth selection module 800 are the same and will not be described in detail.

[0034] The fourth selection module 800 is used to select the received data valid signal as the output data valid signal when the rate is 1000 Mbps. Here, the type of the fourth selection module 800 is, for example, a selector.

[0035] The operation module 400 is used to perform AND operation on the byte data valid signal and the received data valid signal to obtain an operation result; the operation result is 1 or 0; here, the type of the operation module 400 is, for example, an AND operation module, which is used to perform an AND operation, which is a basic operation method in a computer. Among them, the byte data valid signal is Figure 2 The received data valid signal is rx_cnt[0] Figure 2 gmii_rx_dv in .

[0036] The data distribution module 200 is used to obtain the first received data signal and the operation result; when the operation result is 1, the first received data signal is used as the upper four-bit 100M received data signal and transmitted to the data FIFO module 300; when the operation result is 0, the first received data signal is used as the lower four-bit 100M received data signal and transmitted to the data FIFO module 300; here, the type of the data distribution module 200 is, for example, a distributor. In addition, a distributor is a digital circuit component that distributes one input signal to multiple output signals.

[0037] like Figure 6 As shown, the data distribution module 200 has: The third input port is used to obtain the first received data signal; the third input port is Figure 6 Data input port 4.

[0038] The second selection port is used to obtain the operation result; when the operation result is 1, the first received data signal is used as the upper four-bit 100M received data signal; when the operation result is 0, the first received data signal is used as the lower four-bit 100M received data signal; the second selection port is Figure 6 The control signal input port 3.

[0039] The second output port is used to transmit the high four-bit 100M received data signal to the data FIFO module 300; the second output port is Figure 6 Data input port 1.

[0040] The third output port is used to transmit the lower four bits of the 100M received data signal to the data FIFO module 300. The third output port is Figure 6 Data input port 2.

[0041] The first selection module 500 is used to obtain a byte data valid signal, and when the byte data valid signal is 0, output 1 and send a write enable signal to the data FIFO module 300; here, the type of the first selection module 500 is, for example, a selector.

[0042] The third selection module 700 is used to send a read enable signal to the data FIFO module 300 when the data FIFO module 300 is in a data reading state; here, the type of the third selection module 700 is, for example, a selector.

[0043] The data FIFO module 300 is used to form a 100M receiving data signal based on a write enable signal using the upper four-bit 100M receiving data signal and the lower four-bit 100M receiving data signal, and send the 100M receiving data signal to the second selection module 600 based on the read enable signal; here, the type of the data FIFO module 300 is, for example, a data FIFO module, which is widely used in the management and processing of data streams and is a data structure that stores data according to the principle of First In First Out. It is mainly used to transfer data between producers and consumers to solve the problem of speed mismatch. In FPGA chip design, the data FIFO module can help balance the data flow rate and processing rate, thereby improving the overall performance of the system.

[0044] The second selection module 600 is used to select the 100M received data signal as the output data signal when the rate is 100 Mbps.

[0045] The fourth selection module 800 is used to select the read enable signal as the output data valid signal when the rate is 100 Mbps. Here, the type of the fourth selection module 800 is, for example, a selector.

[0046] Furthermore, the system further comprises: a data frame control unit communicatively connected to the data FIFO module 300; The data frame control unit is used to cache the length of the received data frame to the length FIFO module when the rate is 100Mbps; and in the idle state, it detects whether there is data in the length FIFO module. If so, it jumps to the length reading state; the length FIFO module is used to store the length of a frame of data. The number in the length FIFO module indicates how many frames of data the data FIFO module 300 has received. When reading a length, the data of the data FIFO module 300 is read according to half of the length value, that is, the effective length is half of the length read in the length FIFO module.

[0047] The data frame control unit is also used to read the received data frame length stored in the length FIFO module in the length reading state and jump to the data reading state; at 100Mbps, only the lower 4 bits of each 8-bit data in the received data frame are valid data, and the fourth bits of two consecutive data are spliced ​​into an 8-bit data and stored in the data FIFO. Therefore, the number of data actually stored in the FIFO is half of the received data frame length value, and half of the received data frame length is called the number of valid data. The reading and writing process of the length FIFO module is as follows: Figure 3 shown.

[0048] The data frame control unit is also used to read the data in the data FIFO module 300 in the data reading state and record the number of reads; when the number of reads is the number of valid data, jump to the idle state.

[0049] When the rate is 100 Mbps, the upper four bits of the 100M received data signal and the lower four bits of the 100M received data signal are selected to form a 100M received data signal. Therefore, the data FIFO module 300 usually writes two frames of data and then reads the data once to obtain the number of valid data.

[0050] Here, the type of the data frame control unit is, for example, a receiving state machine, which is an important component for processing data frame reception in network communication, and controls the receiving process of the data frame according to different receiving states.

[0051] Wherein, the data frame control unit includes: a length counter, the length counter is used to store the length of the received data frame; The length counter is used to start recording the number of data read in the received data frame when the received data valid signal is 1; when the received data valid signal is 0, it stops recording the number of data read in the received data frame after a delay of two clock cycles.

[0052] Here, the byte data valid signal is the least significant bit valid signal of the length counter.

[0053] During the data frame reception process, the receiving state machine controls each stage of the data flow, while the length FIFO plays the role of data buffering and storage.

[0054] When the receive state machine detects the start signal of the data frame, it starts pushing the received byte data into the FIFO and gradually fills it. During the reception process, the data bytes are stored one by one in the length FIFO. The receive state machine reads data from the PHY layer and puts it into the FIFO until a complete frame is received (1 frame has 8 bits of data). The length FIFO records the byte length of the currently received data frame. Usually, each time a byte is received, the state machine updates the length field in the FIFO to ensure that the total length of the current frame can be accurately obtained. When the receive state machine detects the end of the frame or the length of the frame has been received, that is, when 8 bits of data are received, it reads the data from the FIFO and further checks it. The state machine will check the data in the FIFO, detect errors, and pass it to the upper layer protocol as needed. After receiving the complete frame, the receive state machine checks the integrity of the data (for example, calculates the CRC checksum). If the data is complete and correct, the receive state machine passes the data frame to the upper layer protocol for processing; if an error is detected, the frame may be discarded or the error information may be reported to the upper layer.

[0055] It should be noted that when the rate is 1000Mbps, the data frame length of the 1000M received data signal is equal to the data frame length of the output data signal; when the rate is 100Mbps, the data frame length of the 100M received data signal is twice the data frame length of the output data signal.

[0056] like Figure 4 As shown in the figure, when the rate is 100M, the data frame control unit includes three states: idle state, length reading state and data reading state. In the idle state, check whether there is data in the length FIFO. If there is data, it indicates that a complete data frame has been cached, and jump to the length reading state. In the length reading state, read the length value in the length FIFO, and the length of the transmitted data frame is half of the value, and jump to the data reading state. In the data reading state, read the 8-bit data in the data FIFO, and start counting the number of reads. If the number of reads reaches the length of the transmitted data frame, jump to the idle state and clear the number of reads counter.

[0057] The reading and writing process of data frame length: like Figure 3As shown, a length counter rx_cnt[15:0] is defined. When the receive data valid signal gmii_rx_dv changes from 0 to 1, the length counter starts to accumulate counts. When gmii_rx_dv changes from 1 to 0, the length counter stops accumulating counts after two clock cycles. The length FIFO write enable wr_en is controlled to be valid, and the value of the length counter is written into the length FIFO. When the state machine is in the length reading state, the length FIFO read enable rd_en is valid, and the length value in the length FIFO is read.

[0058] Data frame receiving and conversion process: like Figure 2 As shown, the lower four bits gmii_rxd[3:0] and the upper four bits gmii_rxd[7:4] of the received data signal are combined into gmii_rxd_1000M[7:0] through the splicer and enter the selector 2. Here, the selector 2 refers to the second selection module 600.

[0059] The lower four bits of the received data signal gmii_rxd[3:0] enter the distributor. When the lowest bit rx_cnt[0] of the length counter is ANDed with the valid received data signal gmii_rx_dv and the result is 1, the distributor uses gmii_rxd[3:0] as the upper four bits gmii_rxd_100M[7:4] of the 100M received data signal. When the result is 0, the distributor uses gmii_rxd[3:0] as the lower four bits gmii_rxd_100M[3:0] of the 100M received data signal. When rx_cnt[0] is 0, the selector 1 outputs 1 to make the data FIFO write enable signal wr_en valid, and writes gmii_rxd_100M[7:0] into the data FIFO. Here, the selector 1 refers to the first selection module 500. In the data reading state, the selector 3 outputs a read enable signal rd_en to read gmii_rxd_100M[7:0] in the data FIFO to the selector 2. Here, the selector 3 is the third selection module 700.

[0060] When the rate is 1000Mbps, selector 2 selects gmii_rxd_1000M[7:0] as the output data gmii_rxd_out[7:0], and selector 4 selects gmii_rx_dv as the output data valid signal gmii_rx_dv_out. When the rate is 100Mbps, selector 2 selects gmii_rxd_100M[7:0] as the output data gmii_rxd_out[7:0], and selector 4 selects rd_en output by selector 3 as the output data valid signal gmii_rx_dv_out. Here, selector 4 is the fourth selection module 800.

[0061] The present application also provides a GMII interface receiving method supporting multiple rates. Based on the above-mentioned GMII interface receiving system supporting multiple rates, the method comprises the following steps: The first received data signal and the second received data signal are combined to obtain a 1000M received data signal; and when the rate is 1000Mbps, the 1000M received data signal is selected as the output data signal, and the received data valid signal is selected as the output data valid signal; Perform AND operation on the byte data valid signal and the received data valid signal to obtain an operation result; the operation result is 1 or 0; Obtain the first received data signal and the operation result; when the operation result is 1, use the first received data signal as the upper four-bit 100M received data signal and transmit it to the data FIFO module 300; when the operation result is 0, use the first received data signal as the lower four-bit 100M received data signal and transmit it to the data FIFO module 300; Obtain the byte data valid signal, and when the byte data valid signal is 0, output 1 and send a write enable signal to the data FIFO module 300; When the data FIFO module 300 is in a data reading state, a read enable signal is sent to the data FIFO module 300; Based on the write enable signal, the upper four bits of the 100M received data signal and the lower four bits of the 100M received data signal are used to form a 100M received data signal and stored in the data FIFO module 300, and based on the read enable signal, the 100M received data signal is sent to the second selection module 600; When the rate is 100Mbps, the 100M receive data signal is selected as the output data signal, and the read enable signal is selected as the output data valid signal.

[0062] Furthermore, the method further comprises the following steps: When the rate is 100Mbps, the received data frame length is cached in the length FIFO module; in the idle state, it is detected whether there is data in the length FIFO module, and if so, it jumps to the length reading state; In the length reading state, read the received data frame length of the length FIFO module and jump to the data reading state; at 100Mbps, only the lower 4 bits of each 8-bit data in the received data frame are valid data, and the fourth bits of two consecutive data are spliced ​​into an 8-bit data and stored in the data FIFO. Therefore, the number of data actually stored in the FIFO is half of the received data frame length value, and half of the received data frame length is called the number of valid data; In the data reading state, the data in the data FIFO module 300 is read and the number of reads is recorded; when the number of reads is the number of valid data, the state is jumped to the idle state.

[0063] The data splicing module 100, the data distribution module 200, the data FIFO module 300, the operation module 400 and a plurality of selection modules designed and used in conjunction with each other enable the GMII interface receiving system to support a variety of network rates and ensure the flexibility and compatibility of data transmission.

[0064] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A GMII interface receiving system supporting multiple rates, characterized in that: include: A data splicing module (100), a data allocation module (200), a data FIFO module (300), a calculation module (400), a first selection module (500), a second selection module (600), a third selection module (700) and a fourth selection module (800) that are communicatively connected; The data splicing module (100) is used to combine the first received data signal and the second received data signal to obtain a 1000M received data signal; The second selection module (600) is used to select the 1000M received data signal as the output data signal when the rate is 1000Mbps; The fourth selection module (800) is used to select the received data valid signal as the output data valid signal when the rate is 1000 Mbps; The operation module (400) is used to perform an AND operation on the byte data valid signal and the received data valid signal to obtain an operation result; the operation result is 1 or 0; The data distribution module (200) is used to obtain a first received data signal and the operation result; when the operation result is 1, the first received data signal is used as a high-order 100M received data signal and is transmitted to the data FIFO module (300); when the operation result is 0, the first received data signal is used as a low-order 100M received data signal and is transmitted to the data FIFO module (300); The first selection module (500) is used to obtain the byte data valid signal, and when the byte data valid signal is 0, output 1 and send a write enable signal to the data FIFO module (300); The third selection module (700) is used to send a read enable signal to the data FIFO module (300) when the data FIFO module (300) is in a data reading state; The data FIFO module (300) is used to form a 100M received data signal based on the write enable signal using the upper four-bit 100M received data signal and the lower four-bit 100M received data signal, and send the 100M received data signal to the second selection module (600) based on the read enable signal; The second selection module (600) is further configured to select the 100M received data signal as the output data signal when the rate is 100 Mbps; The fourth selection module (800) is further used to select the read enable signal as the output data valid signal when the rate is 100 Mbps.

2. A GMII interface receiving system supporting multiple rates according to claim 1, characterized in that: Also includes: A data frame control unit communicatively connected to the data FIFO module (300); The data frame control unit is used to cache the received data frame length into the length FIFO module when the rate is 100 Mbps; And in the idle state, check whether there is data in the length FIFO module, if so, jump to the length reading state; The data frame control unit is further used to read the received data frame length stored in the length FIFO module in the length reading state, and jump to the data reading state; at 100Mbps, only the lower 4 bits of each 8-bit data of the received data frame are valid data, and the fourth bits of two consecutive data are spliced ​​into an 8-bit data and stored in the data FIFO, so the number of data actually stored in the FIFO is half of the received data frame length value, and half of the received data frame length is called the valid data number; The data frame control unit is further used to read the data in the data FIFO module (300) in the data reading state and record the number of reads; when the number of reads is the number of valid data, jump to the idle state.

3. A GMII interface receiving system supporting multiple rates according to claim 2, characterized in that: The data frame control unit comprises: a length counter, the length counter being used to store the length of the received data frame; The length counter is used to start recording the number of data read in the received data frame when the received data valid signal is 1; when the received data valid signal is 0, stop recording the number of data read in the received data frame after a delay of two clock cycles.

4. A GMII interface receiving system supporting multiple rates according to claim 3, characterized in that: The byte data valid signal is the least significant bit valid signal of the length counter.

5. A GMII interface receiving system supporting multiple rates according to claim 1, characterized in that: The second selection module (600) has: A first input port, used to obtain the 1000M receiving data signal; A second input port is used to obtain the 100M receiving data signal; The first selection port is used to obtain the rate; when the rate is 1000Mbps, the 1000M received data signal is selected as the output data signal; when the rate is 100Mbps, the 100M received data signal is selected as the output data signal; The first output port is used to output the output data signal.

6. A GMII interface receiving system supporting multiple rates according to claim 1, characterized in that: The data distribution module (200) has: A third input port, used to obtain a first received data signal; The second selection port is used to obtain the operation result; when the operation result is 1, the first received data signal is used as the upper four-bit 100M received data signal; when the operation result is 0, the first received data signal is used as the lower four-bit 100M received data signal; A second output port, used for transmitting the upper four-bit 100M received data signal to the data FIFO module (300); The third output port is used to transmit the lower four bits of the 100M received data signal to the data FIFO module (300).

7. A GMII interface receiving system supporting multiple rates according to claim 1, characterized in that: The first received data signal is a lower four-bit received data signal of an eight-bit received data signal, and the second received data signal is a higher four-bit received data signal of an eight-bit received data signal.

8. A GMII interface receiving system supporting multiple rates according to claim 1, characterized in that: When the rate is 1000Mbps, the data frame length of the 1000M received data signal is equal to the data frame length of the output data signal; when the rate is 100Mbps, the data frame length of the 100M received data signal is twice the data frame length of the output data signal.

9. A GMII interface receiving method supporting multiple rates, based on a GMII interface receiving system supporting multiple rates as claimed in any one of claims 1 to 8, characterized in that: The method comprises the following steps: The first received data signal and the second received data signal are combined to obtain a 1000M received data signal; and when the rate is 1000Mbps, the 1000M received data signal is selected as the output data signal, and the received data valid signal is selected as the output data valid signal; Performing AND operation on the byte data valid signal and the received data valid signal to obtain an operation result; the operation result is 1 or 0; Acquire a first received data signal and the operation result; when the operation result is 1, use the first received data signal as the upper four-bit 100M received data signal and transmit it to the data FIFO module (300); when the operation result is 0, use the first received data signal as the lower four-bit 100M received data signal and transmit it to the data FIFO module (300); Acquiring the byte data valid signal, and when the byte data valid signal is 0, outputting 1 and sending a write enable signal to the data FIFO module (300); When the data FIFO module (300) is in a data reading state, sending a read enable signal to the data FIFO module (300); Based on the write enable signal, a 100M received data signal is formed by using the upper four bits of the 100M received data signal and the lower four bits of the 100M received data signal and stored in the data FIFO module (300), and based on the read enable signal, the 100M received data signal is sent to the second selection module (600); When the rate is 100 Mbps, the 100M received data signal is selected as the output data signal, and the read enable signal is selected as the output data valid signal.

10. A GMII interface receiving method supporting multiple rates according to claim 9, characterized in that: The following steps are also included: When the rate is 100Mbps, the received data frame length is cached in the length FIFO module; in the idle state, whether there is data in the length FIFO module is detected, if so, jump to the length reading state; In the length reading state, the received data frame length of the length FIFO module is read, and the module jumps to the data reading state; at 100Mbps, only the lower 4 bits of each 8-bit data in the received data frame are valid data, and the fourth bits of two consecutive data are concatenated into an 8-bit data and stored in the data FIFO. Therefore, the number of data actually stored in the FIFO is half of the received data frame length value, and half of the received data frame length is called the number of valid data; In the data reading state, the data in the data FIFO module (300) is read and the number of reads is recorded; when the number of reads is the number of valid data, the system jumps to the idle state.

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