GaN-based p-channel field effect transistor and preparation method thereof

Abstract

The invention provides an enhanced GaN-based p-channel field effect transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The GaN-based p-channel field effect transistor comprises a substrate, a buffer layer, a first UID-GaN layer, a barrier layer, a first p-type semiconductor layer, a second UID-GaN layer, an n-GaN layer, an n-GaN layer, a second p-type semiconductor layer and an Al < x > GaN layer from bottom to top, a source electrode on the second p-type semiconductor layer; the drain electrode is positioned on the Al < x > GaN layer; the collector electrode is positioned on one end, which is not covered by the n-GaN layer, of the n-GaN layer; the gate dielectric layer is positioned between the source electrode and the AlxGaN layer and on the second p-type semiconductor layer; and the gate electrode is positioned on the gate dielectric layer. According to the GaN-based p-channel field effect transistor, the npn-type triode is prepared below the drain electrode of a traditional GaN-based p-channel field effect transistor, electrons are converted into main carriers, and the output current density is improved by two orders of magnitude.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a GaN-based p-channel field effect transistor and a preparation method thereof. Background Art

[0002] Compared with traditional silicon materials, gallium nitride (GaN) has the advantages of large bandgap, strong breakdown electric field, low on-resistance, high electron mobility, high conversion efficiency, and high thermal conductivity. As a II IV compound, the material itself has a special polarization effect. There are two charges of different polarities on the surface of the semiconductor. When it contacts Al GaN to form a heterojunction, due to the discontinuity of the energy band, a potential well will be generated at the heterojunction interface, which will confine the electrons or holes attracted by the polarized charge in a two-dimensional space, forming a high-density two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG). Since this structure does not require doping, the effects of ion scattering on the carriers are greatly reduced, so it has a higher mobility. The device has the advantages of high switching frequency, fast operating speed, and high power density. Therefore, gallium nitride materials are more suitable for applications in high voltage, high frequency, high temperature, and high power fields, and are widely used in radio frequency communications, switching power supplies, automotive electronics, radars, and other fields.

[0003] GaN monolithic integration is gradually becoming the main development trend of power module design based on GaN devices. At present, in order to effectively reduce parasitic loop inductance and improve system performance, integrated circuits based on GaN power devices have attracted the attention of industry insiders. Existing GaN monolithic integrated power chips are completely dependent on N-type GaN enhancement mode (E-mode) and depletion mode (D-mode) devices. In order to give full play to the huge potential of GaN in on-chip power switches and promote the development of complementary logic circuits in power ICs, it is necessary to prepare GaN-based p-channel field effect transistors. However, due to the large effective mass of holes in GaN, the hole mobility is generally only 7-50cm 2 / Vs; and the p-type GaN layer is often realized by doping Mg, where the activation rate of Mg at room temperature is only 1%-3%, making it difficult to achieve a high hole concentration. These problems result in the low output current of GaN-based p-channel field-effect transistors, which is seriously mismatched with the current transport capacity of n-type devices, making it difficult to achieve high-performance GaN-based CMOS logic circuits.

[0004] Therefore, it is necessary to provide an enhanced GaN-based p-channel field effect transistor and a method for preparing the same. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention proposes an enhanced GaN-based p-channel field effect transistor and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0006] The enhanced GaN-based p-channel field effect transistor and the method for manufacturing the same according to the embodiments of the present invention have at least one of the following advantages:

[0007] 1. The present invention provides an enhanced GaN-based p-channel field effect transistor and a preparation method thereof, which converts electrons into main carriers by epitaxially growing an npn-type triode stack under the drain electrode of a conventional GaN-based p-channel field effect transistor, thereby improving the conduction capacity of the p-channel field effect transistor.

[0008] 2. By changing the drain-source voltage V DS , so that the transistor is in the amplification area, amplifying the current of the GaN-based p-channel field effect transistor, the current gain can be as high as 100 times, greatly improving the output current density of the GaN-based p-channel field effect transistor; at the same time, by adjusting the depth of the first groove, the threshold voltage can be controlled. After exceeding a certain depth, the holes under the first groove are depleted in the off state, and the device realizes enhancement mode.

[0009] 3. By changing the second groove depth, that is, Al x The depth of the GaN layer sinking reduces the thickness of the transistor base region and the probability of electrons and holes recombining in the base region. More electrons are collected at the collector, thereby increasing the amplification factor of the transistor, compensating for the output current density loss caused by etching the first groove, and improving the output characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of the preferred embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A schematic structural diagram of an enhancement-mode GaN-based p-channel field effect transistor provided according to an embodiment of the present invention;

[0012] Figure 2 A comparison diagram of transfer characteristic curves between the GaN-based p-channel field effect transistor with Al GaN / GaN HBT according to Embodiment 1 of the present invention and a conventional GaN-based p-channel field effect transistor without Al GaN / GaN HBT (semi-logarithmic coordinates);

[0013] Figure 3 is a relationship diagram between the threshold voltage and output current of the GaN-based p-channel field effect transistor with high output current density and t1;

[0014] Figure 4 For V GS =-10V, it is the output curve diagram of the enhanced GaN-based p-channel field effect transistor of comparative example 2, embodiment 4 and embodiment 5.

[0015] Description of reference numerals:

[0016] 01 substrate;

[0017] 02 buffer layer;

[0018] 03 first U ID-GaN layer;

[0019] 04 barrier layer;

[0020] 05 first p-type semiconductor layer;

[0021] 06 second U ID-GaN layer;

[0022] 07n-GaN layer;

[0023] 08n - -GaN layer;

[0024] 09 second p-type semiconductor layer;

[0025] 10A x GaN layer;

[0026] 11: gate dielectric layer;

[0027] 12 gate electrode;

[0028] 13 source electrode;

[0029] 14 drain electrode;

[0030] 15 collector;

[0031] 21 first groove;

[0032] 22 second groove. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is further specifically described below by examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation of the present invention.

[0034] In the present invention, the term "etching" refers to a process of selectively removing useless materials from the surface of a substrate by chemical or physical methods.

[0035] In the present invention, the term "inductively coupled plasma etching" means that the reaction gas generates glow discharge by inductive coupling, and the generated plasma with strong chemical activity moves to the sample surface under the acceleration of the electric field, which not only chemically reacts to generate volatile gases on the sample surface, but also has a certain physical etching effect. Because the plasma source is separated from the RF acceleration source, the plasma density can be higher and the acceleration ability can be enhanced to obtain a higher etching rate and better anisotropic etching.

[0036] In the present invention, the term "magnetron sputtering technology" refers to a method of bombarding a target material with high-energy particles to sputter out a large number of target atoms, which are deposited on the surface of a substrate to form a thin film.

[0037] In the present invention, the term "patterning" refers to the generation of a nanoscale regular surface structure in at least one dimensional direction, and patterning can be achieved using a variety of techniques, such as photolithography, micromechanical methods based on scanning probes, microcontact printing, etc.

[0038] The technical solution of the present invention is further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0039] In order to improve the output current density of GaN-based p-channel field effect transistors and solve the problem of current mismatch with n-channel field effect transistors, an embodiment of the present invention provides an enhancement mode GaN-based p-channel field effect transistor and a preparation method thereof.

[0040] See also Figure 1 The enhanced GaN-based p-channel field effect transistor includes, from bottom to top, a substrate 01, an epitaxial structure layer arranged on the substrate 01, and a source electrode, a drain electrode, a gate electrode, a collector, a gate dielectric layer, etc. that cooperate with the epitaxial structure layer. In some embodiments, the enhanced GaN-based p-channel field effect transistor also includes a first groove 21 and a second groove 22.

[0041] The epitaxial structure layer comprises a buffer layer 02, a first U ID-GaN layer 03, a barrier layer 04, a first p-type semiconductor layer 05, a second U ID-GaN layer 06, an n-GaN layer 07, and an n-type semiconductor layer 08. - -GaN layer 08, second p-type semiconductor layer 09; the second p-type semiconductor layer 09 and n - The -GaN layer 08 is partially etched until a portion of the surface of the n-GaN layer 07 is exposed.

[0042] A first groove 21 and a second groove 22 are etched on the second p-type semiconductor layer 09; the bottom and sidewalls of the first groove 21 are covered with a gate dielectric layer 11, and the gate dielectric layer 11 also extends to both sides along the upper surface of the second p-type semiconductor layer 09; Al is filled in the second groove 22 x GaN layer 10.

[0043] The gate electrode 12 is disposed above the gate dielectric layer 11 of the first groove 21; the source electrode 13 is disposed on one side of the upper surface of the second p-type semiconductor layer 09; the drain electrode 14 is disposed on the Al x GaN layer 10; collector electrode 15 is disposed above n-GaN layer 07 and on the same side as drain electrode 14; the n-GaN layer 07, n - -GaN layer 08, second p-type semiconductor layer 09, Al x The GaN layer 10 as a whole forms a triode, and the n-GaN layer 07 and the n - -GaN layer 08 constitutes the collector region of the transistor.

[0044] In order to facilitate understanding of an enhanced GaN-based p-channel field effect transistor proposed in this embodiment, the detailed preparation method steps are given below:

[0045] The first step is to grow the epitaxial structure.

[0046] 1.1 A GaN buffer layer 02, a first U ID-GaN layer 03, a barrier layer 04, a first p-type semiconductor layer 05, a second U ID-GaN layer 06, an n-GaN layer 07, and an n-type semiconductor layer 08 are sequentially grown on a substrate 01 by using a metal organic chemical vapor deposition method (MOCVD). - -GaN layer 08, second p-type semiconductor layer 09;

[0047] 1.2 Treat the epitaxially grown samples in heated KOH for about 20 minutes, rinse with deionized water and blow dry with nitrogen to remove contaminants or residues that may have been generated during the growth process;

[0048] Step 2: etching to form the first groove 21 and the second groove 22.

[0049] 2.1 For the sample after the first step, the inductively coupled plasma (ICP) reactive ion etching (RIE) technology is used, with BC13 gas as the etching gas and SiO2 as the etching mask, to etch the second p-type semiconductor layer 09 and n - The p-GaN layer 08 is partially etched until part of the surface of the n-GaN layer 07 is exposed; after removing SiO2, thermal annealing is performed in a nitrogen atmosphere at 750°C for 30 minutes to activate the Mg doping in the p-GaN layer;

[0050] 2.2 Using low-damage BC l3 / C l2-based inductively coupled plasma (ICP) etching technology, with photoresist as an etching mask, the middle of the second p-type semiconductor layer 09 is etched to form a first groove 21. The etching time is pre-calibrated, and the second p-type semiconductor layer 09 with a thickness of about 5-15 nm is retained;

[0051] 2.3 Similarly, using low-damage BC l3 / C l2-based inductively coupled plasma (ICP) etching technology, with photoresist as an etching mask, one side of the second p-type semiconductor layer 09 is etched to form a second groove 22. The etching time is pre-calibrated, and the second p-type semiconductor layer 09 with a thickness of about 20-65nm is retained;

[0052] 2.4 After the etching of the first groove 21 and the second groove 22 is completed, the sample is immersed in a heated tetramethylammonium hydroxide solution (TMAH) for about 15 minutes. This TMAH dipping removes the photoresist, repairs the damage caused by etching, and reduces the surface roughness induced by etching.

[0053] Step 3: Epitaxial Growth of Al x GaN layer 10.

[0054] 3.1 Growth of Al by Metal Organic Chemical Vapor Deposition (MOCVD) x The GaN layer 10 is filled in the second groove 22 .

[0055] Step 4: Make ohmic contacts between the source electrode 13 , the drain electrode 14 and the collector electrode 15 .

[0056] 4.1 Place the sample on a hot plate and bake it. After coating and spinning the photoresist, place it in a photolithography machine to expose the photoresist in the source electrode 13 area. Immerse the sample in a buffered oxide etchant (BOE) for about 3 minutes, then wash off the photoresist and developer adhering to the device surface with deionized water, and dry it at 90°C for 4 minutes to solidify the photoresist.

[0057] 4.2 Use electron beam evaporation technology to evaporate Ni / Au (20 / 20nm) in the source electrode 13 area to remove the ohmic metal, photoresist and stripping glue outside the source electrode area, wash with deionized water and blow dry with nitrogen; finally anneal in an oxygen environment at 550℃ for 5min to form a good p-type ohmic contact.

[0058] 4.3 Photolithography on Al xThe n-type ohmic contact regions of the drain electrode 14 and the collector 15 are defined above the GaN layer 10 and the n-GaN layer 07. The sample is immersed in a buffered oxide etchant (BOE) for about 3 minutes, and a Ni / Au (20 / 20nm) metal stack is evaporated on the drain electrode 14 and the collector 15 region using electron beam evaporation technology; then annealed in a nitrogen atmosphere at 450°C for 5 minutes to form a good n-type ohmic contact.

[0059] Step 5: Deposit the gate dielectric layer 11. Deposit 20 nm of Al2O3 as the gate dielectric layer 11 using atomic layer deposition (ALD) technology.

[0060] Step 6: Prepare the gate electrode 12. Use electron beam evaporation technology to evaporate Ti / Au (20 / 100 nm) in the gate electrode 12 area. At this point, the device is completed.

[0061] Example 1

[0062] like Figure 1 As shown, the enhanced GaN-based p-channel field effect transistor has a structure that includes, from bottom to top:

[0063] Silicon substrate 01;

[0064] Buffer layer 02, made of GaN, not intentionally doped, with a thickness of 4.2 μm;

[0065] The first UID-GaN layer 03 is not intentionally doped and has a thickness of 420nm;

[0066] Barrier layer 04, made of AlGaN, with an Al component of 0.2 and a thickness of 15 nm;

[0067] The first p-type semiconductor layer 05 is made of GaN and has a Mg doping concentration of 2×10 19 cm -3 , thickness is 70nm;

[0068] The second UID-GaN layer 06 is not intentionally doped and has a thickness of 100 nm;

[0069] n-GaN layer 07, Si doping concentration is 5×10 18 cm -3 , thickness is 120nm;

[0070] n - -GaN layer 08, Si doping concentration is 5×10 17 cm -3 , thickness is 100nm;

[0071] The second p-type semiconductor layer 09 is made of GaN and has a Mg doping concentration of 2×10 19 cm-3 , thickness is 70nm;

[0072] Al x The GaN layer is 10, the Al content is 0.2, and the Si doping concentration is 5×10 18 cm -3 , thickness is 80nm;

[0073] The gate dielectric layer 11 is made of Al2O3 and has a thickness of 20 nm.

[0074] The depth of the first groove 21 is t1 , and in this embodiment, t1 is 64 nm.

[0075] Figure 2 V DS = -10V, the transfer curves (semi-logarithmic coordinates) of Example 1 and the conventional GaN-based p-channel field effect transistor without Al GaN / GaN HBT are compared. Figure 2 It can be seen that the output current density of the enhanced GaN-based p-channel field effect transistor of this embodiment is more than two orders of magnitude higher than that of the conventional GaN-based p-channel field effect transistor without Al GaN / GaN HBT. This is because the npn-type triode integrated under the drain electrode has good current amplification capability, which converts electrons into the main carriers, thereby improving the conduction capability of the device and enhancing the output characteristics. At the same time, the off-state leakage current density is less than 10 -8 mA / mm, conduction ratio up to 10 11 , the device has good gate electrode control capability.

[0076] The structure of the conventional GaN-based p-channel field effect transistor without Al GaN / GaN HBT is as follows:

[0077] Silicon substrate;

[0078] GaN buffer layer, not intentionally doped, 4.2 μm thick;

[0079] The first UID-GaN layer is not intentionally doped and has a thickness of 420nm;

[0080] The barrier layer is made of AlGaN, with an Al component of 0.2 and a thickness of 15 nm;

[0081] p-GaN layer, where the Mg doping concentration is 2×10 19 cm -3 , thickness is 70nm;

[0082] A gate groove structure is etched on the p-GaN layer, and the gate groove structure faces the p-GaN channel layer. The bottom and side walls of the gate groove structure are covered with a gate dielectric layer Al2O3, and the gate dielectric layer also extends to both sides along the upper surface of the p-GaN layer, with a thickness of 20nm. The remaining p-GaN layer thickness under the gate electrode is 6nm; the source electrode and the drain electrode are respectively arranged on both sides of the upper surface of the p-GaN layer, and the gate electrode is arranged above the groove gate dielectric layer.

[0083] Example 2

[0084] The t1 in Example 1 is modified to 62 nm, and the other parameter settings are the same as those in Example 1, so they are not described again.

[0085] Example 3

[0086] The t1 in Example 1 is modified to 60 nm, and the other parameter settings are the same as those in Example 1, so they will not be repeated.

[0087] Comparative Example 1

[0088] The t1 in Example 1 is modified to 66 nm, and the other parameter settings are the same as those in Example 1, so they are not described again.

[0089] Figure 3 is a graph showing the relationship between the threshold voltage and output current density of the GaN-based p-channel field effect transistors of Comparative Example 1 and Examples 1, 2, and 3 and t1. Figure 3 It can be clearly seen that the threshold voltage can be controlled by adjusting the thickness of t1, and the threshold voltage of the device decreases as the depth of the first groove increases. When t1 = 64nm, the threshold voltage is -0.45V, and the device achieves enhancement mode. This is because after etching the second p-type semiconductor, the thickness of the second p-type semiconductor decreases, and the hole concentration under the gate decreases, so that the device can be transformed from depletion mode to enhancement mode. At the same time, it is found that the output current density is inversely proportional to t1. As t1 increases, the output current density decreases. When t1 = 64nm, the device achieves a good balance between threshold voltage and output current density.

[0090] Example 4

[0091] In Example 1, A1 x The GaN layer sinks toward the second p-type semiconductor layer, and the thickness of the sinking is the depth of the second groove, which is denoted as t2. In this embodiment, t2 is 10 nm. The other parameter settings are the same as those in Embodiment 1, so they will not be described again.

[0092] Example 5

[0093] The t2 in Example 4 is modified to 5 nm, and the other parameter settings are the same as those in Example 4, so they will not be repeated here.

[0094] Comparative Example 2

[0095] The t2 in Example 4 is modified to 0 nm, and the other parameter settings are the same as those in Example 4, so they will not be repeated.

[0096] Figure 4 Comparative Example 2 and Example 4, Example 5 at V GS = -10V when the output characteristic curve of the enhanced GaN-based p-channel field effect transistor is Figure 4 It can be seen that with the increase of t2 thickness, the output current density of the device increases. This is because with the deepening of t2, the thickness of the second p-type semiconductor decreases, that is, the thickness of the transistor base region decreases, which reduces the probability of electron-hole recombination in the base region. More electrons pass through the base region and reach the collector. The current amplification capacity of the transistor is significantly improved, which can well compensate for the decrease in output current density caused by etching the second p-type semiconductor and improve the output characteristics.

[0097] The enhanced GaN-based p-channel field effect transistor and the method for manufacturing the same according to the embodiments of the present invention have at least one of the following advantages:

[0098] 1. The present invention provides an enhanced GaN-based p-channel field effect transistor and a method for preparing the same, which converts electrons into main carriers by epitaxially growing an npn-type triode stack under the drain electrode of a conventional GaN-based p-channel field effect transistor, thereby improving the conduction capacity of the p-channel device.

[0099] 2. By changing the drain-source voltage V DS , so that the transistor is in the amplification area, amplifying the current of the GaN-based p-channel field effect transistor, the current gain can be as high as 100 times, greatly improving the output current density of the GaN-based p-channel field effect transistor; at the same time, by adjusting the depth of the first groove, the threshold voltage can be controlled. After exceeding a certain depth, the holes under the first groove are depleted in the off state, and the device realizes enhancement mode.

[0100] 3. By changing the second groove depth, that is, Al x The depth of the GaN layer sinking reduces the thickness of the transistor base region and the probability of electrons and holes recombining in the base region. More electrons are collected at the collector, thereby increasing the amplification factor of the transistor, compensating for the output current density loss caused by etching the first groove, and improving the output characteristics.

[0101] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. An enhancement mode GaN-based p-channel field effect transistor, characterized in that: The enhanced GaN-based p-channel field effect transistor comprises from bottom to top: substrate (01), buffer layer (02), first UID-GaN layer (03), barrier layer (04), first p-type semiconductor layer (05), second UID-GaN layer (06), n-GaN layer (07), n - -GaN layer (08), second p-type semiconductor layer (09), Al x GaN layer (10); A source electrode (13) located on the second p-type semiconductor layer (09); Located in Al x A drain electrode (14) on the GaN layer (10); Located on the n-GaN layer (07) not covered by n - - a collector electrode (15) on one end covered by a GaN layer (08); Located between the source electrode (13) and Al x A gate dielectric layer (11) between the GaN layers (10) and on the second p-type semiconductor layer (09); A gate electrode (12) is located on the gate dielectric layer (11).

2. The enhancement mode GaN-based p-channel field effect transistor according to claim 1, characterized in that: A first groove (21) is etched in the middle of the second p-type semiconductor layer (09), The depth of the first groove (21) is 50-70 nm, and the upper surface and side walls thereof are covered with a gate dielectric layer (11).

3. The enhancement mode GaN-based p-channel field effect transistor according to claim 2, characterized in that: A second groove (22) is etched on one side of the first groove (21), The depth of the second groove (22) is 5-50nm, and the Al x The GaN layer (10) is filled.

4. The enhancement mode GaN-based p-channel field effect transistor according to any one of claims 1 to 3, characterized in that: The material of the substrate (01) includes: silicon, sapphire or silicon carbide; The thickness of the GaN buffer layer (02) is 2 μm-5 μm; The thickness of the first UID-GaN layer (03) is 80-120 nm; The barrier layer (04) is made of AlGaN with a thickness of 10nm-40nm, wherein the proportion of Al is between 20% and 30%; The material of the first p-type semiconductor layer (05) is any one of GaN, InGaN and hBN, with a thickness of 60-80 nm, wherein the Mg doping concentration is 1×10 19 cm -3 ~5×10 19 cm -3 .

5. The enhancement mode GaN-based p-channel field effect transistor according to claim 4, characterized in that: The second UID-GaN layer (06) has a thickness of 80-120 nm; The thickness of the n-GaN layer (07) is 80-120 nm, wherein the Si doping concentration is 1×10 18 cm -3 ~5×10 18 cm -3 ; The - -GaN layer (08) has a thickness of 100-200 nm, wherein the Si doping concentration is 0.5×10 17 cm -3 ~5×10 17 cm -3 ; The material of the second p-type semiconductor layer (09) is any one of GaN and InGaN, with a thickness of 60-80 nm, wherein the Mg doping concentration is 1×10 19 cm -3 ~5×10 19 cm -3 ; The Al x The thickness of the GaN layer (10) is 60-80 nm, wherein x=0.1-0.3 and the Si doping concentration is 1×10 18 cm -3 ~5×10 18 cm -3 .

6. The enhancement mode GaN-based p-channel field effect transistor according to claim 5, characterized in that: The gate dielectric layer (11) is made of any one of Al2O3, AlN, SiO2, HfO2, and ZrO2 or any combination thereof, and has a thickness of 5nm-20nm.

7. The enhancement mode GaN-based p-channel field effect transistor according to claim 6, characterized in that: The gate electrode (12) is made of Ti / Au laminated metal.

8. The enhancement mode GaN-based p-channel field effect transistor according to claim 7, characterized in that: In the Ti / Au laminated metal, the thickness of the Ti metal is 20 nm, and the thickness of the Au metal is 100 nm.

9. The enhancement mode GaN-based p-channel field effect transistor according to claim 8, characterized in that: The material of the ohmic contact of the source electrode (13), the drain electrode (14) and the collector electrode (15) is a Ni / Au metal stack, wherein the thickness of the Ni metal in the Ni / Au metal stack is 20 nm, and the thickness of the Au metal is 20 nm.

10. A method for preparing an enhanced GaN-based p-channel field effect transistor, the method comprising: Step S1: providing a substrate (01); Step S2: using a metal organic chemical vapor deposition process, epitaxially growing a GaN buffer layer (02), a first UID-GaN layer (03), a barrier layer (04), a first p-type semiconductor layer (05), a second UID-GaN layer (06), an n-GaN layer (07), and an n-type semiconductor layer (08) on the substrate (01). - -GaN layer (08), a second p-type semiconductor layer (09); Step S3: etching the second p-type semiconductor layer (09) and n-type semiconductor layer by low-damage BCl3 / Cl2-based inductively coupled plasma (ICP) - The -GaN layer (08) is partially etched until a portion of the surface of the n-GaN layer (07) is exposed; Step S4: using inductively coupled plasma etching (ICP) to form a first groove (21) in the middle of the second p-type semiconductor layer (09), and forming a second groove (22) on one side of the first groove (21); Step S5: Epitaxial growth of Al x The GaN layer (10) fills the second groove (22); Step S6: Using electron beam evaporation technology, on the second p-type semiconductor layer (09), away from Al x Metal is evaporated on one side of the GaN layer (10), and an ohmic contact source electrode (13) is formed after rapid thermal annealing; Step S7: Photolithography on Al x An n-type ohmic contact region is defined above the GaN layer (10) and the n-GaN layer (07), and a metal alloy combination is deposited above the ohmic contact region to form a drain electrode (14) and a collector electrode (15), respectively; Step S8: using atomic layer deposition (ALD) technology, the bottom and sidewalls of the first groove (21) are covered with a gate dielectric layer (11), and the gate dielectric layer (11) also extends to both sides along the upper surface of the second p-type semiconductor layer (09); Step S9: depositing metal on the gate dielectric layer (11) in the first groove (21) to form a gate electrode (12).

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