Power MOSFET device structure capable of improving short circuit endurance capability

Abstract

According to the power MOSFET device structure capable of improving the short circuit endurance capacity, in the structure, a first conductive type epitaxial drift region is located above a first conductive type substrate, a first base region of a second conductive type is arranged in the first conductive type epitaxial drift region, a second base region of the second conductive type is arranged in the first conductive type epitaxial drift region, and a second base region of the second conductive type is arranged in the second conductive type substrate; the first base region and the second base region are in contact with each other, the heavily doped base region of the second conduction type is arranged in the first base region or arranged in the first base region and extends into the second base region, the source region of the first conduction type is heavily doped, and the source region is arranged in the first base region and is in contact with the heavily doped base region; the current expansion region of the first conduction type is in contact with the first base region and the second base region and goes beyond the second base region and goes deep into the epitaxial drift region of the first conduction type, the gate oxide region is located above the first base region, part of the current expansion region and part of the source region in a contact manner, and the polycrystalline silicon region is arranged on the gate oxide region.

Description

Technical Field

[0001] The invention relates to the technical field of silicon carbide (SiC) power devices, and in particular to a power MOSFET device structure with improved short-circuit tolerance. Background Art

[0002] Wide bandgap semiconductor materials have gradually been widely studied and applied, especially in replacing traditional Si-based devices in high power density applications. They have excellent performance. Thanks to the superior performance of the material, they are more suitable for high voltage, high temperature, high frequency and other scenarios. SiC MOSFET, as an excellent substitute for Si IGBT, has better breakdown performance, faster switching speed, and smaller on-resistance. It has gradually been widely used in applications such as electric vehicle inverters and photovoltaic inverters, and has outstanding advantages in improving system power density and miniaturizing the system.

[0003] For SiC power MOSFET, thanks to the higher saturated electron drift velocity and thinner drift region thickness, lower characteristic on-resistance can be achieved, while higher current density can be achieved, and higher current density will bring higher heat generation. Compared with Si IGBT, in the event of a short circuit, IGBT can usually withstand 10μs of short-circuit stress, and the main heat generation is mainly concentrated in the drift region, rather than under the channel. At the same time, because the drift region thickness of Si IGBT is thicker at the same voltage level, it can accommodate more heat diffusion. The heat generation of SiC MOSFET is mainly concentrated in the current expansion region, and the thinner drift region thickness makes the heat of the gate oxide part concentrate faster, resulting in melting of the top of the device. The usual SiC MOSFET can only achieve a short-circuit stress of about 3μs.

[0004] In order to enhance the short-circuit tolerance capability, various schemes have been proposed to regulate the resistance on the conduction path to improve the short-circuit performance, such as adding a lightly doped N drift region in the source region and limiting the P region to improve the resistance on the path. At the same time, it can have a certain pinch-off performance under high voltage. However, at the same time, this type of structure greatly limits the device's room-temperature overcurrent capability.

[0005] The information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0006] In view of the deficiencies or defects of the prior art, a power MOSFET device structure with improved short-circuit tolerance is provided, and a method for improving the doping concentration and distribution of the first conductive type in the current extension region and the doping concentration and distribution shape of the second conductive type in the base region is provided. At the same time, a field plate structure of the source is added to enhance the charge regulation effect, reduce the overcurrent capacity of the SiC MOSFET at high temperature in a short-circuit situation, thereby reducing the heat generated during the short-circuit process, while rarely affecting the overcurrent capacity during the conduction process, thereby improving the short-circuit performance of the device.

[0007] The purpose of the present invention is achieved through the following technical solutions.

[0008] A power MOSFET device structure with improved short circuit tolerance includes:

[0009] a first conductive type substrate,

[0010] A first conductivity type epitaxial drift region is located above the first conductivity type substrate,

[0011] a first base region of a second conductivity type, which is disposed in the epitaxial drift region of the first conductivity type,

[0012] a second base region of a second conductivity type, which is disposed in the epitaxial drift region of the first conductivity type, the first base region and the second base region being in contact with each other,

[0013] A heavily doped base region of a second conductivity type is disposed in the first base region or is disposed in the first base region and extends deep into the second base region,

[0014] A source region of a first conductivity type is heavily doped, the source region being disposed in the first base region and in contact with the heavily doped base region,

[0015] A current extension region of the first conductivity type is in contact with the first base region and the second base region and extends beyond the second base region into the first conductivity type epitaxial drift region.

[0016] The gate oxide region, the contact ground is located above the first base region, part of the current extension region and part of the source region,

[0017] The polysilicon region is disposed on the gate oxide region.

[0018] The power MOSFET device structure for improving short-circuit tolerance also includes:

[0019] A source field plate region is disposed above the current extension region and is spaced between the gate oxide regions.

[0020] The source contact region closely contacts the heavily doped base region, the source field plate region and part of the source region.

[0021] The power MOSFET device structure with improved short-circuit withstand capability also includes an oxide layer isolation region, which is located between the source contact region and the polysilicon region to isolate the source contact region from the polysilicon region.

[0022] In the power MOSFET device structure with improved short-circuit withstand capability, the width of the source field plate region is smaller than the width of the current extension region.

[0023] In the power MOSFET device structure for improving short-circuit withstand capability, the first conductivity type is N-type and the second conductivity type is P-type.

[0024] In the power MOSFET device structure for improving short-circuit withstand capability, the first conductivity type is P-type and the second conductivity type is N-type.

[0025] In the power MOSFET device structure for improving short-circuit withstand capability, the doping concentration of the current extension region of the first conductivity type is 1×10 16 cm -3 ~ 5×10 17 cm -3 .

[0026] In the power MOSFET device structure with improved short-circuit withstand capability, the depth of the current extension region of the first conductivity type exceeds the depth of the second base region of the second conductivity type.

[0027] The power MOSFET device structure with improved short-circuit withstand capability also includes a drain metal electrode region, which is located below the first conductive type substrate.

[0028] In the power MOSFET device structure with improved short-circuit withstand capability, the polysilicon region includes polysilicon of a first doping type, the first base region and the second base region are of a second doping type different from the first doping type, the width of the second base region in the direction extending to the current extension region exceeds the width of the first base region by 0.3 μm to 1 μm, and the narrowest part of the current extension region is 0.3 μm to 1 μm

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention benefits from the current extension region of the first conductivity type that can be more highly doped. The device structure shields and adjusts the resistance distribution through the first base region of the second conductivity type, thereby not reducing the overcurrent capacity of the device during forward operation. The first base region and the second base region of the second conductivity type, together with the source field plate, adjust the charge of the device during reverse operation, protect the gate oxide, and achieve higher reverse performance, that is, achieve a certain degree of device merit improvement. Due to the additional design of the second base region of the device and the structural capacitance conversion characteristics of the split gate, the device has a lower gate charge and can achieve faster switching. The first base region and the second base region of the second doping type and the source field plate regulate the charge inside the device, and the current expansion in the JFET is suppressed, and the current at high temperature is limited, thereby reducing the saturation current of the device at high temperature. When a short circuit occurs, the second base region shielding inside the device structure together with the source field plate limits the high power area, controls the temperature rise of the device, and achieves a longer short circuit tolerance.

[0031] The above description is only an overview of the technical solution of the present invention. In order to make the technical means of the present invention clearer and to achieve the extent that those skilled in the art can implement it according to the contents of the specification, and in order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are exemplified below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] By reading the detailed description of the preferred specific embodiments below, various other advantages and benefits of the present invention will become clear to those of ordinary skill in the art. The drawings in the specification are only for the purpose of illustrating the preferred embodiments and are not considered to be limitations of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work. Moreover, the same reference numerals are used to represent the same components throughout the drawings.

[0033] In the attached picture:

[0034] Figure 1 It is a structural schematic diagram of the present invention;

[0035] Figure 2 A comparison diagram of the transfer characteristic curves of the present invention and the prior art;

[0036] Figure 3 A comparison diagram of the breakdown characteristic curves of the present invention and the prior art;

[0037] Figure 4 A comparison diagram of short-circuit current and junction temperature curves of the present invention and the prior art;

[0038] Figure 5 It is a schematic diagram of the preparation process of the present invention.

[0039] The present invention is further explained below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0040] The specific embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the specific embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0041] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present invention, but the description is based on the general principles of the specification and is not intended to limit the scope of the present invention. The scope of protection of the present invention shall be determined by the attached claims.

[0042] To facilitate understanding of the embodiments of the present invention, several specific embodiments will be further explained below with reference to the accompanying drawings, and each of the accompanying drawings does not constitute a limitation on the embodiments of the present invention.

[0043] For a better understanding, Figures 1 to 5 As shown, a power MOSFET device structure for improving short-circuit withstand capability includes:

[0044] The first conductive type substrate 212,

[0045] A first conductive type epitaxial drift region 211 is located above the first conductive type substrate 212,

[0046] A first base region 208 of the second conductivity type is provided in the epitaxial drift region 211 of the first conductivity type,

[0047] A second base region 209 of the second conductivity type is provided in the first conductivity type epitaxial drift region 211, and the first base region 208 and the second base region 209 are in contact with each other.

[0048] A heavily doped base region 207 of a second conductivity type is disposed in the first base region 208 or is disposed in the first base region 208 and extends deep into the second base region 209.

[0049] A source region 206 of the first conductivity type is heavily doped, and the source region 206 is disposed in the first base region 208 and in contact with the heavily doped base region 207.

[0050] The first conductive type current extension region 210 is in contact with the first base region 208 and the second base region 209 and extends beyond the second base region 209 into the first conductive type epitaxial drift region 211.

[0051] The gate oxide region 204 is located above the first base region 208, a portion of the current extension region 210 and a portion of the source region 206.

[0052] The polysilicon region 203 is disposed on the gate oxide region 204 .

[0053] In a preferred embodiment of the power MOSFET device structure for improving short-circuit withstand capability, the structure further includes:

[0054] The source field plate region 205 is disposed above the current extension region 210 and is spaced between the gate oxide regions 204.

[0055] The source contact region 201 is in close contact with the heavily doped base region 207 , the source field plate region 205 and a portion of the source region 206 .

[0056] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, an oxide layer isolation region 202 is further included, which is located between the source contact region 201 and the polysilicon region 203 to isolate the source contact region 201 and the polysilicon region 203 .

[0057] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the width of the source field plate region 205 is smaller than the width of the current extension region 210 .

[0058] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the first conductivity type is N-type and the second conductivity type is P-type.

[0059] In a preferred embodiment of the power MOSFET device structure for improving short-circuit withstand capability, the first conductivity type is P-type and the second conductivity type is N-type.

[0060] In the preferred embodiment of the power MOSFET device structure for improving the short-circuit withstand capability, the doping concentration of the first conductive type current extension region 210 is 1×10 16 cm -3~ 5×10 17 cm -3 .

[0061] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the depth of the current extension region 210 of the first conductivity type exceeds the depth of the second base region 209 of the second conductivity type.

[0062] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, it further includes a drain metal electrode region 213 , which is located below the first conductive type substrate 212 .

[0063] In a preferred embodiment of the power MOSFET device structure with improved short-circuit withstand capability, the polysilicon region 203 includes polysilicon of a first doping type, the first base region 208 and the second base region 209 are of a second doping type different from the first doping type, the width w2 of the second base region in the direction extending toward the current expansion region exceeds the width of the first base region w1 by 0.3μm~1μm, and the narrowest part of the current expansion region is 0.3μm~1μm.

[0064] In one embodiment, a power MOSFET device structure with improved short circuit withstand capability includes:

[0065] The first conductive type substrate 212,

[0066] A first conductive type epitaxial drift region 211 is located above the first conductive type substrate 212,

[0067] The drain metal electrode region 213 is located below the first conductive type substrate 212.

[0068] A first base region 208 of the second conductivity type is provided in the epitaxial drift region 211 of the first conductivity type,

[0069] A second base region 209 of the second conductivity type is provided in the first conductivity type epitaxial drift region 211, and the first base region 208 and the second base region 209 are in contact with each other.

[0070] A heavily doped base region 207 of a second conductivity type is disposed in the first base region 208 or is disposed in the first base region 208 and extends deep into the second base region 209.

[0071] A source region 206 of the first conductivity type is heavily doped, and the source region 206 is disposed in the first base region 208 and in contact with the heavily doped base region 207.

[0072] The first conductive type current extension region 210 is in contact with the first base region 208 and the second base region 209 and extends beyond the second base region 209 into the first conductive type epitaxial drift region 211.

[0073] The gate oxide region 204 is located above the first base region 208, a portion of the current extension region 210 and a portion of the source region 206.

[0074] A polysilicon region 203 is disposed on the gate oxide region 204, and the polysilicon region 203 includes polysilicon of a first doping type.

[0075] The source field plate region 205 is disposed above the current extension region 210 and is spaced between the gate oxide regions 204.

[0076] The source contact region 201 is in close contact with the heavily doped base region 207, the source field plate region 205 and a portion of the source region 206.

[0077] The oxide layer isolation region 202 is located between the source contact region 201 and the polysilicon region 203 to isolate the source contact region 201 from the polysilicon region 203 .

[0078] In one embodiment, the first conductive type substrate 212 is a silicon carbide substrate.

[0079] In one embodiment, a power MOSFET device structure with improved short-circuit withstand capability includes a silicon carbide substrate of a first conductivity type and a first conductivity type epitaxial drift region 211 located above the silicon carbide substrate, a drain metal electrode region 213 is located below the substrate, and a first conductivity type current extension region 210 and a source region 206, a first base region 208, a second base region 209 and a second conductivity type heavily doped base region 207 are included inside the first conductivity type epitaxial drift region 211. The current extension region 210 is located at a central position and is embedded with the first base region 208 and the second base region 209, the first base region 208 and the second base region 209 are in contact with each other, the source region 206 is wrapped inside by the first base region 208, the lateral width of the second base region 209 is greater than the first base region 208 and extends to the inside of the current extension region 210, and the heavily doped base region 207 extends to the inside of the first base region 208 and the second base region 209 and contacts with the source region 206, presenting an axisymmetric structure. A gate oxide region 204 and a first doping type polysilicon region 203 are provided above the first conductivity type epitaxial drift region 211. The polysilicon region 203 is stacked on the gate oxide region 204 and is a gate region. The gate oxide region 204 is located above the first base region 208, part of the current extension region 210 and part of the source region 206. The source contact region 201 is located above the heavily doped base region 207 and part of the source region 206. The polysilicon region 203 and the source contact region 201 are isolated by an oxide layer isolation region 202. Just above the current extension region 210, there is an oxide layer with a different thickness from the gate oxide region at a distance from the polysilicon region, which is a source field plate region 205. Above it is the source contact region 201, which is a metal structure.

[0080] As a further technical solution, the doping concentration of the first conductive type current extension region 210 is 1×10 16 cm -3 ~ 5×10 17 cm -3 The width of the current extension region 210 depends on the width of the first base region 208 and the second base region 209 of the second conductivity type.

[0081] As a further technical solution, the depth of the current extension region 210 of the first conductivity type exceeds the depth of the second base region 209 of the second conductivity type.

[0082] As a further technical solution, the depth of the current extension region 210 of the first conductivity type is located within the depth interval of the second base region 209 of the second conductivity type.

[0083] As a further technical solution, the depth of the current extension region 210 of the first conductivity type is shallower than the depth of the second base region 209 of the second conductivity type.

[0084] As a further technical solution, the doping concentration of the first conductive type current extension zone 210 is a gradient type, and the doping concentration above the second base region 209 and the doping concentration of the remaining parts are different concentrations. Depending on the design, it can present positive doping, reverse doping, or a trapezoidal doping distribution.

[0085] As a further technical solution, the doping concentration of the second base region 209 of the second conductivity type is 1×10 17 cm -3 ~ 1×10 19 cm -3 Generally, the distribution decays from the top position downward, and the doping concentration is higher at the center position, which can present a uniform doping distribution.

[0086] As a further technical solution, the second base region 209 of the second conductivity type can be realized by epitaxy. After the drift region of the first conductivity type is grown, the second base region 209 of the second conductivity type is grown, and then a layer of epitaxy of the first conductivity type is grown for other structures. In order to realize the corresponding structure, the width needs to be controlled by ion implantation of the first conductivity type.

[0087] As a further technical solution, the width of the second base region 209 of the second conductivity type exceeding the first base region 208 is 0.3 μm-1 μm, and the width between the second base regions 209, that is, the narrowest part of the current extension region 210 is 0.3 μm-1 μm.

[0088] As a further technical solution, the depth and doping concentration of the second base region 209 of the second conductivity type are determined according to the depth and doping concentration of the current extension region 210 of the first conductivity type located above the second base region 209 .

[0089] As a further technical solution, the thickness of the source field plate region 205 is 10 nm to 1 μm, and the dielectric type can be changed from silicon dioxide to High-K dielectric.

[0090] As a further technical solution, the width of the source field plate region 205 determines the charge control capability of this part. The source field plate region 205 and the nearby areas where the first base region 208, the second base region 209 and the current extension region 210 contact each other also have charge control capability. The relative relationship between the various parts is adjusted to achieve the desired charge control capability.

[0091] As a further technical solution, the source field plate region 205 structure is eliminated while the structure of the split gate is maintained to achieve different charge control capabilities. The split gate includes a gate oxide region 204 and a polysilicon region 203 .

[0092] As a further technical solution, the structure parts of the source field plate and the split gate are eliminated at the same time to achieve different charge regulation capabilities.

[0093] In the above technical solution, for an N-type SiC power MOS device, the first conductivity type refers to N-type and the second conductivity type is P-type; and for a P-type SiC power MOS device, the first conductivity type refers to P-type and the second conductivity type is N-type.

[0094] In one embodiment, a SiC power MOSFET device structure with improved short-circuit withstand capability includes a first conductive type substrate 212, a first conductive type epitaxial drift region 211, which is located above the first conductive type substrate 212, a drain metal electrode region 213 below the first conductive type substrate 212, a second conductive type first base region 208 and a second base region 209 inside the first conductive type substrate 212, the first base region 208 and the second base region 209 are in contact with each other, a second conductive type heavily doped base region 207 is inside the first base region 208 and the second base region 209, the heavily doped base region 207 can be only inside the first base region 208, or can go deep into the second base region 209, a heavily doped first conductive type source region 206 is inside the first base region 208, and the source region 206 is in contact with the heavily doped base region 207. A first conductive type current extension region is in contact with the first base region 208 and the second base region 209, and goes beyond the second base region 209 and goes deep into the first conductive type epitaxial drift region 211. Above the first conductive type epitaxial drift region 211 are the gate oxide region 204 and the polysilicon region 203 as well as the source contact region 201 and the source field plate region 205. Between the source contact region and the polysilicon region is the oxide layer isolation region 202. Below the source contact region 201, it is in close contact with the heavily doped base region 207 and part of the source region 206. Below the gate oxide region 204, it is in close contact with part of the source region 206, the first base region 208 and part of the current extension region 210. The overall structure is axially symmetrical. The source field plate region 205 is located between the two parts of the split gate. The source field plate region 205 is in close contact with the source contact region 201 and is located between the two parts of the oxide layer isolation region 202. Below the source field plate region 205 is the current extension region 210, and its width is smaller than the current extension region 210.

[0095] In one embodiment, the region may be a layer, such as the current extension region may be a current extension region layer. The arrangement may be a stack of layers.

[0096] Figure 2 The transfer characteristic curve of the newly proposed device structure represents the room temperature overcurrent capability of the device when the drain voltage is 20 V. It is obtained by simulation with the simulation software Sentaurus TCAD.

[0097] Figure 3The breakdown characteristic curve of the newly proposed device structure represents the device's ability to withstand drain voltage when the gate voltage is 0, that is, the reverse withstand voltage level of the device. It was obtained by simulation with the simulation software Sentaurus TCAD.

[0098] Figure 4 It shows the change trend of the drain current and average junction temperature of the device over time when the gate voltage is 20V and the drain voltage is 400V under short circuit conditions. The longer the tolerance time, the stronger the ability. It also shows that the proposed structure can achieve better high-temperature current limiting capability and reduce the temperature rise of the device. It was obtained by simulation software Sentaurus TCAD.

[0099] Figure 5 A process flow chart for realizing the device structure is given, which can be realized by combining with actual process.

[0100] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0101] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A power MOSFET device structure with improved short-circuit withstand capability, characterized in that: These include, a first conductive type substrate, A first conductivity type epitaxial drift region is located above the first conductivity type substrate, a first base region of a second conductivity type, which is disposed in the epitaxial drift region of the first conductivity type, a second base region of a second conductivity type, which is disposed in the epitaxial drift region of the first conductivity type, the first base region and the second base region being in contact with each other, A heavily doped base region of a second conductivity type is disposed in the first base region or is disposed in the first base region and extends deep into the second base region, A source region of a first conductivity type is heavily doped, the source region being disposed in the first base region and in contact with the heavily doped base region, A current extension region of the first conductivity type is in contact with the first base region and the second base region and extends beyond the second base region into the first conductivity type epitaxial drift region. The gate oxide region, the contact ground is located above the first base region, part of the current extension region and part of the source region, The polysilicon region is disposed on the gate oxide region.

2. The power MOSFET device structure for improving short-circuit withstand capability as claimed in claim 1, characterized in that: Preferably, it also includes, A source field plate region is disposed above the current extension region and is spaced between the gate oxide regions. The source contact region closely contacts the heavily doped base region, the source field plate region and part of the source region.

3. The power MOSFET device structure for improving short-circuit withstand capability as claimed in claim 2, characterized in that: The invention also includes an oxide layer isolation region, which is located between the source contact region and the polysilicon region to isolate the source contact region from the polysilicon region.

4. The power MOSFET device structure for improving short-circuit withstand capability as claimed in claim 2, characterized in that: The width of the source field plate region is smaller than the width of the current extension region.

5. The power MOSFET device structure with improved short circuit withstand capability as claimed in claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

6. The power MOSFET device structure for improving short-circuit withstand capability as claimed in claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

7. The power MOSFET device structure for improving short-circuit withstand capability as claimed in claim 1, characterized in that: The doping concentration of the first conductivity type current extension region is 1×10 16 cm -3 ~ 5×10 17 cm -3 .

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