Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, a highly doped epitaxial layer and a lightly doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, and the semiconductor substrate comprises a first region and a second region; the first part of the semiconductor device is positioned on the lightly doped epitaxial layer of the first region and takes the lightly doped epitaxial layer of the first region as a channel; and the second part of the semiconductor device is located in the low-doped epitaxial layer of the second region, and the second part of the semiconductor device penetrates through the low-doped epitaxial layer and is electrically connected with the high-doped epitaxial layer. The invention provides a semiconductor structure and a forming method thereof. The reliability and the performance of an existing silicon carbide device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Power modules provide functions such as thermal management, electrical insulation, mechanical protection, optimized electrical performance, and low thermal conductivity. Traditional silicon modules are used to package third-generation semiconductor chips such as silicon carbide and gallium nitride. The high parasitic parameters of the gate and power circuits are not conducive to the excellent performance of third-generation semiconductor chips. Traditional silicon carbide power modules are packaged on the back of the chip through a multi-layer substrate, which is costly, has high substrate resistance, high thermal resistance, and high parasitic inductance of the circuit.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the reliability and device performance of existing third-generation semiconductor devices such as silicon carbide and gallium nitride. Summary of the invention

[0004] The invention of this application aims to improve the device reliability and device performance of existing silicon carbide devices.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, a first surface of the semiconductor substrate having a highly doped epitaxial layer and a low doped epitaxial layer formed in sequence, the semiconductor substrate comprising a first region and a second region; forming a first part of a semiconductor device on the low doped epitaxial layer of the first region using the low doped epitaxial layer of the first region as a channel; forming a second part of the semiconductor device in the low doped epitaxial layer of the second region, the second part of the semiconductor device penetrating the low doped epitaxial layer and electrically connected to the highly doped epitaxial layer.

[0006] In some embodiments of the present application, the method for forming the second part of the semiconductor device in the low-doped epitaxial layer in the second region includes: forming a groove in the second region that penetrates the low-doped epitaxial layer and exposes the high-doped epitaxial layer; forming a high-doped contact layer in the low-doped epitaxial layer on the sidewalls of the trench; forming an ohmic contact layer on the surface of the high-doped epitaxial layer at the bottom of the trench and the high-doped contact layer on the sidewalls of the trench; and forming a conductive layer in the trench that fills the trench and is electrically connected to the ohmic contact layer.

[0007] In some embodiments of the present application, the method for forming the second part of the semiconductor device in the low-doped epitaxial layer in the second region includes: forming a highly doped contact layer in the second region that penetrates the low-doped epitaxial layer and is electrically connected to the highly doped epitaxial layer; and forming a conductive layer on the top surface of the highly doped contact layer that is electrically connected to the highly doped contact layer.

[0008] In some embodiments of the present application, the method for forming the second part of the semiconductor device in the low-doped epitaxial layer in the second region includes: forming a highly doped contact layer in the second region that passes through the low-doped epitaxial layer and is electrically connected to the highly doped epitaxial layer; forming an ohmic contact layer in the high-doped contact layer that passes through the high-doped contact layer and is electrically connected to the highly doped epitaxial layer; and forming a conductive layer on the top surfaces of the ohmic contact layer and the high-doped contact layer that is electrically connected to the ohmic contact layer and the high-doped contact layer.

[0009] In some embodiments of the present application, the method of forming the second portion of the semiconductor device in the low-doped epitaxial layer in the second region includes: forming a conductive layer in the second region that penetrates the low-doped epitaxial layer and electrically connects the high-doped epitaxial layer.

[0010] In some embodiments of the present application, the semiconductor substrate further includes a second surface opposite to the first surface, and the method for forming the semiconductor structure further includes: forming a heat dissipation structure on the second surface.

[0011] In some embodiments of the present application, the heat dissipation structure includes: a heat dissipation metal layer or thermal conductive silicone grease.

[0012] In some embodiments of the present application, the material of the semiconductor substrate includes undoped silicon carbide, the material of the highly doped epitaxial layer includes doped silicon carbide, and the material of the low doped epitaxial layer includes doped silicon carbide.

[0013] In some embodiments of the present application, the doping concentration of the highly doped epitaxial layer is greater than the doping concentration of the low doped epitaxial layer, and the doping concentration of the highly doped epitaxial layer is 1E18 to 1E21 cm -3 The doping concentration of the low-doped epitaxial layer is 1E16 to 3E19 cm -3 .

[0014] In some embodiments of the present application, the first region includes a core device region and a protection region located around the core device region, and the second region includes a dicing region.

[0015] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, a first surface of which is sequentially formed with a highly doped epitaxial layer and a low doped epitaxial layer, the semiconductor substrate including a first region and a second region; a first part of a semiconductor device, located on the low doped epitaxial layer of the first region with the low doped epitaxial layer of the first region as a channel; a second part of the semiconductor device, located in the low doped epitaxial layer of the second region, the second part of the semiconductor device penetrates the low doped epitaxial layer and is electrically connected to the highly doped epitaxial layer.

[0016] In some embodiments of the present application, the second part of the semiconductor device includes: a trench that penetrates the second region and exposes the high-doped epitaxial layer through the low-doped epitaxial layer; a high-doped contact layer in the low-doped epitaxial layer on the sidewalls of the trench; an ohmic contact layer on the surface of the high-doped epitaxial layer at the bottom of the trench and the high-doped contact layer on the sidewalls of the trench; and a conductive layer in the trench that fills the trench and is electrically connected to the ohmic contact layer.

[0017] In some embodiments of the present application, the second part of the semiconductor device includes: a highly doped contact layer that runs through the second region and is electrically connected to the highly doped epitaxial layer; and a conductive layer located on the top surface of the highly doped contact layer and is electrically connected to the highly doped contact layer.

[0018] In some embodiments of the present application, the second part of the semiconductor device includes: a highly doped contact layer that passes through the low-doped epitaxial layer of the second region and is electrically connected to the highly doped epitaxial layer; an ohmic contact layer that passes through the highly doped contact layer and is electrically connected to the highly doped epitaxial layer; and a conductive layer located on the top surfaces of the ohmic contact layer and the highly doped contact layer and is electrically connected to the ohmic contact layer and the highly doped contact layer.

[0019] In some embodiments of the present application, the second portion of the semiconductor device includes: a conductive layer that penetrates the low-doped epitaxial layer of the second region and is electrically connected to the high-doped epitaxial layer.

[0020] In some embodiments of the present application, the semiconductor substrate further includes a second surface opposite to the first surface, and the semiconductor structure further includes: a heat dissipation structure located on the second surface.

[0021] In some embodiments of the present application, the heat dissipation structure includes: a heat dissipation metal layer or thermal conductive silicone grease.

[0022] In some embodiments of the present application, the material of the semiconductor substrate includes undoped silicon carbide, the material of the highly doped epitaxial layer includes doped silicon carbide, and the material of the low doped epitaxial layer includes doped silicon carbide.

[0023] In some embodiments of the present application, the doping concentration of the highly doped epitaxial layer is greater than the doping concentration of the low doped epitaxial layer, and the doping concentration of the highly doped epitaxial layer is 1E18 to 1E21 cm -3 The doping concentration of the low-doped epitaxial layer is 1E16 to 3E19 cm -3 .

[0024] In some embodiments of the present application, the first region includes a core device region and a protection region located around the core device region, and the second region includes a dicing region.

[0025] The present application provides a semiconductor structure and a method for forming the same, which can improve the device reliability and device performance of existing silicon carbide devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0027] in:

[0028] Figures 1 to 9 It is a structural schematic diagram of each step in the method for forming a semiconductor structure according to some embodiments of the present application;

[0029] Fig.10 It is a schematic structural diagram of a semiconductor structure described in some other embodiments of the present application;

[0030] Fig.11 It is a schematic structural diagram of a semiconductor structure described in some other embodiments of the present application;

[0031] Fig.12 Schematic diagram of the semiconductor structure described in some other embodiments of the present application. DETAILED DESCRIPTION

[0032] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0033] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0034] Figures 1 to 9 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.

[0035] refer to Figure 1As shown, a semiconductor substrate 100 is provided, a first surface of which is sequentially formed with a highly doped epitaxial layer 110 and a low doped epitaxial layer 120 , and the semiconductor substrate 100 includes a first region 101 and a second region 102 .

[0036] In some embodiments of the present application, the material of the semiconductor substrate 100 includes undoped silicon carbide, the material of the highly doped epitaxial layer 110 includes doped silicon carbide, and the material of the low doped epitaxial layer 120 includes doped silicon carbide. The highly doped epitaxial layer 110 and the low doped epitaxial layer 120 have the same doping type, for example, N-type.

[0037] In some embodiments of the present application, the doping concentration of the highly doped epitaxial layer 110 is greater than the doping concentration of the low doped epitaxial layer 120, and the doping concentration of the highly doped epitaxial layer 110 is 1E18 to 1E21 cm -3 The doping concentration of the low-doped epitaxial layer 120 is 1E16 to 3E19 cm -3 .

[0038] In some embodiments of the present application, the thickness of the semiconductor substrate 100 is 2-200 microns, the thickness of the highly doped epitaxial layer 110 is 2-200 microns, and the thickness of the low doped epitaxial layer 120 is 2-200 microns.

[0039] In some embodiments of the present application, the method for sequentially forming the highly doped epitaxial layer 110 and the low doped epitaxial layer 120 on the first surface of the semiconductor substrate 100 includes: performing a first in-situ doping epitaxial growth process to form the highly doped epitaxial layer 110 on the first surface of the semiconductor substrate 100; performing a second in-situ doping epitaxial growth process to form the low doped epitaxial layer 120 on the surface of the highly doped epitaxial layer 110. The concentration of the doping source gas in the second in-situ doping epitaxial growth process is lower than the concentration of the doping source gas in the first in-situ doping epitaxial growth process.

[0040] In some embodiments of the present application, the first region 101 includes a core device region and a protection region located around the core device region, and the second region 102 includes a dicing region.

[0041] Then refer to Figures 2 to 9 As shown, a first part of a semiconductor device is formed on the low-doped epitaxial layer 120 of the first region 101 using the low-doped epitaxial layer 120 of the first region 101 as a channel; a second part of the semiconductor device is formed in the low-doped epitaxial layer 120 of the second region 102, and the second part of the semiconductor device penetrates the low-doped epitaxial layer 120 and is electrically connected to the high-doped epitaxial layer 110.

[0042] It should be noted that the technical solution of the present application does not limit the specific type of semiconductor device. The semiconductor device described in the present application is, for example, any one or more of a diode, a transistor (MOSFET), an IGBT, and a HMET. Therefore, the specific structure of the first part of the semiconductor device and the second part of the semiconductor device varies according to the type of semiconductor device. For example, when the semiconductor device is a transistor, the first part of the semiconductor device includes a source portion and a gate portion, and the second part of the semiconductor device includes a drain portion. When the semiconductor device is a diode, the first part of the semiconductor device includes an anode, and the second part of the semiconductor device includes a cathode. When the semiconductor device is an IGBT, the first part of the semiconductor device includes an emitter portion and a gate portion, and the second part of the semiconductor device includes a collector portion. When the semiconductor device is an HMET, the first part of the semiconductor device includes a source portion and a gate portion, and the second part of the semiconductor device includes a drain portion. The basic structure and manufacturing process of semiconductor devices such as diodes, transistors (MOSFET), IGBTs, and HMETs may be known to those skilled in the art. This application is only explained using transistors as examples. Those skilled in the art should be able to understand the structures and processes of other semiconductor devices in the technical solutions of this application based on the examples of transistors disclosed in this application.

[0043] In addition, the technical solution of the present application does not limit the order in which the first part of the semiconductor device and the second part of the semiconductor device are formed. In the case where the first part of the semiconductor device and the second part of the semiconductor device both include multiple steps, the respective steps of the first part of the semiconductor device and the second part of the semiconductor device can be mixed with each other, rather than forming the first part first and then forming the second part.

[0044] As described above, the present application will continue to be described below by taking the semiconductor device as a transistor as an example.

[0045] refer to Figure 2 As shown, an ion implantation process is used to form a well region 121 and a first high-concentration implantation region 122 in the low-doped epitaxial layer 120 of the first region 101. The well region 121 and the first high-concentration implantation region 122 have the same doping type and are opposite to the doping type of the low-doped epitaxial layer 120, for example, P-type. The well region 121 and the first high-concentration implantation region 122 belong to the first part of the semiconductor device.

[0046] In the technical solution of the present application, the structure of the first part of the semiconductor device is the same as the conventional structure, and the focus is on improving the second part of the semiconductor device and placing it in the second area. Therefore, the first part of the semiconductor device is only briefly described in this application, and the second part of the semiconductor device is described in detail. Therefore, the detailed structure and process of the well region 121 and the first high-concentration injection region 122 are not described here. Similar situations will not be described separately in the following text.

[0047] refer to Figure 3 As shown, a groove 130 is formed in the second region 102 to penetrate the low-doped epitaxial layer 120 and expose the highly-doped epitaxial layer 110. In some embodiments of the present application, the angle between the sidewall and the bottom surface of the groove 130 may be a right angle or an obtuse angle. When the angle between the sidewall and the bottom surface of the groove 130 is an obtuse angle, it is convenient for subsequent ion implantation to form a highly-doped contact layer in the low-doped epitaxial layer on the sidewall of the groove.

[0048] refer to Figure 4 As shown, a highly doped contact layer 140 is formed in the low-doped epitaxial layer 120 on the sidewall of the trench 130 by an ion implantation process, and a second high-concentration implantation region 123 is formed in the well region 121. The highly doped contact layer 140 and the second high-concentration implantation region 123 may be formed simultaneously or separately. The highly doped contact layer 140 belongs to the second part of the semiconductor device, and the second high-concentration implantation region 123 belongs to the first part of the semiconductor device.

[0049] In some embodiments of the present application, the doping type of the highly doped contact layer 140 is N-type, and the doping concentration is 1E18 to 1E21 cm -3 .

[0050] In some embodiments of the present application, after forming the highly doped contact layer 140 and the second high concentration implantation region 123 , a high temperature annealing process is performed on the semiconductor structure to activate all doping ions.

[0051] refer to Figure 5 As shown, a field oxide 124 covering the first high-concentration injection region 122 and a gate structure 125 partially covering the adjacent second high-concentration injection region 123 are formed in the first region 101. The field oxide 124 and the gate structure 125 belong to the first part of the semiconductor device and are not described in detail here. The gate structure 125 may include, for example, a gate dielectric layer, a gate layer, and a sidewall. An interlayer dielectric layer (omitted here) is also formed on the top surface and sidewalls of the gate structure 125.

[0052] refer to Figure 6As shown, an ohmic contact layer 150 is formed on the surface of the highly doped epitaxial layer 110 at the bottom of the trench 130 , the surface of the highly doped contact layer 140 on the sidewall of the trench 130 , and the surface of the well region 121 and the second high concentration implantation region 123 .

[0053] In some embodiments of the present application, the material of the ohmic contact layer 150 includes any one or more of Ni, AlNi and TiAl.

[0054] refer to Figure 7 As shown, a conductive layer 160 is formed in the trench 130 to fill the trench 130 and electrically connect the ohmic contact layer 150 . The conductive layer 160 also covers the field oxide 124 and the gate structure 125 and is electrically connected to the ohmic contact layer 150 in the first region 101 .

[0055] In some embodiments of the present application, the material of the conductive layer 160 includes any one or more of aluminum, copper, and aluminum-copper alloy.

[0056] refer to Figure 8 As shown, an isolation structure 170 penetrating the conductive layer 160 is formed above the field oxide 124. The isolation structure 170 may also partially extend to the surface of the conductive layer 160.

[0057] In some embodiments of the present application, the material of the isolation structure 170 includes polyimide.

[0058] refer to Figure 8 As shown, in the technical solution of the present application, the first part of the semiconductor device includes a well region 121, a first high-concentration doped region 122, a second high-concentration doped region 123, an ohmic contact layer 150, a gate structure 125, a field oxide 124 and a conductive layer 160 located in the first region 101, which includes a gate portion (gate structure 125) and a source portion (the conductive layer 160 of the first region 101 is used as a source contact). The second part of the semiconductor device includes a high-doped contact layer 140, an ohmic contact layer 150 and a conductive layer 160 located in the second region 102, which includes a drain portion (the conductive layer 160 of the second region 102 is used as a drain contact).

[0059] refer to Fig. 9 As shown, in some embodiments of the present application, the semiconductor substrate 100 further includes a second surface opposite to the first surface, and the method for forming the semiconductor structure further includes: forming a heat dissipation structure 180 on the second surface.

[0060] In some embodiments of the present application, the heat dissipation structure 180 includes: a heat dissipation metal layer (Thermal Contact Metal) or thermal conductive silicone grease.

[0061] Compared with housing, molding and smart p2 packaging technologies, the technical solution of the present application can have low power loop parasitic inductance and low gate loop parasitic inductance.

[0062] Compared with traditional packaging technology, the technical solution of the present application can save costs and reduce thickness because it does not have a substrate, solder and base plate, and has low thermal conductivity and high PC cycle capability.

[0063] Compared with the simple chip process, the technical solution of the present application does not require thinning of the substrate, saves costs, and has a low substrate resistivity.

[0064] Fig.10 Schematic diagram of the semiconductor structure described in some other embodiments of the present application. Fig.10 The embodiment shown is Fig. 9 The difference between the illustrated embodiments mainly lies in the second portion of the semiconductor device in the second region, while the remaining structures are similar or identical.

[0065] refer to Fig.10 As shown, in some other embodiments of the present application, the method for forming the second part of the semiconductor device in the low-doped epitaxial layer 120 of the second region 102 includes: forming a highly doped contact layer 140 in the second region 102 that penetrates the low-doped epitaxial layer 120 and is electrically connected to the highly doped epitaxial layer 110; and forming a conductive layer 160 on the top surface of the highly doped contact layer 140 that is electrically connected to the highly doped contact layer 140.

[0066] In addition, Fig. 9 The difference of the illustrated embodiment is that the conductive layer 160 in the first region 101 is formed separately, and is not formed together with the conductive layer 160 in the second region 102. The field oxide 124 and the isolation structure 170 also cover the second region 102.

[0067] Fig.11 Schematic diagram of the semiconductor structure described in some other embodiments of the present application. Fig.11 The embodiment shown is Fig.10 The difference between the illustrated embodiment mainly lies in that an ohmic contact layer 150 is formed in the highly doped contact layer 140 and penetrates the highly doped contact layer 140 to electrically connect the highly doped epitaxial layer 110 .

[0068] refer to Fig.11As shown, in some other embodiments of the present application, the method for forming the second part of the semiconductor device in the low-doped epitaxial layer 120 of the second region 102 includes: forming a highly doped contact layer 140 in the second region 102 and passing through the low-doped epitaxial layer 120 to electrically connect to the highly doped epitaxial layer 110; forming an ohmic contact layer 150 in the highly doped contact layer 140 and passing through the highly doped contact layer 140 and electrically connecting to the highly doped epitaxial layer 110; and forming a conductive layer 160 on the top surfaces of the ohmic contact layer 150 and the highly doped contact layer 140 and electrically connecting the ohmic contact layer 150 and the highly doped contact layer 140.

[0069] Fig.12 Schematic diagram of the semiconductor structure described in some other embodiments of the present application. Fig.12 The embodiment shown is Fig.10 The difference between the illustrated embodiment mainly lies in that the highly doped contact layer 140 is eliminated, and the conductive layer 160 penetrates the low doped epitaxial layer 120 and directly electrically connects the highly doped epitaxial layer 110 .

[0070] refer to Fig.12 As shown, in some other embodiments of the present application, the method for forming the second part of the semiconductor device in the low-doped epitaxial layer 110 of the second region 102 includes: forming a conductive layer 160 in the second region 102 that penetrates the low-doped epitaxial layer 120 and electrically connects the high-doped epitaxial layer 110.

[0071] In the above embodiments of the present application, various structures are designed to realize the electrical connection of the conductive layer 160 to the low-doped epitaxial layer 120 and the high-doped epitaxial layer 110 while the structure of the first region 101 remains basically unchanged.

[0072] The present application provides a method for forming a semiconductor structure, which can improve the device reliability and device performance of existing silicon carbide devices.

[0073] Some embodiments of the present application also provide a semiconductor structure, referring to Fig. 9 As shown, it includes: a semiconductor substrate 100, a first surface of which is sequentially formed with a highly doped epitaxial layer 110 and a low doped epitaxial layer 120, and the semiconductor substrate 100 includes a first region 101 and a second region 102; a first part of the semiconductor device is located on the low doped epitaxial layer 120 of the first region 101 and takes the low doped epitaxial layer 120 of the first region 101 as a channel; a second part of the semiconductor device is located in the low doped epitaxial layer 120 of the second region 102, and the second part of the semiconductor device penetrates the low doped epitaxial layer 120 and is electrically connected to the highly doped epitaxial layer 110.

[0074] In some embodiments of the present application, the material of the semiconductor substrate 100 includes undoped silicon carbide, the material of the highly doped epitaxial layer 110 includes doped silicon carbide, and the material of the low doped epitaxial layer 120 includes doped silicon carbide. The highly doped epitaxial layer 110 and the low doped epitaxial layer 120 have the same doping type, for example, N-type.

[0075] In some embodiments of the present application, the doping concentration of the highly doped epitaxial layer 110 is greater than the doping concentration of the low doped epitaxial layer 120, and the doping concentration of the highly doped epitaxial layer 110 is 1E18 to 1E21 cm -3 The doping concentration of the low-doped epitaxial layer 120 is 1E16 to 3E19 cm -3 .

[0076] In some embodiments of the present application, the thickness of the semiconductor substrate 100 is 2-200 microns, the thickness of the highly doped epitaxial layer 110 is 2-200 microns, and the thickness of the low doped epitaxial layer 120 is 2-200 microns.

[0077] In some embodiments of the present application, the method for sequentially forming the highly doped epitaxial layer 110 and the low doped epitaxial layer 120 on the first surface of the semiconductor substrate 100 includes: performing a first in-situ doping epitaxial growth process to form the highly doped epitaxial layer 110 on the first surface of the semiconductor substrate 100; performing a second in-situ doping epitaxial growth process to form the low doped epitaxial layer 120 on the surface of the highly doped epitaxial layer 110. The concentration of the doping source gas in the second in-situ doping epitaxial growth process is lower than the concentration of the doping source gas in the first in-situ doping epitaxial growth process.

[0078] In some embodiments of the present application, the first region 101 includes a core device region and a protection region located around the core device region, and the second region 102 includes a dicing region.

[0079] It should be noted that the technical solution of the present application does not limit the specific type of semiconductor device. The semiconductor device described in the present application is, for example, any one or more of a diode, a transistor (MOSFET), an IGBT, and a HMET. Therefore, the specific structure of the first part of the semiconductor device and the second part of the semiconductor device varies according to the type of semiconductor device. For example, when the semiconductor device is a transistor, the first part of the semiconductor device includes a source portion and a gate portion, and the second part of the semiconductor device includes a drain portion. When the semiconductor device is a diode, the first part of the semiconductor device includes an anode, and the second part of the semiconductor device includes a cathode. When the semiconductor device is an IGBT, the first part of the semiconductor device includes an emitter portion and a gate portion, and the second part of the semiconductor device includes a collector portion. When the semiconductor device is an HMET, the first part of the semiconductor device includes a source portion and a gate portion, and the second part of the semiconductor device includes a drain portion. The basic structure and manufacturing process of semiconductor devices such as diodes, transistors (MOSFET), IGBTs, and HMETs may be known to those skilled in the art. This application is only explained using transistors as examples. Those skilled in the art should be able to understand the structures and processes of other semiconductor devices in the technical solutions of this application based on the examples of transistors disclosed in this application.

[0080] refer to Fig. 9 As shown, in the technical solution of the present application, the first part of the semiconductor device includes a well region 121 located in the first region 101, a first high-concentration doped region 122, a second high-concentration doped region 123, an ohmic contact layer 150, a gate structure 125, a field oxide 124 and a conductive layer 160, which includes a gate portion (gate structure 125) and a source portion (the conductive layer 160 of the first region 101 serves as a source contact).

[0081] refer to Fig. 9 As shown, in some embodiments of the present application, the second part of the semiconductor device includes: a groove of the low-doped epitaxial layer 120 that penetrates the second region 102 and exposes the high-doped epitaxial layer 110; a high-doped contact layer 140 located in the low-doped epitaxial layer 120 on the sidewall of the groove; an ohmic contact layer 150 located on the surface of the high-doped epitaxial layer 110 at the bottom of the groove and the high-doped contact layer 140 on the sidewall of the groove; and a conductive layer 160 located in the groove, filling the groove and electrically connecting the ohmic contact layer 150.

[0082] In some embodiments of the present application, the well region 121 and the first high-concentration implantation region 122 have the same doping type, and are opposite to the doping type of the low-doped epitaxial layer 120 , for example, P type.

[0083] In some embodiments of the present application, the doping type of the highly doped contact layer 140 is N-type, and the doping concentration is 1E18 to 1E21 cm -3 .

[0084] In some embodiments of the present application, the material of the ohmic contact layer 150 includes any one or more of Ni, AlNi and TiAl.

[0085] In some embodiments of the present application, the conductive layer 160 further covers the field oxide 124 and the gate structure 125 and is electrically connected to the ohmic contact layer 150 in the first region 101 .

[0086] In some embodiments of the present application, the material of the conductive layer 160 includes any one or more of aluminum, copper, and aluminum-copper alloy.

[0087] refer to Fig. 9 As shown, an isolation structure 170 penetrating the conductive layer 160 is formed above the field oxide 124. The isolation structure 170 may also partially extend to the surface of the conductive layer 160.

[0088] In some embodiments of the present application, the material of the isolation structure 170 includes polyimide.

[0089] refer to Fig. 9 As shown, in some embodiments of the present application, the semiconductor substrate 100 further includes a second surface opposite to the first surface, and the semiconductor structure further includes: a heat dissipation structure 180 located on the second surface.

[0090] In some embodiments of the present application, the heat dissipation structure 180 includes: a heat dissipation metal layer or thermal conductive silicone grease.

[0091] Compared with housing, molding and smart p2 packaging technologies, the technical solution of the present application can have low power loop parasitic inductance and low gate loop parasitic inductance.

[0092] Compared with traditional packaging technology, the technical solution of the present application can save costs and reduce thickness because it does not have a substrate, solder and base plate, and has low thermal conductivity and high PC cycle capability.

[0093] Compared with the simple chip process, the technical solution of the present application does not require thinning of the substrate, saves costs, and has a low substrate resistivity.

[0094] refer to Fig.10As shown, in some other embodiments of the present application, the second part of the semiconductor device includes: a highly doped contact layer 140 that runs through the low-doped epitaxial layer 120 in the second region 102 and is electrically connected to the highly doped epitaxial layer 110; and a conductive layer 160 that is located on the top surface of the highly doped contact layer 140 and is electrically connected to the highly doped contact layer 140.

[0095] refer to Fig.11 As shown, in some other embodiments of the present application, the second part of the semiconductor device includes: a highly doped contact layer 140 that passes through the low-doped epitaxial layer 120 in the second region 102 and electrically connects the highly doped epitaxial layer 110; an ohmic contact layer 150 that passes through the highly doped contact layer 140 and electrically connects the highly doped epitaxial layer 110; and a conductive layer 160 that is located on the top surfaces of the ohmic contact layer 150 and the highly doped contact layer 140 and electrically connects the ohmic contact layer 150 and the highly doped contact layer 140.

[0096] refer to Fig.12 As shown, in some other embodiments of the present application, the second portion of the semiconductor device includes: a conductive layer 160 that penetrates the low-doped epitaxial layer 120 in the second region 102 and electrically connects the high-doped epitaxial layer 110 .

[0097] In the above embodiments of the present application, various structures are designed to realize the electrical connection of the conductive layer 160 to the low-doped epitaxial layer 120 and the high-doped epitaxial layer 110 while the structure of the first region 101 remains basically unchanged.

[0098] The present application provides a semiconductor structure and a method for forming the same, which can improve the device reliability and device performance of existing silicon carbide devices.

[0099] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0100] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there are no intermediate elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0101] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0102] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein a high-doped epitaxial layer and a low-doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, and the semiconductor substrate includes a first region and a second region; Forming a first part of a semiconductor device on the low-doped epitaxial layer in the first region using the low-doped epitaxial layer in the first region as a channel; A second portion of the semiconductor device is formed in the low-doped epitaxial layer in the second region, and the second portion of the semiconductor device penetrates the low-doped epitaxial layer and is electrically connected to the high-doped epitaxial layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a second portion of the semiconductor device in the low-doped epitaxial layer of the second region comprises: forming a trench in the second region penetrating the low-doped epitaxial layer and exposing the high-doped epitaxial layer; forming a highly doped contact layer in the low-doped epitaxial layer on the sidewall of the trench; Forming an ohmic contact layer on the surface of the highly doped epitaxial layer at the bottom of the trench and the highly doped contact layer on the sidewall of the trench; A conductive layer is formed in the trench to fill the trench and electrically connect the ohmic contact layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a second portion of the semiconductor device in the low-doped epitaxial layer of the second region comprises: forming a highly doped contact layer in the second region, penetrating the low doped epitaxial layer and electrically connecting the highly doped epitaxial layer; A conductive layer electrically connected to the highly doped contact layer is formed on a top surface of the highly doped contact layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a second portion of the semiconductor device in the low-doped epitaxial layer of the second region comprises: forming a highly doped contact layer in the second region, penetrating the low doped epitaxial layer and electrically connecting the highly doped epitaxial layer; forming an ohmic contact layer in the highly doped contact layer and penetrating through the highly doped contact layer to electrically connect to the highly doped epitaxial layer; A conductive layer electrically connecting the ohmic contact layer and the highly doped contact layer is formed on the top surfaces of the ohmic contact layer and the highly doped contact layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming a second portion of the semiconductor device in the low-doped epitaxial layer of the second region comprises: A conductive layer is formed in the second region, penetrating the low-doped epitaxial layer and electrically connecting the high-doped epitaxial layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The semiconductor substrate further includes a second surface opposite to the first surface, and the method for forming the semiconductor structure further includes: forming a heat dissipation structure on the second surface.

7. The method for forming a semiconductor structure according to claim 6, wherein: The heat dissipation structure includes: a heat dissipation metal layer or a thermal conductive silicone grease.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the semiconductor substrate includes undoped silicon carbide, the material of the highly doped epitaxial layer includes doped silicon carbide, and the material of the low doped epitaxial layer includes doped silicon carbide.

9. The method for forming a semiconductor structure according to claim 9, wherein: The doping concentration of the highly doped epitaxial layer is greater than the doping concentration of the low doped epitaxial layer, and the doping concentration of the highly doped epitaxial layer is 1E18 to 1E21 cm -3 The doping concentration of the low-doped epitaxial layer is 1E16 to 3E19 cm -3 .

10. The method for forming a semiconductor structure according to claim 1, wherein: The first area includes a core device area and a protection area located around the core device area, and the second area includes a dicing area.

11. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein a high-doped epitaxial layer and a low-doped epitaxial layer are sequentially formed on a first surface of the semiconductor substrate, and the semiconductor substrate includes a first region and a second region; A first part of the semiconductor device is located on the low-doped epitaxial layer in the first region and uses the low-doped epitaxial layer in the first region as a channel; The second part of the semiconductor device is located in the low-doped epitaxial layer of the second region. The second part of the semiconductor device penetrates the low-doped epitaxial layer and is electrically connected to the high-doped epitaxial layer.

12. The semiconductor structure according to claim 11, wherein: The second part of the semiconductor device comprises: A trench penetrating the low-doped epitaxial layer in the second region and exposing the high-doped epitaxial layer; a highly doped contact layer in the low doped epitaxial layer on the sidewall of the trench; an ohmic contact layer located at the surface of the highly doped epitaxial layer at the bottom of the trench and the highly doped contact layer on the sidewall of the trench; A conductive layer is located in the trench, fills the trench and is electrically connected to the ohmic contact layer.

13. The semiconductor structure according to claim 11, wherein: The second part of the semiconductor device comprises: The low-doped epitaxial layer that runs through the second region is electrically connected to the high-doped contact layer of the high-doped epitaxial layer; A conductive layer is located on a top surface of the highly doped contact layer and is electrically connected to the highly doped contact layer.

14. The semiconductor structure according to claim 11, wherein: The second part of the semiconductor device comprises: The low-doped epitaxial layer that runs through the second region is electrically connected to the high-doped contact layer of the high-doped epitaxial layer; An ohmic contact layer that penetrates the highly doped contact layer and is electrically connected to the highly doped epitaxial layer; A conductive layer is located on the top surfaces of the ohmic contact layer and the highly doped contact layer and electrically connects the ohmic contact layer and the highly doped contact layer.

15. The semiconductor structure according to claim 11, wherein: The second part of the semiconductor device comprises: The low-doped epitaxial layer that passes through the second region is electrically connected to the conductive layer of the high-doped epitaxial layer.

16. The semiconductor structure according to claim 11, wherein: The semiconductor substrate further includes a second surface opposite to the first surface, and the semiconductor structure further includes: a heat dissipation structure located on the second surface.

17. The semiconductor structure according to claim 16, wherein: The heat dissipation structure includes: a heat dissipation metal layer or a thermal conductive silicone grease.

18. The semiconductor structure according to claim 11, wherein: The material of the semiconductor substrate includes undoped silicon carbide, the material of the highly doped epitaxial layer includes doped silicon carbide, and the material of the low doped epitaxial layer includes doped silicon carbide.

19. The semiconductor structure according to claim 19, wherein: The doping concentration of the highly doped epitaxial layer is greater than the doping concentration of the low doped epitaxial layer, and the doping concentration of the highly doped epitaxial layer is 1E18 to 1E21 cm -3 The doping concentration of the low-doped epitaxial layer is 1E16 to 3E19 cm -3 .

20. The semiconductor structure according to claim 11, wherein: The first area includes a core device area and a protection area located around the core device area, and the second area includes a dicing area.

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