Fault diagnosis method of ultrasonic equipment and ultrasonic equipment

Abstract

The invention discloses a fault diagnosis method for ultrasonic equipment and the ultrasonic equipment, and the method comprises the steps: starting a first timer after determining the execution of first-stage monitoring, the timing duration of the first timer being the time of N frames of images, and N being a positive integer; during the operation period of the first timer, receiving radio frequency (RF) data frames, and adding one to the number of the received frames after the RF data frames are received each time; after the first timer reaches the timing duration, judging whether the number of received frames is greater than or equal to N; if yes, determining that the ultrasonic equipment has no fault, and entering a normal use interface; and if not, executing secondary monitoring, and determining a fault code according to a secondary monitoring result. Through the method, the ultrasonic equipment can accurately report the fault code on the premise that a hardware circuit of the ultrasonic equipment is not changed and professional instruments are not used, so that the fault diagnosis of the ultrasonic equipment is more efficient and convenient, and the maintenance cost of the equipment is reduced.

Description

Technical Field

[0001] The present invention relates to the field of ultrasonic technology, and in particular to a fault diagnosis method for ultrasonic equipment and ultrasonic equipment. Background Art

[0002] Medical ultrasound imaging equipment mainly uses ultrasonic pulse echo technology, which uses ultrasonic waves to irradiate the human body, which is then reflected, refracted and scattered in the human body. The echoes carrying information are then received and processed to obtain an image of the human tissue structure.

[0003] During the life cycle of ultrasound equipment, some boards and cards often malfunction during long-term use due to changes in the temperature and humidity of the working environment, resulting in reduced working performance and problems with ultrasound images, such as no image displayed on the interface after startup, abnormal image frame rate, white lines, dark lines in the image, and other problems.

[0004] Without the help of professional instruments such as oscilloscopes and logic analyzers, it is impossible to initially locate the cause. We can only wait for professional maintenance personnel to disassemble the machine, locate the cause of the problem, and then perform fault repairs, which wastes a lot of time. Summary of the invention

[0005] In an exemplary embodiment of the present invention, a fault diagnosis method for an ultrasonic device and an ultrasonic device are provided to provide an efficient and convenient fault diagnosis solution for the ultrasonic device.

[0006] In a first aspect, an embodiment of the present invention provides a fault diagnosis method for an ultrasonic device, comprising:

[0007] After determining to start executing the first-level monitoring, start a first timer, the timing duration of the first timer is the time of N frames of images, and N is a positive integer;

[0008] During the operation of the first timer, receiving radio frequency (RF) data frames, and increasing the number of received frames by one after each completion of receiving the RF data frames;

[0009] After the first timer reaches the timing duration, determining whether the number of received frames is greater than or equal to N;

[0010] If the conditions are met, it is determined that the ultrasonic device has no faults and the normal use interface is entered; if the conditions are not met, secondary monitoring is performed and the fault code is determined based on the secondary monitoring results.

[0011] Optionally, when performing the secondary monitoring, the method includes:

[0012] Sending a start instruction to each field programmable gate array FPGA controller, wherein the start instruction is used to instruct each FPGA controller to perform secondary monitoring;

[0013] Starting a second timer, and monitoring the scanning timing of each FPGA controller and the synchronization between the multiple FPGA controllers in real time within the timing duration corresponding to the second timer;

[0014] After determining that a monitoring anomaly has occurred, different anomalies are encoded and the fault codes are reported in real time.

[0015] Optionally, starting the second timer and monitoring the scanning timing of each FPGA controller and the synchronization between the multiple FPGA controllers in real time within the timing duration corresponding to the second timer includes:

[0016] Obtain scan timing analysis results of each FPGA logic controller;

[0017] Compare the scan timing analysis result with the scan setting time of the current line, and output the judgment result in real time;

[0018] If the result is correct, continue to determine the synchronization between multiple FPGA controllers; if the result is wrong, report the first fault code, which is used to report a fault error including the scan control timing of each FPGA controller.

[0019] Optionally, if the result is correct, continuing to determine the synchronization between the multiple FPGA controllers includes:

[0020] Obtaining the scan timing synchronization signal analysis and comparison results in multiple FPGA logic controllers;

[0021] If the result is correct, continue to determine whether the second timer has reached the set monitoring time; if the result is wrong, report the second fault code, which is used to report fault errors of single or multiple FPGA controller scanning control synchronization errors.

[0022] Optionally, if the result is correct, continuing to determine whether the second timer reaches a set monitoring time includes:

[0023] If the second timer reaches the set monitoring time, the scanning timing and synchronization are reported to be fault-free and no scanning fault is detected; if the second timer does not reach the set monitoring time, the secondary monitoring continues.

[0024] Optionally, the timing duration of the second timer is a default duration, or the timing duration of the second timer is determined according to a specified time sent by the client.

[0025] Optionally, the method further includes: displaying a corresponding fault code on a software interface of the ultrasound device.

[0026] In a second aspect, an embodiment of the present invention provides an ultrasound device, the device comprising a processor, a controller and a monitoring module;

[0027] The processor is used to start a first timer after determining to start executing the first-level monitoring, wherein the timing duration of the first timer is the time of N frames of images, where N is a positive integer; during the operation of the first timer, receive radio frequency RF data frames, and after each completion of RF data frame reception, increase the number of received frames by one; after the first timer reaches the timing duration, determine whether the number of received frames is greater than or equal to N; if satisfied, determine that the ultrasound device has no faults and enter the normal use interface; if not satisfied, proceed to the next level of monitoring;

[0028] The monitoring module is used to monitor the scanning timing of the controller and the synchronization between the controllers in real time during the operation time of the second timer, and report the corresponding monitoring results in real time.

[0029] As an example, in actual application, the processor may be ultrasound system host computer software.

[0030] Optionally, the controller includes a main FPGA controller, a transmitting FPGA controller and a receiving FPGA controller;

[0031] The monitoring module includes a status monitoring module and a synchronization monitoring module;

[0032] The state monitoring module is used to compare and monitor the scan timing generated in the main FPGA controller, the transmitting FPGA controller and the receiving FPGA controller with the actually set scan timing during the operation time of the second timer, and report the scan timing monitoring result;

[0033] The synchronization monitoring module is used to perform synchronization comparison monitoring on the synchronization signals generated by the main FPGA controller, the transmitting FPGA controller and the receiving FPGA controller during the operation time of the second timer, and report the synchronization monitoring result.

[0034] Optionally, the main FPGA controller further includes a front-end fault analysis module, a front-end fault processing module, and a fault reporting module;

[0035] The front-end fault analysis module aggregates the data of the status monitoring modules corresponding to each FPGA controller and the synchronization monitoring module, encodes different abnormal monitoring results, and generates corresponding fault codes;

[0036] The fault reporting module is used to report the fault code corresponding to the abnormal monitoring result to the processor;

[0037] The front-end fault processing module is used to perform fault processing on the target fault code.

[0038] Optionally, the fault handling includes stopping transmission and scanning, resetting and restarting scanning, and turning off voltage.

[0039] Optionally, the device includes three status monitoring modules, which are respectively located in the main FPGA controller, the transmitting FPGA controller and the receiving FPGA controller;

[0040] The synchronization monitoring module is located in the main FPGA controller.

[0041] Optionally, the processor includes an uploaded data monitoring module, a fault analysis module, a fault processing module and a data receiving module;

[0042] The uploaded data monitoring module is used to determine that after the first level monitoring is started, the first timer is started, and the timing duration of the first timer is the time of N frames of images, where N is a positive integer; during the operation of the first timer, the radio frequency RF data frame is received, and after each completion of the RF data frame reception, the number of received frames is increased by one; after the first timer reaches the timing duration, it is determined whether the number of received frames is greater than or equal to N; if satisfied, it is determined that the ultrasound device has no fault and enters the normal use interface; if not satisfied, the next level of monitoring is performed;

[0043] The data receiving module is used to receive the front-end ultrasonic data transmitted by the controller;

[0044] The fault analysis module is used to analyze and judge according to the information of the uploaded data monitoring module and the fault reporting module, and determine the fault code corresponding to the abnormal monitoring result;

[0045] The fault processing module is used to record and display the fault code output by the fault analysis module.

[0046] Optionally, the device further comprises a display screen;

[0047] The display screen is used to display corresponding fault codes.

[0048] In a third aspect, an embodiment of the present invention further provides an ultrasonic device, comprising:

[0049] A determination module, used for starting a first timer after determining to start the first-level monitoring, wherein the timing duration of the first timer is the time of N frames of images, where N is a positive integer;

[0050] A transceiver module, used for receiving radio frequency (RF) data frames during the operation of the first timer, and adding one to the number of received frames after each completion of RF data frame reception;

[0051] The processing module is used to determine whether the number of received frames is greater than or equal to N after the first timer reaches the timing duration; if satisfied, determine that the ultrasonic device has no fault and enter the normal use interface; if not satisfied, perform secondary monitoring and determine the fault code according to the secondary monitoring result.

[0052] In a fourth aspect, the present application provides a computer-readable storage medium. When instructions in the computer-readable storage medium are executed by an electronic device, the electronic device is enabled to perform the fault diagnosis method of the ultrasonic device as described in the first aspect above.

[0053] In a fifth aspect, the present application provides a computer program product, including a computer program:

[0054] When the computer program is executed by a processor, the fault diagnosis method for an ultrasonic device as described in the first aspect above is implemented.

[0055] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0056] Since the embodiment of the present application improves the ultrasonic equipment and enables the real-time monitoring function in the ultrasonic system host software, the ultrasonic equipment can perform primary monitoring and secondary monitoring. Without changing the hardware circuit of the ultrasonic equipment, the real-time monitoring function is enabled in the ultrasonic system host software without the aid of professional instruments such as oscilloscopes and logic analyzers. When a problem occurs, the timing correctness and synchronization of the scanning cycles of each FPGA controller are monitored to determine whether the fault is caused by the failure to upload RF data in a package, incorrect control timing logic, or incorrect synchronization. The faulty board can be specifically located and the fault code can be accurately reported, providing users or maintainers with more convenient and accurate fault location, improving the testability and maintainability of the system, and reducing equipment maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0058] Figure 1 The internal structure diagram of an ultrasonic device in the prior art is exemplarily shown;

[0059] Figure 2 A schematic diagram of an ultrasound device system provided by an embodiment of the present application is exemplarily shown;

[0060] Figure 3The schematic diagram of the structure of the internal components of the first ultrasonic device provided in the embodiment of the present application is exemplarily shown;

[0061] Figure 4 The schematic diagram of the internal components structure of the second ultrasonic device provided in the embodiment of the present application is exemplarily shown;

[0062] Figure 5 The schematic diagram of the internal components structure of the third ultrasonic device provided in the embodiment of the present application is exemplarily shown;

[0063] Figure 6 The schematic diagram of the internal components structure of the fourth ultrasonic device provided in the embodiment of the present application is exemplarily shown;

[0064] Figure 7 The schematic diagram of the principle framework of an ultrasound device provided in an embodiment of the present application is exemplarily shown;

[0065] Figure 8 A schematic diagram of a method for diagnosing a fault of an ultrasonic device provided in an embodiment of the present application is exemplarily shown;

[0066] Fig. 9 A schematic diagram of an ultrasound device software interface provided by an embodiment of the present application is exemplarily shown;

[0067] Fig.10 A schematic diagram of a fault diagnosis process of an ultrasonic device provided in an embodiment of the present application is exemplarily shown;

[0068] Fig.11 A schematic diagram of an ultrasonic device provided in an embodiment of the present application is exemplarily shown;

[0069] Fig.12 A schematic diagram of another ultrasonic device provided in an embodiment of the present application is exemplarily shown. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0071] Any number of elements in the drawings is for illustration and not limitation, and any naming is for distinction only and does not have any limiting meaning.

[0072] In the specific practice process, Figure 1As shown in the figure, the current ultrasound equipment is mainly composed of array transducer, ultrasound signal transmitting circuit, ultrasound signal receiving circuit, FPGA controller and ultrasound system host computer software. Among them, the FPGA controller plays a core role in the entire ultrasound equipment and is mainly responsible for three tasks: first, the scanning control module of the transmitting FPGA controller generates the transmitting control signal in the scanning sequence, controls the corresponding transmitting channel in the transmitting circuit to generate the delay and transmitting waveform of the transmitting signal; second, the scanning control module of the transmitting FPGA controller generates the receiving control signal in the scanning sequence, controls the corresponding analog receiving channel in the receiving circuit to complete the analog-to-digital sampling, beam synthesis and data upload of the echo signal; third, the scanning control module of the main control FPGA controller distributes the parameters of the ultrasound line scanning to the transmitting FPGA controller and the receiving FPGA controller through the synchronization control signal in the scanning sequence, and processes the beam synthesis data of multiple channels and uploads the data.

[0073] In the related art, in the ultrasonic equipment, all the transmitting FPGA controllers, receiving FPGA controllers and main control FPGA controllers have scanning control modules, which need to be fully synchronized and run under the correct timing parameters to ensure that the transmitting signal transmitting circuit of the ultrasonic equipment generates the correct focused beam energy to be transmitted through the array transducer, and at the same time control the ultrasonic signal receiving circuit to receive the reflected beam energy, and obtain the correct echo beam data after beam synthesis, and the ultrasonic system host computer software interface displays the correct ultrasonic image. No matter which FPGA controller generates inaccurate scanning timing or the scanning timing generated by multiple controllers is not synchronized, it will cause abnormal problems such as no data display and image confusion on the ultrasonic image display interface. Without the help of professional instruments such as oscilloscopes and logic analyzers, it is impossible to initially locate the cause, and can only wait for professional maintenance personnel to disassemble the machine, locate the cause of the problem, and then perform fault repair, which delays a lot of time.

[0074] In order to solve the problem without disassembling the machine and without the help of professional instruments such as oscilloscopes and logic analyzers, this application uses ultrasonic software to enable real-time monitoring. By monitoring the number of uploaded data frames and the scanning timing operation of each FPGA controller, it is possible to locate whether the board failure is caused by a certain FPGA control timing error, and locate the specific board. The manufacturer can solve the problem by simply replacing the board, which greatly saves maintenance time and reduces maintenance costs.

[0075] After introducing the design ideas of the embodiments of the present application, the following briefly introduces the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In specific implementation, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.

[0076] Figure 2 The system architecture of an ultrasonic equipment fault diagnosis applicable to an embodiment of the present invention is exemplarily shown, and the system architecture may include an ultrasonic system host computer software 100, a main control field programmable gate array (FPGA) controller 200, a transmitting FPGA controller 300 and a receiving FPGA controller 400.

[0077] The ultrasound system host computer software 100 is used to perform primary monitoring of the ultrasound equipment.

[0078] Specifically, when the ultrasound system host computer software performs the first-level monitoring, the monitoring time is the time of N frames of images.

[0079] As an optional method, the time of one frame of image in the embodiment of the present application is calculated by the frame rate, number of scanning lines and number of beams of the current ultrasound scene.

[0080] Each FPGA controller is used to perform secondary monitoring of the ultrasound equipment.

[0081] Specifically, the secondary monitoring described in the embodiment of the present application is performed in each FPGA controller, and the scanning timing of each FPGA controller and the synchronization between multiple FPGA controllers are monitored in real time within a preset monitoring time. When a monitoring abnormality occurs, different abnormalities are encoded and fault codes are reported in real time.

[0082] As an optional method, the preset monitoring time can be a default time, for example, it can default to the time of 2 frames of images; or the preset monitoring time can be a specified time sent by the PC, for example, the PC sends a specified time of 3 frames of images as the preset time.

[0083] like Figure 3 As shown, the ultrasound system host computer software 100 includes an uploaded data monitoring module 110 , a fault analysis module 120 , a fault processing module 130 , and a data receiving module 140 .

[0084] The uploaded data monitoring module 110 is used to calculate and determine the time for receiving N frames of image data based on the line scanning parameters, the number of lines in the frame and other information set in the current ultrasound scanning scene. After starting the real-time monitoring program, the frame header information in the RF data packet actually uploaded by the ultrasound front end is judged within this time. When a correct frame data packet is received, the frame count is increased by 1, and the frame count value and N are used to make a judgment. If the frame count value is greater than or equal to N, it is determined that the data flow is normal and there is no fault; if the frame count value is less than N, it is decided to perform the next level of monitoring and set the next level of monitoring time.

[0085] The fault analysis module 120 is used to analyze and judge according to the information of the RF data monitoring module and the fault reporting module, and form different fault codes to distinguish whether the FPGA controller and error event are abnormal or erroneous, so as to determine which board has a fault.

[0086] The fault processing module 130 is used to log and display the fault code output by the fault analysis module.

[0087] An optional method is to display a real-time monitoring fault code interface on the ultrasound system host computer software interface. Different fault codes represent different fault information. The display code of the fault code can be translated from the code given by the fault reporting module to form a fault code that only the manufacturer's maintenance personnel know, so that the manufacturer can provide preliminary maintenance positioning.

[0088] For example, the embodiment of the present application may further include a fault code list, which may be a fault type coding list obtained by synthesizing various abnormal states of the status monitoring module, the synchronization monitoring module, and the data monitoring module.

[0089] The data receiving module 140 is a module for receiving front-end ultrasound data transmitted from the FPGA, and is a module that conventional ultrasound equipment has.

[0090] like Figure 4 As shown, the main FPGA controller 200 includes a status monitoring module 210, a synchronization monitoring module 220, a front-end fault analysis module 230, a front-end fault processing module 240, a fault reporting module 250, a data upload module 260, a scanning control module 270, and a synchronous scanning module 280.

[0091] The status monitoring module 210 is used to analyze the scanning control timing generated in the FPGA controller within the set monitoring time, compare the analysis result with the scanning timing set in the actual ultrasound scanning scenario, determine whether the FPGA controller correctly generates the scanning control timing, and send the comparison result to the fault reporting module 250 in real time.

[0092] The synchronization monitoring module 220 is used to perform synchronization comparison monitoring on the synchronization signals generated by the receiving FPGA controller, the transmitting FPGA controller, and the main control FPGA controller within the set monitoring time, and send the comparison results to the fault reporting module in real time.

[0093] The front-end fault analysis module 230 is used to aggregate the data of each FPGA status monitoring module and the synchronization monitoring module, encode different monitoring results, and form different fault codes to distinguish whether the FPGA controller or error event is abnormal or erroneous, so as to determine which board has a fault.

[0094] The front-end fault processing module 240 is used to process the codes specified in the fault code list in real time in the FPGA, including but not limited to stopping transmission and scanning, resetting and restarting scanning, turning off voltage, etc.

[0095] The fault reporting module 250 is used to report the fault code of each FPGA fault analysis to the ultrasound system host computer software.

[0096] The data upload module 260 is a module used by FPGA to package and process the processed front-end ultrasound data and upload it to the ultrasound system host computer software. It is a module that conventional ultrasound equipment has.

[0097] The scanning control module 270 is used to generate a synchronous scanning start and stop signal for each FPGA controller by receiving the start or stop scanning mode instruction from the ultrasound system host computer software. It is a module that conventional ultrasound equipment has.

[0098] The synchronous scanning module 280 is a module used to generate a transmission and reception scanning timing in a unified time domain after receiving the synchronization signal of the scanning control module. It is a module that conventional ultrasound equipment has.

[0099] like Figure 5 As shown, the transmitting FPGA controller 300 includes a state monitoring module 310 and a synchronous scanning module 320 .

[0100] The status monitoring module 310 is used to analyze the scanning control timing generated in the FPGA controller within the set monitoring time, compare the analysis result with the scanning timing set in the actual ultrasound scanning scenario, determine whether the FPGA controller correctly generates the scanning control timing, and send the comparison result to the fault reporting module in real time.

[0101] The synchronous scanning module 320 is a module used to generate a transmission and reception scanning timing in a unified time domain after receiving the synchronization signal of the scanning control module. It is a module that conventional ultrasound equipment has.

[0102] like Figure 6 As shown, the receiving FPGA controller 400 includes a status monitoring module 410 and a synchronous scanning module 420.

[0103] The status monitoring module 410 is used to analyze the scanning control timing generated in the FPGA controller within the set monitoring time, compare the analysis result with the scanning timing set in the actual ultrasound scanning scenario, determine whether the FPGA controller correctly generates the scanning control timing, and send the comparison result to the fault reporting module in real time.

[0104] The synchronous scanning module 420 is a module used to generate a transmission and reception scanning timing in a unified time domain after receiving the synchronization signal of the scanning control module. It is a module that conventional ultrasound equipment has.

[0105] Furthermore, the embodiment of the present application adopts the above-mentioned ultrasonic equipment fault diagnosis system architecture, and the principle block diagram of real-time fault scanning and monitoring can be found in Figure 7 shown.

[0106] It should be noted that the above Figure 2 to Figure 7 The structure shown is only an example and is not limited to this embodiment of the present invention.

[0107] Please refer to Figure 8 , which is a flow chart of a fault diagnosis method for an ultrasonic device provided in an embodiment of the present application. Figure 8 The embodiment shown is applicable to Figures 2 to 7 Any of the application scenarios shown.

[0108] Step 801, after determining to start executing the first level monitoring, start the first timer, the timing duration of the first timer is the time of N frames of images, and N is a positive integer.

[0109] Step 802: During the operation of the first timer, RF data frames are received, and after each RF data frame reception is completed, the number of received frames is increased by one.

[0110] Step 803: After the first timer reaches the timing duration, determine whether the number of received frames is greater than or equal to N. If so, execute step 804; if not, execute step 805.

[0111] Step 804, determine that the ultrasound device has no faults and enter the normal use interface.

[0112] Step 805, performing secondary monitoring, and determining a fault code according to the secondary monitoring result.

[0113] Furthermore, the embodiment of the present application can notify each FPGA controller to perform secondary monitoring in the following manners, which are not limited to the following manners:

[0114] Mode 1: Sending a startup instruction to each field programmable gate array FPGA controller, wherein the startup instruction is used to instruct each FPGA controller to perform secondary monitoring.

[0115] Specifically, after the ultrasound system host computer software determines to perform the next level of monitoring, it sends the startup instruction to each FPGA controller. After receiving the startup instruction, each FPGA controller triggers to enter the second level of monitoring.

[0116] Method 2: Determine that the first timer has timed out.

[0117] In this mode 2, when it is determined that the first timer has timed out, each FPGA controller is automatically triggered to perform secondary monitoring.

[0118] As an optional method, after each FPGA controller in the embodiment of the present application determines to perform secondary monitoring, a second timer can be started to monitor the scanning timing of each FPGA controller and the synchronization between multiple FPGA controllers in real time within the timing duration corresponding to the second timer. When it is determined that a monitoring abnormality has occurred, different abnormalities are encoded and the fault code is reported in real time.

[0119] It can be understood that if the second timer reaches the set monitoring time, the scanning timing and synchronization are reported to be fault-free, and no scanning fault is detected; if the second timer does not reach the set monitoring time, the secondary monitoring continues.

[0120] As an optional method, the timing duration of the second timer is a default duration, for example, the timing duration of the second timer may be 2 frames; or, the timing duration of the second timer is determined according to the specified time sent by the client, for example, the specified time sent by the client is 3 frames, then the timing duration of the second timer is 3 frames.

[0121] The following are introduced based on different abnormal situations:

[0122] Abnormal situation 1: Fault error in the scan control timing of each FPGA controller.

[0123] Specifically, the scan timing analysis results of each FPGA logic controller are obtained; the scan timing analysis results are compared with the scan setting time of the current line, and the judgment result is output in real time.

[0124] If the result is correct, continue to determine the synchronization between multiple FPGA controllers; if the result is wrong, report a first fault code, which is used to report a fault error including the scan control timing of each FPGA controller.

[0125] Abnormal situation 2: Fault error of single or multiple FPGA controller scanning control synchronization error.

[0126] Specifically, the scan timing synchronization signal analysis and comparison results in multiple FPGA logic controllers are obtained.

[0127] Among them, if the result is correct, continue to determine whether the second timer reaches the set monitoring time; if the result is wrong, report the second fault code, and the second fault code is used to report the fault error of single or multiple FPGA controller scanning control synchronization errors.

[0128] It should be noted that the embodiments of the present application are not limited to the above two abnormalities. Any solution for determining abnormal conditions based on the concepts of the embodiments of the present application falls within the protection scope of the present application.

[0129] Furthermore, in the embodiment of the present application, after the fault code is determined, the first fault code may be reported, and the corresponding fault code may be displayed on the software interface of the ultrasound device.

[0130] For example, the ultrasound system host computer software interface is as follows: Fig. 9 As shown, the real-time monitoring function button in the interface can be clicked to issue a command to start the real-time monitoring function. The ultrasound system host computer software enters the real-time monitoring workflow and displays the summarized fault codes in the fault code display area.

[0131] In order to better explain the embodiments of the present invention, the fault diagnosis method of the ultrasonic equipment provided by the present application is described in detail based on specific embodiments.

[0132] Specifically, Fig.10 As shown, including:

[0133] Step 1001, the real-time monitoring function is started.

[0134] Step 1002, first-level monitoring timing accumulation.

[0135] Step 1003, the frame count is accumulated.

[0136] Step 1004, determine whether the first-level monitoring timing has arrived, if so, execute step 1005, if not, execute step 1002.

[0137] Step 1005, determine whether the frame count is greater than the application frame count, if so, execute step 1006, if not, execute step 1007.

[0138] Step 1006, report no fault.

[0139] Step 1007, proceed to the next level of monitoring.

[0140] Step 1008, secondary monitoring is accumulated regularly.

[0141] Step 1009, determine whether each state monitoring has an error, if so, execute step 1010, if not, execute step 1011.

[0142] Step 1010, reporting fault 1.

[0143] Step 1011, determine whether there is a synchronization error, if so, execute step 1012, if not, execute step 1013.

[0144] Step 1012, report fault 2.

[0145] Step 1013, determine whether the secondary monitoring timing has arrived, if so, execute step 1014, if not, execute step 1008.

[0146] Step 1014, report no fault.

[0147] The embodiment of the present application improves the ultrasonic equipment and enables the real-time monitoring function in the ultrasonic system host software, so that the ultrasonic equipment can perform primary monitoring and secondary monitoring. Without changing the hardware circuit of the ultrasonic equipment, the real-time monitoring function is enabled in the ultrasonic system host software without the aid of professional instruments such as oscilloscopes and logic analyzers. When a problem occurs, the timing correctness and synchronization of the scanning cycle of each FPGA controller are monitored to determine whether the fault is caused by the failure to package and upload RF data, incorrect control timing logic or incorrect synchronization. The faulty board can be specifically located and the fault code can be accurately reported, providing users or maintainers with more convenient and accurate fault location, improving the testability and maintainability of the system and reducing equipment maintenance costs.

[0148] Based on the same technical concept, Fig.11 The structure of an ultrasonic device provided by an embodiment of the present invention is exemplarily shown, and the device can execute the fault diagnosis method of the ultrasonic device mentioned above.

[0149] like Fig.11 As shown, the device specifically includes:

[0150] A determination module 1110 is used to start a first timer after determining to start the first-level monitoring, wherein the timing duration of the first timer is the time of N frames of images, where N is a positive integer;

[0151] The transceiver module 1120 is used to receive the radio frequency RF data frame during the operation of the first timer, and increase the number of received frames by one after each completion of the RF data frame reception;

[0152] Processing module 1130 is used to determine whether the number of received frames is greater than or equal to N after the first timer reaches the timing duration; if satisfied, determine that the ultrasonic device has no fault and enter the normal use interface; if not satisfied, perform secondary monitoring and determine the fault code based on the secondary monitoring results.

[0153] Optionally, the transceiver module 1120 is specifically used for:

[0154] Sending a start instruction to each field programmable gate array FPGA controller, wherein the start instruction is used to instruct each FPGA controller to perform secondary monitoring;

[0155] The processing module 1130 is specifically used for:

[0156] Starting a second timer, and monitoring the scanning timing of each FPGA controller and the synchronization between the multiple FPGA controllers in real time within the timing duration corresponding to the second timer;

[0157] The determining module 1100 is specifically configured to:

[0158] After determining that a monitoring anomaly has occurred, different anomalies are encoded and the fault codes are reported in real time.

[0159] Optionally, the processing module 1130 is specifically configured to:

[0160] Obtain scan timing analysis results of each FPGA logic controller;

[0161] Compare the scan timing analysis result with the scan setting time of the current line, and output the judgment result in real time;

[0162] If the result is correct, continue to determine the synchronization between multiple FPGA controllers; if the result is wrong, report the first fault code, which is used to report a fault error including the scan control timing of each FPGA controller.

[0163] Optionally, the processing module 1130 is specifically configured to:

[0164] Obtaining the scan timing synchronization signal analysis and comparison results in multiple FPGA logic controllers;

[0165] If the result is correct, continue to determine whether the second timer has reached the set monitoring time; if the result is wrong, report the second fault code, which is used to report fault errors of single or multiple FPGA controller scanning control synchronization errors.

[0166] Optionally, the processing module 1130 is specifically configured to:

[0167] If the second timer reaches the set monitoring time, the scanning timing and synchronization are reported to be fault-free and no scanning fault is detected; if the second timer does not reach the set monitoring time, the secondary monitoring continues.

[0168] Optionally, the timing duration of the second timer is a default duration, or the timing duration of the second timer is determined according to a specified time sent by the client.

[0169] Optionally, the processing module 1130 is further configured to:

[0170] The corresponding fault code is displayed on the software interface of the ultrasonic device.

[0171] The present application also provides an ultrasonic device, please refer to Fig.12 , Fig.12 A structural diagram of an ultrasonic device provided in an embodiment of the present application.

[0172] The device 1201 includes: at least one processor 1202 and a memory 1203 communicatively connected to the at least one processor.

[0173] The memory 1203 stores instructions that can be executed by at least one processor 1202 , and the at least one processor 1202 implements the fault diagnosis method of the ultrasonic device as described in any of the above items by executing the instructions stored in the memory 1203 .

[0174] As an example, Fig.12 The processor 1202 in the above text can implement Fig.11 The functions of the processing module 1130 and the function of the determination module 1100.

[0175] Based on the same technical concept, an embodiment of the present invention further provides a computer-readable non-volatile storage medium, including computer-readable instructions. When a computer reads and executes the computer-readable instructions, the computer executes the above-mentioned fault diagnosis method of the ultrasonic device.

[0176] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0177] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0178] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0179] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0180] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A fault diagnosis method for ultrasonic equipment, characterized in that: include: After determining to start executing the first-level monitoring, start a first timer, the timing duration of the first timer is the time of N frames of images, and N is a positive integer; During the operation of the first timer, receiving radio frequency (RF) data frames, and increasing the number of received frames by one after each completion of receiving the RF data frames; After the first timer reaches the timing duration, determining whether the number of received frames is greater than or equal to N; If the conditions are met, it is determined that the ultrasonic device has no faults and the normal use interface is entered; if the conditions are not met, secondary monitoring is performed and the fault code is determined based on the secondary monitoring results.

2. The method according to claim 1, characterized in that When performing the secondary monitoring, the method includes: Sending a start instruction to each field programmable gate array FPGA controller, wherein the start instruction is used to instruct each FPGA controller to perform secondary monitoring; Starting a second timer, and monitoring the scanning timing of each FPGA controller and the synchronization between the multiple FPGA controllers in real time within the timing duration corresponding to the second timer; After determining that a monitoring anomaly has occurred, different anomalies are encoded and the fault codes are reported in real time.

3. The method according to claim 2, characterized in that The step of starting the second timer and monitoring the scanning timing of each FPGA controller and the synchronization between the multiple FPGA controllers in real time within the timing duration corresponding to the second timer includes: Obtain scan timing analysis results of each FPGA logic controller; Compare the scan timing analysis result with the scan setting time of the current line, and output the judgment result in real time; If the result is correct, continue to determine the synchronization between multiple FPGA controllers; if the result is wrong, report the first fault code, which is used to report a fault error including the scan control timing of each FPGA controller.

4. The method according to claim 3, characterized in that If the result is correct, continue to determine the synchronization between the multiple FPGA controllers, including: Obtaining the scan timing synchronization signal analysis and comparison results in multiple FPGA logic controllers; If the result is correct, continue to determine whether the second timer has reached the set monitoring time; if the result is wrong, report the second fault code, which is used to report fault errors of single or multiple FPGA controller scanning control synchronization errors.

5. The method according to claim 4, characterized in that If the result is correct, continuing to determine whether the second timer reaches a set monitoring time includes: If the second timer reaches the set monitoring time, the scanning timing and synchronization are reported to be fault-free and no scanning fault is detected; if the second timer does not reach the set monitoring time, the secondary monitoring continues.

6. The method according to claim 5, characterized in that The timing duration of the second timer is a default duration, or the timing duration of the second timer is determined according to a specified time sent by the client.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: The corresponding fault code is displayed on the software interface of the ultrasonic device.

8. An ultrasonic device, characterized in that: The device includes a processor, a controller and a monitoring module; The processor is used to start a first timer after determining to start executing the first-level monitoring, wherein the timing duration of the first timer is the time of N frames of images, where N is a positive integer; during the operation of the first timer, receive radio frequency RF data frames, and after each completion of RF data frame reception, increase the number of received frames by one; after the first timer reaches the timing duration, determine whether the number of received frames is greater than or equal to N; if satisfied, determine that the ultrasound device has no faults and enter the normal use interface; if not satisfied, proceed to the next level of monitoring; The monitoring module is used to monitor the scanning timing of the controller and the synchronization between the controllers in real time during the operation time of the second timer, and report the corresponding monitoring results in real time.

9. The device according to claim 8, characterized in that The controller includes a main FPGA controller, a transmitting FPGA controller and a receiving FPGA controller; The monitoring module includes a status monitoring module and a synchronization monitoring module; The state monitoring module is used to compare and monitor the scan timing generated in the main FPGA controller, the transmitting FPGA controller and the receiving FPGA controller with the actually set scan timing during the operation time of the second timer, and report the scan timing monitoring result; The synchronization monitoring module is used to perform synchronization comparison monitoring on the synchronization signals generated by the main FPGA controller, the transmitting FPGA controller and the receiving FPGA controller during the operation time of the second timer, and report the synchronization monitoring result.

10. An ultrasonic device, characterized in that: The device includes a determination module, a transceiver module, and a processing module; The determining module is used to start a first timer after determining to start the first-level monitoring, wherein the timing duration of the first timer is the time of N frames of images, where N is a positive integer; The transceiver module is used to receive radio frequency (RF) data frames during the operation of the first timer, and increase the number of received frames by one after each RF data frame reception is completed; The processing module is used to determine whether the number of received frames is greater than or equal to N after the first timer reaches the timing duration; If the conditions are met, it is determined that the ultrasonic device has no faults and the normal use interface is entered; if the conditions are not met, secondary monitoring is performed and the fault code is determined based on the secondary monitoring results.

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