Half-bridge gate driver and method for detecting faulty operating condition

Abstract

A half-bridge gate driver and a method for detecting a faulty operating condition are disclosed. The half-bridge gate driver includes: a phase node terminal configured to be coupled to a phase node coupled to a high-side transistor and a low-side transistor of a half-bridge; a diode including an anode and a cathode, where the cathode is coupled to the phase node terminal; and a comparator including a first input terminal coupled to the anode of the diode to receive a measured value indicative of the phase voltage at the phase node terminal, a second input terminal coupled to the threshold source to receive a threshold, and an output terminal configured to output a comparison result indicative of whether the measured value satisfies the threshold. The phase node terminal is configured to be connected to a high-side power supply potential through a high-side transistor and configured to be connected to a low-side power supply potential through a low-side transistor.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronics, and in particular to protecting power converters by sensing phase node voltages. Background Art

[0002] Modern devices rely on power semiconductor devices for many functions in motor vehicle applications, consumer applications, and industrial applications, such as driving motors or electric motors. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] A transistor typically includes a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures of the transistor. In addition, the load current can be controlled by a control electrode (sometimes referred to as a gate electrode) of the transistor. For example, upon receiving a corresponding control signal from, for example, a gate driver, the control electrode can set its transistor to one of an on state or a blocking state. Thus, the semiconductor structure behaves like a switch having an on and off state (i.e., an on state and a blocking state, respectively).

[0004] Typically, the power converter includes two complementary transistors (e.g., high-side transistor and low-side transistor) for driving a load. In some implementations, the power converter includes two complementary transistors for each motor phase of the motor, wherein the two complementary transistors form a half-bridge to drive an output disk connected to the motor winding. The half-bridge gate driver for driving the two complementary transistors can be supplied with a fixed positive voltage by a positive power rail, and a fixed negative voltage is supplied by a negative power rail. The positive power rail can be connected to the output disk via a high-side transistor in the two complementary transistors to supply a load current to the motor winding, and the negative power rail can be connected to the output disk via a low-side transistor in the two complementary transistors to absorb the load current from the motor winding. The two complementary transistors can be turned on and off complementarily to avoid cross conduction.

[0005] Therefore, the load current (also referred to as the phase current) can be controlled by driving two complementary transistors. The amplitude of the control signal received from the gate driver for each transistor can be varied to drive the two complementary transistors between the switching states. This in turn drives the load. For example, the gate-source voltage Vgs of a MOSFET is usually driven to approximately zero to turn off the MOSFET, and is usually driven to a maximum value to fully turn on the MOSFET. For this reason, the gate-source voltage Vgs can be referred to as a control voltage. Summary of the invention

[0006] In some implementations, a half-bridge gate driver includes: a low-side output terminal configured to be coupled to a control terminal of a low-side transistor of the half-bridge and configured to output a low-side output signal to drive the low-side transistor between switching states; a high-side output terminal configured to be coupled to a control terminal of the high-side transistor of the half-bridge and configured to output a high-side output signal to drive the high-side transistor between switching states; a phase node terminal configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and wherein the phase node terminal is configured to be connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; a diode including an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator including a first input terminal coupled to the anode of the diode to receive a measured value indicating a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source to receive a threshold, and an output terminal configured to output a comparison result indicating whether the measured value meets the threshold.

[0007] In some implementations, a half-bridge gate driver includes: a low-side output terminal configured to be coupled to a control terminal of a low-side transistor of a half-bridge and configured to output a low-side output signal to drive the low-side transistor between corresponding switching states; a high-side output terminal configured to be coupled to a control terminal of a high-side transistor of the half-bridge and configured to output a high-side output signal to drive the high-side transistor between corresponding switching states; a phase node terminal configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and wherein the phase node terminal is configured to be connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; an inverter including an inverter input, an inverter output, and a floating voltage configured to receive a floating voltage. a first power supply terminal for a source voltage, and a second power supply terminal configured to receive a floating reference voltage, wherein the inverter input is coupled to the high-side output terminal and is configured to receive the high-side output signal as an input signal, wherein the second power supply terminal is coupled to the phase node terminal and is configured to receive the phase voltage at the phase node terminal as a floating reference voltage, wherein the inverter is configured to generate an inverter output signal at the inverter output terminal based on the input signal, the floating power supply voltage and the floating reference voltage; a diode, which includes an anode and a cathode, wherein the cathode is coupled to the inverter output terminal for receiving the inverter output signal from the inverter output terminal; and a comparator, which includes a first input terminal coupled to the anode of the diode to receive a measurement value representing the inverter output signal, a second input terminal coupled to the threshold source to receive the threshold, and an output terminal configured to output a comparison result indicating whether the measurement value meets the threshold.

[0008] In some implementations, a method for detecting a faulty operating condition includes: generating a low-side output signal to drive a low-side transistor of a half-bridge between corresponding switching states; generating a high-side output signal to drive a high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; providing the high-side output signal as an input signal to an inverter; providing a floating power supply voltage to the ... supplying a first power supply terminal of an inverter; supplying a phase voltage generated at a phase node terminal as a floating reference voltage to a second power supply terminal of the inverter; generating an inverter output signal by the inverter based on an input signal, the floating power supply voltage and the floating reference voltage; supplying the inverter output signal to a cathode of a diode; and comparing a measured value at an anode of the diode with a threshold to generate a comparison result indicating whether the measured value meets the threshold, wherein the measured value represents the inverter output signal of the inverter, and wherein the comparison result indicates whether a faulty operating condition exists during an on-state interval in which the high-side output signal sets the high-side transistor to an on-state.

[0009] In some implementations, a method for detecting a faulty operating condition includes generating a low-side output signal to drive a low-side transistor of a half-bridge between corresponding switching states, generating a high-side output signal to drive a high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on, wherein a voltage at the phase node terminal is a phase voltage; providing the phase voltage to a cathode of a diode; and comparing a measured value at an anode of the diode with a threshold to generate a comparison result indicating whether the measured value meets the threshold, wherein the measured value represents the phase voltage, and wherein the comparison result indicates whether a faulty operating condition exists.

[0010] In some implementations, a half-bridge gate driver includes: a low-side output terminal configured to be coupled to a control terminal of a low-side transistor of a half-bridge and configured to output a low-side output signal to drive the low-side transistor between corresponding switching states; a high-side output terminal configured to be coupled to a control terminal of a high-side transistor of the half-bridge and configured to output a high-side output signal to drive the high-side transistor between corresponding switching states; a phase node terminal configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor. When the high-side transistor is turned on, the phase node terminal is connected to the high-side power supply potential through the high-side transistor, and wherein the phase node terminal is configured to be connected to the low-side power supply potential through the low-side transistor when the low-side transistor is turned on; an inverter, which includes an inverter input terminal, an inverter output terminal, a first power supply terminal configured to receive a floating power supply voltage, and a second power supply terminal configured to receive a floating reference voltage, wherein the inverter input terminal is coupled to the high-side output terminal and is configured to receive the high-side output signal as an input signal, wherein the second power supply terminal is coupled to the phase node terminal, and and is configured to receive a phase voltage at a phase node terminal as a floating reference voltage, wherein the inverter is configured to generate an inverter output signal at an inverter output terminal based on an input signal, a floating supply voltage, and a floating reference voltage; a first diode, comprising a first anode and a first cathode, wherein the first cathode is coupled to the inverter output terminal for receiving the inverter output signal from the inverter output terminal; a first comparator, comprising a first input terminal coupled to the first anode of the first diode to receive a first measurement value representing the inverter output signal, a second input terminal coupled to a first threshold source to receive the first threshold, and a first output terminal configured to output a first comparison result indicating whether the first measurement value meets the first threshold; a second diode, comprising a second anode and a second cathode, wherein the second cathode is coupled to the phase node terminal; and a second comparator, comprising a third input terminal coupled to the second anode of the second diode to receive a second measurement value indicating the phase voltage at the phase node terminal, a fourth input terminal coupled to the second threshold source to receive the second threshold, and a second output terminal configured to output a second comparison result indicating whether the second measurement value meets the second threshold.

[0011] In some implementations, a method for detecting multiple fault operating conditions includes: generating a low-side output signal to drive a low-side transistor of a half-bridge between corresponding switching states; generating a high-side output signal to drive a high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; providing the high-side output signal as an input signal to an inverter; providing a floating power supply voltage to a first power supply terminal of the inverter; providing the phase voltage generated at the phase node terminal as a floating reference voltage to a second power supply terminal of the inverter; and providing the phase voltage generated at the phase node terminal as a floating reference voltage to a second power supply terminal of the inverter based on the input signal, the floating power supply voltage and the phase node terminal of the inverter. A floating reference voltage generates an inverter output signal; provides the inverter output signal to a first cathode of a first diode; compares a first measurement value at a first anode of the first diode with a first threshold value to generate a first comparison result indicating whether the first measurement value meets the first threshold value, wherein the first measurement value represents the inverter output signal of the inverter, and wherein the first comparison result indicates whether a first fault operating condition exists during an on-state interval in which the high-side output signal sets the high-side transistor to an on-state; provides a phase voltage to a second cathode of a second diode; and compares a second measurement value at a second anode of the second diode with a second threshold value to generate a second comparison result indicating whether the second measurement value meets the second threshold value, wherein the second measurement value represents the phase voltage, and wherein the second comparison result indicates whether a second fault operating condition exists. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Implementations are described herein with reference to the accompanying drawings.

[0013] Figure 1 A schematic block diagram illustrating a motor control system according to one or more implementations is shown.

[0014] Figure 2A A schematic block diagram of a gate driver system according to one or more implementations is shown.

[0015] Figure 2B is a truth table corresponding to monitoring the first fault operating condition.

[0016] Figure 2C A schematic block diagram of a gate driver system according to one or more implementations is shown.

[0017] Figure 2D is a truth table corresponding to monitoring the second fault operating condition.

[0018] Figure 2EA schematic block diagram of a gate driver system according to one or more implementations is shown.

[0019] Figure 2F is a truth table corresponding to monitoring the third fault operating condition. DETAILED DESCRIPTION

[0020] In the following, the details are set forth to provide a more comprehensive explanation of the exemplary implementations. However, it will be apparent to those skilled in the art that these implementations may be practiced without these specific details. In other cases, in order to avoid obscuring the implementations, known structures and devices are shown in block diagram form or in schematic diagrams rather than in detail. In addition, unless otherwise specifically stated, the features of the different implementations described below may be combined with each other.

[0021] In addition, equivalent or similar elements or elements having equivalent or similar functions are indicated by equivalent or similar reference numerals in the following description. Since the same elements or elements having equivalent functions are given the same reference numerals in the drawings, repeated descriptions of elements provided with the same reference numerals may be omitted. Therefore, descriptions provided for elements having the same or similar reference numerals may be interchangeable.

[0022] Each of the x-axis, y-axis, and z-axis is shown to be substantially perpendicular to the other two axes. In other words, the x-axis is substantially perpendicular to the y-axis and the z-axis, the y-axis is substantially perpendicular to the x-axis and the z-axis, and the z-axis is substantially perpendicular to the x-axis and the y-axis. In some cases, a single reference numeral is shown to refer to a surface, or less than all instances of a component may be labeled with all surfaces of the component. All instances of a component may include associated surfaces of the component, although not every surface is labeled.

[0023] The orientation of various elements in the figure is shown as an example, and the example shown can be rotated relative to the drawn orientation. The description provided herein and the attached claims relate to any structure having the relationship described between various features, regardless of whether these structures are in a specific orientation of the drawings, or rotated relative to such an orientation. Similarly, for ease of description, spatial relative terms such as "top", "bottom", "below", "below", "lower", "above", "upper", "middle", "left side" and "right side" are used herein to describe the relationship between an element and one or more other elements shown in the figures. Spatial relative terms are intended to be included in different orientations of elements, structures and / or components in use or operation except for the orientation drawn in the figures. Structures and / or components can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article can be interpreted accordingly. In addition, in order to simplify the drawings, the cross-sectional views in the figures only show the features in the cross-sectional plane, and the materials behind the cross-sectional plane are not shown, unless otherwise stated.

[0024] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in the same manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0025] In the implementations described herein or shown in the drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented through an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, or vice versa), as long as the general purpose of the connection or coupling (e.g., sending a certain signal or transmitting certain information) is substantially maintained. Features from different implementations may be combined to form additional implementations. For example, changes or modifications described with respect to one of the implementations may also apply to other implementations unless otherwise indicated.

[0026] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, without departing from aspects of the implementations described herein, the terms "substantially" and "approximately" may be used herein to explain small manufacturing tolerances or other factors that are considered acceptable in the industry (e.g., within 5%). For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal within an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0027] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. can modify various elements. However, such elements are not limited by the above expressions. For example, such expressions do not limit the order and / or importance of elements. Instead, such expressions are only used for the purpose of distinguishing elements from other elements. For example, the first box and the second box indicate different boxes, although both are boxes. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element.

[0028] A transistor may be referred to as a power switch, a logic switch, or a transistor switch, which may be used to drive a current, such as a load current. In particular, a power transistor is a power semiconductor device that may be used to drive a load current. A power transistor includes a first load terminal (e.g., a source or emitter) and a second load terminal (e.g., a drain or collector). Additionally, the load current path of the power transistor may be controlled by a control electrode (sometimes referred to as a gate) connected to a control terminal of the power transistor. The load current path of the power transistor is a gate-controlled conduction channel, the conductivity of which may be controlled by a control voltage applied to the control electrode of the power transistor. For example, a power transistor may be turned on or off by activating and deactivating its control electrode. For example, applying a positive voltage across the gate and source of a MOSFET will keep the MOSFET in an "on" state, while applying an approximately zero or slightly negative voltage across the gate and source of the MOSFET will turn the MOSFET "off".

[0029] There is a turn-on process for switching the transistor to on and a turn-off process for switching the transistor to off. During the turn-on process of the n-channel transistor, the gate driver can be used to provide (supply) a gate current (e.g., a turn-on current) to the gate of the n-channel transistor so as to charge the gate voltage to a voltage sufficient to turn on the n-channel transistor. On the contrary, during the turn-off process of the n-channel transistor, the gate driver is used to draw (absorb) a gate current (e.g., a turn-off current) from the gate of the n-channel transistor so as to fully discharge the gate voltage to turn off the n-channel transistor. According to a pulse width modulation (PWM) scheme, a voltage pulse can be output from the gate driver as a control signal. Therefore, during the PWM cycle for controlling the n-channel transistor, the control signal can be switched between a turn-on voltage level and a turn-off voltage level. This in turn charges and discharges the gate capacitance to modulate the gate voltage accordingly, thereby turning on and off the n-channel transistor, respectively.

[0030] The situation is exactly the opposite for p-channel transistors. The gate driver can be used to draw (absorb) a gate current (e.g., a turn-on current) from the gate of the p-channel transistor in order to discharge the gate voltage to a voltage sufficient to turn on the p-channel transistor. Conversely, during the turn-off process of the p-channel transistor, the gate driver is used to provide (supply) a gate current (e.g., a turn-off current) to the gate of the p-channel transistor in order to sufficiently charge the gate voltage of the p-channel transistor to turn off the p-channel transistor. During the PWM cycle for controlling the p-channel transistor, the control signal applied to the gate of the p-channel transistor can be switched between an on voltage level and an off voltage level. This in turn charges and discharges the gate voltage to turn on and off the p-channel transistor, respectively.

[0031] For both the n-channel transistor and the p-channel transistor, when the gate-source voltage Vgs is approximately zero or lower than the threshold voltage, the n-channel transistor and the p-channel transistor are turned off, and when the gate-source voltage Vgs is equal to or greater than the threshold voltage, the n-channel transistor and the p-channel transistor are turned on.

[0032] In order to drive the load in this way, two transistors are usually arranged in a half-bridge configuration, and a converter branch of a power converter can be formed.Two transistors can include a high-side transistor and a low-side transistor coupled together at a phase node, and a phase voltage (e.g., a phase node voltage) is generated based on the switching state of the two transistors at the phase node.The phase voltage is used to generate a phase current.The high-side transistor can be a p-channel transistor connected to a high-side power supply potential, and the low-side transistor can be an n-channel transistor connected to a low-side power supply potential.In some implementations, the high-side transistor and the low-side transistor can be the same transistor type (e.g., both are n-channel types or both are p-channel types).

[0033] When the load current flows from the half-bridge to the load (for example, from the phase node to the load), the load current (for example, the phase current) is referred to as a positive load current, and when the load current flows away from the load to the half-bridge (for example, from the load toward the phase node), the load current is referred to as a negative load current. The high-side transistor is responsible for conducting the positive load current when it is turned on, so that when its complementary low-side transistor is turned off (for example, the low-side transistor is in a blocking or high-impedance mode), the load current is supplied to the load. In order to absorb the load current from the load, the role of the high-side transistor and the low-side transistor is reversed. Here, the low-side transistor is responsible for conducting the negative load current when it is turned on, so that when its complementary high-side transistor is turned off (for example, the high-side transistor is in a blocking or high-impedance mode), the load current is absorbed from the load. Two complementary transistors are usually switched so that they are not turned on at the same time.

[0034] The transistor may include an IGBT and a MOSFET (e.g., a Si MOSFET or a SiC MOSFET), etc. It should be understood that one type of transistor may replace another type of transistor. In this context, when a MOSFET is substituted for an IGBT, in any of the examples described herein, the drain of the MOSFET may replace the collector of the IGBT, the source of the MOSFET may replace the emitter of the IGBT, the drain-source voltage Vds of the MOSFET may replace the collector-emitter voltage Vce of the IGBT, and the gate-source voltage Vgs of the MOSFET may replace the gate-emitter voltage Vge of the IGBT, and vice versa.

[0035] Some implementations described in the present disclosure relate to, but are not limited to, a half-bridge for driving a motor. For example, as a power converter, a multiphase converter is configured to provide multiphase power by supplying a multiphase load (e.g., a three-phase motor). For example, three-phase power involves three symmetrical sine waves, which are 120 electrical degrees out of phase with each other. In a symmetrical three-phase power supply system, three conductors each carry an alternating current (AC) with the same frequency and voltage amplitude but with a phase difference of one-third of a drive cycle relative to a common reference. Due to the phase difference, the voltage on any one of the three conductors reaches its voltage peak at one-third of the drive cycle, and the voltage peaks of the three conductors are distributed with substantially equal phase delays to each other within the drive cycle. The phase delay provides constant power transmission for a balanced linear load. This also makes it possible to generate a rotating magnetic field in the motor.

[0036] The three-phase converter includes three converter branches, one converter branch for each of the three phases, and each converter branch is connected to a direct current (DC) voltage source in parallel with each other. As described above, each converter branch includes a pair of transistors arranged in a half-bridge configuration for converting DC to AC to drive a phase load. However, the multiphase converter is not limited to three phases, and may include two or more phases, wherein a converter branch is provided for each phase. In some cases, two half-bridges may be connected as an H-bridge circuit, wherein a load (e.g., a motor) is connected as a cross switch between two half-bridges as a single-phase load.

[0037] The typical simple power converter stage of low-power motor drive system (for example, the motor drive system for refrigerator) is very sensitive to cost. Therefore, some manufacturers do not implement any overcurrent or short-circuit protection in the power converter stage (for example, in the gate driver of the power converter stage). Instead, some manufacturers rely on the short-circuit capability of the transistor (for example, the short-circuit capability of the IGBT) and the fuse placed on the AC line to ensure the required safety. However, the new generation of IGBT has less short-circuit withstand time, and the new package (for example, small outline transistor (SOT) package (for example, SOT-223)) introduced recently is smaller and has a reduced thermal mass. Therefore, it is difficult to realize the protection that relies on the short-circuit capability of the transistor and combines the fuse on the AC line only.

[0038] Some implementations disclosed herein relate to a half-bridge gate driver configured to sense the phase node of a converter branch with a specific timing compared to a gate driver input / output signal. For example, a half-bridge gate driver may be configured to monitor and detect a first fault operating condition by sensing the phase voltage at the phase node when the low-side transistor is turned on (and the high-side transistor is turned off), and comparing the phase voltage with a first threshold. As another example, a half-bridge gate driver may be configured to monitor and detect a second fault operating condition by sensing the phase voltage at the phase node when the high-side transistor is turned on (and the low-side transistor is turned off) and comparing the phase voltage with a second threshold. As another example, a half-bridge gate driver may be configured to monitor and detect a third fault operating condition by sensing the phase voltage at the phase node during a startup sequence of a half-bridge gate driver in which both the low-side transistor and the high-side transistor are turned off and comparing the phase voltage with a third threshold.

[0039] In some implementations, the half-bridge gate driver may be a monolithic half-bridge gate driver. By monolithically integrating the monitoring and detection circuitry onto the half-bridge gate driver, the amount of space and cost required to monitor the first fault operating condition, the second fault operating condition, and / or the third fault operating condition may be reduced.

[0040] Thus, a half-bridge gate driver may provide a solution for protecting a system using a new generation of power transistor devices having a smaller short circuit capability and a smaller thermal mass. Additionally, a half-bridge gate driver may be particularly attractive because the half-bridge gate driver may be implemented using a small and simple 8-pin package that is already popular in low power applications. Thus, the half-bridge gate driver may be able to monitor a first fault operating condition, a second fault operating condition, and / or a third fault operating condition without increasing the number of pins of the gate driver package, which is beneficial for saving manufacturing costs and for integration into current systems.

[0041] Figure 1A schematic block diagram of a motor control system 100 according to one or more implementations is shown. In particular, the motor control system 100 includes a power converter 102, a controller 104, and a gate driver system 106. The controller 104 and the gate driver system 106 operate together as a motor control unit. In some implementations, the motor control unit can be a monolithic integrated circuit (IC), wherein the controller 104 and the gate driver system 106 are arranged on a single IC. "Monolithic" refers to an IC or semiconductor device manufactured on a single chip of a single material (usually silicon). The IC is called "monolithic" because the active and passive components of the circuit (such as transistors, resistors, capacitors, and interconnects) are all integrated into a single piece of material or substrate. In some implementations, the motor control unit can be divided into two or more ICs, for example, wherein the controller 104 is arranged on a first IC, and the gate driver system 106 is arranged on one or more second ICs. Therefore, the gate driver system 106 can be a monolithic gate driver. In other implementations, the gate driver system 106 may be implemented on two or more substrates that may be arranged in the same housing. In other implementations, one or more of the active components and / or passive components of the gate driver system 106 may be provided as discrete components. It should be understood that while the implementations described herein are directed to driving motors, the concepts described herein may be extended to other types of inductive loads and are not limited to motors.

[0042] The motor control system 100 is further coupled to a motor M (e.g., a permanent magnet synchronous motor (PMSM) as an AC motor) including three phases U, V, and W. In this example, the power converter 102 is a three-phase voltage generator configured to provide three-phase power to drive the motor M by supplying a three-phase voltage.

[0043] Deviations in both amplitude and phase may result in power and torque losses in the motor M. Therefore, the controller 104 may be configured to monitor and control the amplitude and phase of the voltage supplied to the motor M in real time to ensure that proper current balance is maintained based on a feedback control loop.

[0044] The power converter 102 for motor M comprises the switch array of six transistors 108u, 108v, 108w, 109u, 109v and 109w arranged in complementary pairs.Each complementary pair forms a half-bridge circuit, and constitutes a converter branch for supplying phase voltage to motor M.Therefore, each converter branch comprises high-side transistor 108u, 108v or 108w and low-side transistor 109u, 109v or 109w.Additionally, each transistor 108u, 108v, 108w, 109u, 109v and 109w can be connected to corresponding freewheeling diode D1 to D6 in anti-parallel.Freewheeling diode D1 to D6 provides alternative current path for load current during the off period of corresponding transistor 108u, 108v, 108w, 109u, 109v and 109w for current commutation. For example, the freewheeling diode D1 provides an alternative current path with respect to the low-side transistor 109u during the off-time of the low-side transistor 109u.Similarly, the freewheeling diode D2 provides an alternative current path with respect to the high-side transistor 108u during the off-time of the high-side transistor 108u.

[0045] The load current paths U, V and W extend from the output disk Uout, Vout or Wout of each converter branch (e.g., the output terminal of each half-bridge circuit) located between the complementary transistors and are configured to be coupled to a load, such as a motor M. Each load current path U, V and W carries a corresponding phase current Iu, Iv and Iw. Each phase current Iu, Iv and Iw has an AC electrical frequency that directly corresponds to the actual motor speed of the motor M.

[0046] The power converter 102 is coupled to a DC power source (eg, a battery or a diode bridge rectifier) ​​and a gate driver system 106 .

[0047] The controller 104 can be a microcontroller or another hardware-based controller that performs the motor control functions of the motor control system 100 in real time (or near real time) and sends PWM control signals to the gate driver system 106. The controller 104 can use a PWM scheme to control the state of each transistor and ultimately control each phase current provided on the corresponding load current paths U, V, and W. The gate driver system 106 generates a driver signal based on the PWM control signal to control the switch state (e.g., on and off state) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. Therefore, the load current paths U, V, and W can be controlled by the controller 104 and the gate driver system 106 by controlling the control electrodes (e.g., gate electrodes) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. For example, upon receiving a PWM control signal from the controller 104, the gate driver system 106 may set the corresponding transistor 108u, 108v, 108w, 109u, 109v, or 109w to one of a conducting state (eg, an on state) or a blocking state (eg, an off state).

[0048] The gate driver system 106 may include one or more gate drivers for driving transistors 108u, 108v, 108w, 109u, 109v, and 109w between switch states. For example, the gate driver system 106 may include a gate driver for each half-bridge circuit. The gate driver system 106 may be configured to receive instructions including PWM control signals from the controller 104, and turn on and off transistors 108u, 108v, 108w, 109u, 109v, and 109w respectively according to the received instructions and control signals. For example, during the turn-on process of transistors 108u, 108v, 108w, 109u, 109v, or 109w, the gate driver system 106 may be used to provide (supply) a gate current to the gate of transistors 108u, 108v, 108w, 109u, 109v, or 109w to charge the gate. Conversely, during the turn-off process, the gate driver system 106 may be used to draw (sink) a gate current from the gate of the transistor 108u, 108v, 108w, 109u, 109v, or 109w to discharge the gate.

[0049] In addition, the transistor 108u, 108v, 108w, 109u, 109v and 109w of control power converter 102 make both high-side transistor and low-side transistor in same converter branch non-conductive at any time, otherwise DC power supply will be short-circuited.According to motor control algorithm, this requirement can be met by the complementary operation of transistor 108u, 108v, 108w, 109u, 109v and 109w in converter branch.For example, during operation, motor M can be driven according to motor control algorithm, to realize the desired motor speed corresponding to the electrical frequency of control signal.Controller 104 can apply dead time, during which high-side transistor and low-side transistor of same converter branch are turned off simultaneously.

[0050] As mentioned above, Figure 1 Provided as an example only. Other examples may vary from Figure 1 For example, in some implementations, the motor phases may be different, or two half-bridges may be connected as an H-bridge circuit. In some implementations, additional circuit components may be added without departing from the disclosure provided above.

[0051] Figure 2A 1 is a schematic block diagram of a gate driver system 200A according to one or more implementations. The gate driver system 200A may be used with Figure 1 The gate driver system 106 corresponds to Figure 2A As shown, the gate driver system 200A includes a single-phase motor drive stage 202 (eg, a converter leg or a half-bridge circuit) and a half-bridge gate driver 204 electrically coupled to the single-phase motor drive stage 202. The gate driver system 200A may be replicated for each converter leg in the gate driver system 200.

[0052] The single-phase motor drive stage 202 includes a high-side transistor 206 and a low-side transistor 208, which are controlled to supply a load current I to the motor M. LOAD In other words, the single-phase motor drive stage 202 in this example corresponds to the combination of Figure 1 One of the phase converter branches of the electrical machine M described.

[0053] The half-bridge gate driver 204 may be a monolithic half-bridge gate driver including a low-side gate driver 210 for driving the low-side transistor 208 and a high-side gate driver 212 for driving the high-side transistor 206. Both the low-side gate driver 210 and the high-side gate driver 212 may perform gate driving of their respective low-side transistors 208 and high-side transistors 206 based on PWM control signals LIN and HIN received from a PWM controller such as the controller 104. The low-side gate driver 210 may control the switching state of the low-side transistor 208 using the PWM control signal LIN. The high-side gate driver 212 may control the switching state of the high-side transistor 206 using the PWM control signal HIN.

[0054] The half-bridge gate driver 204 may include a package including a plurality of terminals 1 to 8 (e.g., 8 pins) used as input terminals (e.g., for receiving a control signal or a supply voltage) and output terminals (e.g., for providing a drive signal or a gate control signal). The PWM control signals LIN and HIN may be received from the controller 104 at control terminals 1 and 2 of the half-bridge gate driver 204, respectively, and may be provided to the logic unit 214. The logic unit 214 may include one or more processors and / or logic circuits, which may be configured to perform signal processing, logic control, filtering, fault detection, dead time control, and operate in one or more evaluation modes based on one or more conditions satisfied. For example, the logic unit 214 may be configured to receive the PWM control signals LIN and HIN from the controller 104 and ensure that a minimum dead time is achieved during which both the high-side transistor 206 and the low-side transistor 208 are turned off simultaneously.

[0055] The PWM control signals LIN and HIN are transmitted to the corresponding low-side gate driver 210 and high-side gate driver 212 through the logic unit 214. In some implementations, the PWM control signal HIN provided to the high-side gate driver 212 can pass through the level converter 216. The level converter 216 can be used to convert (e.g., level shift) the PWM control signal HIN, and thus transfer the control information from the low voltage domain of the half-bridge gate driver 204 to the high voltage domain. Thereafter, the low-side gate driver 210 and the high-side gate driver 212 perform gate driving.

[0056] The half-bridge gate driver 204 can be a multi-voltage domain device, comprising: a low-side region 218 including a first circuit operating in a low voltage domain; a high-side region 220 including a second circuit operating in a high voltage domain; and an isolation region 222 that electrically isolates the low-side region 218 and the high-side region 220. For example, the low voltage domain and the high voltage domain can have different ground potentials. For example, the low voltage domain can have a first ground potential (e.g., 0V or COM), and the high voltage domain can have a second ground potential (e.g., a floating ground potential) that is different from the first ground potential. For example, the second ground potential can be greater than the first ground potential, and therefore, the high voltage domain can be referred to as a higher voltage domain.

[0057] The low-side gate driver 210 and the high-side gate driver 212 are configured to receive PWM control signals LIN and HIN signals, and based on this, control the on / off state of the low-side transistor 208 and the high-side transistor 206. Therefore, the half-bridge gate driver 204 can be configured to receive PWM control signals LIN and HIN from the controller 104, and turn on or off the corresponding high-side transistor 206 and the low-side transistor 208 according to the received PWM control signals LIN and HIN. For example, during the turn-on process of one of the high-side transistor 206 and the low-side transistor 208, the half-bridge gate driver 204 can be used to provide (supply) gate current to the gate of one of the high-side transistor 206 or the low-side transistor 208 to charge the gate. On the contrary, during the turn-on process of one of the high-side transistor 206 and the low-side transistor 208, the half-bridge gate driver 204 can be used to draw (absorb) gate current from the gate of one of the high-side transistor 206 or the low-side transistor 208 to discharge the gate.

[0058] Thus, the controller 104 is electrically coupled to the half-bridge gate driver 204 for communicating information and control signals therebetween, and the half-bridge gate driver 204 is electrically coupled to the single-phase motor drive stage 202 for driving the high-side transistor 206 and the low-side transistor 208 .

[0059] The half-bridge gate driver 204 also includes a bootstrap diode 224 to charge a voltage charging device 226. In this case, the voltage charging device 226 may be a bootstrap capacitor. However, the voltage charging device 226 may be a rechargeable battery or another voltage charging device. The voltage charging device 226 may be charged by connection to a low-side fixed supply voltage VCC.

[0060] exist Figure 2AIn the figure, VB refers to a high-side floating power supply voltage; VS refers to a phase voltage that can be used as a high-side floating ground voltage or a high-side reference voltage; VCC refers to a low-side fixed power supply voltage; COM refers to a low-side ground voltage or a low-side reference voltage; HO refers to an output terminal for a high-side output signal (e.g., a high-side floating output voltage) configured to control the high-side transistor 206; LO refers to an output terminal for a low-side output signal (e.g., a low-side output voltage) configured to control the low-side transistor 208; DC+ refers to a DC link positive power supply (e.g., a high-side power supply potential); DC- refers to a DC link negative power supply (e.g., a low-side power supply potential) such as a ground potential or a negative potential, and is connected to COM; and HIN and LIN refer to PWM control signals (e.g., logic input voltages) received from the controller 104.

[0061] The low-side fixed power supply voltage VCC can provide power to certain logic components in the half-bridge gate driver 204 that operate using the fixed power supply voltage, and can be used to charge the voltage charging device 226 when the bootstrap diode 224 is forward biased. For example, the low-side fixed power supply voltage VCC can provide power to a circuit located in the low-side region 218 (e.g., in the low voltage domain). Similarly, the low-side ground voltage COM can be used as a reference potential for a circuit located in the low-side region 218. Therefore, the logic component located in the low-side region 218 can have: a power supply terminal, which is configured to receive the low-side fixed power supply voltage VCC; and another power supply terminal, which is configured to accept the low-side ground voltage COM to provide power to the logic component.

[0062] The high-side floating power supply voltage VB can provide power to the circuit located in the high-side region 220 (e.g., the high voltage domain), and the phase voltage VS can be used as a reference potential (e.g., a high-side floating reference voltage) for the circuit located in the high voltage domain. For example, the logic component located in the high-side region 220 can have: one power supply terminal, which is configured to receive the high-side floating power supply voltage VB; and another power supply terminal, which is configured to accept the phase voltage VS as the high-side floating reference voltage to provide power to the logic component.

[0063] The half-bridge gate driver 204 may include a fixed power supply terminal 3 coupled to a power supply for receiving a low-side fixed power supply voltage VCC. The power supply terminal 3 may be configured to be charged to a low-side fixed power supply voltage VCC (e.g., power supply potential) provided by the power supply during a startup operation or a reset operation of the half-bridge gate driver 204. For example, the power supply terminal 3 may be charged to a low-side fixed power supply voltage VCC using a voltage charging device 228 during a startup operation or a reset operation of the half-bridge gate driver 204.

[0064] The half-bridge gate driver 204 may include a common terminal 4 coupled to COM and a DC link negative power supply DC-.

[0065] The half-bridge gate driver 204 may include a low-side output terminal 5 configured to output a low-side output signal LO as a control signal for controlling the low-side transistor 208 .

[0066] The half-bridge gate driver 204 may include a phase node terminal 6 coupled to a phase voltage VS. In particular, the phase voltage VS may be generated at a phase node 230 of the single-phase motor drive stage 202. For example, the phase node 230 may be coupled to a high-side transistor 206 and a low-side transistor 208. The phase node terminal 6 may be configured to be connected to a high-side power supply potential provided by the DC link positive power supply DC+ through the high-side transistor 206 when the high-side transistor 206 is turned on. Alternatively, the phase node terminal 6 may be configured to be connected to a low-side power supply potential provided by the DC link negative power supply DC- through the low-side transistor 208 when the low-side transistor 208 is turned on.

[0067] The half-bridge gate driver 204 may include a high-side output terminal 7 configured to output a high-side output signal HO as a control signal for controlling the high-side transistor 206 .

[0068] The half-bridge gate driver 204 may include a floating power supply terminal 8 coupled to a voltage charging device 226 to receive a high-side floating power supply voltage VB and provide the high-side floating power supply voltage VB to circuits located in the high voltage domain.

[0069] The high-side floating supply voltage VB may be equal to VCC-VS-VD, where VD is the forward bias voltage drop across the bootstrap diode 224. As an example implementation, when the low-side fixed supply voltage VCC is equal to 15V and the high-side floating ground voltage VS is equal to 0V, and the bootstrap diode 224 is forward biased and has a forward bias voltage drop of VD=0.5V, then VB=15V-0V-0.5V=14.5V. That is, during normal operation, the high-side floating supply voltage VB is about 15V higher than the high-side floating ground voltage VS due to the voltage charging device 226 supplying power to the high side of the half-bridge gate driver 204. For example, the positive power rail providing the DC link positive power supply DC+ may be in the range of 100V to 1200V, but is not limited thereto. In addition, when the low-side transistor 208 is turned on (and the high-side transistor 206 is turned off), the high-side floating ground voltage VS is equal to DC- (e.g., COM or 0V). The negative power rail provides the DC link negative power supply DC- and can be shorted to COM as shown, but it does not have to be so. In this case, the high-side floating supply voltage VB is close to 15V, and the voltage charging device 226 is charged by the low-side fixed supply voltage VCC through the bootstrap diode 224. In other cases, when the high-side transistor 206 is turned on (and the low-side transistor 208 is turned off) and the bootstrap diode 224 is reverse biased and not conducting, the high-side floating ground voltage VS is equal to the DC link positive supply DC+. In the case of reverse bias of the bootstrap diode 224, the high-side floating supply voltage VB is 15V higher than the DC link positive supply DC+, and the voltage charging device 226 is slowly discharged. It should be understood that certain circuit values ​​and device parameters used herein are used as examples for the purpose of illustrating one or more possible implementations of many possible implementations, and should not be considered to be limiting or required in any way unless explicitly stated.

[0070] The above voltages are set so that the high-side voltage domain of the half-bridge gate driver 204 operates at a higher voltage or domain than the low-side voltage domain of the half-bridge gate driver 204. For example, when the DC link positive power supply DC+ is supplied at 100V, the low-side fixed power supply voltage VCC can be set to 15V, and the high-side floating power supply voltage VB can operate at a maximum voltage of 115V.

[0071] The half-bridge gate driver 204 can be configured to receive instructions from the controller 104 to drive the motor phase (e.g., the single-phase motor drive stage 202) connected to the high-side floating ground voltage VS using PWM control signals. These PWM control signals, depicted as PWM control signals HIN and LIN, are received by the half-bridge gate driver 204 and are passed to the high-side gate driver 212 and the low-side gate driver 210 via appropriate logic (e.g., a PWM logic unit 214 for the low-side gate driver 210 and a level converter 216 for the high-side gate driver 212). The low-side gate driver 210 can be configured to receive the PWM control signal LIN, while the high-side gate driver 212 can be configured to receive the PWM control signal HIN through the high-side logic 232, and use the output terminals HO and LO of the half-bridge gate driver 204 to drive the low-side transistor 208 and the high-side transistor 206, respectively.

[0072] The half-bridge gate driver 204 may also include a VCC undervoltage lockout (UVLO) circuit 234, a first comparator 236, a second comparator 238, a bit transfer diode 240, a desaturation (DESAT) diode 242, a logic inverter 244, a VBS UVLO circuit 246, a current source I1, and a blanking circuit 248. The current source I1 may be used to forward bias the bit transfer diode 240.

[0073] The half-bridge gate driver 204 can be configured to monitor and detect a first fault operating condition, such as a low-side desaturation fault condition. When the low-side output signal LO is high (e.g., the PWM control signal LIN is high), the low-side transistor 208 is turned on, and the phase node 230 is shorted to DC+ or some other potential corresponding to the high-side region 220, a first fault operating condition may occur, resulting in a phase voltage VS higher than expected. In other words, under normal operating conditions, the phase voltage VS should be pulled toward DC- and should be close to the low-side power supply potential (e.g., the phase voltage VS should be different from the low-side power supply potential according to the voltage drop across the low-side transistor 208).

[0074] The low-side output terminal 5 and the second comparator 238 are arranged in the low-side region 218, the high-side output terminal 7 and the phase node terminal 6 are arranged in the high-side region 220, and the DESAT diode 242 is coupled to the first circuit of the low-side region 218 and the second circuit of the high-side region 220. In some implementations, the DESAT diode 242 can be arranged in the low-side region 218. In some implementations, the DESAT diode 242 can be arranged in the isolation region 222.

[0075] The DESAT diode 242 includes an anode and a cathode. The cathode is coupled to the phase node terminal 6, and the anode is coupled to the first input terminal of the second comparator 238. Therefore, the cathode of the DESAT diode 242 is coupled to the phase voltage VS. A measurement value VDES_L is provided at the anode of the DESAT diode 242 based on the phase voltage VS. For example, the measurement value VDES_L can be clamped to the phase voltage VS plus the forward voltage VF of the DESAT diode 242 (e.g., VDES_L=VS+VF). Therefore, the measurement value VDES_L can represent the phase voltage VS at the phase node terminal 6.

[0076] The second comparator 238 includes a second input terminal coupled to the threshold source to receive the threshold Vth2. The threshold Vth2 may be generated internally by the half-bridge gate driver 204, for example, by the logic unit 214 based on VCC and a programmable voltage divider.

[0077] The second comparator 238 also includes an output terminal coupled to the logic unit 214. The second comparator 238 can be configured to compare the value (e.g., measured value VDES_L and threshold value Vth2) at its two input terminals, and outputs an indication that the measured value VDES_L meets the comparison result of the threshold value Vth2. In other words, the comparison result of the second comparator 238 can indicate whether there is a first fault operating condition. In some implementations, when the measured value VDES_L is greater than the threshold value Vth2, the measured value VDES_L can meet the threshold value Vth2. The logic unit 214 can refer to the PWM control signal LIN to determine when the low-side transistor 208 is turned on, and can monitor the comparison result of the second comparator 238 when the low-side transistor 208 is turned on.

[0078] Under normal operating conditions corresponding to a no-fault condition, when the low-side output signal LO is configured to set the low-side transistor 208 to an on state, and the high-side output signal HO is configured to set the high-side transistor 206 to an off state: the phase voltage VS at the phase node terminal 6 is configured to be pulled toward the low-side power supply potential, the measured value VDES_L is pulled to less than the threshold value Vth2 by the phase voltage VS, and the comparison result of the second comparator 238 should indicate that the measured value VDES_L does not meet the threshold value, thereby indicating a normal operating condition.

[0079] Under normal operating conditions, where the low-side output signal LO is configured to set the low-side transistor 208 to an on-state, and the high-side output signal HO is configured to set the high-side transistor 206 to an off-state: the measured value VDES_L may be clamped to the difference between the forward voltage VF of the DESAT diode 242 and the voltage drop across the low-side transistor 208. The difference should be less than the threshold Vth2.

[0080] On the contrary, under the first fault operation condition, when the low-side output signal LO is configured to set the low-side transistor 208 to the on state and the high-side output signal HO is configured to set the high-side transistor 206 to the off state: the phase voltage VS at the phase node terminal 6 can be pulled to the high-side power supply potential provided by the DC link positive power supply DC+. Therefore, the measured value VDES_L is pulled to be greater than the threshold value Vth2 by the phase voltage VS, and the comparison result of the second comparator 238 indicates that the measured value VDES_L meets the threshold value Vth2, thereby indicating that there is a first fault operation condition. The logic unit 214 can turn off the low-side transistor 208 in response to detecting the first fault operation condition to prevent damage to the gate driver system 200A.

[0081] The blanking circuit 248 may include a DESAT transistor DESAT NMOS_L and a current source I2. The current source I2 may be used to forward bias the DESAT diode 242. The DESAT transistor DESAT NMOS_L may be controlled by the logic unit 214. When the DESAT transistor DESAT NMOS_L is turned on, the measured value VDES_L is pulled down to COM, which effectively disables monitoring of the first fault operating condition. When the DESAT transistor DESAT NMOS_L is turned off, the measured value VDES_L is controlled by the phase voltage VS.

[0082] As mentioned above, Figure 2A Provided as an example only. Other examples may vary from Figure 2A Examples described. Figure 2A The number and arrangement of components shown in FIG. 1 are provided as examples. In practice, Figure 2A The gate driver system 200A may include additional components, fewer components, different components, or differently arranged components compared to the components shown in FIG. Figure 2A Two or more components shown in the figure may be implemented in a single component, or Figure 2A The single components shown in FIG. 200A may be implemented as multiple distributed components. Additionally or alternatively, a set of components (eg, one or more components) of the gate driver system 200A may perform one or more functions described as being performed by another set of components of the gate driver system 200A.

[0083] Figure 2B is a truth table 200B corresponding to monitoring the first fault operation condition. "LO-COM" refers to the potential difference between LO and COM, "VS-COM" refers to the potential difference between VS and COM, and "VDES_L-COM" refers to the potential difference between VDES_L and COM. As described above, Figure 2B Provided as an example only. Other examples may vary from Figure 2BExamples described.

[0084] Figure 2C 1 shows a schematic block diagram of a gate driver system 200A according to one or more implementations. In particular, Figure 2C The invention relates to using the half-bridge gate driver 204 to monitor and detect a second fault operating condition. Therefore, the half-bridge gate driver 204 can be configured to monitor such as in combination with Figure 2A and Figure 2B The first fault operating condition and / or the second fault operating condition are described.

[0085] For example, the half-bridge gate driver 204 may be configured to monitor the second fault operating condition during a startup operation or a reset operation of the half-bridge gate driver 204. Additionally or alternatively, the half-bridge gate driver 204 may be configured to monitor the first fault operating condition after completing a startup operation or a reset operation of the half-bridge gate driver 204. The second fault operating condition may correspond to a short circuit of a phase node to ground present during a startup operation or a reset operation of the half-bridge gate driver 204.

[0086] During the startup operation or reset operation of the half-bridge gate driver 204, the low-side output signal LO and the high-side output signal HO are maintained at the off signal level to set the low-side transistor 208 and the high-side transistor 206 to the off state. Under normal operating conditions of the startup operation or the reset operation, when the low-side output signal LO and the high-side output signal HO are maintained at the off signal level, the phase voltage VS at the phase node terminal 6 is configured to be charged by the charging current Icharge through the charging path. For example, the phase voltage VS can be charged by the bootstrap diode 224 and the voltage charging device 226. The phase voltage VS should be charged to a voltage level greater than a predefined voltage, such as the UVLO voltage set by the VCC UVLO circuit 234 or the VBS UVLO circuit 246. Therefore, the phase voltage VS is charged to a voltage level greater than the predefined voltage, the measured value VDES_L is pulled to be greater than the threshold value Vth2 of the second comparator 238 by the phase voltage VS, and the comparison result of the second comparator 238 indicates that the measured value VDES_L meets the threshold value Vth2, thereby indicating a normal operating condition. For example, when the measured value VDES_L satisfies the threshold Vth2 by being greater than the threshold Vth2, there is no fault condition and the gate driver system 200A is detected as operating normally.

[0087] In contrast, during a second fault operating condition corresponding to a fault operating condition of a startup operation or a reset operation, while the low-side output signal LO and the high-side output signal HO are maintained at the shutdown signal level, the measured value VDES_L is pulled to less than the threshold value Vth by the phase voltage VS, and the comparison result of the second comparator 238 indicates that the measured value VDES_L does not satisfy the threshold value Vth2 (for example, VDES_L is not greater than Vth2), thereby indicating the presence of a second fault operating condition.

[0088] The logic unit 214 may be configured to implement monitoring of the second fault operating condition based on charging of VCC by the fixed power supply terminal 3. For example, during a startup operation or a reset operation of the half-bridge gate driver 204, the fixed power supply terminal 3 may be charged to a low-side fixed power supply voltage VCC provided by a power supply (e.g., by the voltage charging device 228). The VCC UVLO circuit 234 may be configured as part of a monitoring circuit to monitor the voltage level of the fixed power supply terminal 3 (e.g., monitor the charging of VCC), and trigger monitoring operation of the phase node terminal 6 in response to the voltage level of the fixed power supply terminal 3 satisfying the VCC UVLO voltage (e.g., in response to the voltage level of the fixed power supply terminal 3 being equal to and / or greater than the VCC UVLO voltage). Once the voltage level of the fixed power supply terminal 3 satisfies the VCC UVLO voltage, the measured value VDES_L may be considered a reliable representation of the operating condition of the half-bridge gate driver 204. Therefore, the logic unit 214 may be configured to monitor the comparison result of the second comparator 238 for the second fault operating condition in response to receiving a trigger from the VCC UVLO circuit 234 indicating that the fixed power supply terminal 3 satisfies the VCC UVLO voltage.

[0089] The logic unit 214 can be configured to monitor the comparison result of the second comparator 238 during the monitoring operation for a predetermined time interval. For example, the predetermined time interval can be a startup interval. The predetermined time interval can start at the trigger time of the monitoring operation triggered by the monitoring circuit (for example, triggered by the VCC UVLO circuit 234). In addition, in response to the second comparator 238 not indicating the second fault operation condition (for example, the startup or reset operation is completed) through the predetermined time interval, the logic unit 214 can determine that there is no second fault operation condition and can be configured to start driving the high-side output signal HO and the low-side output signal LO between the corresponding switch states. In addition, the logic unit 214 can be configured to start monitoring the first fault operation condition in response to the predetermined time interval when the low-side transistor 208 is in the on state.

[0090] As mentioned above, Figure 2C Provided as an example only. Other examples may vary from Figure 2CDescribed Examples. For example, in some implementations, additional circuit components can be added without departing from the disclosure provided above.

[0091] Figure 2D is a truth table 200D corresponding to monitoring the second fault operation condition. "LO-COM" refers to the potential difference between LO and COM, "VS-COM" refers to the potential difference between VS and COM, "VDES_L-COM" refers to the potential difference between VDES_L and COM, and "HO-VS" refers to the potential difference between HO and VS. As described above, Figure 2D Provided as an example only. Other examples may vary from Figure 2D Examples described.

[0092] Figure 2E 1 shows a schematic block diagram of a gate driver system 200A according to one or more implementations. In particular, Figure 2E The invention relates to using the half-bridge gate driver 204 to monitor and detect a third fault operating condition, such as a high-side desaturation fault condition. Therefore, the half-bridge gate driver 204 can be configured to monitor such as in combination with Figure 2A and Figure 2B The first fault operation condition described, such as the combination of Figure 2C and Figure 2D The second fault operating condition and / or the third fault operating condition described. The logic unit 214 can be configured to monitor the third fault operating condition when the high-side transistor 206 is in the on state. Therefore, when the high-side output signal HO is high (e.g., the PWM control signal HIN is high), the high-side transistor 206 is turned on, and the phase node 230 is short-circuited to DC- or COM, a third fault operating condition may occur, resulting in a phase voltage VS higher than expected. In other words, under normal operating conditions, the phase voltage VS should be pulled toward DC+ and should be close to the high-side power supply potential (e.g., the phase voltage VS should be different from the high-side power supply potential according to the voltage drop across the high-side transistor 206).

[0093] The logic inverter 244 includes: an inverter input; an inverter output; a first power supply terminal configured to receive a high-side floating power supply voltage VB; and a second power supply terminal configured to receive a phase voltage VS as a high-side floating reference voltage. The inverter input is coupled to the high-side output terminal 7 and is configured to receive a high-side output signal HO as an input signal. The second power supply terminal is coupled to the phase node terminal 6 and is configured to receive the phase voltage VS at the phase node terminal 6 as a high-side floating reference voltage. The logic inverter 244 can be configured to generate an inverter output signal VND at the inverter output based on an input signal (e.g., a high-side output signal HO), a floating power supply voltage (e.g., VB) and a floating reference voltage (e.g., VS). For example, the power supply voltage provided to the logic inverter 244 represents a logical high value and a logical low value at the inverter output. Logic inverter 244 can measure its input and determine whether the input meets a logic high input (e.g., above a threshold) or a logic low input (e.g., below a threshold), and then output one of the power supply voltages VB or VS that is "logically" opposite to the input. Thus, if a logic high input has been received (e.g., if HO is at a logic high value, such as VB), a logic low power supply voltage (e.g., reference power supply voltage VS) will be output by logic inverter 244. Conversely, if a logic low input has been received (e.g., if HO is at a logic low value, such as VS), a logic high power supply voltage (e.g., positive power supply voltage VB) will be output by logic inverter 244. Thus, logic inverter 244 inverts the input signal.

[0094] The voltage level of the inverter output signal VND depends on the logic low power supply voltage and the logic high power supply voltage. For example, the reference (" ground ") power supply terminal of the logic inverter 244 is connected to the phase voltage VS. Therefore, the logic low output of the logic inverter 244 will change based on any change of the phase voltage VS. For example, if the high-side output signal HO is configured to set the high-side transistor 206 to the on-state, the logic inverter 244 is configured to generate the inverter output signal VND with a logic low value proportional to the phase voltage VS. On the other hand, if the high-side output signal HO is configured to set the high-side transistor 206 to the off-state, the logic inverter 244 is configured to generate the inverter output signal VND with a logic high value proportional to the high-side floating power supply voltage VB.

[0095] When there is a short circuit at the low-side transistor 208, the phase voltage VS is pulled down to COM when it should normally be only about 15V lower than VB. Therefore, the logic low value of the logic inverter 244 (e.g., the output when the high-side transistor 206 is turned on) drops far below the normal value. The first comparator 236 is configured to detect that the inverter output signal VND has dropped below the threshold Vth1. It is this change in the logic low output value of the logic inverter 244 that the half-bridge gate driver 204 uses to detect the third fault operating state.

[0096] The low-side output terminal 5 and the first comparator 236 are arranged in the low-side region 218, the high-side output terminal 7 and the phase node terminal 6 are arranged in the high-side region 220, and the bit transfer diode 240 is coupled to the first circuit of the low-side region 218 and the second circuit of the high-side region 220. In some implementations, the bit transfer diode 240 can be arranged in the low-side region 218. In some implementations, the bit transfer diode 240 can be arranged in the isolation region 222.

[0097] The bit transfer diode 240 may be configured to transfer a single bit from the second voltage domain to the first voltage domain of the half-bridge gate driver 204. The single bit may indicate whether a third fault operating condition exists during the on-state interval in which the high-side output signal HO is configured to set the high-side transistor 206 to the on-state.

[0098] The bit transfer diode 240 includes an anode and a cathode. The cathode is coupled to the inverter output terminal for receiving the inverter output signal VND from the inverter output terminal. The anode is coupled to the first input terminal of the first comparator 236. A measurement value VDES_H is provided at the anode of the bit transfer diode 240 based on the inverter output signal VND. For example, the measurement value VDES_H can be clamped to the voltage level of the inverter output signal VND plus the forward voltage VF of the bit transfer diode 240 (for example, VDES_H=VND+VF). Therefore, the measurement value VDES_H can represent the voltage level of the inverter output signal VND. The first comparator 236 includes a second input terminal coupled to a threshold source to receive a threshold value Vth1. The threshold value Vth1 can be generated internally by the half-bridge gate driver 204, for example, by the logic unit 214 based on VCC and a programmable voltage divider.

[0099] The first comparator 236 also includes an output terminal coupled to the logic unit 214. The first comparator 236 can be configured to compare the values ​​at its two input terminals (e.g., the measured value VDES_H and the threshold value Vth1), and output a comparison result indicating whether the measured value VDES_H meets the threshold value Vth1. In other words, the comparison result of the first comparator 236 can indicate whether there is a third fault operation condition. In some implementations, when the measured value VDES_H is greater than the threshold value Vth1, the measured value VDES_H can meet the threshold value Vth1. The comparison result of the first comparator 236 can indicate that the half-bridge gate driver 204 operates normally when the measured value VDES_H meets the threshold value Vth1 (e.g., the measured value VDES_H is greater than the threshold value Vth1), and can indicate that there is a third fault operation condition when the measured value VDES_H does not meet the threshold value Vth1 (e.g., the measured value VDED_H is not greater than the threshold value Vth1). The logic unit 214 may refer to the PWM control signal HIN to determine when the high-side transistor 206 is turned on, and may monitor the comparison result of the first comparator 236 when the high-side transistor 206 is turned on.

[0100] Under normal operating conditions corresponding to a no-fault condition, when the high-side output signal Ho is configured to set the high-side transistor 206 to an on state, and the low-side output signal LO is configured to set the low-side transistor 208 to an off state: the phase voltage VS at the phase node terminal 6 is configured to be pulled toward the high-side power supply potential provided by the DC link positive power supply DC+, the logic inverter 244 is configured to generate an inverter output signal VND having a logic low value representing the phase voltage VS, the measured value VDES_H is pulled to be greater than the threshold value Vth1 through the inverter output signal VND, and the comparison result of the first comparator 236 indicates that the measured value VDES_H meets the threshold, thereby indicating a normal operating condition.

[0101] Under the third fault operating condition, when the high-side output signal HO is configured to set the high-side transistor 206 to the on state, and the low-side output signal LO is configured to set the low-side transistor 208 to the off state: the phase voltage VS at the phase node terminal 6 is configured to be pulled toward the low-side power supply potential provided by the DC link negative power supply DC- or COM, the logic inverter 244 is configured to generate an inverter output signal VND having a logic low value representing the phase voltage VS, the measured value VDES_H is pulled to less than the threshold value Vth1 through the inverter output signal VND, and the comparison result of the first comparator 236 indicates that the measured value VDES_H does not meet the threshold value Vth1, thereby indicating the third fault operating condition. Therefore, under the third fault operating condition, when the high-side output signal HO is configured to set the high-side transistor 206 to the on state, and the low-side output signal LO is configured to set the low-side transistor 208 to the off state: the measured value VDES_H can be clamped to the difference between the forward voltage VF of the bit transfer diode 240 and the voltage drop across the low-side transistor 208, and the difference is less than the threshold Vth1.

[0102] As mentioned above, Figure 2E Provided as an example only. Other examples may vary from Figure 2E Described Examples. For example, in some implementations, additional circuit components can be added without departing from the disclosure provided above.

[0103] Figure 2F is a truth table 200F corresponding to monitoring the third fault operation condition. "HO-VS" refers to the potential difference between HO and VS, "VS-COM" refers to the potential difference between VS and COM, "VND-COM" refers to the potential difference between VND and COM, and "VDES_H-COM" refers to the potential difference between VDES_H and COM. In the truth table 200F, the symbol "~" means "approximately". As described above, Figure 2F Provided as an example only. Other examples may vary from Figure 2F Examples described.

[0104] The following provides an overview of some aspects of the disclosure:

[0105] Aspect 1: A half-bridge gate driver, comprising: a low-side output terminal, which is configured to be coupled to a control terminal of a low-side transistor of a half-bridge and is configured to output a low-side output signal to drive the low-side transistor between switching states; a high-side output terminal, which is configured to be coupled to a control terminal of a high-side transistor of the half-bridge and is configured to output a high-side output signal to drive the high-side transistor between switching states; a phase node terminal, which is configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be switched on when the high-side transistor is turned on In some aspects, the half-bridge gate driver can be configured as a monolithic half-bridge gate driver.

[0106] Aspect 2: A half-bridge gate driver according to Aspect 1, wherein, under normal operating conditions corresponding to a fault-free condition, when the low-side output signal is configured to set the low-side transistor to an on state and the high-side output signal is configured to set the high-side transistor to an off state: the phase voltage at the phase node terminal is configured to be pulled toward the low-side power supply potential, the measured value is pulled to be less than the threshold by the phase voltage, and the comparison result indicates that the measured value does not meet the threshold, thereby indicating the normal operating condition.

[0107] Aspect 3: A half-bridge gate driver according to Aspect 2, wherein, under the normal operating condition, when the low-side output signal is configured to set the low-side transistor to an on state and the high-side output signal is configured to set the high-side transistor to an off state: the measured value is clamped to the difference between the forward voltage of the diode and the voltage drop across the low-side transistor, wherein the difference is less than the threshold.

[0108] Aspect 4: A half-bridge gate driver according to any one of Aspects 1 to 3, wherein, under a fault operating condition, when the low-side output signal is configured to set the low-side transistor to an on state and the high-side output signal is configured to set the high-side transistor to an off state: the phase voltage at the phase node terminal is configured to be pulled toward the high-side power supply potential, the measured value is pulled to be greater than the threshold by the phase voltage, and the comparison result indicates that the measured value meets the threshold, thereby indicating the fault operating condition.

[0109] Aspect 5: The half-bridge gate driver according to any one of Aspects 1 to 4, further comprising: a low-side region, which includes a first circuit operating in a first voltage domain; a high-side region, which includes a second circuit operating in a second voltage domain; and an isolation region, which electrically isolates the low-side region and the high-side region, wherein the low-side output terminal and the comparator are arranged in the low-side region, wherein the high-side output terminal and the phase node terminal are arranged in the high-side region, and wherein the diode is coupled to the first circuit and the second circuit.

[0110] Aspect 6: A half-bridge gate driver according to Aspect 5, wherein the first circuit includes a low-side gate driver coupled to the low-side output terminal, the low-side gate driver is configured to generate the low-side output signal and provide the low-side output signal to the low-side output terminal, and wherein the second circuit includes a high-side gate driver coupled to the high-side output terminal, the high-side gate driver is configured to generate the high-side output signal and provide the high-side output signal to the high-side output terminal.

[0111] Aspect 7: A half-bridge gate driver according to any one of Aspects 1 to 6, wherein, during a startup operation or a reset operation of the half-bridge gate driver, the low-side output signal and the high-side output signal are maintained at a shutdown signal level to set the low-side transistor and the high-side transistor to an off state, wherein, during normal operating conditions of the startup operation or the reset operation, when the low-side output signal and the high-side output signal are maintained at the shutdown signal level: the phase voltage at the phase node terminal is configured to be charged to a voltage level greater than a predefined voltage, the measured value is pulled to be greater than the threshold by the phase voltage, and the comparison result indicates that the measured value meets the threshold, thereby indicating the normal operating condition.

[0112] Aspect 8: The half-bridge gate driver according to Aspect 7, wherein the predefined voltage is an undervoltage lockout (UVLO) voltage.

[0113] Aspect 9: A half-bridge gate driver according to any one of Aspects 1 to 8, wherein, during a startup operation or a reset operation of the half-bridge gate driver, the low-side output signal and the high-side output signal are maintained at a shutdown signal level to set the low-side transistor and the high-side transistor to an off state, wherein, during a fault operation condition of the startup operation or the reset operation, when the low-side output signal and the high-side output signal are maintained at the shutdown signal level: the measured value is pulled to less than the threshold by the phase voltage, and the comparison result indicates that the measured value does not meet the threshold, thereby indicating the fault operation condition.

[0114] Aspect 10: The half-bridge gate driver according to Aspect 9 further includes: a power supply terminal configured to be coupled to a power supply, wherein the power supply terminal is configured to be charged to a power supply potential provided by the power supply during the startup operation or the reset operation of the half-bridge gate driver, and a monitoring circuit configured to monitor the voltage level of the power supply terminal and trigger a monitoring operation of the phase node terminal in response to the voltage level of the power supply terminal satisfying an undervoltage lockout (UVLO) voltage, wherein the monitoring circuit is configured to monitor the comparison result in response to the monitoring operation being triggered.

[0115] Aspect 11: A half-bridge gate driver according to Aspect 10, wherein the monitoring circuit is configured to monitor the comparison result within a predetermined time interval during the monitoring operation, wherein the predetermined time interval starts at a trigger time when the monitoring operation is triggered by the monitoring circuit.

[0116] Aspect 12: A half-bridge gate driver according to aspect 11, wherein, in response to the predetermined time interval not indicating the fault operating condition, the half-bridge gate driver is configured to drive the high-side output signal and the low-side output signal between corresponding switching states.

[0117] Aspect 13: A half-bridge gate driver, comprising: a low-side output terminal, which is configured to be coupled to the control terminal of the low-side transistor of the half-bridge, and is configured to output a low-side output signal to drive the low-side transistor between corresponding switching states; a high-side output terminal, which is configured to be coupled to the control terminal of the high-side transistor of the half-bridge, and is configured to output a high-side output signal to drive the high-side transistor between corresponding switching states; a phase node terminal, which is configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and wherein the phase node terminal is configured to be connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; an inverter, which comprises an inverter input, an inverter output, a first power supply terminal configured to receive a floating power supply voltage, and a first power supply terminal configured to receive a floating power supply voltage. a second power supply terminal configured to receive a floating reference voltage, wherein the inverter input is coupled to the high-side output terminal and is configured to receive the high-side output signal as an input signal, wherein the second power supply terminal is coupled to the phase node terminal and is configured to receive the phase voltage at the phase node terminal as the floating reference voltage, wherein the inverter is configured to generate an inverter output signal at the inverter output terminal based on the input signal, the floating power supply voltage and the floating reference voltage; a diode comprising an anode and a cathode, wherein the cathode is coupled to the inverter output terminal for receiving the inverter output signal from the inverter output terminal; and a comparator comprising a first input terminal coupled to the anode of the diode to receive a measured value representing the inverter output signal, a second input terminal coupled to a threshold source to receive a threshold, and an output terminal configured to output a comparison result indicating whether the measured value meets the threshold. In some aspects, the half-bridge gate driver can be configured as a monolithic half-bridge gate driver.

[0118] Aspect 14: A half-bridge gate driver according to Aspect 13, wherein, under normal operating conditions corresponding to a fault-free condition, when the high-side output signal is configured to set the high-side transistor to an on state and the low-side output signal is configured to set the low-side transistor to an off state: the phase voltage at the phase node terminal is configured to be pulled toward the high-side power supply potential, the inverter is configured to generate the inverter output signal having a logical low value representing the phase voltage, the measured value is pulled to be greater than the threshold through the inverter output signal, and the comparison result indicates that the measured value meets the threshold, thereby indicating the normal operating condition.

[0119] Aspect 15: A half-bridge gate driver according to any one of Aspects 13 to 14, wherein, under a fault operating condition, when the high-side output signal is configured to set the high-side transistor to an on state and the low-side output signal is configured to set the low-side transistor to an off state: the phase voltage at the phase node terminal is configured to be pulled toward the low-side power supply potential, the inverter is configured to generate the inverter output signal having a logical low value representing the phase voltage, the measured value is pulled to be less than the threshold through the inverter output signal, and the comparison result indicates that the measured value does not meet the threshold, thereby indicating the fault operating condition.

[0120] Aspect 16: A half-bridge gate driver according to Aspect 15, wherein, under the fault operating condition, when the high-side output signal is configured to set the high-side transistor to an on state and the low-side output signal is configured to set the low-side transistor to an off state: the measured value is clamped to the difference between the forward voltage of the diode and the voltage drop across the low-side transistor, wherein the difference is less than the threshold.

[0121] Aspect 17: A half-bridge gate driver according to any one of Aspects 13 to 16, wherein, when the high-side output signal is configured to set the high-side transistor to an on state, the inverter is configured to generate the inverter output signal having a logic low value proportional to the phase voltage, and wherein, when the high-side output signal is configured to set the high-side transistor to an off state, the inverter is configured to generate the inverter output signal having a logic high value proportional to the floating supply voltage.

[0122] Aspect 18: The half-bridge gate driver according to any one of Aspects 13 to 17, further comprising: a low-side region comprising a first circuit operating in a first voltage domain; a high-side region comprising a second circuit operating in a second voltage domain; and an isolation region electrically isolating the low-side region and the high-side region, wherein the low-side output terminal and the comparator are arranged in the low-side region, wherein the high-side output terminal and the phase node terminal are arranged in the high-side region, and wherein the diode is coupled to the first circuit and the second circuit.

[0123] Aspect 19: A half-bridge gate driver according to Aspect 18, wherein the diode is a bit transfer diode configured to transfer a single bit from the second voltage domain to the first voltage domain, wherein the single bit indicates whether a fault operating condition exists during an on-state interval in which the high-side output signal is configured to set the high-side transistor to an on-state.

[0124] Aspect 20: A half-bridge gate driver according to Aspect 18, wherein the first circuit includes a low-side gate driver coupled to the low-side output terminal, the low-side gate driver is configured to generate the low-side output signal and provide the low-side output signal to the low-side output terminal, and wherein the second circuit includes a high-side gate driver coupled to the high-side output terminal, the high-side gate driver is configured to generate the high-side output signal and provide the high-side output signal to the high-side output terminal.

[0125] Aspect 21: A method for detecting a faulty operating condition, comprising: generating a low-side output signal to drive a low-side transistor of a half-bridge between corresponding switching states; generating a high-side output signal to drive a high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; providing the high-side output signal as an input signal to an inverter; providing a floating power supply voltage to a first phase of the inverter a power supply terminal; providing the phase voltage generated at the phase node terminal as a floating reference voltage to a second power supply terminal of the inverter; generating an inverter output signal by the inverter based on the input signal, the floating power supply voltage and the floating reference voltage; providing the inverter output signal to a cathode of a diode; and comparing a measured value at an anode of the diode with a threshold value to generate a comparison result indicating whether the measured value meets the threshold value, wherein the measured value represents the inverter output signal of the inverter, and wherein the comparison result indicates whether the fault operating condition exists during an on-state interval in which the high-side output signal sets the high-side transistor to an on-state.

[0126] Aspect 22: A method for detecting a faulty operating condition, comprising: generating a low-side output signal to drive a low-side transistor of a half-bridge between corresponding switching states; generating a high-side output signal to drive a high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on, wherein the voltage at the phase node terminal is a phase voltage; providing the phase voltage to a cathode of a diode; and comparing a measured value at an anode of the diode with a threshold to generate a comparison result indicating whether the measured value meets the threshold, wherein the measured value represents the phase voltage, and wherein the comparison result indicates whether the faulty operating condition exists.

[0127] Aspect 23: A half-bridge gate driver, comprising: a low-side output terminal, which is configured to be coupled to the control terminal of the low-side transistor of the half-bridge, and is configured to output a low-side output signal to drive the low-side transistor between corresponding switching states; a high-side output terminal, which is configured to be coupled to the control terminal of the high-side transistor of the half-bridge, and is configured to output a high-side output signal to drive the high-side transistor between corresponding switching states; a phase node terminal, which is configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be turned on when the high-side transistor is turned on In the case of the low-side transistor being turned on, the phase node terminal is connected to the high-side power supply potential through the high-side transistor, and wherein the phase node terminal is configured to be connected to the low-side power supply potential through the low-side transistor when the low-side transistor is turned on; an inverter, which includes an inverter input, an inverter output, a first power supply terminal configured to receive a floating power supply voltage, and a second power supply terminal configured to receive a floating reference voltage, wherein the inverter input is coupled to the high-side output terminal and is configured to receive the high-side output signal as an input signal, wherein the second power supply terminal is coupled to the phase node terminal and is configured to receive the a first diode including a first anode and a first cathode, wherein the first cathode is coupled to the inverter output terminal for receiving the inverter output signal from the inverter output terminal; a first comparator including a first input terminal coupled to the first anode of the first diode to receive a first measurement value representing the inverter output signal, a second input terminal coupled to a first threshold source to receive a first threshold, and a first output terminal configured to output a first comparison result indicating whether the first measurement value meets the first threshold; a second diode including a second anode and a second cathode, wherein the second cathode is coupled to the phase node terminal; and a second comparator including a third input terminal coupled to the second anode of the second diode to receive a second measurement value indicating the phase voltage at the phase node terminal, a fourth input terminal coupled to a second threshold source to receive a second threshold, and a second output terminal configured to output a second comparison result indicating whether the second measurement value meets the second threshold. In some aspects, the half-bridge gate driver can be configured as a monolithic half-bridge gate driver.

[0128] Aspect 24: A method for detecting multiple fault operating conditions, comprising: generating a low-side output signal to drive a low-side transistor of a half-bridge between corresponding switching states; generating a high-side output signal to drive the high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; providing the high-side output signal as an input signal to an inverter; providing a floating power supply voltage to a first power supply terminal of the inverter; providing a phase voltage generated at the phase node terminal as a floating reference voltage to a second power supply terminal of the inverter; and providing a phase voltage generated at the phase node terminal as a floating reference voltage to a second power supply terminal of the inverter based on the input signal, the floating power supply voltage and the floating A reference voltage generates an inverter output signal; provides the inverter output signal to a first cathode of a first diode; compares a first measurement value at a first anode of the first diode with a first threshold value to generate a first comparison result indicating whether the first measurement value meets the first threshold value, wherein the first measurement value represents the inverter output signal of the inverter, and wherein the first comparison result indicates whether a first fault operating condition exists during an on-state interval in which the high-side output signal sets the high-side transistor to an on-state; provides the phase voltage to a second cathode of a second diode; and compares a second measurement value at a second anode of the second diode with a second threshold value to generate a second comparison result indicating whether the second measurement value meets the second threshold value, wherein the second measurement value represents the phase voltage, and wherein the second comparison result indicates whether a second fault operating condition exists.

[0129] Aspect 25: A system configured to perform one or more operations described in one or more of Aspects 1 to 24.

[0130] Aspect 26: An apparatus comprising means for performing one or more operations as recited in one or more of Aspects 1 to 24.

[0131] Aspect 27: A non-transitory computer-readable medium storing an instruction set, wherein the instruction set includes one or more instructions, and when the one or more instructions are executed by a device, the device causes the device to perform one or more operations described in one or more of aspects 1 to 24.

[0132] Aspect 28: A computer program product comprising instructions or codes for performing one or more operations described in one or more of Aspects 1 to 24.

[0133] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made based on the above disclosure, or may be acquired from practice of the implementation.

[0134] Some implementations may be described herein in conjunction with thresholds. As used herein, "satisfying" a threshold may refer to a value being greater than a threshold, exceeding a threshold, being above a threshold, being greater than or equal to a threshold, being less than a threshold, being less than a threshold, being below a threshold, being less than or equal to a threshold, being equal to a threshold, etc.

[0135] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software codes, and it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0136] Any processing component can be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transitory computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" used in this article refers to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. The software can be stored on a non-transitory computer-readable medium, so that the non-transitory computer-readable medium includes a program code or a program algorithm stored thereon, which causes the processor to perform the steps of the method via a computer program when executed.

[0137] A controller including hardware may also perform one or more of the techniques of the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its reception, analysis, and control functions, which may also include correction functions. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure.

[0138] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive additional information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal so that the signal meets the requirements of the next stage for further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0139] Even if a particular feature combination is listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementation described herein. Many of these features can be combined in a manner not specifically listed in the claims and / or not disclosed in the specification. For example, the disclosure includes each dependent claim in the claim set combined with each other independent claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase "at least one" in the list of items refers to any combination of these items, including a single member. For example, "at least one of a, b or c" is intended to cover a, b, c, a and b, a and c, b and c and a, b and c, and any combination with multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c, or any other order of a, b and c).

[0140] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple actions or functions will not limit these actions or functions to a specific order unless these actions or functions are not interchangeable due to technical reasons. In addition, in some implementations, a single action may include multiple sub-actions or may be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action.

[0141] Unless explicitly stated, any element, action or instruction used in this article should not be interpreted as key or necessary. In addition, as used in this article, the article "a" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used in this article, the article "the" is intended to include one or more projects quoted in combination with the article "the", and can be used interchangeably with "one or more". In the case of being intended to only one project, phrases "only one", "single" or similar language are used. In addition, as used in this article, the term "has", "have", "having" etc. are intended to be open terms (for example, "having" A elements can also have B) that do not limit the elements modified. In addition, unless otherwise clearly stated, the phrase "based on" is intended to mean "based on at least in part". As used in this article, the term "multiple" can be replaced with "a plurality of", and vice versa. Furthermore, as used herein, the term "or" when used in series is intended to be inclusive and may be used interchangeably with "and / or" unless expressly stated otherwise (eg, if used in conjunction with "either" or "only one").

Claims

1. A half-bridge gate driver, comprising: a low-side output terminal configured to be coupled to a control terminal of a low-side transistor of the half-bridge and configured to output a low-side output signal to drive the low-side transistor between switching states; a high-side output terminal configured to be coupled to a control terminal of a high-side transistor of the half-bridge and configured to output a high-side output signal to drive the high-side transistor between switching states; a phase node terminal configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be connected to a high-side power supply potential through the high-side transistor if the high-side transistor is turned on, and wherein the phase node terminal is configured to be connected to a low-side power supply potential through the low-side transistor if the low-side transistor is turned on; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and A comparator includes a first input terminal coupled to the anode of the diode to receive a measurement value indicating the phase voltage at the phase node terminal, a second input terminal coupled to a threshold source to receive a threshold value, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold value.

2. The half-bridge gate driver according to claim 1, wherein: Under normal operating conditions corresponding to a non-fault condition, where the low-side output signal is configured to set the low-side transistor to an on-state and the high-side output signal is configured to set the high-side transistor to an off-state: The phase voltage at the phase node terminal is configured to be pulled toward the low-side supply potential, The measured value is pulled below the threshold by the phase voltage, and The comparison result indicates that the measured value does not meet the threshold value, thereby indicating the normal operating condition.

3. The half-bridge gate driver according to claim 2, wherein: Under the normal operating condition, where the low-side output signal is configured to set the low-side transistor to an on-state and the high-side output signal is configured to set the high-side transistor to an off-state: The measurement is clamped to a difference between a forward voltage of the diode and a voltage drop across the low-side transistor, wherein the difference is less than the threshold.

4. The half-bridge gate driver according to claim 1, wherein: Under a fault operating condition, where the low-side output signal is configured to set the low-side transistor to an on-state and the high-side output signal is configured to set the high-side transistor to an off-state: The phase voltage at the phase node terminal is configured to be pulled towards the high-side supply potential, The measured value is pulled above the threshold by the phase voltage, and The comparison result indicates that the measured value satisfies the threshold value, thereby indicating the faulty operating condition.

5. The half-bridge gate driver according to claim 1 , further comprising: a low-side region including a first circuit operating in a first voltage domain; a high-side region including a second circuit operating in a second voltage domain; as well as an isolation region that electrically isolates the low-side region from the high-side region, wherein the low-side output terminal and the comparator are arranged in the low-side region, wherein the high-side output terminal and the phase node terminal are arranged in the high-side region, and The diode is coupled to the first circuit and the second circuit.

6. The half-bridge gate driver according to claim 5, wherein: The first circuit includes a low-side gate driver coupled to the low-side output terminal, the low-side gate driver being configured to generate the low-side output signal and provide the low-side output signal to the low-side output terminal, and The second circuit includes a high-side gate driver coupled to the high-side output terminal, wherein the high-side gate driver is configured to generate the high-side output signal and provide the high-side output signal to the high-side output terminal.

7. The half-bridge gate driver according to claim 1, wherein: The half-bridge gate driver is configured as a monolithic half-bridge gate driver.

8. The half-bridge gate driver according to claim 1, wherein: During a startup operation or a reset operation of the half-bridge gate driver, the low-side output signal and the high-side output signal are maintained at a turn-off signal level to set the low-side transistor and the high-side transistor to a turn-off state, Wherein, during the normal operation condition of the startup operation or the reset operation, when the low-side output signal and the high-side output signal are maintained at the shutdown signal level: The phase voltage at the phase node terminal is configured to be charged to a voltage level greater than a predefined voltage, The measured value is pulled above the threshold by the phase voltage, and The comparison result indicates that the measured value satisfies the threshold value, thereby indicating the normal operating condition.

9. The half-bridge gate driver according to claim 8, wherein: The predefined voltage is an under voltage lockout voltage.

10. The half-bridge gate driver according to claim 1, wherein: During a startup operation or a reset operation of the half-bridge gate driver, the low-side output signal and the high-side output signal are maintained at a turn-off signal level to set the low-side transistor and the high-side transistor to a turn-off state, Wherein, during the fault operation condition of the startup operation or the reset operation, when the low-side output signal and the high-side output signal are maintained at the shutdown signal level: The measured value is pulled below the threshold by the phase voltage, and The comparison result indicates that the measured value does not satisfy the threshold value, thereby indicating the faulty operating condition.

11. The half-bridge gate driver according to claim 10, further comprising: a power supply terminal configured to be coupled to a power supply, wherein the power supply terminal is configured to be charged to a power supply potential provided by the power supply during the startup operation or the reset operation of the half-bridge gate driver, a monitoring circuit configured to monitor a voltage level of the power supply terminal and trigger a monitoring operation of the phase node terminal in response to the voltage level of the power supply terminal satisfying an undervoltage lockout voltage, The monitoring circuit is configured to monitor the comparison result in response to the monitoring operation being triggered.

12. The half-bridge gate driver according to claim 11, wherein: The monitoring circuit is configured to monitor the comparison result within a predetermined time interval during the monitoring operation, wherein the predetermined time interval starts at a triggering time when the monitoring operation is triggered by the monitoring circuit.

13. The half-bridge gate driver according to claim 12, wherein: The half-bridge gate driver is configured to, in response to the predetermined time interval passing without indicating the faulty operating condition, drive the high-side output signal and the low-side output signal between respective switching states.

14. A half-bridge gate driver, comprising: a low-side output terminal configured to be coupled to a control terminal of a low-side transistor of the half-bridge and configured to output a low-side output signal to drive the low-side transistor between corresponding switching states; a high-side output terminal configured to be coupled to a control terminal of a high-side transistor of the half-bridge and configured to output a high-side output signal to drive the high-side transistor between corresponding switching states; a phase node terminal configured to be coupled to a phase node coupled to the high-side transistor and the low-side transistor, wherein the phase node terminal is configured to be connected to a high-side power supply potential through the high-side transistor if the high-side transistor is turned on, and wherein the phase node terminal is configured to be connected to a low-side power supply potential through the low-side transistor if the low-side transistor is turned on; an inverter comprising an inverter input, an inverter output, a first power supply terminal configured to receive a floating power supply voltage, and a second power supply terminal configured to receive a floating reference voltage, wherein the inverter input terminal is coupled to the high-side output terminal and is configured to receive the high-side output signal as an input signal, wherein the second power supply terminal is coupled to the phase node terminal and is configured to receive the phase voltage at the phase node terminal as the floating reference voltage, wherein the inverter is configured to generate an inverter output signal at the inverter output terminal based on the input signal, the floating supply voltage and the floating reference voltage; a diode comprising an anode and a cathode, wherein the cathode is coupled to the inverter output terminal for receiving the inverter output signal from the inverter output terminal; and A comparator includes a first input terminal coupled to the anode of the diode to receive a measurement value representing the inverter output signal, a second input terminal coupled to a threshold source to receive a threshold value, and an output terminal configured to output a comparison result indicating whether the measurement value meets the threshold value.

15. The half-bridge gate driver according to claim 14, wherein: Under normal operating conditions corresponding to a non-fault condition, where the high-side output signal is configured to set the high-side transistor to an on-state and the low-side output signal is configured to set the low-side transistor to an off-state: The phase voltage at the phase node terminal is configured to be pulled towards the high-side supply potential, the inverter being configured to generate an inverter output signal having a logic low value representative of the phase voltage, The measured value is pulled above the threshold by the inverter output signal, and The comparison result indicates that the measured value satisfies the threshold value, thereby indicating the normal operating condition.

16. The half-bridge gate driver according to claim 14, wherein: Under a fault operating condition, where the high-side output signal is configured to set the high-side transistor to an on-state and the low-side output signal is configured to set the low-side transistor to an off-state: The phase voltage at the phase node terminal is configured to be pulled toward the low-side supply potential, the inverter being configured to generate an inverter output signal having a logic low value representative of the phase voltage, The measured value is pulled below the threshold value by the inverter output signal, and The comparison result indicates that the measured value does not satisfy the threshold value, thereby indicating the faulty operating condition.

17. The half-bridge gate driver according to claim 16, wherein: Under the fault operating condition, where the high-side output signal is configured to set the high-side transistor to an on-state and the low-side output signal is configured to set the low-side transistor to an off-state: The measurement is clamped to a difference between a forward voltage of the diode and a voltage drop across the low-side transistor, wherein the difference is less than the threshold.

18. The half-bridge gate driver according to claim 14, wherein: The inverter is configured to generate an inverter output signal having a logic low value proportional to the phase voltage if the high-side output signal is configured to set the high-side transistor to an on state, and Wherein, the inverter is configured to generate an inverter output signal having a logic high value proportional to the floating supply voltage when the high-side output signal is configured to set the high-side transistor to an off state.

19. The half-bridge gate driver of claim 14, further comprising: a low-side region including a first circuit operating in a first voltage domain; a high-side region including a second circuit operating in a second voltage domain; as well as an isolation region that electrically isolates the low-side region from the high-side region, wherein the low-side output terminal and the comparator are arranged in the low-side region, wherein the high-side output terminal and the phase node terminal are arranged in the high-side region, and The diode is coupled to the first circuit and the second circuit.

20. The half-bridge gate driver according to claim 19, wherein the diode being a bit transfer diode configured to transfer a single bit from the second voltage domain to the first voltage domain, wherein the single bit indicates whether a fault operating condition exists during an on-state interval in which the high-side output signal is configured to set the high-side transistor to an on-state.

21. The half-bridge gate driver according to claim 19, wherein: The first circuit includes a low-side gate driver coupled to the low-side output terminal, the low-side gate driver being configured to generate the low-side output signal and provide the low-side output signal to the low-side output terminal, and The second circuit includes a high-side gate driver coupled to the high-side output terminal, wherein the high-side gate driver is configured to generate the high-side output signal and provide the high-side output signal to the high-side output terminal.

22. The half-bridge gate driver according to claim 14, wherein: The half-bridge gate driver is configured as a monolithic half-bridge gate driver.

23. A method for detecting a faulty operating condition, comprising: generating a low-side output signal to drive a low-side transistor of the half-bridge between corresponding switching states; generating a high-side output signal to drive a high-side transistor of the half-bridge between corresponding switching states, wherein the high-side transistor and the low-side transistor are coupled to a phase node terminal, wherein the phase node terminal is connected to a high-side power supply potential through the high-side transistor when the high-side transistor is turned on, and the phase node terminal is connected to a low-side power supply potential through the low-side transistor when the low-side transistor is turned on; providing the high-side output signal as an input signal to an inverter; providing a floating supply voltage to a first supply terminal of the inverter; providing a phase voltage generated at the phase node terminal as a floating reference voltage to a second power supply terminal of the inverter; generating an inverter output signal by the inverter based on the input signal, the floating supply voltage and the floating reference voltage; providing the inverter output signal to a cathode of a diode; and comparing a measured value at the anode of the diode with a threshold value to generate a comparison result indicating whether the measured value meets the threshold value, wherein the measured value represents the inverter output signal of the inverter, and The comparison result indicates whether the faulty operating condition exists during an on-state interval in which the high-side output signal sets the high-side transistor to an on-state.

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