Driving circuit of parallel transistors, driving chip and cascade driving circuit

Abstract

The invention discloses a driving circuit of parallel transistors, a driving chip and a cascade driving circuit. The driving circuit comprises a pulse width modulation signal input end and at least one current detection end in one-to-one correspondence with the at least one transistor; the pulse width modulation signal input end is used for inputting a pulse width modulation signal of a control electrode of the control transistor; the current detection end is electrically connected with the first electrode of the transistor; the driving circuit further comprises a control unit and at least one current detection unit. The current detection unit is used for detecting source-drain current of the transistor; the second end of the current detection unit is electrically connected with the control unit; the control unit is electrically connected with the pulse width modulation signal input end, and the control unit is used for receiving the source and drain current of a preset transistor in the parallel transistors and adjusting the delay time of the conduction level of the pulse width modulation signal output to the transistors according to the current detected by the current detection unit and the source and drain current of the preset transistor. According to the invention, the current sharing effect can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor driving, and in particular to a driving circuit, a driving chip and a cascade driving circuit of parallel transistors. Background Art

[0002] In modern electronic technology, transistors are widely used, and the corresponding requirements for transistor driving are becoming increasingly higher.

[0003] Among various transistors, transistors made of third-generation semiconductor materials such as GaN (gallium nitride) and SiC (silicon carbide) have a wider energy gap, better breakdown field strength, thermal conductivity, electron saturation velocity and radiation resistance, and are more conducive to applications such as higher switching frequencies and higher output powers.

[0004] When GaN transistors are used, multiple GaN transistors are usually used in parallel to accommodate higher power. However, due to the influence of GaN process and materials, the electrical parameters of different GaN transistors will be different. When used in parallel, the differences in the transistors themselves will cause different conduction currents of the transistors, making the probability of failure of the parallel transistors higher. Summary of the invention

[0005] The present invention provides a driving circuit, a driving chip and a cascade driving circuit of parallel transistors, so as to balance the driving currents of the parallel transistors and achieve a current balance effect.

[0006] According to one aspect of the present invention, there is provided a driving circuit for parallel transistors, the parallel transistors comprising at least two transistors connected in parallel, the driving circuit being used to drive at least one of the parallel transistors, the driving circuit comprising a pulse width modulation signal input terminal and at least one current detection terminal corresponding one-to-one to the at least one transistor;

[0007] The pulse width modulation signal input terminal is used to input a pulse width modulation signal for controlling the control electrode of the transistor; the current detection terminal is used to be electrically connected to the first electrode of the transistor;

[0008] The driving circuit further comprises a control unit and at least one current detection unit corresponding one-to-one to the at least one current detection terminal;

[0009] The first end of the current detection unit is electrically connected to the current detection end, and is used to detect the source-drain current of the transistor; the second end of the current detection unit is electrically connected to the control unit;

[0010] The control unit is electrically connected to the pulse width modulation signal input terminal, and is used to receive the source-drain current of the preset transistor in the parallel transistor, and adjust the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the current detected by the current detection unit and the source-drain current of the preset transistor.

[0011] Optionally, the control unit is used to determine the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the difference between the current detected by the current detection unit and the source / drain current of the preset transistor when the current detected by the current detection unit is greater than the source / drain current of the preset transistor.

[0012] Optionally, the control unit includes: at least one sub-control unit corresponding to the at least one current detection unit on a one-to-one basis, the sub-control unit including:

[0013] a first comparator, a differential amplifier, a second comparator and a pulse width controller,

[0014] The first input terminal of the first comparator is electrically connected to the second terminal of the current detection unit, the second input terminal of the first comparator is connected to the source-drain current of the preset transistor, and the output terminal of the first comparator is electrically connected to the control terminal of the pulse width controller;

[0015] The first input terminal of the differential amplifier is electrically connected to the second terminal of the current detection unit, the second input terminal of the differential amplifier is connected to the source-drain current of the preset transistor, and the output terminal of the differential amplifier is electrically connected to the first input terminal of the second comparator;

[0016] The second input terminal of the second comparator is used to input a preset triangular wave; the output terminal of the second comparator is electrically connected to the pulse width controller;

[0017] The pulse width controller is electrically connected to the pulse width modulation signal input terminal, and is used to enable a delay function of the pulse width controller when the current detected by the current detection unit is greater than the source-drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator.

[0018] Optionally, each of the driving circuits includes one current detection unit and one sub-control unit;

[0019] The driving circuit further comprises a current output terminal and a current input terminal; the current input terminal is used to be electrically connected to the current output terminal of other driving circuits, and the current output terminal is used to be electrically connected to the current input terminal of other driving circuits; wherein the other driving circuit has the same structure as the driving circuit;

[0020] The second input terminal of the first comparator is electrically connected to the current input terminal, the second input terminal of the differential amplifier is electrically connected to the current input terminal; the second terminal of the current detection unit is electrically connected to the current output terminal;

[0021] Alternatively, each of the driving circuits comprises two of the current detection units and two of the sub-control units;

[0022] The second input terminal of the first comparator is electrically connected to the second terminal of another current detection unit; the second input terminal of the differential amplifier is electrically connected to the second terminal of another current detection unit

[0023] Alternatively, each of the driving circuits comprises at least three of the current detection units and at least three of the sub-control units;

[0024] The driving circuit also includes a selection unit, at least three input terminals of the selection unit are electrically connected to the second terminals of the at least three current detection units in a one-to-one correspondence, the output terminal of the selection unit is electrically connected to the second input terminal of the first comparator in each of the sub-control units and the second input terminal of the differential amplifier, and the selection unit is used to select the minimum value output among its input terminals.

[0025] Optionally, the current detection unit includes a Hall sensor.

[0026] Optionally, the drive circuit also includes: at least one driver corresponding one-to-one to the at least one transistor, the input end of the driver being electrically connected to the output end of the control unit, the driver being used to modulate the pulse width modulation signal output by the control unit and output a first signal from its first output end to drive the transistor to turn on, and output a second signal from its second output end to drive the transistor to turn off; the drive circuit also includes a first signal output end and a second signal output end, the first signal output end being electrically connected to the corresponding first output end of the driver, and the second signal output end being electrically connected to the corresponding second output end of the driver.

[0027] According to another aspect of the present invention, a driving chip is provided. The driving chip includes the driving circuit of the parallel transistors as described above.

[0028] According to another aspect of the present invention, there is provided a cascade driving circuit for driving at least two transistors connected in parallel, wherein the cascade driving circuit comprises at least two driving circuits as described above.

[0029] Optionally, the cascade driving circuit includes a first driving circuit and a second driving circuit, a total of two driving circuits;

[0030] The control unit comprises: at least one sub-control unit corresponding to the at least one current detection unit, the sub-control unit comprises: a first comparator, a differential amplifier, a second comparator and a pulse width controller, the first input end of the first comparator is electrically connected to the second end of the current detection unit, the second input end of the first comparator is connected to the source-drain current of the preset transistor, and the output end of the first comparator is electrically connected to the control end of the pulse width controller; the first input end of the differential amplifier is electrically connected to the second end of the current detection unit, the second input end of the differential amplifier is connected to the source-drain current of the preset transistor, and the output end of the differential amplifier is electrically connected to the first input end of the second comparator; the second input end of the second comparator is used to input a preset triangular wave; the output end of the second comparator is electrically connected to the pulse width controller; the pulse width controller is electrically connected to the pulse width modulation signal input end, and the pulse width controller is used to enable the delay function of the pulse width controller when the current detected by the current detection unit is greater than the source-drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator; each of the driving circuits comprises one current detection unit and one sub-control unit;

[0031] The current input terminal of the first driving circuit is electrically connected to the current output terminal of the second driving circuit, and the current output terminal of the first driving circuit is electrically connected to the current input terminal of the second driving circuit.

[0032] Optionally, the control unit includes: at least one sub-control unit corresponding to the at least one current detection unit, the sub-control unit includes: a first comparator, a differential amplifier, a second comparator and a pulse width controller, the first input end of the first comparator is electrically connected to the second end of the current detection unit, the second input end of the first comparator is connected to the source and drain current of the preset transistor, and the output end of the first comparator is electrically connected to the control end of the pulse width controller; the first input end of the differential amplifier is electrically connected to the second end of the current detection unit, the second input end of the differential amplifier is connected to the source and drain current of the preset transistor, and the output end of the differential amplifier is electrically connected to the first input end of the second comparator; the second input end of the second comparator is used to input a preset triangular wave; the output end of the second comparator is electrically connected to the pulse width controller; the pulse width controller is electrically connected to the pulse width modulation signal input end, and the pulse width controller is used to enable the delay function of the pulse width controller when the current detected by the current detection unit is greater than the source and drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator; each of the driving circuits includes one current detection unit and one sub-control unit;

[0033] The cascade drive circuit includes at least three drive circuits; the cascade drive circuit also includes a current selection module; the current output end of the drive circuit is electrically connected to the input end of the current selection module in a one-to-one correspondence, and the output end of the current selection module is electrically connected to the current input end of the drive circuit; the current selection module is used to compare the currents of the current output ends of the at least three drive circuits, and output the smallest current from its output end.

[0034] The technical solution of the embodiment of the present invention adopts a parallel transistor driving circuit, including a pulse width modulation signal input terminal and at least one current detection terminal corresponding to at least one transistor; the pulse width modulation signal input terminal is used to input a pulse width modulation signal of a control electrode of the control transistor; the current detection terminal is used to be electrically connected to the first electrode of the transistor; the driving circuit also includes a control unit and at least one current detection unit corresponding to at least one current detection terminal; the first end of the current detection unit is electrically connected to the current detection terminal, and is used to detect the source and drain current of the transistor; the second end of the current detection unit is electrically connected to the control unit; the control unit is electrically connected to the pulse width modulation signal input terminal, and the control unit is used to receive the source and drain current of the preset transistor in the parallel transistor, and adjust the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the current detected by the current detection unit and the source and drain current of the preset transistor. By comparing the source and drain current of the driven transistor with the source and drain current of the preset transistor, the conduction level of the driven transistor is delayed, so that the preset transistor and the driven transistor are compensated towards the same source and drain current, so that the current of all transistors in the parallel transistor tends to be the same when they are turned on, that is, the current balancing effect is achieved. In addition, since the current is balanced between different transistors, the problem of uneven temperature of different transistors can be improved and the risk of thermal failure can be reduced.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of a circuit structure of a driving circuit of parallel transistors provided in an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a circuit structure in which a parallel transistor is connected to a driving circuit according to an embodiment of the present invention;

[0039] Figure 3 A timing diagram of a driving circuit of parallel transistors provided in an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the circuit structure of another driving circuit of parallel transistors provided in an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of the circuit structure of another driving circuit of parallel transistors provided in an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of the circuit structure of another driving circuit of parallel transistors provided in an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of a circuit structure of a cascade drive circuit provided by an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of the circuit structure of another cascade driving circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1A schematic diagram of a circuit structure of a driving circuit of parallel transistors provided in an embodiment of the present invention, referring to Figure 1 , the driving circuit 11 is used to drive at least one transistor in the parallel transistor, wherein the parallel transistor includes at least two transistors in parallel. The driving circuit includes: a pulse width modulation signal input terminal PWM and at least one current detection terminal CS corresponding to at least one transistor; the pulse width modulation signal input terminal is used to input a pulse width modulation signal of a control electrode of the control transistor; the current detection terminal CS is used to be electrically connected to the first electrode of the transistor; the driving circuit also includes a control unit 112 and at least one current detection unit 111 corresponding to at least one current detection terminal CS; the first end of the current detection unit 111 is electrically connected to the current detection terminal CS, and is used to detect the source and drain current of the transistor; the second end of the current detection unit 111 is electrically connected to the control unit 112; the control unit 112 is electrically connected to the pulse width modulation signal input terminal PWM, and the control unit 112 is used to receive the source and drain current of the preset transistor in the parallel transistor, and adjust the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the current detected by the current detection unit 111 and the source and drain current of the preset transistor.

[0048] Specifically, Figure 2 A schematic diagram of a circuit structure of a parallel transistor connected to a drive circuit according to an embodiment of the present invention, referring to Figure 1 and Figure 2 The parallel transistor 20 includes at least two transistors connected in parallel. Figure 2 Two transistors connected in parallel are shown, namely, a first transistor Q1 and a second transistor Q2. The transistor may be a gallium nitride transistor or a silicon carbide transistor, etc. The transistors are connected in parallel in that the sources of the transistors are electrically connected to each other, and the drains of the transistors are electrically connected to each other, wherein the source of each transistor can be connected to a source voltage V_BULK, and the drain of each transistor can be grounded. In addition, the first electrode of the transistor is, for example, a drain, the second electrode is, for example, a source, and the control electrode is, for example, a gate.

[0049] The driving circuit 11 is used to drive at least one transistor in the parallel transistor 20, which means that one driving circuit 11 can drive one transistor in the parallel transistor 20, or at least two transistors in the parallel transistor 20, such as driving all transistors in the parallel transistor 20. The driving circuit 11 can adjust the pulse width modulation signal to a signal that can drive the transistor to turn on and off and then output it to control the control electrode (i.e., the gate) of the corresponding transistor. For example, the voltage level of the pulse width modulation signal can be adjusted to the voltage level that controls the on state of the transistor. The duty cycle of the on level in the pulse width modulation signal controls the on time of the transistor. The on level is, for example, a high level, and the corresponding off level is a low level.

[0050] In this embodiment, one driving circuit 11 can drive at least one transistor, but the driving circuit 11 can control the driven transistor according to the conduction current of all transistors in the parallel transistor 20. Specifically, for the transistor driven by the driving circuit 11 (which can be defined as the transistor to be adjusted), the control unit 112 obtains the source-drain current (Ids) of the transistor to be adjusted through the current detection unit 111 corresponding to the transistor to be adjusted, and the control unit 112 can receive the source-drain current of the preset transistor in the parallel transistor 20. Wherein, when the parallel transistor is two transistors in parallel, the preset transistor can be another transistor other than the transistor to be driven (the transistor to be adjusted); when the parallel transistor is at least three transistors in parallel, the preset transistor can be the transistor with the smallest source-drain current when turned on in the parallel transistor, and the specific determination method of the preset transistor will be described later. In the initial stage, all transistors in the parallel transistor are turned on at the same time and turned off at the same time; due to the different inherent properties of different transistors, the source-drain currents of different transistors are different when they are turned on at the same time. The control unit 112 compares the source-drain current of the transistor to be adjusted with the source-drain current of the preset transistor. If the source-drain current of the transistor to be adjusted is greater than the source-drain current of the preset transistor, the conduction level of the pulse width modulation signal output to the gate of the transistor to be adjusted can be controlled to be delayed, wherein the delay means the conduction level of the pulse width modulation signal inputted at the pulse width modulation signal input terminal. For the preset transistor, the conduction level of the preset transistor is not delayed, and thus, the transistor to be adjusted is delayed compared to the turn-on and turn-off moments of the preset transistor. Since, in the parallel transistors, the source-drain current of the transistor turned on first is larger, and the source-drain current of the transistor turned on later is relatively smaller, therefore, by delaying the turn-on, the source-drain current of the transistor with a larger inherent source-drain current when turned on is compensated in the direction of a smaller source-drain current, and the source-drain current of the transistor with a smaller inherent source-drain current when turned on is compensated in the direction of a larger source-drain current, so that the source-drain current of each transistor in the parallel transistor is closer when turned on, and the current sharing effect is achieved.

[0051] The technical solution of this embodiment adopts a parallel transistor driving circuit, including a pulse width modulation signal input terminal and at least one current detection terminal corresponding to at least one transistor; the pulse width modulation signal input terminal is used to input a pulse width modulation signal of a control electrode of the control transistor; the current detection terminal is used to be electrically connected to the first electrode of the transistor; the driving circuit also includes a control unit and at least one current detection unit corresponding to at least one current detection terminal; the first end of the current detection unit is electrically connected to the current detection terminal, and is used to detect the source and drain current of the transistor; the second end of the current detection unit is electrically connected to the control unit; the control unit is electrically connected to the pulse width modulation signal input terminal, and the control unit is used to receive the source and drain current of the preset transistor in the parallel transistor, and adjust the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the current detected by the current detection unit and the source and drain current of the preset transistor. By comparing the source and drain current of the driven transistor with the source and drain current of the preset transistor, the conduction level of the driven transistor is delayed, so that the preset transistor and the driven transistor are compensated towards the same source and drain current, so that the current of all transistors in the parallel transistor tends to be the same when they are turned on, that is, the current balancing effect is achieved. In addition, since the current is balanced between different transistors, the problem of uneven temperature of different transistors can be improved and the risk of thermal failure can be reduced.

[0052] It should be noted that the pulse width modulation signal is a periodic signal, which can detect the source and drain current of each transistor in one cycle, and adjust the delay of the conduction level of the pulse width modulation signal corresponding to the transistor to be adjusted in the next cycle. In addition, the conduction process of the transistor is divided into a starting stage and a stable stage. In the starting stage, the source and drain current of the transistor increases rapidly to a peak value and then decreases, while in the stable stage, the source and drain current of the transistor are the same. The source and drain current of the transistor described in this article refers to the maximum value of the source and drain current of the transistor during the conduction process.

[0053] Optionally, the control unit 112 is used to determine the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the difference between the current detected by the current detection unit 111 and the source / drain current of the preset transistor when the current detected by the current detection unit 111 is greater than the source / drain current of the preset transistor.

[0054] Specifically, the delay time of the conduction level of the pulse width modulation signal of the transistor is proportional to the above difference. The larger the difference is, the longer the delay time is; correspondingly, the smaller the difference is, the shorter the delay time is.

[0055] Optionally, Figure 3 A timing diagram of a driving circuit of parallel transistors provided in an embodiment of the present invention, combined with Figures 1 to 3The control unit 112 includes at least one sub-control unit 1120 corresponding to at least one current detection unit 111, and the sub-control unit 1120 includes: a first comparator 1121, a differential amplifier 1122, a second comparator 1123 and a pulse width controller 1124; the first input terminal of the first comparator 1121 is electrically connected to the second terminal of the current detection unit 111, the second input terminal of the first comparator 1121 is connected to the source-drain current of the preset transistor, and the output terminal of the first comparator 1121 is electrically connected to the control terminal of the pulse width controller 1124; the first input terminal of the differential amplifier 1122 is electrically connected to the second terminal of the current detection unit 111, the differential amplifier 1122 is electrically connected to the second terminal of the current detection unit 111, and the second input terminal of the first comparator 1123 is connected to the source-drain current of the preset transistor. The second input terminal of the differential amplifier 1122 is connected to the source-drain current of the preset transistor, and the output terminal of the differential amplifier 1122 is electrically connected to the first input terminal of the second comparator 1123; the second input terminal of the second comparator 1123 is used to input a preset triangular wave; the output terminal of the second comparator 1123 is electrically connected to the pulse width controller 1124; the pulse width controller 1124 is electrically connected to the pulse width modulation signal input terminal PWM, and the pulse width controller 1124 is used to enable the delay function of the pulse width controller 1124 when the current detected by the current detection unit 111 is greater than the source-drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator 1123.

[0056] Specifically, Figure 3 As shown, in this embodiment, taking the driving circuit driving two transistors as an example, the preset transistor is another transistor other than the transistor to be adjusted. For the first transistor Q1, in the first cycle of the pulse width modulation signal, at time t1, the first transistor Q1 and the second transistor Q2 are turned on, and the current detection unit 111 corresponding to the first transistor Q1 detects the source-drain current (Ids) of the first transistor Q1. The first comparator compares that the maximum value of the source-drain current of the first transistor Q1 is greater than the maximum value of the source-drain current (Ids) of the second transistor Q2, then the first comparator 1121 outputs an enable signal, such as a high level output, so that the pulse width controller 1124 in the control subunit 1120 corresponding to the first transistor Q1 is enabled. In the next cycle, the pulse width controller 1124 will delay the conduction level of the pulse width modulation signal input by the pulse width modulation signal input terminal PWM. As for the control subunit corresponding to the second transistor Q2, since the first comparator compares that the source-drain current of the second transistor Q2 is smaller than the source-drain current of the first transistor Q1, the first comparator will not output an enable signal, such as a low level. In the next cycle, the pulse width controller will not delay the conduction level of the pulse width modulation signal inputted from the pulse width modulation signal input terminal. Figure 4 As shown, in the next cycle, at time t2, the conduction level of the second transistor Q2 arrives, and the second transistor Q2 starts to be turned on. However, since the conduction level of the first transistor is delayed, the first transistor Q1 is still in the off state at time t2.

[0057] For the control subunit corresponding to the first transistor Q1, the differential amplifier 1122 amplifies the difference between the source-drain current of the first transistor and the source-drain current of the second transistor, and outputs it to the first input terminal of the second comparator 1123. The period of the preset triangular wave input to the second input terminal of the second comparator 1123 is the same as the period of the pulse width modulation signal. In each period, the difference between the source-drain current of the first transistor and the source-drain current of the second transistor is compared with the triangular wave. When the difference is different, the duty cycle of the output signal of the second comparator is different. For example, when the amplified difference is greater than the triangular wave, the second comparator outputs a high level, and when the amplified difference is less than the triangular wave, the second comparator outputs a low level. As a result, different differences will cause the second comparator to output signals with different duty cycles. The pulse width controller 1124 uses the duration of the high level of the output signal of the second comparator as the delay time of the conduction level, such as Figure 4 As shown, in the first cycle, the delay time required for the conduction level is calculated to be t3-t2, then at the moment t2+(t3-t2), that is, at the moment t3, the first transistor Q1 will be turned on. As a result, the source-drain current when the first transistor Q1 and the second transistor Q2 are turned on can be compensated to the same source-drain current value to achieve a current sharing effect. Of course, it is understandable that the first transistor Q1 may need to go through multiple cycles of compensation to achieve the same effect as the source-drain current when the second transistor Q1 is turned on.

[0058] In addition, the first comparator 1121 may be a comparator with a storage function to compare the maximum value of the source-drain current. The differential amplifier 1122 may be a differential amplifier with a storage function to make a difference between the maximum values ​​of the two input terminals and amplify them. The pulse width controller is, for example, a PWM controller.

[0059] It should be noted that, in this embodiment, the amplitude of the driving voltage Vdrive of the transistor in different periods remains unchanged.

[0060] In some embodiments, optionally, reference Figure 1 , each driving circuit drives a transistor. The driving circuit includes a current detection unit 111 and a sub-control unit 1120. The driving circuit also includes a current output terminal Isenso and a current input terminal Isensi; the current input terminal Isensi is used to be electrically connected to the current input terminal of other driving circuits, and the current output terminal Isenso is used to be electrically connected to the current input terminal of other driving circuits; wherein the other driving circuits have the same structure as the driving circuit. The second input terminal of the first comparator 1121 is electrically connected to the current input terminal Isensi; the second terminal of the current detection unit 111 is electrically connected to the current output terminal Isenso.

[0061] Specifically, in this embodiment, each driving circuit drives only one transistor, and different driving circuits can be cascaded to drive parallel transistors. The current input terminal Isensi is used to input the source-drain current corresponding to the preset transistor. For example, when two driving circuits are cascaded, the current input terminal Isenso of one driving circuit is connected to the current output terminal of another driving circuit, that is, electrically connected to the second terminal of the current detection unit 111 of the other driving circuit, so that the current input terminal Isensi inputs the source-drain current of the preset transistor. Similarly, the current output terminal Isenso outputs the source-drain current of the transistor detected by the driving circuit to the outside for reference by other driving circuits, such as the source-drain current of the preset transistor corresponding to other driving circuits.

[0062] In some other embodiments, optionally, Figure 4 As shown, Figure 4 A circuit structure diagram of another parallel transistor driving circuit provided in an embodiment of the present invention. In this embodiment, each driving circuit can drive two transistors, and each corresponding driving circuit includes two current detection units, such as a first current detection unit 111A and a second current detection unit 111B, wherein the first end of the first current detection unit 111A is electrically connected to the first current detection terminal CS1, and the first end of the second current detection unit 111B is electrically connected to the second current detection terminal CS2. The control unit 112 includes two sub-control units, namely a first sub-control unit 1120A and a second control sub-unit 1120B. The first input end of the first comparator in the first control sub-unit 1120A is electrically connected to the second end of the first current detection unit 111A, and the second input end is electrically connected to the second end of the second current detection unit 111B. The first input end of the differential amplifier in the first control sub-unit 1120A is electrically connected to the second end of the first current detection unit 111A, and the second input end is electrically connected to the second end of the second current detection unit 111B. The first input terminal of the first comparator in the second control subunit 1120B is electrically connected to the second terminal of the second current detection unit 111B, and the second input terminal is electrically connected to the second terminal of the first current detection unit 111A. The first input terminal of the differential amplifier in the second control subunit 1120B is electrically connected to the second terminal of the second current detection unit 111B, and the second input terminal is electrically connected to the second terminal of the first current detection unit 111A. In this embodiment, each driving circuit can drive two transistors, and the integration is higher.

[0063] It should be noted that in Figures 1 to 3 In an embodiment, each driving circuit includes a driving output terminal OUT, and the signal output by the pulse width controller is output to the gate of the transistor through the driving output terminal OUT. Figure 4In the illustrated embodiment, each driving circuit includes two driving output terminals, namely a first driving output terminal OUT1 and a second driving output terminal OUT2, each sub-control unit 1120 corresponds to one driving output terminal, and outputs the signal output by the pulse width controller to the gate of the corresponding transistor through the corresponding driving output terminal.

[0064] In some other embodiments, Figure 5 As shown, Figure 5 A circuit structure diagram of another parallel transistor driving circuit provided in an embodiment of the present invention. In this embodiment, the driving circuit includes at least three current detection units and at least three sub-control units. For example, it includes n current detection units (111 (1) ~ 111 (n)), n sub-control units (1120 (1) ~ 1120 (n)), and correspondingly also includes n current detection terminals (CS (1) ~ CS (n)), and n drive output terminals (OUT (1) ~ OUT (n)). The driving circuit also includes a selection unit 30, at least three input terminals of the selection unit 30 are electrically connected to the second terminals of the at least three current detection units in a one-to-one correspondence, the output terminal of the selection unit is electrically connected to the second input terminal of the first comparator in each sub-control unit and the second input terminal of the differential amplifier, and the selection unit 30 is used to select the minimum value output among its input terminals.

[0065] Specifically, a driving circuit of this embodiment can drive at least three transistors and can achieve a current balancing effect. The driving circuit detects the source-drain current of each transistor, and after selection by the selection unit 30, the source-drain current corresponding to the transistor with the smallest source-drain current is output to the second input terminal of each first comparator and the second input terminal of each differential amplifier. That is to say, for each transistor in this embodiment, the preset transistor is the transistor with the smallest source-drain current among the parallel transistors. The preset transistor may be different in different cycles. The source-drain current of each transistor is compared with the source-drain current of the preset transistor to determine the delay of the pulse width modulation signal corresponding to each transistor, so that all transistors achieve a current balancing effect.

[0066] It should be noted that when the source-drain currents of the transistors are the same when they are turned on, the corresponding delay values ​​of the sub-control units will remain unchanged.

[0067] Optionally, the current detection unit 111 includes a Hall sensor. The Hall sensor can be used to implement non-destructive detection of the current without the need for an additional sampling resistor, thereby achieving more accurate detection and the like.

[0068] Optionally, Figure 6 A circuit structure diagram of another driving circuit of parallel transistors provided in an embodiment of the present invention is shown in FIG. Figure 6The driving circuit also includes: at least one driver 113 corresponding to at least one transistor, the input end of the driver 113 is electrically connected to the output end of the control unit, and the driver 113 is used to modulate the pulse width modulation signal output by the control unit 112 and output a first signal for driving the transistor to be turned on from its first output end, and output a second signal for driving the transistor to be turned off from its second output end; the driving circuit also includes a first signal output end OUTH and a second signal output end OUTL, the first signal output end OUTH is electrically connected to the first output end of the corresponding driver 113, and the second signal output end OUTL is electrically connected to the second output end of the corresponding driver.

[0069] Specifically, the driver 113 may be, for example, a push-pull circuit, etc., which divides the pulse width modulation signal output by the control unit 112 into two signal outputs, namely, a first signal for controlling the transistor to be turned on, and a second signal for controlling the transistor to be turned off. The first signal is, for example, a high level, and the second signal is, for example, a low level. Each sub-control unit corresponds to a driver 113. Each driver 113 corresponds to a first signal output terminal OUTH and a second signal output terminal OUTL.

[0070] Optionally, continue to refer to Figure 6 The driving circuit also includes a voltage input terminal VIN for inputting an operating voltage. The driving circuit also includes a first voltage controller 114 and a preset voltage output terminal LDO5. The first voltage controller 114 is, for example, a low voltage difference linear regulator, a first terminal of which is electrically connected to the voltage input terminal VIN, and a second terminal of which is electrically connected to the preset voltage output terminal LDO5. The first voltage controller 114 modulates the voltage inputted by the voltage input terminal VIN into a preset voltage and then outputs it from the preset voltage output terminal LDO5. The preset voltage is, for example, 5V, and can provide a power supply signal for other structures.

[0071] The driving circuit may further include a second voltage controller 115, a reference voltage input terminal ADJ and a feedback voltage input terminal VDRV. The input terminal of the second voltage controller 115 is electrically connected to the voltage input terminal VIN, the first output terminal is electrically connected to the reference voltage input terminal ADJ, and the second output terminal is electrically connected to the driver 113 and the feedback voltage input terminal VDRV. The second voltage controller 115 is, for example, a low voltage drop linear regulator, the reference voltage input terminal ADJ provides a reference voltage for the second voltage controller 115; the feedback voltage input terminal VDRV provides a feedback signal for the second voltage controller 115, and the second voltage can power the driver 113. In addition, the second voltage controller 113 can also power the components in the control unit 112.

[0072] The driving circuit may further include a first ground terminal GND, a second ground terminal GND2, a first resistor R1, a second resistor R2 and a standby pulse width modulation signal input terminal PWMB. The standby pulse width modulation signal input terminal PWMB is connected to the pulse width controller 1124. The driving circuit may drive the transistor through the pulse width modulation signal inputted by the pulse width modulation signal input terminal PWM, or may drive the transistor through the pulse width modulation signal inputted by the standby pulse width modulation signal input terminal PWMB. The second resistor R2 is connected between the first ground terminal GND and the pulse width modulation signal input terminal PWM. The second ground terminal GND2 is electrically connected to the current detection unit 111 and the driver 113 to provide grounding for the corresponding components.

[0073] The embodiment of the present invention further provides a driver chip, which includes the driver circuit of the transistor provided in any embodiment of the present invention. The driver chip encapsulates the driver circuit inside to protect the driver circuit. The ports of the driver circuit serve as the pins of the driver chip. Since the driver chip provided in the embodiment of the present invention includes the driver circuit provided in any embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0074] Optionally, in some implementations, the driver chip also integrates transistors inside, thereby realizing an integrated design of the driver circuit and the transistors. It should be noted that the number of transistors that the driver chip can drive is the same as the number of integrated transistors.

[0075] The embodiment of the present invention further provides a cascade drive circuit, which includes at least two drive circuits provided by any embodiment of the present invention. The cascade drive circuit is used to drive at least two transistors in parallel so that the transistors achieve a current sharing effect when turned on.

[0076] Alternatively, if Figure 7 As shown, Figure 7 A circuit structure diagram of a cascade drive circuit provided in an embodiment of the present invention. The cascade drive circuit includes two drive circuits 11, a first drive circuit 11A and a second drive circuit 11B; each drive circuit includes a current detection unit 111 and a control subunit. In this embodiment, the current input terminal Isensi of the first drive circuit 11A is electrically connected to the current output terminal Isenso of the second drive circuit 11B, and the current output terminal Isenso of the first drive circuit 11A is electrically connected to the current input terminal Isensi of the second drive circuit 11B.

[0077] Specifically, the cascade drive circuit of this embodiment can drive two parallel transistors. The first drive circuit drives the first transistor Q1, and the second drive circuit drives the second transistor Q2. For the first drive circuit, the second transistor Q2 is a preset transistor; and for the second drive circuit, the first transistor Q1 is a preset transistor. In addition, Figure 7 As shown, the pulse width modulation signal PWM_IN is input to the pulse width modulation signal input terminal PWM of the corresponding driving circuit through the isolator. For example, it is input to the pulse width modulation signal input terminal of the first driving circuit 11A through the first isolator 41, and is input to the pulse width modulation signal input terminal of the second driving circuit 11B through the second isolator 41. A resistor can also be connected in series between the isolator and the pulse width modulation signal input terminal. The isolator may include two cascaded isolation units, which are powered by the VCC+5V power supply and the preset voltage output terminal LDO5 of the driving circuit respectively. The voltage input terminal VIN of the driving circuit inputs a 12V power supply. The reference voltage input terminal ADJ is grounded through a resistor, the feedback voltage input terminal VDRV is electrically connected to the reference voltage input terminal ADJ through a resistor, and the feedback voltage input terminal VDRV is grounded through a capacitor. The first signal output terminal and the second signal output terminal are electrically connected to the gate of the transistor through corresponding current limiting resistors, respectively.

[0078] Optionally, Figure 8 A circuit structure diagram of another cascade drive circuit provided by an embodiment of the present invention, referring to Figure 8 .and Figure 7 The difference from the structure shown is that in this embodiment, the cascade drive circuit includes at least three drive circuits, taking three drive circuits as an example, they are a first drive circuit 11A, a second drive circuit 11B and a third drive circuit 11C. The third drive circuit 11C is correspondingly connected to a third isolator. In this embodiment, the cascade drive circuit also includes a current selection module 50; the current output end of the drive circuit is electrically connected to the input end of the current selection module 50 in a one-to-one correspondence, and the output end of the current selection module 50 is electrically connected to the current input end Isensi of the drive circuit; the current selection module 50 is used to compare the currents of the current output ends of at least three drive circuits, and output the smallest current from its output end.

[0079] In this embodiment, after selection by the current selection module 50, the source-drain current corresponding to the transistor with the smallest source-drain current is output to the second input terminal of the first comparator in each driving circuit and the second input terminal of each differential amplifier. That is to say, in this embodiment, for each transistor, the preset transistor is the transistor with the smallest source-drain current among the parallel transistors. The preset transistor may be different in different cycles. The source-drain current of each transistor is compared with the source-drain current of the preset transistor to determine the delay of the pulse width modulation signal corresponding to each transistor, so that all transistors can achieve the current sharing effect.

[0080] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0081] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A driving circuit for parallel transistors, wherein the parallel transistors include at least two transistors connected in parallel, and the driving circuit is used to drive at least one transistor in the parallel transistors, characterized in that: The driving circuit comprises a pulse width modulation signal input terminal and at least one current detection terminal corresponding one-to-one to the at least one transistor; The pulse width modulation signal input terminal is used to input a pulse width modulation signal for controlling the control electrode of the transistor; the current detection terminal is used to be electrically connected to the first electrode of the transistor; The driving circuit further comprises a control unit and at least one current detection unit corresponding one-to-one to the at least one current detection terminal; The first end of the current detection unit is electrically connected to the current detection end, and is used to detect the source-drain current of the transistor; the second end of the current detection unit is electrically connected to the control unit; The control unit is electrically connected to the pulse width modulation signal input terminal, and is used to receive the source-drain current of the preset transistor in the parallel transistor, and adjust the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the current detected by the current detection unit and the source-drain current of the preset transistor.

2. The driving circuit of parallel transistors according to claim 1, characterized in that: The control unit is used to determine the delay time of the conduction level of the pulse width modulation signal output to the transistor according to the difference between the current detected by the current detection unit and the source / drain current of the preset transistor when the current detected by the current detection unit is greater than the source / drain current of the preset transistor.

3. The driving circuit of parallel transistors according to claim 2, characterized in that: The control unit comprises: at least one sub-control unit corresponding to the at least one current detection unit in a one-to-one manner, and the sub-control unit comprises: a first comparator, a differential amplifier, a second comparator and a pulse width controller, The first input terminal of the first comparator is electrically connected to the second terminal of the current detection unit, the second input terminal of the first comparator is connected to the source-drain current of the preset transistor, and the output terminal of the first comparator is electrically connected to the control terminal of the pulse width controller; The first input terminal of the differential amplifier is electrically connected to the second terminal of the current detection unit, the second input terminal of the differential amplifier is connected to the source-drain current of the preset transistor, and the output terminal of the differential amplifier is electrically connected to the first input terminal of the second comparator; The second input terminal of the second comparator is used to input a preset triangular wave; the output terminal of the second comparator is electrically connected to the pulse width controller; The pulse width controller is electrically connected to the pulse width modulation signal input terminal, and is used to enable a delay function of the pulse width controller when the current detected by the current detection unit is greater than the source-drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator.

4. The driving circuit of parallel transistors according to claim 3, characterized in that: Each of the driving circuits comprises a current detection unit and a sub-control unit; The driving circuit further comprises a current output terminal and a current input terminal; the current input terminal is used to be electrically connected to the current output terminal of other driving circuits, and the current output terminal is used to be electrically connected to the current input terminal of other driving circuits; wherein the other driving circuit has the same structure as the driving circuit; The second input terminal of the first comparator is electrically connected to the current input terminal, the second input terminal of the differential amplifier is electrically connected to the current input terminal; the second terminal of the current detection unit is electrically connected to the current output terminal; Alternatively, each of the driving circuits comprises two of the current detection units and two of the sub-control units; The second input terminal of the first comparator is electrically connected to the second terminal of another current detection unit; the second input terminal of the differential amplifier is electrically connected to the second terminal of another current detection unit Alternatively, each of the driving circuits comprises at least three of the current detection units and at least three of the sub-control units; The driving circuit also includes a selection unit, at least three input terminals of the selection unit are electrically connected to the second terminals of the at least three current detection units in a one-to-one correspondence, the output terminal of the selection unit is electrically connected to the second input terminal of the first comparator in each of the sub-control units and the second input terminal of the differential amplifier, and the selection unit is used to select the minimum value output among its input terminals.

5. The driving circuit of parallel transistors according to claim 1, characterized in that: The current detection unit includes a Hall sensor.

6. The transistor driving circuit according to claim 1, characterized in that: The drive circuit also includes: at least one driver corresponding to the at least one transistor one by one, the input end of the driver is electrically connected to the output end of the control unit, the driver is used to modulate the pulse width modulation signal output by the control unit and output a first signal from its first output end to drive the transistor to turn on, and output a second signal from its second output end to drive the transistor to turn off; the drive circuit also includes a first signal output end and a second signal output end, the first signal output end is electrically connected to the corresponding first output end of the driver, and the second signal output end is electrically connected to the corresponding second output end of the driver.

7. A driver chip, characterized in that: The driving chip comprises the driving circuit of the parallel transistor according to any one of claims 1 to 6.

8. A cascade drive circuit for driving at least two transistors in parallel, characterized in that: The cascade driving circuit comprises at least two driving circuits according to any one of claims 1 to 6.

9. The cascade drive circuit according to claim 8, characterized in that: The cascade driving circuit comprises a first driving circuit and a second driving circuit, a total of two driving circuits; The driving circuit also includes a current output terminal and a current input terminal; The control unit comprises: at least one sub-control unit corresponding to the at least one current detection unit one by one, the sub-control unit comprises: a first comparator, a differential amplifier, a second comparator and a pulse width controller, wherein the first input terminal of the first comparator is electrically connected to the second terminal of the current detection unit, the second input terminal of the first comparator is connected to the source-drain current of the preset transistor, and the output terminal of the first comparator is electrically connected to the control terminal of the pulse width controller; the first input terminal of the differential amplifier is electrically connected to the second terminal of the current detection unit, the second input terminal of the differential amplifier is connected to the source-drain current of the preset transistor, and the output terminal of the differential amplifier is electrically connected to the first input terminal of the second comparator; the second comparator The second input terminal of is used to input a preset triangular wave; the output terminal of the second comparator is electrically connected to the pulse width controller; the pulse width controller is electrically connected to the pulse width modulation signal input terminal, and the pulse width controller is used to enable the delay function of the pulse width controller when the current detected by the current detection unit is greater than the source-drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator; each of the driving circuits includes a current detection unit and a sub-control unit; the second input terminal of the first comparator is electrically connected to the current input terminal, and the second input terminal of the differential amplifier is electrically connected to the current input terminal; the second terminal of the current detection unit is electrically connected to the current output terminal; The current input terminal of the first driving circuit is electrically connected to the current output terminal of the second driving circuit, and the current output terminal of the first driving circuit is electrically connected to the current input terminal of the second driving circuit.

10. The cascade driving circuit according to claim 8, characterized in that: The control unit comprises: at least one sub-control unit corresponding to the at least one current detection unit, the sub-control unit comprises: a first comparator, a differential amplifier, a second comparator and a pulse width controller, the first input end of the first comparator is electrically connected to the second end of the current detection unit, the second input end of the first comparator is connected to the source-drain current of the preset transistor, and the output end of the first comparator is electrically connected to the control end of the pulse width controller; the first input end of the differential amplifier is electrically connected to the second end of the current detection unit, the second input end of the differential amplifier is connected to the source-drain current of the preset transistor, and the output end of the differential amplifier is electrically connected to the first input end of the second comparator; the second input end of the second comparator is used to input a preset triangular wave; the output end of the second comparator is electrically connected to the pulse width controller; the pulse width controller is electrically connected to the pulse width modulation signal input end, and the pulse width controller is used to enable the delay function of the pulse width controller when the current detected by the current detection unit is greater than the source-drain current of the preset transistor, wherein the delay of the delay function is the pulse width of the output signal of the second comparator; each of the driving circuits comprises one current detection unit and one sub-control unit; The cascade drive circuit includes at least three drive circuits; the cascade drive circuit also includes a current selection module; the current output end of the drive circuit is electrically connected to the input end of the current selection module in a one-to-one correspondence, and the output end of the current selection module is electrically connected to the current input end of the drive circuit; the current selection module is used to compare the currents of the current output ends of the at least three drive circuits, and output the smallest current from its output end.

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