Linear block code decoding method and device, electronic equipment and readable storage medium

Abstract

The invention provides a linear block code decoding method and device, electronic equipment and a readable storage medium. The method comprises the following steps: receiving a linear block code with noise; decoding the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder comprises a multi-head unified attention module, and the multi-head unified attention module is used for learning information of all code words in the linear block codes. According to the method, the linear block codes with noise are decoded through the neural network decoder comprising the multi-head unified attention module, flexible switching of multiple linear block code decoding algorithms can be achieved, decoding processing of the multiple linear block codes is further achieved, hardware design and resource consumption are reduced, and the decoding efficiency of the multiple linear block codes is improved. And the hardware resource utilization rate is also improved.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a linear block code decoding method, device, electronic device and readable storage medium. Background Art

[0002] The current wireless communication technology is changing with each passing day, and the sixth generation (6G) wireless communication is accelerating its development. Its required performance indicators will far exceed 5G, including ultra-high reliability, extremely low latency and ultra-high transmission rate. In order to meet these demanding requirements, efficient error correction codes play a vital role in 6G networks.

[0003] Linear block codes, such as Polar codes, LDPC codes, and BCH codes, are considered to be candidate core error correction codes for 6G networks due to their excellent error correction performance and coding efficiency. However, existing linear block code decoder designs are usually optimized for specific decoding algorithms to achieve optimal performance, but this leads to two problems: first, when it is necessary to switch to a new decoding algorithm, the fixed hardware circuit needs to be redesigned, which brings huge engineering and time costs; second, the current SOC (System On Chip) often supports multiple code types, and the traditional decoding algorithm designed for a single code type cannot support multiple code types, resulting in low hardware resource utilization and difficulty in fully utilizing hardware capabilities.

[0004] Therefore, there is an urgent need for a linear block code decoder solution with strong flexibility, high robustness and high resource utilization, which can adapt to the needs of flexible switching of multiple decoding algorithms in future 6G networks. Summary of the invention

[0005] The present invention provides a linear block code decoding method, device, electronic device and readable storage medium, which are used to overcome the defect that traditional linear block code decoders are only designed for specific decoding algorithms and cannot decode multiple linear block codes, resulting in a large waste of engineering design and hardware resources, and realize flexible switching of multiple linear block code decoding algorithms, reduce hardware design and resource consumption, and improve hardware resource utilization.

[0006] On the one hand, the present invention provides a linear block code decoding method, comprising: receiving a linear block code with noise; decoding the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code.

[0007] Furthermore, the neural network decoder includes a normalization module, a word embedding module, multiple neural network layers and an output module, wherein each neural network layer includes a normalization layer, a multi-head unified attention module and a feedforward module, and there is a residual connection between the multi-head unified attention module and the feedforward module.

[0008] Furthermore, the pre-trained neural network decoder decodes the linear block code, including: based on a standardization module, aligning the linear block code to obtain a standard input vector; based on a word embedding module, converting the standard input vector into a high-dimensional input vector; based on multiple neural network layers, obtaining an output vector according to the high-dimensional input vector; based on an output module, obtaining a target output vector according to the output vector; wherein the target output vector is the original information sequence obtained by decoding.

[0009] Furthermore, based on multiple neural network layers, an output vector is obtained according to the high-dimensional input vector, wherein the processing steps of each neural network layer include: based on a first normalization layer, normalizing the high-dimensional input vector to obtain a normalized vector; based on a multi-head unified attention module, learning codeword information from the normalized vector to obtain an attention vector; based on a second normalization layer, normalizing the high-dimensional input vector and the attention vector to obtain an intermediate vector; based on a forward feedback module, applying a nonlinear activation function to the intermediate vector to obtain a first output vector; residually connecting the first output vector, the high-dimensional input vector and the attention vector, and using the residual-connected vector as the input of the next neural network layer.

[0010] Furthermore, based on the first normalization layer, the high-dimensional input vector is normalized to obtain a normalized vector, and then includes: constructing a sparse mask matrix according to the parity check matrix corresponding to the linear block code; correspondingly, based on the multi-head unified attention module, the codeword information is learned from the normalized vector to obtain an attention vector, including: initializing the dimension of the normalized vector to obtain an initialization vector; rearranging and transposing the initialization vector according to the batch size, the number of heads and the embedding size to obtain a transposed vector; performing matrix multiplication operation on the transposed vector using a trainable feature tensor to obtain a first target vector; adding the trainable attention tensor to the sparse mask matrix, and applying the Softmax function on the specified dimension to obtain a second target vector; multiplying the first target vector by the second target vector, and rearranging and transposing the multiplied vector to obtain the attention vector.

[0011] Furthermore, according to the parity check matrix corresponding to the linear block code, a sparse mask matrix is ​​constructed, including: obtaining the density of the parity check matrix; initializing an extended parity check matrix according to the number of rows and columns of the parity check matrix; assigning elements in the parity check matrix to the extended parity check matrix and performing transposition processing to obtain an intermediate matrix; generating a random sparse matrix, and assigning the intermediate matrix according to the densities of the random sparse matrix and the parity check matrix to obtain the sparse mask matrix.

[0012] Furthermore, the alignment processing of the linear block code based on the standardization module includes: performing alignment processing on the linear block code according to a preset standardization formula; wherein the preset standardization formula is as follows:

[0013] in, represents the standard input vector, represents a linear block code with noise, represents the parity bit, represents the parity check matrix, represents the hard decision result of the linear block code, and All represent zero vectors, The length is , The length is , Indicates the maximum length of the code length, Indicates the maximum length of the parity bit, represents the length of the linear block code, Indicates the length of the parity check bits.

[0014] In a second aspect, the present invention also provides a linear block code decoding device, comprising: a linear block code receiving module, used to receive a linear block code with noise; a linear block code decoding module, used to decode the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code.

[0015] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the linear block code decoding method as described above is implemented.

[0016] In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the linear block code decoding methods described above.

[0017] The linear block code decoding method provided by the present invention receives a linear block code with noise, and decodes the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code. The method decodes the linear block code with noise by using a neural network decoder including a multi-head unified attention module, and can realize flexible switching of multiple linear block code decoding algorithms, thereby realizing decoding processing of multiple linear block codes, which not only reduces hardware design and resource consumption, but also improves hardware resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flowchart of a linear block code decoding method provided by an embodiment of the present invention.

[0020] Figure 2 It is a structural diagram of a neural network decoder provided in an embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of the structure of a common single-layer decoder (Transformer) provided by the prior art.

[0022] Figure 4 It is a schematic diagram of the architecture of the multi-head consensus attention module provided in an embodiment of the present invention.

[0023] Figure 5 It is a pseudo code diagram of the multi-head unified attention module provided in an embodiment of the present invention.

[0024] Figure 6 It is a pseudo code schematic diagram of constructing a sparse mask matrix provided by an embodiment of the present invention.

[0025] Figure 7 It is a schematic diagram of a sparse mask matrix and its Tanner graph provided by an embodiment of the present invention.

[0026] Figure 8It is a schematic diagram of the application of the linear block code decoding method provided by an embodiment of the present invention.

[0027] Fig. 9 It is a schematic diagram of the structure of a linear block code decoding device provided by an embodiment of the present invention.

[0028] Fig.10 It is a schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that traditional linear block code decoders are usually designed as fixed hardware circuits for specific decoding algorithms. This means that when it is necessary to switch to a new decoding algorithm, the fixed hardware circuit needs to be redesigned, which will result in huge engineering and time costs. At the same time, the hardware resource utilization rate designed for a specific decoding algorithm is low.

[0031] In view of this, the present invention proposes a new linear block code decoding method, specifically, Figure 1 The figure shows a flow chart of a linear block code decoding method provided by an embodiment of the present invention.

[0032] like Figure 1 As shown, the method includes steps S110-S120, and steps S110-S120 and related steps will be described in detail below.

[0033] S110, receiving a linear block code with noise.

[0034] It is easy to understand that the original information sequence passes through the encoder and modulator to obtain a modulated signal. The modulated signal passes through the noisy channel and the receiving end can receive the signal. The received signal is the linear block code with noise in this step. Since this embodiment mainly describes the decoding method of the linear block code, the encoding, modulation and transmission process of the original information sequence will not be described in detail here.

[0035] Linear block codes are a widely used class of forward error correction codes (FEC), which add redundant information to allow the receiver to detect and possibly correct errors caused by noise during transmission.

[0036] Linear block codes usually correspond to a dimension The generator matrix and a dimension of The parity check matrix , and the generated matrix and parity check matrix satisfy .in, Indicates the code length, Indicates the information bit length, Indicates the check bit length.

[0037] In a specific embodiment, the linear block code is any one of a Polar code, an LDPC code and a BCH code. Of course, the linear block code may also be other codes, which are not specifically limited here.

[0038] Based on receiving the linear block code with noise in step S110, further, step S120 is performed.

[0039] S120, based on a pre-trained neural network decoder, decode the linear block code to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code.

[0040] It is easy to understand that by inputting the received noisy linear block code into a pre-trained neural network decoder, the original information sequence can be decoded.

[0041] It is worth mentioning that the neural network decoder applicable to this embodiment is not a general decoder, but an improved decoder.

[0042] Specifically, the neural network decoder used in this embodiment includes a multi-head unified attention module for learning all codeword information in the linear block code. The multi-head unified attention module allows the model to focus on different positions of the input at the same time, thereby improving the model's ability to handle long-distance dependencies. When applied to the decoding of linear block codes, the multi-head unified attention module can help the neural network decoder better capture the correlation between codewords, thereby improving the accuracy of decoding.

[0043] The neural network decoder in this embodiment is pre-trained. During this process, the learnable weight matrix in the multi-head unified attention module compresses and learns the information of all codewords, thereby enabling the neural network decoder to realize decoding processing of various linear block codes.

[0044] In this embodiment, a linear block code with noise is received and decoded based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code. The method decodes the linear block code with noise by using a neural network decoder including a multi-head unified attention module, and can realize flexible switching of multiple linear block code decoding algorithms, thereby realizing decoding processing of multiple linear block codes, which not only reduces hardware design and resource consumption, but also improves hardware resource utilization.

[0045] On the basis of the above embodiments, the network structure of the neural network decoder will be described in detail below.

[0046] Figure 2 A schematic diagram of the structure of a neural network decoder provided in an embodiment of the present invention is shown.

[0047] like Figure 2 As shown in the figure, the neural network decoder includes a standardization module (Standardized), a word embedding module (WordEmbedding), multiple neural network layers (L blocks) and an output module (1 Layer Normalization + 2 Fully Connected). Among them, each neural network layer includes 2 normalization layers (Layer Normalization), 1 multi-head unified attention module (Multi-Head Unified-Attention) and 1 feedforward module (FeedForward), and there is a residual connection between the multi-head unified attention module and the feedforward module, and there is a residual connection between the word embedding module and the multi-head unified attention module.

[0048] Correspondingly, Figure 3 FIG. 2 shows a schematic diagram of the structure of a common single-layer decoder (Transformer) provided by the prior art. Figure 3 As shown in the figure, the common Transformer architecture mainly includes modules such as word embedding, multi-head self-attention, forward feedback, residual and layer normalization.

[0049] according to Figure 2 and Figure 3 It can be seen that the neural network decoder provided in this embodiment is additionally designed with a standardization module, the purpose of which is to enable the neural network decoder to support linear block codes of different code types, code lengths and code rates. At the same time, a multi-head unified attention module different from the multi-head attention mechanism is also used, the purpose of which is to enable the neural network decoder to realize decoding processing of multiple linear block codes.

[0050] On the basis of the above embodiment, the process of decoding the linear block code by the neural network decoder is further described in detail below. The data flow can be specifically referred to in Figure 2 .

[0051] Based on a pre-trained neural network decoder, the linear block code is decoded, including: based on a standardization module, the linear block code is aligned to obtain a standard input vector; based on a word embedding module, the standard input vector is converted into a high-dimensional input vector; based on multiple neural network layers, an output vector is obtained according to the high-dimensional input vector; based on an output module, a target output vector is obtained according to the output vector; wherein the target output vector is the original information sequence obtained by decoding.

[0052] Firstly, based on the standardization module, the linear block codes with noise are aligned to obtain the standard input vector.

[0053] It is easy to understand that in order to enable the neural network decoder to support linear block codes with different code types, code lengths and code rates, a standardization module is designed in this embodiment. Through the standardization module, linear block codes with different code types, code lengths and code rates can be converted into a preset standard format to facilitate subsequent decoder processing.

[0054] Assume that the maximum length of the code is , the maximum length of the parity bit is , then, the standardization module can be defined as the following formula (1), which is the preset standardization formula.

[0055] (1).

[0056] In formula (1), represents the standard input vector, represents a linear block code with noise, represents the parity bit, represents the parity check matrix, represents the hard decision result of the linear block code, and All represent zero vectors, The length is , The length is , Indicates the maximum length of the code length, Indicates the maximum length of the parity bit, represents the length of the linear block code, Indicates the length of the parity check bits.

[0057] Then, based on the word embedding module, the standard input vector is converted into a high-dimensional input vector.

[0058] It is easy to understand that the word embedding module is used to convert the input X into a high-dimensional representation, as shown in the following formula (2).

[0059] (2).

[0060] In formula (2), Represents the input signal, that is, the standard input vector , the length is , with a dimension of 1. Represents a matrix that can be learned through training, with dimension . Represents the Hadamard product.

[0061] Next, based on multiple neural network layers, according to the high-dimensional input vector , and obtain the output vector. The processing steps of each neural network layer include: based on the first normalization layer, the high-dimensional input vector is normalized to obtain the normalized vector; based on the multi-head unified attention module, the codeword information is learned from the normalized vector to obtain the attention vector; based on the second normalization layer, the high-dimensional input vector and the attention vector are normalized to obtain the intermediate vector; based on the forward feedback module, a nonlinear activation function is applied to the intermediate vector to obtain the first output vector; the first output vector, the high-dimensional input vector and the attention vector are residually connected, and the residually connected vector is used as the input of the next neural network layer.

[0062] Figure 4 FIG. 2 shows a schematic diagram of the architecture of a multi-head consensus attention module provided by an embodiment of the present invention. Figure 4 As shown, multiple heads share the same attention .

[0063] Based on the multi-head unified attention module, the codeword information is learned from the normalized vector to obtain the attention vector. This process can be implemented as follows:

[0064] (3).

[0065] In formula (3), represents a trainable attention tensor, represents a trainable feature tensor, , represents a definable hyperparameter, Represents the output of the previous network layer, that is, the normalized vector.

[0066] To facilitate understanding of the processing of the multi-head unified attention module, Figure 5A pseudocode schematic diagram of the multi-head unified attention module provided by an embodiment of the present invention is shown.

[0067] like Figure 5 As shown, first, initialize the dimension of the normalized vector X to obtain the initialization vector, the dimension of the initialization vector is (B, N, d h ). Where B represents the batch size, N represents the code length, and d h =H×d k , where H represents the number of heads, d k Denotes the embedding size. Then, according to the batch size, the number of heads, and the embedding size, the initialization vector is rearranged and transposed to obtain the transposed vector, the dimension of the transposed vector is (B, N, H, d k ). Next, using the trainable feature tensor Perform matrix multiplication with the transposed vector to obtain the first target vector, the dimension of the first target vector is (B, H, d l , d k ). At the same time, the trainable attention tensor Apply the Softmax function on the specified dimension to obtain the second target vector, the dimension of the second target vector is (B, 1, N, d l Then, the first target vector is multiplied by the second target vector, and the multiplied vector is rearranged and transposed to obtain the attention vector. The dimension of the attention vector is (B, N, d h ), which is consistent with the dimension of the initialization vector.

[0068] After obtaining the attention vector, the high-dimensional input vector and the attention vector are normalized based on the second normalization layer to obtain an intermediate vector, and a nonlinear activation function is applied to the intermediate vector based on the forward feedback module to obtain the first output vector. Finally, the first output vector, the high-dimensional input vector, and the attention vector are residually connected, and the vector after the residual connection is the output of the first neural network layer. Furthermore, the output of the first neural network layer is used as the input of the next neural network layer, and the cycle is repeated. After processing by L neural network layers, the output vector, that is, the output of the last neural network layer, can be obtained.

[0069] Finally, based on the output module, the target output vector is obtained according to the output vector. Specifically, the output vector is passed through the normalization layer and two fully connected layers in sequence to obtain the target output vector, which is the original information sequence obtained by decoding.

[0070] The above is the process of decoding linear block codes using a neural network decoder.

[0071] In this embodiment, the linear block code is aligned based on the standardization module to obtain a standard input vector, and the standard input vector is converted into a high-dimensional input vector based on the word embedding module, and then based on multiple neural network layers, an output vector is obtained according to the high-dimensional input vector, and based on the output module, a target output vector is obtained according to the output vector; wherein the target output vector is the original information sequence obtained by decoding. This method decodes the noisy linear block code by a neural network decoder including a multi-head unified attention module, and can realize flexible switching of multiple linear block code decoding algorithms, and then realizes the decoding processing of multiple linear block codes, which not only reduces hardware design and resource consumption, but also improves hardware resource utilization.

[0072] On the basis of the above embodiments, the process of constructing a sparse mask matrix before the multi-head unified attention module will be described in detail below.

[0073] It can be understood that in order to further enhance performance and reduce computational complexity, this embodiment proposes a sparse mask (sparse mask matrix), which acts on the parity check matrix and is then applied to the multi-head unified attention module.

[0074] Specifically, after normalizing the high-dimensional input vector based on the first normalization layer to obtain the normalized vector, and before learning the codeword information from the normalized vector based on the multi-head unified attention module, it also includes: constructing a sparse mask matrix according to the parity check matrix corresponding to the linear block code.

[0075] First, the density of the parity check matrix H corresponding to the linear block code is defined, which can be calculated by the following formula (4).

[0076] (4).

[0077] In formula (4), represents the density of the parity check matrix, represents the parity check matrix, Indicates the code length, Indicates the length of information bits.

[0078] Then, assuming , , define the extended parity check matrix , please refer to the following formula (5) for details.

[0079] (5).

[0080] In formula (5), Indicates a The random sparse matrix is ​​a 0-1 matrix, that is, a constructed sparse mask matrix.

[0081] To further understand the process of constructing a sparse mask matrix, Figure 6 A pseudo code schematic diagram for constructing a sparse mask matrix provided by an embodiment of the present invention is shown.

[0082] like Figure 6 As shown, for the linear block code, the parity check matrix H has a dimension of (nk, n). First, the density of the parity check matrix is ​​obtained. , can be calculated by the above formula (4).

[0083] Then, according to the number of rows and columns of the parity check matrix, an extended parity check matrix is ​​initialized, that is, .

[0084] Next, the elements in the parity check matrix are assigned to the extended parity check matrix and transposed to obtain an intermediate matrix.

[0085] Then, generate a random sparse matrix , and assign values ​​to the intermediate matrix according to the density of the random sparse matrix and the parity check matrix to obtain a sparse mask matrix. Specifically, if the element in the random sparse matrix is ​​less than the density of the parity check matrix, it is assigned a value of 1, and if the element in the random sparse matrix is ​​greater than the density of the parity check matrix, it is assigned a value of 0. After the assignment, the elements in the matrix are inverted (element 0 is mapped to negative infinity, element 1 is mapped to 0), and the sparse mask matrix can be obtained. .

[0086] The above is the complete process of constructing a sparse mask matrix.

[0087] Taking the (7,4) Hamming code as an example, its corresponding parity check matrix H is as follows (6).

[0088] (6).

[0089] The sparse mask matrix generated according to the above sparse mask matrix construction method can be found in Figure 7 , Figure 7 FIG. 1 is a schematic diagram of a sparse mask matrix and its Tanner graph provided by an embodiment of the present invention. Figure 7 In the figure, the leftmost figure is the transposed matrix of the parity check matrix H, and the middle figure is the constructed coefficient mask matrix , the rightmost figure is the Tanner graph of the parity check matrix.

[0090] In general, the process of constructing a sparse mask matrix can be expressed as follows:

[0091] (7).

[0092] Construct a sparse mask matrix (i.e. ), the sparse mask matrix is ​​applied to the multi-head unified attention module. The mathematical expression of the multi-head unified attention module using the sparse mask matrix can be seen in the following equation (8).

[0093] (8).

[0094] For formula (8), first, initialize the dimension of the normalized vector to obtain the initialization vector; rearrange and transpose the initialization vector according to the batch size, the number of heads, and the embedding size to obtain the transposed vector; perform matrix multiplication on the trainable feature tensor and the transposed vector to obtain the first target vector; add the trainable attention tensor to the sparse mask matrix, and apply the Softmax function on the specified dimension to obtain the second target vector; multiply the first target vector by the second target vector, and rearrange and transpose the multiplied vector to obtain the attention vector.

[0095] In this embodiment, the density of the parity check matrix is ​​obtained, and an extended parity check matrix is ​​initialized according to the number of rows and columns of the parity check matrix. The elements in the parity check matrix are then assigned to the extended parity check matrix and transposed to obtain an intermediate matrix. A random sparse matrix is ​​generated, and the intermediate matrix is ​​assigned according to the densities of the random sparse matrix and the parity check matrix to obtain a sparse mask matrix. Thus, the sparse mask matrix is ​​applied to the multi-head unified attention module, which can effectively enhance the performance and reduce the computational complexity.

[0096] Additionally, in some embodiments, Figure 8 The following is a schematic diagram showing an application of a linear block code decoding method provided by an embodiment of the present invention.

[0097] like Figure 8 As shown, the original information sequence m passes through the encoder and modulator to obtain a modulated signal, and the modulated signal passes through the noise channel, and the receiving end receives the signal y. The received signal y is sent to the neural network decoder provided in the embodiment of the present invention, and the original information sequence m can be successfully restored.

[0098] Corresponding to the linear block code decoding method described in the above embodiments, the present invention also provides a linear block code decoding device, specifically, Fig. 9 A schematic diagram of the structure of a linear block code decoding device provided by an embodiment of the present invention is shown.

[0099] like Fig. 9As shown, the device includes: a linear block code receiving module 910, used to receive a linear block code with noise; a linear block code decoding module 920, used to decode the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code.

[0100] In this embodiment, a linear block code with noise is received by a linear block code receiving module 910, and a linear block code decoding module 920 decodes the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code. The device decodes the linear block code with noise by a neural network decoder including a multi-head unified attention module, and can realize flexible switching of multiple linear block code decoding algorithms, thereby realizing decoding processing of multiple linear block codes, which not only reduces hardware design and resource consumption, but also improves hardware resource utilization.

[0101] It should be noted that the linear block code decoding device provided in the embodiment of the present invention and the linear block code decoding method described in the above embodiments can be referred to each other, and will not be described in detail here.

[0102] Fig.10 An example of a physical structure diagram of an electronic device is shown in FIG. Fig.10 As shown, the electronic device may include: a processor 1010, a communication interface 1020, a memory 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020 and the memory 1030 communicate with each other through the communication bus 1040. The processor 1010 may call the logic instructions in the memory 1030 to execute a linear block code decoding method, the method comprising: receiving a linear block code with noise; decoding the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder includes a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code.

[0103] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0104] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the linear block code decoding method provided by the above-mentioned methods, the method comprising: receiving a linear block code with noise; decoding the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; wherein the neural network decoder comprises a multi-head unified attention module, and the multi-head unified attention module is used to learn the information of all codewords in the linear block code.

[0105] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0106] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A linear block code decoding method, characterized in that: include: Receive linear block codes with noise; Decoding the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; Among them, the neural network decoder includes a multi-head unified attention module, which is used to learn the information of all codewords in the linear block code.

2. The linear block decoding method according to claim 1, characterized in that: The neural network decoder includes a normalization module, a word embedding module, a plurality of neural network layers and an output module, wherein: Each neural network layer includes a normalization layer, a multi-head unified attention module and a feedforward module, and there is a residual connection between the multi-head unified attention module and the feedforward module.

3. The linear block code decoding method according to claim 2, characterized in that: The pre-trained neural network decoder decodes the linear block code, comprising: Based on the standardization module, the linear block code is aligned to obtain a standard input vector; Based on a word embedding module, converting the standard input vector into a high-dimensional input vector; Based on multiple neural network layers, obtaining an output vector according to the high-dimensional input vector; Based on the output module, a target output vector is obtained according to the output vector; The target output vector is the original information sequence obtained by decoding.

4. The linear block code decoding method according to claim 3, characterized in that: The method is based on multiple neural network layers, and obtains an output vector according to the high-dimensional input vector, wherein the processing steps of each neural network layer include: Based on the first normalization layer, the high-dimensional input vector is normalized to obtain a normalized vector; Based on a multi-head unified attention module, codeword information is learned from the normalized vector to obtain an attention vector; Based on the second normalization layer, the high-dimensional input vector and the attention vector are normalized to obtain an intermediate vector; Applying a nonlinear activation function to the intermediate vector based on a forward feedback module to obtain a first output vector; The first output vector, the high-dimensional input vector, and the attention vector are residually connected, and the vector after residual connection is used as the input of the next neural network layer.

5. The linear block code decoding method according to claim 4, characterized in that: The method of performing normalization processing on the high-dimensional input vector based on the first normalization layer to obtain a normalized vector includes: Constructing a sparse mask matrix according to a parity check matrix corresponding to the linear block code; Correspondingly, the multi-head unified attention module learns codeword information from the normalized vector to obtain an attention vector, including: Initializing the dimension of the normalized vector to obtain an initialization vector; According to the batch size, number of heads, and embedding size, the initialization vector is rearranged and transposed to obtain the transposed vector; Perform matrix multiplication on the trainable feature tensor and the transposed vector to obtain the first target vector; Add the trainable attention tensor to the sparse mask matrix and apply the Softmax function on the specified dimension to obtain the second target vector; The first target vector is multiplied by the second target vector, and the multiplied vector is rearranged and transposed to obtain the attention vector.

6. The linear block code decoding method according to claim 5, characterized in that: Constructing a sparse mask matrix according to the parity check matrix corresponding to the linear block code, including: Get the density of the parity check matrix; Initialize an extended parity check matrix according to the number of rows and columns of the parity check matrix; Assigning elements in the parity check matrix to the extended parity check matrix and performing transposition processing to obtain an intermediate matrix; A random sparse matrix is ​​generated, and an intermediate matrix is ​​assigned values ​​according to the densities of the random sparse matrix and the parity check matrix to obtain the sparse mask matrix.

7. The linear block code decoding method according to claim 3, characterized in that: The step of performing alignment processing on the linear block code based on the standardization module includes: Performing alignment processing on the linear block code according to a preset standardization formula; The preset normalization formula is as follows: in, represents the standard input vector, represents a linear block code with noise, represents the parity bit, represents the parity check matrix, represents the hard decision result of the linear block code, and All represent zero vectors, The length is , The length is , Indicates the maximum length of the code length, Indicates the maximum length of the parity bit, represents the length of the linear block code, Indicates the length of the parity check bits.

8. A linear block code decoding device, characterized in that: include: A linear block code receiving module, used for receiving a linear block code with noise; A linear block code decoding module, used for decoding the linear block code based on a pre-trained neural network decoder to obtain an original information sequence; Among them, the neural network decoder includes a multi-head unified attention module, which is used to learn the information of all codewords in the linear block code.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the linear block code decoding method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the linear block code decoding method according to any one of claims 1 to 7 is implemented.

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