Printed circuit board, manufacturing method thereof and electronic equipment

Abstract

The invention relates to the technical field of circuit boards, and discloses a printed circuit board, a manufacturing method thereof and electronic equipment, and the printed circuit board comprises a signal wiring layer and a signal reference layer adjacent to the signal wiring layer; wherein the signal wiring layer comprises a wiring width abrupt change area; the signal reference layer comprises a clearance area; a part of the clearance area is located at the projection of the wiring width abrupt change area on the signal reference layer. Through the design of adding the clearance area on the signal reference layer, the change distance of characteristic impedance can be prolonged, the impedance change rate of the wire can be adjusted, and the electric field distribution between the wire and the reference ground is more uniform, so that the smooth transition of the characteristic impedance of the wire is realized, the continuity of the characteristic impedance of the wire is improved, the signal reflection caused by the characteristic impedance is reduced, and the signal quality is improved. The integrity and quality of the signal are maintained; in addition, electromagnetic radiation and interference can be reduced by reducing signal reflection, and the electromagnetic compatibility of the system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and in particular to a printed circuit board and a manufacturing method thereof, and electronic equipment. Background Art

[0002] With the continuous upgrading of electronic products, the requirements for signal printed circuit board (PCB) routing and design are getting higher and higher, among which the impedance matching requirements for high-speed signals entering and exiting the chip are also getting higher and higher. However, with the trend of product miniaturization, chips are also getting smaller and smaller, and the routing of high-speed signals out of the chip usually needs to be widened to the required characteristic impedance requirements. The sudden widening or narrowing of high-speed signal routing will cause a sudden change in characteristic impedance, which is easy to cause impedance mismatch. When the signal encounters impedance mismatch during transmission, it will cause signal reflection and attenuation, further affecting the transmission quality of the signal.

[0003] It can be seen that the problem of sudden changes in characteristic impedance of high-speed signal routing is a technical problem that people in this field need to solve urgently. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a printed circuit board and a manufacturing method thereof, and an electronic device, which can adjust the impedance change rate, improve the continuity of the characteristic impedance of the routing, and reduce the signal reflection and signal quality degradation caused by it.

[0005] In order to solve the above technical problems, the present invention provides a printed circuit board, comprising: a signal routing layer, and a signal reference layer adjacent to the signal routing layer;

[0006] Wherein, the signal routing layer includes a routing width mutation area;

[0007] The signal reference layer includes a clearance area; a portion of the clearance area is located at the projection of the routing width mutation area on the signal reference layer.

[0008] In a first aspect, in the above-mentioned printed circuit board provided by the present invention, the trace width mutation area is the area where the trace changes from the first width to the second width or the area where the trace changes from the second width to the first width;

[0009] wherein the first width is greater than the second width;

[0010] The width of the clearance area is smaller than the first width and larger than the second width.

[0011] On the other hand, in the above-mentioned printed circuit board provided by the present invention, the length of the clearance area along the extension direction of the trace is greater than the length of the trace width mutation area.

[0012] On the other hand, in the above-mentioned printed circuit board provided by the present invention, the length of the clearance area along the extension direction of the trace is less than or equal to twice the length of the trace width mutation area.

[0013] On the other hand, in the above-mentioned printed circuit board provided by the present invention, the cross-sectional shape of the clearance area along the plane direction where the signal reference layer is located is a regular geometric figure;

[0014] The regular geometric shape includes at least one of a rhombus, an ellipse, and a hexagon.

[0015] On the other hand, in the above-mentioned printed circuit board provided by the present invention, when the cross-sectional shape of the clearance area along the plane where the signal reference layer is located is a rhombus, the first diagonal line of the rhombus is parallel to the extension direction of the trace, and the second diagonal line is perpendicular to the extension direction of the trace;

[0016] The length of the second diagonal line is smaller than the first width and larger than the second width;

[0017] The length of the first diagonal line is greater than the length of the routing width mutation region and is less than or equal to twice the length of the routing width mutation region.

[0018] On the other hand, in the above-mentioned printed circuit board provided by the present invention, the signal reference layer is located directly above the signal routing layer;

[0019] Alternatively, the signal reference layer is located directly below the signal routing line.

[0020] On the other hand, in the above-mentioned printed circuit board provided by the present invention, the signal reference layer includes a first signal reference layer and a second signal reference layer;

[0021] The signal routing layer includes a first signal routing layer, a second signal routing layer and a third signal routing layer;

[0022] The first signal reference layer is located between the first signal routing layer and the second signal routing layer;

[0023] The second signal reference layer is located between the second signal routing layer and the third signal routing layer;

[0024] The distance between the first signal reference layer and the second signal reference layer ranges from 4 mil to 10 mil;

[0025] The dielectric constant of the dielectric material between the first signal reference layer and the second signal reference layer is in the range of 4.0 to 4.8;

[0026] The first signal reference layer and the second signal reference layer are both planar layers made of conductive materials;

[0027] The first signal reference layer and / or the second signal reference layer includes the clearing area.

[0028] In order to solve the above technical problems, the present invention also provides a method for manufacturing a printed circuit board, comprising:

[0029] Set the routing width mutation area on the signal routing layer;

[0030] A clearance area is formed on a signal reference layer adjacent to the signal routing layer; a portion of the clearance area is located at a projection of the routing width mutation area on the signal reference layer.

[0031] In order to solve the above technical problem, the present invention further provides an electronic device, comprising the above printed circuit board provided by the present invention.

[0032] It can be seen from the above technical solution that a printed circuit board provided by the present invention comprises: a signal routing layer, and a signal reference layer adjacent to the signal routing layer; wherein the signal routing layer comprises a routing width mutation zone; the signal reference layer comprises a clearance zone; a portion of the clearance zone is located at the projection of the routing width mutation zone on the signal reference layer.

[0033] The beneficial effect of the present invention is that, in the above-mentioned printed circuit board provided by the present invention, a clearance area is set on the signal reference layer, and part of the clearance area is located at the projection of the routing width mutation area on the signal reference layer. In this way, by adding the clearance area on the signal reference layer, the distance of characteristic impedance change can be extended, and the impedance change rate of the routing can be adjusted, so that the electric field distribution between the routing and the reference ground is more uniform, thereby achieving a smooth transition of the routing characteristic impedance, improving the continuity of the routing characteristic impedance, reducing the signal reflection caused by it, effectively improving the performance of the routing, maintaining the integrity of the signal, ensuring that the signal maintains a high quality during the transmission process, and solving the problem that the characteristic impedance of the high-speed signal routing changes suddenly and affects the signal transmission quality; and reducing signal reflection can reduce electromagnetic radiation and interference, and improve the electromagnetic compatibility of the system.

[0034] In addition, the present invention also provides a corresponding manufacturing method and electronic device for a printed circuit board, which have the same or corresponding technical features as the above-mentioned printed circuit board, further making the above-mentioned printed circuit board more practical, and the manufacturing method and electronic device have corresponding advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of the structure of a signal routing layer in a printed circuit board provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the structure of a routing width mutation region in a signal routing layer provided by an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the structure of a clear area in a signal reference layer provided by an embodiment of the present invention;

[0039] Figure 4 A flow chart of a method for manufacturing a printed circuit board provided in an embodiment of the present invention.

[0040] Among them, 1 is the routing in the signal routing layer, 2 is the routing width mutation area in the signal routing layer, and 3 is the clearance area in the signal reference layer. DETAILED DESCRIPTION

[0041] With the advent of the big data era, the development of electronic products (such as servers) has risen rapidly. The performance of electronic products is getting higher and higher, and the transmission efficiency of signals is getting faster and faster. In the design of electronic products, the requirements for signal printed circuit board (PCB) routing and design are getting higher and higher, and the impedance matching requirements for high-speed signals entering and exiting the chip are also getting higher and higher. However, with the trend of product miniaturization, chips are also getting smaller and smaller. Sometimes, due to the limitation of space around the chip, the routing from the chip end has to be thinner, and the characteristic impedance of the routing is higher. After the signal leaves the chip area, the routing width is required by the signal, so the routing will become wider, and the characteristic impedance of the routing will also become lower.

[0042] Characteristic impedance is also called "characteristic impedance". It is not a DC resistance, but a concept in long-distance transmission. In the high-frequency range, during the signal transmission process, when the signal reaches the place, an instantaneous current will be generated between the signal line and the reference plane (power supply or ground plane) due to the establishment of an electric field. If the trace is isotropic, then as long as the signal is transmitted, there will always be a current I. If the output level of the signal is V, during the signal transmission process, the trace will be equivalent to a resistor with a size of V / I. This equivalent resistance is called the characteristic impedance Z of the trace. During the transmission of the signal, if the characteristic impedance on the transmission path changes, the signal will be reflected at the node where the impedance is discontinuous.

[0043] The so-called characteristic impedance means the impedance determined by the characteristics of the line itself, as follows: Line impedance is determined by several factors: line width, copper thickness, and dielectric layer thickness. Once the printed circuit board is designed, the impedance of each line is theoretically determined because the above factors have been determined. However, due to the influence of the manufacturing process, the variation of line width, the change of copper thickness, and the control of dielectric layer thickness will cause the impedance to change. At the high-speed signal chip end, it is usually widened to the required impedance characteristic line, for example, from 4mil to 8mil. The characteristic impedance of the high-speed signal line changes suddenly, which is easy to cause signal reflection and impedance mismatch. The narrowing of the line will cause the characteristic impedance to change, resulting in impedance mismatch during the signal transmission process, which will cause signal reflection and attenuation, further affecting the signal transmission quality.

[0044] In order to solve the above-mentioned technical problem of sudden changes in characteristic impedance of high-speed signal routing, the present invention provides a printed circuit board that can extend the distance of characteristic impedance change, adjust the impedance change rate of the routing, improve the continuity of the characteristic impedance of the routing, and reduce signal reflection and signal quality degradation caused by it.

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. An embodiment of the present invention provides a printed circuit board, which may include: a signal routing layer, and a signal reference layer adjacent to the signal routing layer; wherein the signal routing layer includes a routing width mutation region; the signal reference layer includes a clearance region; and part of the clearance region is located at the projection of the routing width mutation region on the signal reference layer.

[0047] Figure 1 A schematic diagram of the structure of a signal routing layer in a printed circuit board provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the printed circuit board includes a signal routing layer, which is a conductive layer for routing. The signal routing layer may include a plurality of routing lines 1. Figure 1 Two traces 1 are shown. The traces 1 are used to connect the pins of the electronic components, so that the electrical signals can be transmitted between the various electronic components, and are a key part in realizing the circuit function.

[0048] Figure 2 A schematic diagram of the structure of a signal wiring width mutation region in a signal wiring layer provided by an embodiment of the present invention, such as Figure 2 As shown in FIG. 1 , the signal routing layer includes a routing width mutation area 2. The routing width mutation area 2 refers to the area where the width of routing 1 changes suddenly. It can also be understood that there is a routing mutation at the coupling point of routing 1, and the width of routing 1 varies greatly. The impedance mismatch at this point is serious, and the signal attenuation or degradation observed at the receiving end is more serious. Under normal circumstances, routing 1 maintains a certain width to transmit signals, but at certain locations, due to design requirements or other factors, the width of routing 1 will change. For example: in order to connect different types of electronic components, the pin spacing and required trace width are different. When connecting from a component with a wider pin to a component with a narrower pin, a trace width mutation will occur; when connecting a power amplifier chip (with thicker pins, requiring a wider trace to carry large current) and a small signal processing chip (with thinner pins and corresponding narrower traces), there will be a trace width change area; when the wiring space on the printed circuit board is tight, the trace width may need to be adjusted to avoid other components or traces; in a printed circuit board with high-density wiring, in order to complete the connection of all signals in a limited space, the trace width sometimes has to be changed, forming a trace width mutation area 2. Trace width mutation area 2 may cause signal integrity problems and electromagnetic compatibility problems.

[0049] Figure 3 A schematic diagram of the structure of the clear area in the signal reference layer provided by an embodiment of the present invention. Figure 3 As shown, a clearance area 3 is set in the signal reference layer. The signal reference layer is a conductive layer that provides a reference potential for signal transmission. It is an important part of the circuit signal loop, usually a ground (GND) layer or a power layer (POWER), and plays a key role in a multi-layer circuit board. The clearance area 3 of the present invention refers to a specific area in the signal reference layer of the circuit board where no obstacles such as components, traces, and vias are placed.

[0050] In the above-mentioned printed circuit board provided by the embodiment of the present invention, a clearance area is set in the signal reference layer, and part of the clearance area is located at the projection of the routing width mutation area 2 on the signal reference layer. In this way, by adding the clearance area in the signal reference layer, the distance of the characteristic impedance change can be extended, and the impedance change rate of the routing 1 can be adjusted, so that the electric field distribution between the routing 1 and the reference ground is more uniform, thereby achieving a smooth transition of the characteristic impedance of the routing 1, improving the continuity of the characteristic impedance of the routing 1, reducing the signal reflection caused by it, effectively improving the performance of the routing, maintaining the integrity of the signal, ensuring that the signal maintains a high quality during the transmission process, and solving the problem that the characteristic impedance of the high-speed signal routing changes suddenly and affects the signal transmission quality; and reducing signal reflection can reduce electromagnetic radiation and interference, and improve the electromagnetic compatibility of the system.

[0051] It should be pointed out that when a signal is sent from the signal source and propagates along trace 1, if the characteristic impedance of trace 1 changes at a certain point (impedance mismatch point), the signal will be reflected at that point. The degree of reflection depends on the magnitude of the impedance change and the frequency of the signal, while the direction of the reflected wave depends on the position of the signal source relative to the impedance change point. Impedance discontinuity can cause signal reflections, leading to signal integrity issues. This effect can be explained by the following aspects:

[0052] The first aspect is the reflection coefficient. The reflection coefficient is determined by the input impedance and the load impedance, and its calculation formula is:

[0053] Γ = (Zl-Zi) / (Zl+Zi);

[0054] Among them, Γ represents the reflection coefficient, Zi is the input impedance, and Zl represents the load impedance.

[0055] When the impedance becomes larger, the reflection coefficient will also be larger, resulting in more obvious reflections.

[0056] When there is an impedance change on the trace 1, if the smooth transition region of this impedance change is longer, that is, the longer the physical length required for the impedance value to gradually and smoothly transition from one state to another, the signal will experience less impedance mismatch in this transition region, so the reflection and loss will be reduced accordingly. Especially in high-frequency applications, due to the shorter wavelength of the signal, they are more sensitive to impedance discontinuity. Therefore, the present invention can more effectively reduce the reflection and loss of high-frequency signals by designing a longer smooth transition region, that is, a smoother impedance change, thereby improving the transmission performance of the signal. Smooth transition region: This refers to the impedance value gradually and smoothly changing during the transition process, avoiding sudden jumps or mutations.

[0057] The second aspect is the sensitivity of high frequency signals. Since high frequency signals have shorter wavelengths, they are more susceptible to small changes on the trace 1, including impedance discontinuities. Therefore, in high frequency applications, the present invention focuses on the smoothness and continuity of impedance changes.

[0058] The third aspect is to improve transmission performance. By designing a longer smooth transition area, the present invention can reduce reflection and loss of signals during transmission, thereby improving signal integrity and quality. This is particularly important for high-frequency applications such as high-speed data transmission and wireless communication.

[0059] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided by the embodiment of the present invention, the track width mutation area 2 can be a region where the track 1 changes from the first width to the second width or from the second width to the first width; wherein the first width can be greater than the second width. The width of the clearance area can be less than the first width and greater than the second width.

[0060] In implementation, the line width mutation region 2 may be a region where the line 1 changes from thick to thin, or a region where the line 1 changes from thin to thick. Figure 1 As shown in the figure, the characteristic impedance of trace 1 can change from 50 ohms to 75 ohms along the direction from thick to thin. Figure 2 As shown, the line 1 changes from the first width a to the second width b, and the line width mutation area 2 is the area where the line 1 changes from the first width a to the second width b. The first width a is greater than the second width b. Figure 3 As shown, the width c of the clearance area 3 may be smaller than the first width a and larger than the second width b, that is, b<c<a.

[0061] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided by the embodiment of the present invention, the length e of the clearance area 3 along the extension direction of the trace 1 may be greater than the length d of the trace width mutation area 2 .

[0062] In implementation, Figure 2 As shown, the length d of the track width mutation zone 2 can be understood as the change distance of the characteristic impedance of the track 1, indicating the distance interval in which the characteristic impedance changes. When the length d of the track width mutation zone 2 is small, the characteristic impedance changes relatively quickly, which means that the characteristic impedance undergoes a large change in a shorter length. On the contrary, when the length d of the track width mutation zone 2 is long, the characteristic impedance changes relatively slowly because the characteristic impedance gradually transitions in a longer length.

[0063] In order to optimize the performance of the routing line 1, the present invention considers that the change of the characteristic impedance should be as smooth as possible to reduce the reflection and loss of the signal during the transmission process. Therefore, the present invention smoothes the characteristic impedance of the routing line 1 by extending the length d of the routing width mutation area 2. In this way, the characteristic impedance can be gradually transitioned over a longer distance, thereby avoiding sudden impedance jumps and reducing signal discontinuity.

[0064] In actual operation, impedance change may occur in the trace width mutation area 2 in the signal trace layer, and the impedance change distance is Figure 2The length d shown in the figure, the present invention adds a clearance area 3 in the signal reference layer at the projection of the line width mutation area 2 to optimize the impedance change of the line 1, so that the distance of the impedance change d is extended by adding the clearance area 3 to the reference ground. This method not only effectively improves the performance of the line 1, but also improves the integrity and quality of the signal.

[0065] It should be noted that although extending the length of d can smooth the characteristic impedance, an excessively long d may also cause the transmission line to occupy more space resources. Therefore, in actual design, the present invention can weigh the relationship between the length of d and the performance of the routing 1 according to specific application scenarios and requirements.

[0066] The distance d represents the distance of characteristic impedance change. The smaller d is, the faster the characteristic impedance changes. The longer d is, the slower the characteristic impedance changes. Therefore, the present invention smoothes the characteristic impedance of the trace by extending d. It can be understood that the characteristic impedance of the trace is related to many factors, including the thickness, line width, material, reference ground, etc. Here, the present invention extends the distance d by designing a clearance area 3 in the signal reference layer. Figure 3 As shown, the length e of the clearance area 3 along the extension direction of the line 1 can be greater than the length d of the line width mutation area 2, that is, e>d. In this way, the characteristic impedance of the line 1 can be effectively adjusted.

[0067] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided by the embodiment of the present invention, the length e of the clearance area 3 along the extension direction of the trace 1 may be less than or equal to twice the length d of the trace width mutation area 2 .

[0068] In implementation, since the length e of the clearance area 3 along the extension direction of the routing line 1 cannot be too large, otherwise it will affect the signal quality of the routing line. Therefore, the length e of the clearance area 3 along the extension direction of the routing line 1 of the present invention can be set to be less than or equal to twice the length d of the routing width mutation zone 2, that is, e≤2d.

[0069] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided by an embodiment of the present invention, the cross-sectional shape of the clearance area 3 along the plane direction where the signal reference layer is located can be a regular geometric figure. The regular geometric figure can include at least one of a rhombus, an ellipse, and a hexagon.

[0070] In implementation, the present invention can adjust the layout or shape of the signal reference layer by changing the shape of the clearance area 3 in the signal reference layer, further making the electric field distribution between the routing and the reference ground more uniform, thereby achieving a smooth transition of the characteristic impedance and ensuring the integrity and quality of the signal.

[0071] The cross-sectional shape of the clearance area 3 of the present invention along the plane direction where the signal reference layer is located can be designed as a regular geometric figure. The regular geometric figure can be a rhombus, an ellipse, a hexagon, etc. That is, the cross-sectional shape of the clearance area 3 along the plane direction where the signal reference layer is located can be a rhombus, an ellipse or a hexagon, etc. When the cross-sectional shape of the clearance area 3 along the plane direction where the signal reference layer is located is a rhombus, the two sides of the rhombus can be separately styled during the manufacturing process to form a rhombus-like figure, and when it is infinitely divided, an ellipse-like figure can be formed.

[0072] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided in an embodiment of the present invention, when the cross-sectional shape of the clearance area 3 along the plane direction where the signal reference layer is located is a rhombus, the first diagonal line of the rhombus can be parallel to the routing extension direction, and the second diagonal line can be perpendicular to the routing extension direction; the length of the second diagonal line can be less than the first width and greater than the second width; the length of the first diagonal line is greater than the length of the routing width mutation zone 2 and is less than or equal to twice the length of the routing width mutation zone 2.

[0073] In implementation, Figure 3 As shown, the cross-sectional shape of the clearance area 3 along the plane direction where the signal reference layer is located is a rhombus, and the rhombus has a first diagonal line and a second diagonal line. The first diagonal line of the rhombus can be parallel to the extension direction of the routing line 1, and the second diagonal line can be perpendicular to the extension direction of the routing line 1. The length of the second diagonal line can be less than the first width a and greater than the second width b; the length of the first diagonal line is greater than the length d of the routing width mutation area 2 and less than or equal to twice the length d of the routing width mutation area 2.

[0074] When the cross-sectional shape of the clearance area 3 along the plane where the signal reference layer is located is an ellipse, the ellipse has a major axis and a minor axis, the major axis of the ellipse can be parallel to the extension direction of the trace 1, and the minor axis can be perpendicular to the extension direction of the trace 1. The length of the minor axis can be less than the first width a and greater than the second width b; the length of the major axis is greater than the length d of the trace width mutation area 2 and less than or equal to twice the length d of the trace width mutation area 2.

[0075] When the cross-sectional shape of the clearance area 3 along the plane where the signal reference layer is located is a hexagon, the hexagon has a first symmetry axis and a second symmetry axis that are perpendicular to each other, the first symmetry axis of the hexagon can be parallel to the extension direction of the routing 1, and the second symmetry axis can be perpendicular to the extension direction of the routing 1. The length of the second symmetry axis can be less than the first width a and greater than the second width b; the length of the first symmetry axis is greater than the length d of the routing width mutation region 2 and less than or equal to twice the length d of the routing width mutation region 2.

[0076] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided in the embodiment of the present invention, the signal reference layer may be located directly above the signal routing layer; or, the signal reference layer may be located directly below the signal routing layer.

[0077] In implementation, the signal reference layer may be located directly above or directly below the signal routing layer, as long as the signal reference layer is adjacent to the signal routing layer, which is not limited herein.

[0078] Further, in a specific implementation, in the above-mentioned printed circuit board provided in an embodiment of the present invention, the signal reference layer may include a first signal reference layer and a second signal reference layer; the signal routing layer may include a first signal routing layer, a second signal routing layer and a third signal routing layer; the first signal reference layer is located between the first signal routing layer and the second signal routing layer; the second signal reference layer is located between the second signal routing layer and the third signal routing layer; the distance between the first signal reference layer and the second signal reference layer ranges from 4 mil to 10 mil; the dielectric constant of the dielectric material between the first signal reference layer and the second signal reference layer ranges from 4.0 to 4.8; the first signal reference layer and the second signal reference layer are both planar layers made of conductive materials; the first signal reference layer and / or the second signal reference layer include the clearance area.

[0079] In implementation, the signal reference layer can have multiple layers, and the signal routing layer can also have multiple layers. Assuming that the signal reference layer includes a first signal reference layer and a second signal reference layer, and the signal routing layer includes a first signal routing layer, a second signal routing layer, and a third signal routing layer, the first signal reference layer can be located between the first signal routing layer and the second signal routing layer; the second signal reference layer is located between the second signal routing layer and the third signal routing layer. Such an interval arrangement ensures that the signal reference layer is adjacent to the signal routing layer.

[0080] The distance between two adjacent signal reference layers can be set to between 4mil and 10mil; the dielectric material between two adjacent signal reference layers can be selected from FR4 (glass fiber epoxy resin), and its dielectric constant can be set to between 4.0 and 4.8. The present invention can accurately control the value of characteristic impedance by designing the distance between these adjacent signal reference layers, the dielectric constant of the dielectric material, and the geometric dimensions (such as length, width or curvature) of the clearance area where the routing is changed. In this way, the transmission of signals on the circuit board can be ensured to be more stable, and the overall performance and reliability of the circuit can be improved.

[0081] In addition, the first signal reference layer and the second signal reference layer of the present invention can both be planar layers made of conductive materials. In fact, all signal reference layers can be specifically planar layers made of copper foil. The first signal reference layer and / or the second signal reference layer can include a clearance area 3, that is, all signal reference layers of the present invention can be provided with a clearance area 3, or only part of the signal reference layers can be provided with a clearance area 3. The clearance area can be drawn in the signal reference layer when drawing a picture, and the desired clearance area profile is given an empty attribute, which is equivalent to deducting the clearance area from the copper foil, so that the impedance change is more gentle, thereby reducing the reflection of the signal and reducing the signal noise.

[0082] Assume that the printed circuit board provided by the present invention has 12 layers, and the stacking arrangement is L1, L2, ..., L12, wherein L1 is the first signal routing layer, L2 is the first signal reference layer, L3 is the second signal routing layer, L4 is the first power layer, L5 is the second signal reference layer, L6 is the third signal routing layer, L7 is the third signal reference layer, L8 is the second power layer, L9 is the fourth signal reference layer, L10 is the fourth signal routing layer, L11 is the fifth signal reference layer, and L12 is the fifth signal routing layer. The routing can be arranged on the above-mentioned signal routing layer, and the signal routing layer must have an adjacent signal reference layer. The present invention can add a clearance area on the signal reference layer and at the projection of the impedance change area, and optimize the change of routing impedance by changing the shape of the clearance area.

[0083] Furthermore, in a specific implementation, in the above-mentioned printed circuit board provided in an embodiment of the present invention, an impedance matcher is installed on the surface of the printed circuit board, one end of the impedance matcher is connected to a trace of a first width a, and the other end of the impedance matcher is connected to a trace of a second width b. Such an impedance matcher can ensure that the energy of the signal source is efficiently transmitted to the load end, further reduce reflection and loss of the signal during transmission, enable the load to obtain maximum power, and effectively avoid signal distortion, overshoot and ringing problems caused by the superposition of reflected waves and original signals, reduce signal fluctuations and interference caused by impedance mismatch, reduce system noise, and further ensure signal accuracy and stability.

[0084] In the above embodiments, the printed circuit board is described in detail. Based on the same inventive concept, the embodiments of the present invention also provide an embodiment corresponding to a method for manufacturing a printed circuit board.

[0085] Figure 4 Flow chart of the method for manufacturing a printed circuit board provided in an embodiment of the present invention. The method for manufacturing a printed circuit board provided in this embodiment, such as Figure 4 As shown, the specific steps include:

[0086] S401. Set a routing width mutation area on the signal routing layer.

[0087] S402, forming a clearance area on a signal reference layer adjacent to the signal routing layer; part of the clearance area is located at a projection of the routing width mutation area on the signal reference layer.

[0088] In the method for manufacturing the printed circuit board provided in the embodiment of the present invention, a clearance area can be formed in the signal reference layer by executing the above steps S401 and S402, and part of the clearance area is located at the projection of the line width mutation area on the signal reference layer. In this way, by adding the clearance area in the signal reference layer, the distance of the characteristic impedance change can be extended, and the impedance change rate of the line can be adjusted, so that the electric field distribution between the line and the reference ground is more uniform, thereby achieving a smooth transition of the characteristic impedance of the line, improving the continuity of the characteristic impedance of the line, reducing the signal reflection caused by it, effectively improving the performance of the line, maintaining the integrity of the signal, ensuring that the signal maintains a high quality during the transmission process, and solving the problem that the characteristic impedance of the high-speed signal line changes suddenly and affects the signal transmission quality; and reducing signal reflection can reduce electromagnetic radiation and interference, and improve the electromagnetic compatibility of the system.

[0089] Since the embodiments of the manufacturing method part correspond to the embodiments of the printed circuit board part, the embodiments of the manufacturing method part refer to the description of the embodiments of the printed circuit board part, which will not be repeated here. And it has the same beneficial effects as the printed circuit board mentioned above.

[0090] Further, in the specific implementation, in the method for manufacturing the printed circuit board provided in the embodiment of the present invention, step S402 forms a clearance area on the signal reference layer adjacent to the signal routing layer, which may specifically include: forming a clearance area on the signal reference layer adjacent to the signal routing layer, the clearance area having a cross-sectional shape along the plane direction of the signal reference layer being a regular geometric figure. The regular geometric figure may include at least one of a rhombus, an ellipse, and a hexagon.

[0091] For more specific working processes of the above steps, please refer to the corresponding contents disclosed in the above embodiments, which will not be repeated here.

[0092] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned printed circuit board. Since the principle of solving the problem by the electronic device is similar to that of the above-mentioned printed circuit board, the implementation of the electronic device can refer to the implementation of the printed circuit board, and the repeated parts will not be repeated.

[0093] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0094] Finally, it should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "include", "comprise" and "have" and any other variations thereof in the present application are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the elements. In the present application, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0095] For the above-mentioned embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the order of the actions described, because according to the present invention, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0096] Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on these embodiments, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in this field can still combine, add, delete or make other adjustments to the features in the embodiments of the present invention according to the circumstances without conflict and without making creative work, so as to obtain different other technical solutions that do not deviate from the concept of the present invention in essence, and these technical solutions also belong to the scope of protection of the present invention.

[0097] The printed circuit board and its manufacturing method and electronic device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention, but not to limit the protection scope of the invention; at the same time, for ordinary technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A printed circuit board, characterized in that: include: A signal routing layer, and a signal reference layer adjacent to the signal routing layer; Wherein, the signal routing layer includes a routing width mutation area; The signal reference layer includes a clearance area; a portion of the clearance area is located at the projection of the routing width mutation area on the signal reference layer.

2. The printed circuit board according to claim 1, characterized in that: The line width mutation area is the area where the line changes from the first width to the second width or from the second width to the first width; wherein the first width is greater than the second width; The width of the clearance area is smaller than the first width and larger than the second width.

3. The printed circuit board according to claim 2, characterized in that: The length of the clearance area along the extension direction of the routing is greater than the length of the routing width mutation area.

4. The printed circuit board according to claim 3, characterized in that: The length of the clearance area along the extension direction of the line is less than or equal to twice the length of the line width mutation area.

5. The printed circuit board according to claim 4, characterized in that: The cross-sectional shape of the clearance area along the plane where the signal reference layer is located is a regular geometric figure; The regular geometric shape includes at least one of a rhombus, an ellipse, and a hexagon.

6. The printed circuit board according to claim 5, characterized in that: When the cross-sectional shape of the clearance area along the plane where the signal reference layer is located is a rhombus, the first diagonal line of the rhombus is parallel to the extension direction of the routing, and the second diagonal line is perpendicular to the extension direction of the routing; The length of the second diagonal line is smaller than the first width and larger than the second width; The length of the first diagonal line is greater than the length of the routing width mutation region and is less than or equal to twice the length of the routing width mutation region.

7. The printed circuit board according to claim 1, characterized in that: The signal reference layer is located directly above the signal routing layer; Alternatively, the signal reference layer is located directly below the signal routing line.

8. The printed circuit board according to claim 1, characterized in that: The signal reference layer includes a first signal reference layer and a second signal reference layer; The signal routing layer includes a first signal routing layer, a second signal routing layer and a third signal routing layer; The first signal reference layer is located between the first signal routing layer and the second signal routing layer; The second signal reference layer is located between the second signal routing layer and the third signal routing layer; The distance between the first signal reference layer and the second signal reference layer ranges from 4 mil to 10 mil; The dielectric constant of the dielectric material between the first signal reference layer and the second signal reference layer is in the range of 4.0 to 4.8; The first signal reference layer and the second signal reference layer are both planar layers made of conductive materials; The first signal reference layer and / or the second signal reference layer includes the clearing area.

9. A method for manufacturing a printed circuit board, characterized in that: include: Set the routing width mutation area on the signal routing layer; forming a clearance area on a signal reference layer adjacent to the signal routing layer; Part of the clearance area is located at the projection of the routing width mutation area on the signal reference layer.

10. An electronic device, characterized in that: Comprising a printed circuit board as claimed in any one of claims 1 to 8.

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