Semiconductor structure and method for manufacturing the same

Abstract

The present application provides a semiconductor structure and a preparation method thereof, which relates to the field of semiconductor technology. The method includes: providing a substrate provided with a gate structure; forming a first groove in the substrate between the gate structures; etching a sigma groove in the first groove to obtain a connected groove consisting of the first groove and the sigma groove; wherein the top width of the sigma groove is smaller than the bottom width of the first groove; epitaxial growth of germanium silicon is performed in the connected groove to form a germanium silicon epitaxial layer to obtain a semiconductor structure; in the germanium silicon epitaxial layer, the first epitaxial layer is arranged on the sidewall and bottom of the connected groove; the second epitaxial layer is arranged in the middle area of ​​the connected groove, and fills the connected groove with the first epitaxial layer; the boron atom concentration in the second epitaxial layer is higher than the boron atom concentration in the first epitaxial layer. The present application can alleviate the leakage problem caused by the diffusion of boron atoms in the second epitaxial layer into the channel, and improve the device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As CMOS technology enters the critical size of 28 nm and below, in order to achieve the performance requirements of PMOS devices, the source and drain embedded in germanium silicon process began to be applied. This process uses the compressive stress generated by the difference in lattice constants of germanium and silicon to embed in the source and drain regions, thereby improving the mobility and saturation current of PMOS holes.

[0003] In the germanium silicon epitaxial technology, the use of sigma trenches can reduce the spacing between adjacent trenches compared to ordinary trenches, thereby increasing channel stress and improving device performance. Studies have shown that step-concentration SiGe epitaxy can achieve higher strain, so three layers of germanium silicon epitaxial layers are usually grown inside and above the sigma trench, and doping silicon with boron can increase the hole concentration of the source and drain, thereby increasing the conductivity of the semiconductor material. Due to the difference in the concentration of boron atoms doped in different epitaxial layers, and the thickness of the epitaxial layer at the edge of the sigma trench is very thin, it is easy for the boron atoms in the epitaxial layer to diffuse from the edge of the sigma trench to the channel and accumulate in the channel, causing serious leakage and resulting in reduced device performance. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor structure and a method for preparing the same, so as to alleviate the leakage problem caused by the diffusion of boron in the second epitaxial layer into the channel in the sigma trench and improve the device performance.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, the method comprising: providing a substrate provided with a gate structure; forming a first trench in the substrate between the gate structures; etching in the first trench to form a sigma trench, to obtain a connecting trench consisting of the first trench and the sigma trench; wherein the top width of the sigma trench is smaller than the bottom width of the first trench; performing germanium-silicon epitaxial growth in the connecting trench to form a germanium-silicon epitaxial layer, to obtain a semiconductor structure; wherein, in the germanium-silicon epitaxial layer, the first epitaxial layer is arranged on the side wall and the bottom of the connecting trench; the second epitaxial layer is arranged in the middle area of ​​the connecting trench, and fills the entire connecting trench with the first epitaxial layer; the boron concentration in the second epitaxial layer is higher than the boron concentration in the first epitaxial layer.

[0006] Furthermore, the above-mentioned gate structure includes a gate layer structure and a first sidewall arranged on both sides of the gate layer structure; before the step of forming a first trench in the substrate between the gate structures, it also includes: depositing a silicon dioxide layer covering the gate structure on the substrate; the step of forming the first trench in the substrate between the gate structures includes: removing the silicon dioxide layer covering the top of the gate structure and on the substrate except the gate structure, forming a second sidewall on both sides of the gate structure, and forming a first trench in the substrate between the gate structures including the second sidewall.

[0007] Furthermore, the step of etching a sigma trench in the first trench to obtain a connecting trench consisting of the first trench and the sigma trench includes: depositing a silicon nitride layer covering the first trench and the gate structure including the second sidewall; etching the silicon nitride layer to form a third sidewall on both sides of the gate structure, and forming a second trench in the substrate between the gate structures including the third sidewall; etching the second trench to form a sigma trench; removing the third sidewall to form a connecting trench consisting of the first trench and the sigma trench between the gate structures.

[0008] Furthermore, the step of performing epitaxial growth of silicon germanium in the connecting grooves to form a silicon germanium epitaxial layer includes: moving the substrate structure forming the connecting grooves into the epitaxial chamber while maintaining vacuum conditions; introducing a first specified gas into the epitaxial chamber to form a first epitaxial layer on the side walls and the bottom of the connecting grooves; the first specified gas includes: H2, HCl, SiH2Cl2, GeH4, B2H6; increasing the current reaction temperature and the concentration and flow rate of GeH4 and B2H6 gases to form a second epitaxial layer filling the connecting grooves on the basis of the first epitaxial layer; the germanium boron content of the second epitaxial layer is greater than the germanium boron content in the first epitaxial layer.

[0009] Furthermore, the first epitaxial layer includes a first sub-epitaxial layer formed on the sidewall of the first trench, and a second sub-epitaxial layer formed on the sidewall and bottom of the sigma trench.

[0010] Furthermore, the upper surface of the above-mentioned second epitaxial layer is flush with the upper surface of the first sub-epitaxial layer; after the step of forming the second epitaxial layer filling the connecting grooves on the basis of the first epitaxial layer, it also includes: continuing to introduce SiH2Cl2 and B2H6 gases into the epitaxial chamber to form a third epitaxial layer covering the first sub-epitaxial layer and the second epitaxial layer.

[0011] Furthermore, the upper surface of the second epitaxial layer is higher than the upper surface of the first sub-epitaxial layer and covers the first epitaxial layer; after the step of forming the second epitaxial layer filling the connecting grooves on the basis of the first epitaxial layer, it also includes continuing to introduce SiH2Cl2 and B2H6 gases into the epitaxial chamber to form a third epitaxial layer covering the second epitaxial layer.

[0012] Furthermore, the side-view thickness of the first sub-epitaxial layer is greater than or equal to the side-view thickness at a position where the third side wall and the substrate meet.

[0013] In the second aspect, the present application also provides a semiconductor structure, which includes: a substrate; a plurality of gate structures, arranged on the substrate; a connecting groove formed by a first groove and a sigma groove connected up and down is opened in the substrate between the gate structures; wherein the top width of the sigma groove is smaller than the bottom width of the first groove; a germanium silicon epitaxial layer, arranged in the connecting groove; wherein the first epitaxial layer is arranged on the side wall and bottom of the connecting groove; the second epitaxial layer is arranged in the middle area of ​​the connecting groove, and fills the entire connecting groove with the first epitaxial layer; the boron concentration in the second epitaxial layer is higher than the boron concentration in the first epitaxial layer.

[0014] Furthermore, the above-mentioned first epitaxial layer includes a first sub-epitaxial layer formed on the side wall of the first trench, and a second sub-epitaxial layer formed on the side wall and bottom of the sigma trench; the germanium silicon epitaxial layer also includes: a third epitaxial layer; the upper surface of the second epitaxial layer is higher than the upper surface of the first sub-epitaxial layer and covers the first sub-epitaxial layer, and the third epitaxial layer covers the second epitaxial layer; or, the upper surface of the second epitaxial layer is flush with the upper surface of the first sub-epitaxial layer, and the third epitaxial layer covers the first sub-epitaxial layer and the second epitaxial layer.

[0015] The unexpected technical effect of the present application is that in the semiconductor structure and preparation method thereof provided by the present application, a first trench is formed in the substrate between the gate structures, and a sigma trench whose top width is smaller than the bottom width of the first trench is formed in the first trench, and finally a connecting trench consisting of the first trench and the sigma trench is formed. Since in the connecting trench, the width of the first trench is wider than the width of the top of the sigma trench below, after the first epitaxial layer is epitaxially grown on the side wall of the connecting trench, the side-view thickness of the first epitaxial layer in the first trench can be made thicker, thereby slowing down the diffusion of boron atoms in the second epitaxial layer into the channel, reducing the leakage phenomenon caused by the accumulation of boron atoms in the channel, and thus improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 The present invention is a schematic diagram of a semiconductor structure including a sigma trench epitaxial structure provided in the prior art.

[0018] Figure 2A flowchart of a method for preparing a semiconductor structure provided in one embodiment of the present application.

[0019] Figure 3 A schematic cross-sectional view of a semiconductor structure for forming a substrate and a gate structure provided in one embodiment of the present application.

[0020] Figure 4 A schematic cross-sectional view of a semiconductor structure after a first trench is formed according to an embodiment of the present application.

[0021] Figure 5 A schematic cross-sectional view of a semiconductor structure after forming a sigma trench according to an embodiment of the present application.

[0022] Figure 6 A schematic cross-sectional view of a semiconductor structure after forming a connecting trench according to an embodiment of the present application.

[0023] Figure 7 A schematic cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present application.

[0024] Figure 8 A schematic cross-sectional view of a semiconductor structure after forming a first sub-epitaxial layer and a second sub-epitaxial layer provided in one embodiment of the present application.

[0025] Fig. 9 A schematic cross-sectional view of another semiconductor structure provided in accordance with an embodiment of the present application.

[0026] Fig.10 A schematic cross-sectional view of a semiconductor structure after forming a detailed structure of a gate structure according to an embodiment of the present application.

[0027] Fig.11 A schematic cross-sectional view of a semiconductor structure after a silicon dioxide layer is deposited according to an embodiment of the present application.

[0028] Fig.12 A schematic cross-sectional view of a semiconductor structure after forming a second sidewall spacer and a first trench according to an embodiment of the present application.

[0029] Fig.13 A schematic cross-sectional view of a semiconductor structure after a silicon nitride layer is deposited according to an embodiment of the present application.

[0030] Fig.14 A schematic cross-sectional view of a semiconductor structure after forming a second trench and a third sidewall spacer according to an embodiment of the present application.

[0031] Fig.15 A schematic cross-sectional view of a semiconductor structure after a sigma trench is formed based on a third sidewall spacer according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0033] The existing epitaxial structure based on sigma trench usually grows three layers of SiGe in the sigma trench, such as Figure 1 The three epitaxial layers L1, L2, and L3 shown in the figure are doped with boron to increase the hole concentration of the source and drain. For the sigma structure, the thickness of the top first epitaxial layer is relatively thin, and the concentration of boron atoms between the second epitaxial layer and the first epitaxial layer is quite different, so it is easy for the boron atoms in the second epitaxial layer L2 to diffuse into the channel, causing the boron atoms to accumulate in the channel, causing serious leakage, and thus reducing the device performance.

[0034] In order to solve the above leakage problem, two solutions are generally adopted in the prior art. First, the leakage is reduced by slowing down the device speed, but slowing down the device speed will cause the product yield to be lower during the final test; second, the boron concentration of the epitaxial layer is reduced to reduce boron diffusion, but an epitaxial layer with too low a concentration will cause device performance to decrease. Based on this, an embodiment of the present application provides a semiconductor structure and a preparation method thereof. This technology can alleviate the leakage problem caused by the diffusion of boron atoms in the epitaxial layer in the sigma groove and ensure device performance by thickening the thickness of the first epitaxial layer L1 at the channel to form a structure similar to a buffer layer. To facilitate the understanding of this embodiment, a preparation method of a semiconductor structure disclosed in an embodiment of the present application is first introduced in detail.

[0035] Figure 2 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application, the method specifically comprises the following steps:

[0036] Step S202, providing a substrate provided with a gate structure; Figure 3 As shown, a plurality of gate structures 11 are disposed on the substrate 10 (as shown in the dotted line frame in the figure), and a preset spacing distance is set between adjacent gate structures 11 .

[0037] The above-mentioned gate structure generally includes a gate layer structure and sidewalls arranged on both sides of the gate layer structure, and the gate layer structure includes multiple layers, for example, a silicon oxide layer, a high-K gate dielectric layer, a cap layer (Cap layer, including a titanium nitride layer or a titanium layer), a polysilicon layer, a hard mask layer (Hard Mask Layer, including a silicon nitride layer and a silicon oxide layer) grown sequentially from bottom to top. The above-mentioned sidewalls may include a single sidewall or multiple sidewalls, which may be arranged according to actual needs.

[0038] Step S204, forming a first trench in the substrate between the gate structures; Figure 4 As shown, a first trench 12 is formed in the substrate between every two adjacent gate structures (as shown in the dotted line frame in the figure), and the depth of the first trench 12 is 5nm-10nm. The first trench 12 is formed by dry etching the substrate, for example, using CHF3, CF4 gas for dry etching.

[0039] Step S206, etching to form a sigma groove in the first groove to obtain a connected groove consisting of the first groove and the sigma groove; wherein the top width of the sigma groove is smaller than the bottom width of the first groove;

[0040] In a specific implementation, the sigma trench 13 is formed by continuing to etch in the substrate below the first trench 12; Figure 5 As shown, a connecting groove 14 consisting of the first groove 12 and the sigma groove 13 is obtained, as shown in FIG. Figure 6 shown.

[0041] The top width of the above-mentioned sigma groove 13 is smaller than the bottom width of the first groove 12. In a specific implementation, side walls arranged on both sides of the gate structure 11 can be prepared in the first groove 12, and then the etching process of the sigma groove 13 is carried out in the substrate between the gate structures including the side walls. The sigma groove 13 can be completed by a wet etching process; finally, the side walls on both sides of the gate structure 11 are removed to obtain a connecting groove 14.

[0042] Step S208, performing epitaxial growth of silicon germanium in the connecting groove to form a silicon germanium epitaxial layer to obtain a semiconductor structure; wherein, in the silicon germanium epitaxial layer, a first epitaxial layer is arranged on the side wall and bottom of the connecting groove; a second epitaxial layer is arranged in the middle area of ​​the connecting groove and fills the entire connecting groove with the first epitaxial layer; and a boron concentration in the second epitaxial layer is higher than a boron concentration in the first epitaxial layer.

[0043] As a possible implementation manner, the method further includes epitaxially growing a third epitaxial layer above the connecting trench.

[0044] Epitaxial growth of germanium silicon generally involves many gases, and the main gases may include a variety of the following gases: hydrogen, hydrogen chloride, dichlorosilane, silane, germane and diborane; these gases play different roles in the germanium silicon epitaxial process, including providing a stable reaction environment, cleaning the surface, adjusting the composition and growth rate, and doping the required impurities. By reasonably controlling the use and parameters of these gases, high-quality germanium silicon epitaxial growth can be achieved and device performance can be improved. In the embodiments of the present application, the epitaxial process can achieve the effect of growing epitaxial layers with different doping concentrations by adjusting some process conditions, such as gas concentration and gas flow rate, etc.

[0045] In the embodiment of the present application, the first epitaxial layer L1 can be grown first, then the second epitaxial layer L2 can be grown, and finally the third epitaxial layer L3 can be grown. The germanium and boron contents of the three epitaxial layers (there is no germanium in the third epitaxial layer) are different. The flow rate and time of gases such as HCl, SiH2Cl2, GeH4, B2H6 are adjusted to make the Ge and B concentrations in different layers different.

[0046] The preparation process of the germanium silicon epitaxial layer is described in detail below, including the following steps:

[0047] (1) The substrate structure with the connected grooves is moved into the epitaxial chamber under vacuum conditions.

[0048] (2) introducing a first designated gas into the epitaxial chamber to form a first epitaxial layer L1 on the sidewalls and the bottom of the communicating groove; the first designated gas includes: H2, HCl, SiH2Cl2, GeH4, B2H6;

[0049] Among them, H2 is mainly used to provide a suitable atmosphere and a stable reaction environment, thereby improving the quality and stability of epitaxial growth; HCl is used to remove impurities and residues generated in the sigma trench reaction and inhibit the growth of germanium silicon, thereby selectively growing in specific areas.

[0050] In the embodiment of the present application, the germanium content in the first epitaxial layer L1 is between 15% and 30%, and the boron atom doping concentration is between 5E18 and 1E20.

[0051] like Figure 7 As shown, the first epitaxial layer L1 is arranged on the sidewall and bottom of the connecting trench, specifically including a first sub-epitaxial layer L11 formed on the sidewall of the first trench, and a second sub-epitaxial layer L12 formed on the sidewall and bottom of the sigma trench, as shown in FIG. Figure 8 As shown. The side-view thickness of the first sub-epitaxial layer L11 is greater than or equal to the side-view thickness at the position where the third sidewall and the substrate meet. In this way, it can be ensured that the first epitaxial layer L1 shields the silicon substrate to prevent the subsequent epitaxial second epitaxial layer L2 from directly contacting the silicon substrate, resulting in lattice mismatch and dislocation defects.

[0052] In one embodiment, the side-view thickness of the first epitaxial sub-layer L11 (eg Figure 8 In this case, the second sub-epitaxial layer L12 just completely covers the sigma groove, that is, the substrate is not exposed, so that the substrate and the second epitaxial layer L2 are not in contact, thereby avoiding the generation of lattice mismatch and dislocation defects.

[0053] In another embodiment, the side-view thickness D1 of the first sub-epitaxial layer L11 is slightly larger than the side-view thickness at the junction of the third side wall and the substrate. For example, the side-view thickness of the third side wall is between 9nm and 11nm, and the side-view thickness of the first sub-epitaxial layer is approximately between 10nm and 15nm. In this case, the first sub-epitaxial layer L11 and the second sub-epitaxial layer L12 are actually connected as an integral buffer layer, that is, the second epitaxial layer is thicker than the substrate. Figure 8 The one shown in is narrower and will not contact the silicon substrate, avoiding the generation of lattice mismatch and dislocation defects.

[0054] (3) The current reaction temperature and the concentration and flow rate of GeH4 and B2H6 gases are increased to form a second epitaxial layer L2 that fills the connected grooves on the basis of the first epitaxial layer L1; the germanium-boron content of the second epitaxial layer L2 is greater than the germanium-boron content of the first epitaxial layer L1. In the embodiment of the present application, the germanium content of the second epitaxial layer is between 30% and 45%, and the boron atom doping concentration is between 1E20 and 5E20.

[0055] In one embodiment, the second epitaxial layer L2 is arranged in the middle area of ​​the connecting groove, and its side cross-sectional view is similar to a U-shaped structure, and fills the entire connecting groove with the first epitaxial layer L1, and the upper surface of the second epitaxial layer L2 is flush with the upper surface of the first sub-epitaxial layer L11; after the step of forming the second epitaxial layer L2 on the basis of the first epitaxial layer L1, it also includes: continuing to introduce SiH2Cl2 and B2H6 gases into the epitaxial chamber to form a third epitaxial layer L3 covering the first sub-epitaxial layer L11 and the second epitaxial layer L2, such as Figure 7 As shown in . The third epitaxial layer L3 may form a metal silicide to reduce the resistance of the resulting source / drain region.

[0056] In another embodiment, the upper surface of the second epitaxial layer L2 is higher than the upper surface of the first sub-epitaxial layer L11 and covers the first sub-epitaxial layer L11; after the step of forming the second epitaxial layer L2 on the basis of the first epitaxial layer L1, the following steps are also included: SiH2Cl2 and B2H6 gases are continuously introduced into the epitaxial chamber to form a third epitaxial layer L3 covering the second epitaxial layer L2, such as Fig. 9 As shown in FIG. 1 , since the concentration of boron atoms in the third epitaxial layer L3 is relatively high, the second epitaxial layer L2 is epitaxially higher, which can prevent the boron atoms from diffusing downward.

[0057] In the preparation method of the semiconductor structure provided in the embodiment of the present application, a first trench is formed in the substrate between the gate structures, and a sigma trench with a top width smaller than a bottom width of the first trench is formed in the first trench, and finally a connecting trench consisting of the first trench and the sigma trench is formed. Since in the connecting trench, the cross-sectional width of the first trench is wider than the cross-sectional width of the top of the sigma trench below, after the first epitaxial layer is epitaxially grown on the side wall of the connecting trench, the side-view thickness of the first sub-epitaxial layer epitaxially grown in the first trench can be made thicker, thereby slowing down the diffusion of boron atoms in the second epitaxial layer into the channel, avoiding the accumulation of boron atoms in the channel to cause leakage, thereby improving device performance.

[0058] In one embodiment, the gate structure 11 includes a gate layer structure 111 and first sidewalls 112 disposed on both sides of the gate layer structure 111. In this embodiment, the gate layer structure 111 includes a three-layer structure, such as a polysilicon layer, a silicon nitride layer, and a silicon oxide layer grown sequentially from bottom to top. Fig.10 As shown, the first sidewall 112 here can be a silicon nitride sidewall, which is used to define the doping size of the subsequent LDD (Lightly Doped Drain) process. The LDD lightly doped drain process generally injects some ions into the substrate, that is, ion implantation, which are some p-type elements, and the area is generally near the lower left and lower right areas of the gate structure; the LDD lightly doped drain process can weaken the electric field in the drain area and improve hot electron degradation.

[0059] As a possible implementation, the first sidewall 112 may be formed by the following process: depositing a silicon nitride layer covering the gate layer structure on the substrate; removing the silicon nitride layer covering the top of the gate layer structure 111 and the substrate, forming the first sidewall 112 on both sides of the gate layer structure 111, and obtaining a gate structure.

[0060] As a possible implementation, before the step of forming the first trench in the substrate between the gate structures, the step further includes: depositing a silicon dioxide layer 15 covering the gate structure 11 on the substrate 10; Fig.11 As shown, the silicon dioxide layer 15 is used to protect the gate when performing the LDD process.

[0061] As a possible implementation, the step of forming the first trench in the substrate between the gate structures includes: removing the silicon dioxide layer 15 covering the top of the gate structure and on the substrate other than the gate structure, forming a second sidewall 113 on both sides of the gate structure, and forming a first trench 12 in the substrate between the gate structures 11 including the second sidewall 113, such as Fig.12 In this embodiment, the silicon dioxide layer 15 and the first trench 12 are completed by etching once, so as to reduce the process steps and improve the manufacturing efficiency.

[0062] In another embodiment, the first sidewall and the second sidewall can also be completed by etching once. Specifically, a silicon nitride layer and a silicon dioxide layer covering the gate layer structure are first deposited on the substrate in sequence, and then, by etching once, not only the silicon nitride layer and the silicon dioxide layer on the top of the gate layer structure are removed, but also the first sidewall and the second sidewall are formed on both sides of the gate layer structure, and the first trench is formed in the substrate between the gate structure including the first sidewall and the second sidewall. This method can further reduce the process steps and improve the preparation efficiency.

[0063] As a possible implementation, the above step S206, i.e., the step of etching a sigma groove in the first groove to obtain a connecting groove consisting of the first groove and the sigma groove, specifically includes the following steps (1) to (4):

[0064] (1) depositing a silicon nitride layer 16 covering the first trench 12 and the gate structure including the second spacer 113; Fig.13 shown.

[0065] (2) etching the silicon nitride layer 16 to form a third spacer 114 on both sides of the gate structure, and forming a second trench 17 in the substrate between the gate structures including the third spacer 114;

[0066] like Fig.14 As shown, the third sidewall spacer 114 is formed on both sides of the gate structure including the first sidewall spacer 112 and the second sidewall spacer 113. In the cross section shown in the figure, the sidewall of the second trench 17 is aligned with the edge of the third sidewall spacer 114; the third sidewall spacer 114 can be a silicon nitride sidewall spacer, which is used to define the etching size of the subsequent sigma trench 14. In the first trench 12, the side view thickness of the third sidewall spacer 114 at the position where it connects with the substrate 10 is 9nm-11nm, for example, the side view thickness of the third sidewall spacer 114 at the position where it connects with the substrate 10 is 10nm; the side view thickness here refers to Fig.14 The distance shown by D2 in FIG. After epitaxy, the side-view thickness of the first epitaxial layer in the first trench is greater than or equal to the distance shown by D2. Therefore, the larger the distance, the larger the side-view thickness of the first epitaxial layer in the first trench after epitaxy, and the more it can alleviate the diffusion of boron in the second epitaxial layer into the channel. However, D2 cannot be too large, which will affect the size of the subsequent sigma trench. Therefore, when preparing the third sidewall 114, it is better to control D2 to be about 9nm-11nm.

[0067] The steps of forming the third sidewall 114 and the second trench 17 can be completed by dry etching once to reduce the process steps. For example, by dry etching with halogen gas (CHF3, CF4 gas, etc.), while forming the third sidewall 114, the second trench 17 is formed downward at the same time, and the etching depth of the second trench 17 is 45-60nm. After etching, the edge of the second trench 17 is aligned with the silicon nitride sidewall.

[0068] (3) Etching the second groove 17 to form the sigma groove 13. Fig.15 As shown, the sigma trench 13 is obtained by further etching downward on the basis of the second trench 17. After the sigma trench 13 is formed, the second trench 17 disappears.

[0069] In this step, wet etching is used, and tetramethylammonium hydroxide solution (TMAH) can be used for etching. <100> Face to face <110> The etching selectivity ratio of silicon on the surface is 40:1-70:1, which can stop the wet etching of substrate silicon at <111> surface, thereby forming a sigma groove 14. Among them, <100> noodle, <110> and <111> The direction of the face is Fig.15 shown.

[0070] (4) The third spacer 114 is removed, and a connecting trench 14 consisting of the first trench 12 and the sigma trench 13 is formed between the gate structures.

[0071] In this step, phosphoric acid solution may be used for wet etching to remove the outermost third sidewall spacer 114. Figure 6 As shown, after the third spacer 114 is removed, a connecting trench 14 consisting of a first trench and a sigma trench is formed between the gate structures 11 .

[0072] A detailed method for preparing a semiconductor structure is listed below, and the specific steps of the method include:

[0073] 1. Provide a substrate including a gate structure; the gate structure includes a gate layer structure (a polysilicon layer, a silicon nitride layer and a silicon oxide layer grown sequentially from bottom to top) and a first sidewall spacer (SiN sidewall spacer) arranged on both sides of the gate layer structure.

[0074] 2. Deposit a SiO2 layer covering the gate structure on the substrate; then perform an LDD process in the lower left and lower right areas near the gate structure to weaken the drain area electric field and improve hot electron degradation.

[0075] 3. Dry-etch the SiO2 layer on the substrate to form a second sidewall (i.e., SiO2 sidewall) on both sides of the gate structure including the first sidewall, and form a first groove aligned with the edge of the second sidewall; dry etching can use CHF3, CF4 gas, and the etching depth is about 5nm.

[0076] 4. Deposit a SiN layer covering the first trench and the gate structure including the second sidewall; the SiN layer is used to define the size of the subsequent sigma trench structure. It is necessary to ensure that the side view thickness of the SiN layer deposited on both sides of the gate structure reaches a certain thickness, which should not be too thick or too thin, and is preferably in the range of 9nm-11nm. This can make the size of the sigma trench etched later appropriate, and the side view thickness of the first epitaxial layer in the first trench is relatively thick, between 10nm-15nm, to alleviate the diffusion of boron in the second epitaxial layer into the channel.

[0077] 5. Dry-etch the SiN layer in the first trench to form a third sidewall, i.e., a SiN sidewall, on both sides of the gate structure including the first sidewall and the second sidewall, and form a second trench aligned with the edge of the SiN sidewall. The second trench is to prepare for the subsequent etching of the sigma trench;

[0078] This step can be completed by a halogen gas dry etching process, such as CHF3, CF4 gas, etc. The etching depth is 50-60nm, and the etching is flush with the SiN side wall, and the SiN side wall is slightly thinned.

[0079] 6. Wet-etching the second trench to form a sigma trench;

[0080] Wet etching uses tetramethylammonium hydroxide solution (TMAH) for etching, which is characterized by <100> Face to face <110> The etching selectivity ratio of silicon on the surface is 40:1-70:1, which can stop the wet etching of silicon at <111> surface, thereby forming a sigma groove.

[0081] 7. Remove the third sidewalls, i.e., the SiN sidewalls, on both sides of the gate structure to form a connecting trench consisting of the first trench and the sigma trench in the substrate; in this step, a phosphoric acid solution can be used to remove the outermost SiN sidewall.

[0082] 8. Silicon germanium epitaxy, specifically including the following steps:

[0083] (1) moving the substrate structure with the connected grooves into the epitaxial chamber under vacuum conditions;

[0084] (2) introducing a first designated gas into the epitaxial chamber to form a first epitaxial layer on the sidewalls and the bottom of the communicating groove; the first designated gas includes: H2, HCl, SiH2Cl2, GeH4, B2H6;

[0085] Among them, H2 is mainly used to provide a suitable atmosphere and a stable reaction environment, thereby improving the quality and stability of epitaxial growth; HCl is used to remove impurities and residues generated in the sigma trench reaction and inhibit the growth of germanium silicon, thereby selectively growing in specific areas.

[0086] In the embodiment of the present application, the germanium content of the first epitaxial layer is between 15% and 30%, and the boron atom doping concentration is between 5E18 and 1E20.

[0087] (3) The current reaction temperature and the concentration and flow rate of GeH4 and B2H6 gases are increased to form a second epitaxial layer based on the first epitaxial layer; the germanium-boron content of the second epitaxial layer is greater than the germanium-boron content of the first epitaxial layer. The upper surface of the second epitaxial layer is flush with or higher than the upper surface of the substrate.

[0088] In the embodiment of the present application, the germanium content of the second epitaxial layer is between 30% and 45%, and the boron atom doping concentration is between 1E20 and 5E20.

[0089] (4) SiH2Cl2 and B2H6 are then introduced to form a third epitaxial layer that does not contain Ge on the second epitaxial layer.

[0090] The third epitaxial layer may form a metal silicide to reduce the resistance of the resulting source / drain regions.

[0091] The method for preparing a semiconductor structure provided in the embodiment of the present application is actually a new germanium silicon epitaxial trench structure in the prepared semiconductor structure, and epitaxy is performed in the connected trench composed of the first trench and the sigma trench, so that the side-view thickness of the first epitaxial layer L1 in the first trench is thicker, that is, the side-view thickness of the aforementioned first sub-epitaxial layer is thicker, which is equivalent to forming a buffer layer, slowing down the diffusion of boron atoms in the second epitaxial layer L2 into the channel, reducing leakage, and improving device performance. The method adopted in this embodiment only adds a step of dry etching the first trench on the basis of the original process, and the process can be carried out on the same machine with the etching of the first side wall SiN and the second side wall SiO2, and the third side wall SiN is removed in advance. The whole process does not actually add a new process, and the existing equipment can be used, which saves costs and improves device performance.

[0092] Based on the above method embodiment, the present application embodiment also provides a semiconductor structure, see Figure 7 As shown, the semiconductor structure includes: a substrate 10; a plurality of gate structures 11, arranged on the substrate 10; a connecting groove 14 consisting of a first groove and a sigma groove connected up and down is opened in the substrate between the gate structures 11, as shown in the dotted box in the figure; wherein the top width of the sigma groove is smaller than the bottom width of the first groove; a germanium silicon epitaxial layer, arranged in the connecting groove; wherein the first epitaxial layer L1 is arranged on the side wall and the bottom of the connecting groove; the second epitaxial layer L2 is arranged in the middle area of ​​the connecting groove, and fills the entire connecting groove with the first epitaxial layer; the boron concentration in the second epitaxial layer L2 is higher than the boron concentration in the first epitaxial layer L1.

[0093] In the semiconductor structure provided in the embodiment of the present application, a connecting groove consisting of a first groove and a sigma groove is formed in the substrate between the gate structures. Since the top width of the sigma groove is smaller than the bottom width of the first groove, after the first epitaxial layer is epitaxially grown on the side wall of the connecting groove, the side view thickness of the first sub-epitaxial layer at the first trench can be made thicker, thereby slowing down the diffusion of boron in the second epitaxial layer into the channel, avoiding leakage caused by boron accumulation in the channel, and thus improving device performance.

[0094] Furthermore, the gate structure includes: a gate layer structure, and sidewalls disposed on both sides of the gate layer structure. The sidewalls include: a first sidewall disposed on both sides of the gate layer structure, and a second sidewall disposed on both sides of the first sidewall. The first sidewall is a silicon nitride sidewall; the second sidewall is a silicon dioxide sidewall.

[0095] In one embodiment, the first epitaxial layer includes a first sub-epitaxial layer formed on the sidewall of the first trench, and a second sub-epitaxial layer formed on the sidewall and bottom of the sigma trench. In another embodiment, the first sub-epitaxial layer at the sidewall of the first trench and the second sub-epitaxial layer at the sidewall and bottom of the sigma trench are a connected integral film layer, which plays a buffering role.

[0096] The semiconductor structure further includes: a third epitaxial layer L3; the upper surface of the second epitaxial layer L2 is flush with the upper surface of the first sub-epitaxial layer L11, and the third epitaxial layer L3 covers the first sub-epitaxial layer L11 and the second epitaxial layer L2, such as Figure 8 as shown in .

[0097] In another embodiment, the upper surface of the second epitaxial layer L2 is higher than the upper surface of the first sub-epitaxial layer L11 and covers the first sub-epitaxial layer L11, and the third epitaxial layer L3 covers the second epitaxial layer L2. Fig. 9 Generally, the concentration of boron atoms in the third epitaxial layer L3 is higher than that in the second epitaxial layer L2. Therefore, by growing the second epitaxial layer L2 higher than the substrate, the diffusion of boron atoms in the third epitaxial layer L3 into the second epitaxial layer L2 can be slowed down.

[0098] The semiconductor structure provided in the embodiment of the present application is actually a germanium silicon epitaxial trench structure, which makes the L1 epitaxial layer at the channel thicker, equivalent to forming a buffer layer, which slows down the diffusion of boron in the L2 epitaxial layer into the channel, reduces leakage, and improves device performance.

[0099] The semiconductor structure provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the structure, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0100] Based on the above method embodiment, the present application embodiment also provides a semiconductor device, which is prepared using the above semiconductor device preparation method. The semiconductor device can be applied to different electronic devices. The device provided in the present application embodiment has the same implementation principle and technical effects as the above method embodiment. For the sake of brief description, for the parts not mentioned in the device embodiment, please refer to the corresponding contents in the above method embodiment.

[0101] Based on the above structural embodiment, the embodiment of the present application further provides an electronic device, including the semiconductor structure described in the above structural embodiment. The electronic device may include optoelectronic devices, light-emitting diode devices, laser diode devices, photodetectors, solar cells, field effect transistors, charge-coupled devices, semiconductor discrete devices, power semiconductor devices, etc.

[0102] The device provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the device, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0103] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0104] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: providing a substrate provided with a gate structure; forming a first trench in the substrate between the gate structures; Etching a sigma groove in the first groove to obtain a connected groove consisting of the first groove and the sigma groove; wherein the top width of the sigma groove is smaller than the bottom width of the first groove; Germanium-silicon epitaxial growth is performed in the connecting groove to form a germanium-silicon epitaxial layer to obtain a semiconductor structure; wherein, in the germanium-silicon epitaxial layer, a first epitaxial layer is arranged on the side wall and the bottom of the connecting groove; a second epitaxial layer is arranged in the middle area of ​​the connecting groove and fills the entire connecting groove with the first epitaxial layer; and a boron concentration in the second epitaxial layer is higher than a boron concentration in the first epitaxial layer.

2. The method according to claim 1, characterized in that The gate structure includes a gate layer structure and first sidewalls disposed on both sides of the gate layer structure; Before the step of forming a first trench in the substrate between the gate structures, the method further includes: depositing a silicon dioxide layer covering the gate structure on the substrate; The step of forming a first trench in the substrate between the gate structures comprises: The silicon dioxide layer covering the top of the gate structure and on the substrate except the gate structure is removed, a second spacer is formed on both sides of the gate structure, and a first trench is formed in the substrate between the gate structures including the second spacer.

3. The method according to claim 2, characterized in that The step of etching a sigma groove in the first groove to obtain a connecting groove consisting of the first groove and the sigma groove comprises: Depositing a silicon nitride layer covering the first trench and the gate structure including the second spacer; Etching the silicon nitride layer to form third spacers on both sides of the gate structure, and forming a second trench in the substrate between the gate structures including the third spacers; etching the second groove to form a sigma groove; The third spacer is removed, and a connecting trench consisting of the first trench and the sigma trench is formed between the gate structures.

4. The method according to claim 3, characterized in that The step of performing epitaxial growth of silicon germanium in the connecting trench to form a silicon germanium epitaxial layer comprises: Moving the substrate structure with the connected grooves formed thereon into an epitaxial chamber under vacuum conditions; A first designated gas is introduced into the epitaxial chamber to form a first epitaxial layer on the sidewall and the bottom of the connecting groove; the first designated gas includes: H2, HCl, SiH2Cl2, GeH4, B2H6; The current reaction temperature and the concentration and flow rate of the GeH4 and B2H6 gases are increased to form a second epitaxial layer filling the connecting grooves on the basis of the first epitaxial layer; the germanium-boron content of the second epitaxial layer is greater than the germanium-boron content in the first epitaxial layer.

5. The method according to claim 4, characterized in that The first epitaxial layer includes a first sub-epitaxial layer formed on the sidewall of the first trench, and a second sub-epitaxial layer formed on the sidewall and the bottom of the sigma trench.

6. The method according to claim 5, characterized in that The upper surface of the second epitaxial layer is flush with the upper surface of the first sub-epitaxial layer; after the step of forming the second epitaxial layer filling the connecting trench on the basis of the first epitaxial layer, the method further includes: SiH2Cl2 and B2H6 gases continue to be introduced into the epitaxial chamber to form a third epitaxial layer covering the first sub-epitaxial layer and the second epitaxial layer.

7. The method according to claim 5, characterized in that The upper surface of the second epitaxial layer is higher than the upper surface of the first sub-epitaxial layer and covers the first epitaxial layer; after the step of forming the second epitaxial layer filling the connecting groove on the basis of the first epitaxial layer, the method further includes: SiH2Cl2 and B2H6 gases continue to be introduced into the epitaxial chamber to form a third epitaxial layer covering the second epitaxial layer.

8. The method according to claim 5, characterized in that The side-view thickness of the first sub-epitaxial layer is greater than or equal to the side-view thickness at a position where the third side wall and the substrate meet.

9. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; A plurality of gate structures are disposed on the substrate; A connecting trench formed by connecting a first trench and a sigma trench up and down is opened in the substrate between the gate structures; wherein the top width of the sigma trench is smaller than the bottom width of the first trench; A germanium silicon epitaxial layer is arranged in the connecting groove; wherein, the first epitaxial layer is arranged on the sidewall and bottom of the connecting groove; the second epitaxial layer is arranged in the middle area of ​​the connecting groove and fills the entire connecting groove with the first epitaxial layer; the boron concentration in the second epitaxial layer is higher than the boron concentration in the first epitaxial layer.

10. The semiconductor structure according to claim 9, characterized in that: The first epitaxial layer includes a first sub-epitaxial layer formed on the sidewall of the first trench, and a second sub-epitaxial layer formed on the sidewall and bottom of the sigma trench; the silicon-germanium epitaxial layer also includes: a third epitaxial layer; the upper surface of the second epitaxial layer is higher than the upper surface of the first sub-epitaxial layer and covers the first sub-epitaxial layer, and the third epitaxial layer covers the second epitaxial layer; or, the upper surface of the second epitaxial layer is flush with the upper surface of the first sub-epitaxial layer, and the third epitaxial layer covers the first sub-epitaxial layer and the second epitaxial layer.

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