Integrated circuit device and method of forming same

Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit device may include: an upper transistor including an upper channel region on a substrate; a lower transistor between the substrate and the upper transistor, the lower transistor including a lower channel region; and a power line extending longitudinally in the first horizontal direction. At least one of the upper channel region and the lower channel region may extend longitudinally in a second horizontal direction traversing the first horizontal direction, and the at least one of the upper channel region and the lower channel region may overlap the power line in the thickness direction.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 513,361, filed in the USPTO on July 13, 2023, entitled “STACKED FIELD-EFFECT TRANSISTORS IN MULTI-HEIGHT CELLS AND METHODS OF FORMING THE SAME,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices including stacked field effect transistors in multi-height cells and methods of forming the same. Background Art

[0003] As the demand for high performance and / or high speed of integrated circuit devices increases, the integration level in integrated circuit devices also increases. Therefore, various structures of integrated circuit devices and methods of forming the same have been proposed to increase the integration density of integrated circuit devices. In particular, stacked integrated circuit devices including multi-height standard cells have been studied due to their high integration density. Summary of the invention

[0004] An integrated circuit device according to some embodiments may include: an upper transistor including an upper channel region on a substrate; a lower transistor between the substrate and the upper transistor, the lower transistor including a lower channel region; and a power supply line extending longitudinally in a first horizontal direction. At least one of the upper channel region or the lower channel region may extend longitudinally in a second horizontal direction that crosses the first horizontal direction, and the at least one of the upper channel region or the lower channel region may overlap with the power supply line in a thickness direction.

[0005] According to some embodiments, an integrated circuit device may include: a first transistor including a first channel region on a substrate; and a pair of second transistors each including a pair of second channel regions spaced apart from each other in a first horizontal direction. The first channel region may overlap the pair of second channel regions in a thickness direction.

[0006] A method of forming an integrated circuit device according to some embodiments may include: forming a lower transistor and an upper transistor on a substrate, the lower transistor including a lower channel region and the upper transistor including an upper channel region; and forming a power line extending longitudinally in a first horizontal direction. At least one of the upper channel region or the lower channel region may extend longitudinally in a second horizontal direction that crosses the first horizontal direction, and the at least one of the upper channel region or the lower channel region may overlap with the power line in a thickness direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic layout diagram of an integrated circuit device including a plurality of standard cells according to some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG.

[0009] Figure 3A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG.

[0010] Figure 3B and Figure 3C According to some embodiments, Figure 3A 4 is a cross-sectional view of the first standard cell SC1 taken along lines Y1 - Y1 ′ and Y2 - Y2 ′.

[0011] Figure 4A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG.

[0012] Figure 4B and Figure 4C According to some embodiments, Figure 4A 4 is a cross-sectional view of the first standard cell SC1 taken along lines Y1 - Y1 ′ and Y2 - Y2 ′.

[0013] Figure 5A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG.

[0014] Figure 5B and Figure 5C According to some embodiments, Figure 5A 4 is a cross-sectional view of the first standard cell SC1 taken along lines Y1 - Y1 ′ and Y2 - Y2 ′.

[0015] Fig. 6A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG.

[0016] Figure 6B According to some embodiments, Fig. 6A 4 is a cross-sectional view of the first standard cell SC1 taken along line Y2 - Y2 ′ in FIG.

[0017] Figure 7 According to some embodiments, Figure 1 0 is a circuit diagram of an example logic circuit in the first standard cell SC1 in FIG.

[0018] Figure 8 is a flow chart of a method of forming an integrated circuit device according to some embodiments.

[0019] Figures 9 to 12 is a cross-sectional view illustrating a method of forming an integrated circuit device according to some embodiments. DETAILED DESCRIPTION

[0020] An integrated circuit device may include a plurality of standard cells. A stacked field effect transistor (FET) may be included in the standard cell to form a logic circuit therein. The stacked FET may reduce the area of ​​the standard cell by about half compared to the area of ​​the standard cell including the non-stacked FET, thereby promoting a higher level of integration in the integrated circuit device. In order to improve the performance of the integrated circuit device, one or more of the standard cells may be a multi-height (y-axis) standard cell. However, the channel region in the multi-height standard cell may be spaced apart from the power line defining the cell boundary in the multi-height standard cell. Therefore, the channel region in the multi-height standard cell may not overlap with the power line, which may limit the effective channel width, increase the contact complexity, and hinder the performance of the integrated circuit device. According to some embodiments of the present disclosure, the integrated circuit device may include a stacked FET in a multi-height standard cell, the stacked FET having a merged lower channel region and / or upper channel region so that it overlaps with the power line, thereby increasing the effective channel width, reducing the contact complexity in the multi-height standard cell, and improving the performance of the integrated circuit device.

[0021] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0022] Figure 1 is a schematic layout diagram of an integrated circuit device including a plurality of standard cells according to some embodiments. Figure 1 Only power lines (eg, a first power line P1 and a second power line P2 ) are shown. Figure 1 The dotted lines in represent cell boundaries CB, and the black solid lines depict standard cells (eg, first to fourth standard cells SC1, SC2, SC3, and SC4). Figure 1 , the integrated circuit device 100 may include first to fourth standard cells SC1 , SC2 , SC3 , and SC4 . Figure 1 The number of standard cells in is only an example, and the integrated circuit device 100 may include more or less than four standard cells. The integrated circuit device 100 may also include a plurality of first power lines P1 and a plurality of second power lines P2. The first power line P1 may be electrically connected to a first voltage (e.g., a drain voltage V DD ) of the first power source. The second power line P2 may be electrically connected to a first power source having a second voltage (eg, a source voltage V SS). For example, the second voltage may be an electrical ground voltage. A first power line P1 and a second power line P2 may be provided to supply power to the first to fourth standard cells SC1, SC2, SC3, and SC4. The first power line P1 and the second power line P2 may supply different potentials to the first to fourth standard cells SC1, SC2, SC3, and SC4.

[0023] Each of the first to fourth standard cells SC1, SC2, SC3, and SC4 may constitute a small circuit or circuit component for establishing a logic or memory function (e.g., an inverter, a 2-input NAND gate, a 3-input NAND gate, a 2-input NOR gate, a 3-input NOR gate, an AND-OR inverter (AOI), an OR-AND inverter (OAI), an XNOR gate, an XOR gate, a multiplexer (MUX), a latch, a D flip-flop, etc.).

[0024] The first power line P1 and the second power line P2 may extend longitudinally in a first direction X (also referred to as a first horizontal direction). As used herein, "element A extends longitudinally in the first direction X" (or similar language) means that the longest dimension of element A extends in the first direction X. The first power line P1 and the second power line P2 may be arranged alternately in a second direction Y (also referred to as a second horizontal direction, or a unit "height"). The first power line P1 and the second power line P2 may be spaced apart from each other in the second direction Y. The first direction X may traverse the second direction Y. In some embodiments, the first direction X may be perpendicular to the second direction Y.

[0025] The cell boundaries CB in the integrated circuit device 100 may be defined by the first power line P1 and the second power line P2 (and therefore, their lengths in the first direction X). For example, each cell boundary CB may correspond to a central portion of one of the first power line P1 and the second power line P2 in the second direction Y. Each cell boundary CB may be an imaginary line extending in the first direction X and intersecting with a central portion of one of the first power line P1 and the second power line P2 in the second direction Y. Each cell boundary CB may also be an imaginary plane defined by the first direction X and a third direction Z (also referred to as a thickness direction). The third direction Z may be perpendicular to the first direction X and the second direction Y. Although the cell boundary CB defined by the second power line P2 is shown in the first standard cell SC1 and the second standard cell SC2, the cell boundary CB is not a cell boundary of the first standard cell SC1 and the second standard cell SC2. Instead, the cell boundary CB is a cell boundary of an adjacent standard cell (e.g., a single height cell).

[0026] The cell boundary CB may define the cell height of each of the first to fourth standard cells SC1, SC2, SC3, and SC4. As used herein, "cell height" refers to the height of the standard cell in the second direction Y in a plan view (i.e., a layout view). For example, a single-height standard cell SHC may be defined by a pair of cell boundaries CB with no power line therebetween (i.e., the cell extends from power line P1 to an immediately adjacent power line P2). A double-height standard cell DHC may be defined by a pair of cell boundaries CB with a power line therebetween. For example, such a cell would extend from power line P1 (or P2) and extend to the next power line of the same type of P1 (or P2), and include power lines of the opposite type. A triple-height standard cell THC may be defined by a pair of cell boundaries CB with two power lines therebetween. For example, such a cell would extend from power line P1 to the second most adjacent power line P2, and therefore also include closer power lines P1 and P2. Although in Figure 1 , but a quadruple (and more) height standard cell may be defined by a pair of cell boundaries CB with three (or more) power lines therebetween. Double, triple, quadruple, etc. height standard cells may also be referred to as multi-height standard cells.

[0027] The height of each standard cell (e.g., a single, double, triple, or quadruple height standard cell) in the second direction Y may be at a fixed interval defined by the cell boundary CB and / or the distance between the power lines P1 and P2. The height of a double height standard cell (DHC) in the second direction Y may be twice the height of a single height standard cell (SHC) in the second direction Y. Similarly, the height of a triple height standard cell (THC) in the second direction Y may be three times the height of a single height standard cell (SHC) in the second direction Y, and the height of a quadruple height standard cell in the second direction Y may be four times the height of a single height standard cell (SHC) in the second direction Y.

[0028] Some standard cells in the integrated circuit device 100 may be single-height standard cells SHC, and each single-height standard cell SHC may include a single first power line P1 and a single second power line P2 extending on a cell boundary CB thereof, respectively. Figure 1 The third standard cell SC3 and the fourth standard cell SC4 in FIG. 1 are single-height standard cells SHC.

[0029] Some standard cells in the integrated circuit device 100 may be double-height standard cells DHC, and each double-height standard cell DHC may include a pair of first power lines P1 or a pair of second power lines P2 extending on a cell boundary CB thereof, respectively, and an opposite (e.g., opposite type) power line P2 or P1 between the pair of first power lines P1 or the pair of second power lines P2, respectively. For example, Figure 1 The first standard cell SC1 in is a double height standard cell DHC.

[0030] Some standard cells in the integrated circuit device 100 may be triple height standard cells THC, and each triple height standard cell THC may include a single first power line P1 and a single second power line P2 extending on its cell boundary CB, and a first power line P1 and a second power line P2 between the single first power line P1 and the single second power line P2. For example, Figure 1 The second standard cell SC2 in is a triple-height standard cell THC.

[0031] Despite Figure 1 Although not shown, some standard cells in the integrated circuit device 100 may be quadruple-height standard cells, and each quadruple-height standard cell may include a pair of first power lines P1 or a pair of second power lines P2 extending on a cell boundary CB thereof, respectively.

[0032] The first to fourth standard cells SC1, SC2, SC3, and SC4 may be arranged in the first direction X and the second direction Y. The cell height of the second standard cell SC2 may be substantially equal to the combined cell height of the first standard cell SC1 and the third standard cell SC3. In some embodiments, the standard cells may have different widths in the first direction X. For example, the fourth standard cell SC4 may have a width different from that of the first to third standard cells SC1, SC2, and SC3 in the first direction X. The width of each standard cell in the first direction X may not necessarily be at a fixed interval. In some embodiments, the height of each of the first to fourth standard cells SC1, SC2, SC3, and SC4 in the second direction Y and / or the width in the first direction X may be determined according to the design of the logic circuit in the first to fourth standard cells SC1, SC2, SC3, and SC4.

[0033] Among the first power lines P1 and the second power lines P2, the power lines located at the cell boundary CB between the standard cells in the second direction Y may be shared power lines. For example, the first power line P1 located at the cell boundary CB between the first standard cell SC1 and the third standard cell SC3 may be a shared power line. Similarly, the second power line P2 located at the cell boundary CB between the third standard cell SC3 and the fourth standard cell SC4 may be a shared power line.

[0034] Figure 2 According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG.

[0035] Reference Figure 2, the first standard cell SC1 may include a first lower channel region 101 and a second lower channel region 103 (also referred to as a pair of lower channel regions) and a first upper channel region 105 and a second upper channel region 107 (also referred to as a pair of upper channel regions). The first upper channel region 105 and the second upper channel region 107 may be on the first lower channel region 101 and the second lower channel region 103, respectively. The first lower channel region 101 may be electrically connected to the first pair of lower source / drain regions 109 (e.g., the first lower source / drain region 109a and the second lower source / drain region 109b) on opposite sides thereof in the first direction X, respectively. Similarly, the second lower channel region 103 may be electrically connected to the second pair of lower source / drain regions 111 (e.g., the third lower source / drain region 111a and the fourth lower source / drain region 111b) on opposite sides thereof in the first direction X, respectively. The first upper channel region 105 may be electrically connected to the first pair of upper source / drain regions 113 (e.g., the first upper source / drain region 113a and the second upper source / drain region 113b) on opposite sides thereof in the first direction X, respectively. Similarly, the second upper channel region 107 may be electrically connected to the second pair of upper source / drain regions 115 (e.g., the third upper source / drain region 115a and the fourth upper source / drain region 115b) on opposite sides thereof in the first direction X, respectively.

[0036] The first lower channel region 101 and the second lower channel region 103, the first upper channel region 105 and the second upper channel region 107, the first pair of lower source / drain regions 109 and the second pair of lower source / drain regions 111, and the first pair of upper source / drain regions 113 and the second pair of upper source / drain regions 115 may be included in one or more stacked FETs. Each of the first lower channel region 101 and the second lower channel region 103 and the first upper channel region 105 and the second upper channel region 107 may be spaced apart from the second power line P2 in the second direction Y, and the second power line P2 is between a pair of first power lines P1 (and a cell boundary CB thereof) defining the cell height of the first standard cell SC1 (e.g., a double height cell). Therefore, the first lower channel region 101 and the second lower channel region 103 and the first upper channel region 105 and the second upper channel region 107 may not overlap with the second power line P2 in the third direction Z, which may limit the effective channel width and hinder the performance of the integrated circuit device 100.

[0037] For example, the first lower channel region 101 and the second lower channel region 103 may be separated (e.g., may not be merged or formed as a single unit) so that the first lower channel region 101 and the second lower channel region 103 are respectively spaced apart from the second power line P2 on opposite sides thereof in the second direction Y. Similarly, the first upper channel region 105 and the second upper channel region 107 may be separated (e.g., may not be merged or formed as a single unit) so that the first upper channel region 105 and the second upper channel region 107 are respectively spaced apart from the second power line P2 on opposite sides thereof in the second direction Y. Each of the first pair of lower source / drain regions 109 and the second pair of lower source / drain regions 111 and the first pair of upper source / drain regions 113 and the second pair of upper source / drain regions 115 may also not overlap with the second power line P2 in the third direction Z. In other words, each of the first lower channel region 101 and the second lower channel region 103, the first upper channel region 105 and the second upper channel region 107, the first pair of lower source / drain regions 109 and the second pair of lower source / drain regions 111, and the first pair of upper source / drain regions 113 and the second pair of upper source / drain regions 115 may not overlap with the second power line P2 in the third direction Z.

[0038] Figure 3A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG. Figure 3B and Figure 3C According to some embodiments, Figure 3A 1 is a cross-sectional view of the first standard cell SC1 taken along the lines Y1-Y1' and Y2-Y2'. Figure 3A Only some elements included in the first standard cell SC1 are shown.

[0039] Reference Figure 3A , Figure 3B and Figure 3C , the first standard cell SC1 may include a substrate 214 . A lower surface 214L of the substrate 214 may extend in a first direction X and a second direction Y. The first direction X and the second direction Y may be parallel to the lower surface 214L of the substrate 214 .

[0040] The substrate 214 may include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP) and / or may include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or a low-k material). In some embodiments, the substrate 214 may be a bulk substrate (e.g., a silicon wafer), a semiconductor on insulator (SOI) substrate, or an insulating layer (e.g., a monolithic insulating layer). The thickness of the substrate 214 in the third direction Z may be in the range of 50 nanometers (nm) to 100 nm. For example, the low-k material may include fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics.

[0041] The substrate 214 may include portions separated from each other by a trench isolation layer 216. The trench isolation layer 216 may include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boronitride, and / or a low-k material). The lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 (also referred to as a pair of upper channel regions) may be on a portion of the substrate 214 between the trench isolation layers 216.

[0042] In some embodiments, each of the lower channel region 202 and the first and second upper channel regions 204 and 206 may include a plurality of channel regions stacked in the third direction Z, and the channel regions may be spaced apart from each other in the third direction Z. Figure 3C It is shown that each of the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 includes two channel regions stacked in the third direction Z, but the present disclosure is not limited thereto. In some embodiments, each of the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 may include more or less than two channel regions stacked in the third direction Z.

[0043] The first standard cell SC1 may include a gate electrode 224. Although not shown, the first standard cell SC1 may also include a gate insulator. The gate insulator may be disposed between the gate electrode 224 and each of the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 to provide insulation between the gate electrode 224 and each of the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206. The gate electrode 224 and the gate insulator together may constitute a gate structure. Although Figure 3CThe gate electrode 224 is shown to be a common gate layer, but in some embodiments, the lower portion of the gate electrode 224 may be separated and spaced apart from the upper portion of the gate electrode 224 (e.g., by an insulating layer). The lower channel region 202 and the first and second upper channel regions 204 and 206 may extend through the gate electrode 224 in the first direction X, and a gate insulator may be disposed between the gate electrode 224 and each of the lower channel region 202 and the first and second upper channel regions 204 and 206 to provide insulation between the gate electrode 224 and the lower channel region 202 and each of the first and second upper channel regions 204 and 206. The gate insulator may contact the lower channel region 202 and each of the first and second upper channel regions 204 and 206 and / or the gate electrode 224. The gate insulator may separate the gate electrode 224 from the lower channel region 202 and the first and second upper channel regions 204 and 206. Although in Figure 3A Although not shown, the gate electrode 224 may extend longitudinally in the second direction Y to intersect the lower channel region 202 and the first and second upper channel regions 204 and 206 .

[0044] The first standard cell SC1 may further include a pair of lower source / drain regions 208 (e.g., a first lower source / drain region 208a and a second lower source / drain region 208b), a first pair of upper source / drain regions 210 (e.g., a first upper source / drain region 210a and a second upper source / drain region 210b), and a second pair of upper source / drain regions 212 (e.g., a third upper source / drain region 212a and a fourth upper source / drain region 212b). Although in Figure 3A Although not shown in the figure, the gate electrode 224 may be disposed between a pair of lower source / drain regions 208 in the first direction X, between a first pair of upper source / drain regions 210 in the first direction X, and between a second pair of upper source / drain regions 212 in the first direction X. Figure 3A , a pair of lower source / drain regions 208 may respectively contact the back-opposite side surfaces of the lower channel region 202 in the first direction X. Similarly, a first pair of upper source / drain regions 210 may respectively contact the back-opposite side surfaces of the first upper channel region 204 in the first direction X, and a second pair of upper source / drain regions 212 may respectively contact the back-opposite side surfaces of the second upper channel region 206 in the first direction X.

[0045] Each of the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 may include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, each of the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 may be a nanosheet that may have a thickness in the range of 1 nm to 100 nm in the third direction Z, or may be a nanowire that may have a circular cross-section with a diameter in the range of 1 nm to 100 nm.

[0046] Although not shown, in some embodiments, the lower channel region 202 and one or more of the first upper channel region 204 and the second upper channel region 206 may be shaped as a fin. When the lower channel region 202, the first upper channel region 204, and / or the second upper channel region 206 are nanosheets or nanowires, the gate electrode 224 may surround the lower channel region 202, the first upper channel region 204, and / or the second upper channel region 206 on four sides of the lower channel region 202, the first upper channel region 204, and / or the second upper channel region 206. When the lower channel region 202, the first upper channel region 204, and / or the second upper channel region 206 have a fin shape, the gate electrode 224 may surround the lower channel region 202, the first upper channel region 204, and / or the second upper channel region 206 on two, three, or four sides of the lower channel region 202, the first upper channel region 204, and / or the second upper channel region 206.

[0047] Each of the pair of lower source / drain regions 208, the first pair of upper source / drain regions 210, and the second pair of upper source / drain regions 212 may include a semiconductor layer (e.g., a silicon (Si) layer and / or a silicon germanium (SiGe) layer), and may additionally include a dopant in the semiconductor layer. In some embodiments, each of the pair of lower source / drain regions 208, the first pair of upper source / drain regions 210, and the second pair of upper source / drain regions 212 may include a metal layer including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru).

[0048] The gate insulator may include a single layer or multiple layers (eg, an interface layer and / or a high-k material layer). For example, the interface layer may include a silicon oxide layer, and the high-k material layer may include Al 2 O 3 , HfO 2 、ZrO 2 、HfZrO 4 、TiO 2 Sc 2 O 3 , Y 2 O 3 ,La2 O 3 、Lu 2 O 3 , Nb 2 O 5 and / or 2 O 5 .

[0049] The gate electrode 224 may include a single layer or multiple layers. In some embodiments, the gate electrode 224 may include a metal layer including, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0050] In some embodiments, a work function (also known as work function) layer 226 may be disposed between the gate electrode 224 and the gate insulator. In some embodiments, the work function layer 226 may separate the gate electrode 224 from the gate insulator. The work function layer 226 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer.

[0051] The lower transistor may include a lower channel region 202, a pair of lower source / drain regions 208, and "a portion of the gate electrode 224". The first upper transistor may include a first upper channel region 204, a first pair of upper source / drain regions 210, and "a portion of the gate electrode 224". The second upper transistor may include a second upper channel region 206, a second pair of upper source / drain regions 212, and "a portion of the gate electrode 224".

[0052] In some embodiments, according to the specifications of the first standard cell SC1, the lower transistor may be a P-type metal oxide semiconductor FET (PMOSFET), and the first and second upper transistors may be N-type MOSFETs (NMOSFET), or vice versa. The lower transistor and the first and second upper transistors may together constitute a stacked FET.

[0053] like Figure 3C As shown in , in some embodiments, the gate electrode 224 may be a common gate layer. A first portion of the gate electrode 224 may be a first gate electrode of a first upper transistor including a first upper channel region 204, a second portion of the gate electrode 224 may be a second gate electrode of a second upper transistor including a second upper channel region 206, and a third portion of the gate electrode 224 may be a third gate electrode of a lower transistor including a lower channel region 202. Since the gate electrode 224 is shared by the lower transistor and the first and second upper transistors, the input of the first standard cell SC1 may be commonly applied through the gate electrode 224. Although Figure 3CThe gate electrode 224 is shown to be shared by the lower transistor and the first and second upper transistors, but the present disclosure is not limited thereto. In some embodiments, the lower portion of the gate electrode 224 may be separated and spaced apart from the upper portion of the gate electrode 224. For example, an insulating layer may be between the lower portion and the upper portion of the gate electrode 224, and the lower portion of the gate electrode 224 may be separated from the upper portion of the gate electrode 224. In this case, the lower portion of the gate electrode 224 may be the first gate electrode of the lower transistor, and the upper portion of the gate electrode 224 may be the second gate electrode of the first and second upper transistors.

[0054] In some embodiments, each of the lower transistor and the first upper transistor and the second upper transistor may be a three-dimensional (3D) FET (such as a multi-bridge channel FET (MBCFET)). In some embodiments, one or more of the lower transistor and the first upper transistor and the second upper transistor may have a structure different from that shown. For example, one or more of the lower transistor and the first upper transistor and the second upper transistor may be a gate all around FET (GAAFET) or a fin FET (FinFET) including a single channel region.

[0055] An interlayer insulating layer 218 may be disposed on the substrate 214, and the lower transistor and the first and second upper transistors may be disposed in the interlayer insulating layer 218. Specifically, the lower channel region 202, the first and second upper channel regions 204 and 206, a pair of lower source / drain regions 208, a first pair of upper source / drain regions 210, a second pair of upper source / drain regions 212, and a gate electrode 224 may be disposed in the interlayer insulating layer 218.

[0056] Although the interlayer insulating layer 218 is shown as a single layer, in some embodiments, the interlayer insulating layer 218 may include multiple layers. The lower surface of the interlayer insulating layer 218 may contact the upper surface of the trench isolation layer 216. The interlayer insulating layer 218 may extend between the first upper channel region 204 and the second upper channel region 206. The interlayer insulating layer 218 may separate the first upper channel region 204 from the second upper channel region 206 in the second direction Y. For example, the interlayer insulating layer 218 may include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boronitride and / or low-k material). As used herein, the "lower surface" of an element may refer to a surface facing the substrate 214, and the "upper surface" of an element refers to a surface opposite to its lower surface. In addition, as used herein, the "lower portion" of an element refers to a portion closer to the substrate 214 than its "upper portion" and therefore between its upper portion and the substrate 214.

[0057] The first standard cell SC1 may include a BEOL structure 220 formed by a back-end process (BEOL) portion of device manufacturing. The BEOL structure 220 may include a BEOL insulating layer, conductive lines (e.g., metal lines) disposed in the BEOL insulating layer and stacked in a third direction Z, and conductive via plugs (e.g., metal via plugs), each of which may electrically connect two conductive lines spaced apart from each other in the third direction Z. The BEOL insulating layer may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boronitride, and / or a low-k material.

[0058] The first standard cell SC1 may further include a backside power delivery network structure (BSPDNS) 222. The BSPDNS 222 may contact the lower surface 214L of the substrate 214. The BSPDNS 222 may include a backside insulator, and the first power line P1 and the second power line P2 may be disposed in the backside insulator. The BSPDNS 222 may include a power delivery network including the first power line P1 and the second power line P2. The first power line P1 and the second power line P2 may each be electrically connected to a drain voltage having a predetermined voltage (e.g., a drain voltage V DD or source voltage V SS ), the predetermined voltage is used to power the pair of lower source / drain regions 208, the first pair of upper source / drain regions 210, and / or the second pair of upper source / drain regions 212. For example, the first power line P1 and the second power line P2 may be electrically connected to the pair of lower source / drain regions 208, the first pair of upper source / drain regions 210, and / or the second pair of upper source / drain regions 212 through conductive vias and / or contact structures.

[0059] The BSPDNS 222 may include one or more conductive layers (e.g., metal layers) stacked in the third direction Z that provide power delivery. The conductive layers may be included in the insulating layers, respectively, and conductive via plugs (e.g., metal via plugs) may electrically connect the conductive layers to each other in the third direction Z. For example, the backside insulator of the BSPDNS 222 may include a plurality of layers stacked on the lower surface 214L of the substrate 214. The conductive layer may include one or more conductive lines (e.g., metal lines). In some embodiments, an intermediate structure may be disposed between the substrate 214 and the BSPDNS 222, and the substrate 214 may be separated from the BSPDNS 222. The BSPDNS 222 may increase the power delivery efficiency in the first standard cell SC1, reduce the area for power delivery in the first standard cell SC1, and / or improve the voltage drop (i.e., IR drop) in the first standard cell SC1.

[0060] The lower channel region 202 may be formed such that it extends longitudinally in the second direction Y and overlaps with the second power line P2 in the third direction Z. In other words, the second power line P2 and the cell boundary CB defined by the second power line P2 may overlap with the lower channel region 202 in the third direction Z. For example, the lower channel region 202 may include a central portion (e.g., a third portion 202_3) in the second direction Y that overlaps with the second power line P2 along the third direction Z. As used herein, "element A overlaps element B in the third direction Z" (or similar language) means that there is at least one line that extends in the third direction Z and intersects both elements A and B.

[0061] The lower channel region 202 may be electrically connected to a pair of lower source / drain regions 208 on opposite sides thereof in the first direction X, respectively. The pair of lower source / drain regions 208 may extend longitudinally in the second direction Y and overlap the second power line P2 in the third direction Z. For example, each of the pair of lower source / drain regions 208 may include a central portion in the second direction Y overlapping the second power line P2 along the third direction Z.

[0062] The first upper channel region 204 and the second upper channel region 206 may be on the lower channel region 202. The lower channel region 202 may be between the substrate 214 and the first upper channel region 204 and the second upper channel region 206. The first upper channel region 204 and the second upper channel region 206 may not be merged or formed as a single unit, and may not overlap the second power line P2 in the third direction Z. That is, the first upper channel region 204 and the second upper channel region 206 may not overlap the second power line P2 and the cell boundary CB defined by the second power line P2 in the third direction Z.

[0063] The first upper channel regions 204 may be electrically connected to the first pair of upper source / drain regions 210 on opposite sides thereof in the first direction X, respectively. The second upper channel regions 206 may be electrically connected to the second pair of upper source / drain regions 212 on opposite sides thereof in the first direction X, respectively. The first pair of upper source / drain regions 210 and the second pair of upper source / drain regions 212 may not overlap the second power line P2 and the cell boundary CB defined by the second power line P2 in the third direction Z.

[0064] The width of the lower channel region 202 in the second direction Y may be greater than the width of the first upper channel region 204 in the second direction Y. Similarly, the width of the lower channel region 202 in the second direction Y may be greater than the width of the second upper channel region 206 in the second direction Y. For example, the width of the lower channel region 202 in the second direction Y may be at least 1.5 times (i.e., at least 1.5 times) the width of each of the first upper channel region 204 and the second upper channel region 206 in the second direction Y. In some embodiments, the width of the lower channel region 202 in the second direction Y may be at least 2 times (i.e., at least 2 times) the width of each of the first upper channel region 204 and the second upper channel region 206 in the second direction Y. In some embodiments, the width of the lower channel region 202 in the second direction Y may be greater than the combined width of the first upper channel region 204 and the second upper channel region 206 in the second direction Y. In some embodiments, the combined width may be a linear combination of widths (eg, the sum of the width of the first upper channel region 204 in the second direction Y and the width of the second upper channel region 206 in the second direction Y), but is not limited thereto.

[0065] The corresponding width of the pair of lower source / drain regions 208 in the second direction Y may be greater than the corresponding width of the first pair of upper source / drain regions 210 in the second direction Y. Similarly, the corresponding width of the pair of lower source / drain regions 208 in the second direction Y may be greater than the corresponding width of the second pair of upper source / drain regions 212 in the second direction Y. For example, the corresponding width of the pair of lower source / drain regions 208 in the second direction Y may be at least 1.5 times (i.e., at least 1.5 times wider) than the corresponding width of the first pair of upper source / drain regions 210 in the second direction Y. Similarly, the corresponding width of the pair of lower source / drain regions 208 in the second direction Y may be at least 1.5 times (i.e., at least 1.5 times wider) than the corresponding width of the second pair of upper source / drain regions 212 in the second direction Y. In some embodiments, the corresponding width of the pair of lower source / drain regions 208 in the second direction Y may be at least 2 times (i.e., at least 2 times wider) than the corresponding width of the first pair of upper source / drain regions 210 in the second direction Y. Similarly, the respective widths of the pair of lower source / drain regions 208 in the second direction Y may be at least 2 times (ie, at least 2 times wider) than the respective widths of the second pair of upper source / drain regions 212 in the second direction Y.

[0066] In some embodiments, the width of the first lower source / drain region 208a in the second direction Y may be greater than the combined width of the first upper source / drain region 210a and the third upper source / drain region 212a in the second direction Y, and may also be greater than the combined width of the second upper source / drain region 210b and the fourth upper source / drain region 212b in the second direction Y. Similarly, the width of the second lower source / drain region 208b in the second direction Y may be greater than the combined width of the first upper source / drain region 210a and the third upper source / drain region 212a in the second direction Y, and may also be greater than the combined width of the second upper source / drain region 210b and the fourth upper source / drain region 212b in the second direction Y.

[0067] The lower channel region 202 may overlap the first upper channel region 204 and the second upper channel region 206 in the third direction Z. The first lower source / drain region 208a may overlap the first upper source / drain region 210a and the third upper source / drain region 212a in the third direction Z. The second lower source / drain region 208b may overlap the second upper source / drain region 210b and the fourth upper source / drain region 212b in the third direction Z.

[0068] The lower channel region 202 may include a first portion 202_1, a second portion 202_2, and a third portion 202_3 (see Figure 3C ). The first portion 202_1 and the second portion 202_2 of the lower channel region 202 may not overlap with the second power line P2 in the third direction Z. The third portion 202_3 of the lower channel region 202 may be between the first portion 202_1 and the second portion 202_2, and may overlap with the second power line P2 in the third direction Z. For example, the first portion 202_1 of the lower channel region 202 may be between the first upper channel region 204 and the substrate 214, and the second portion 202_2 of the lower channel region 202 may be between the second upper channel region 206 and the substrate 214. The third portion 202_3 of the lower channel region 202 may be a central portion of the lower channel region 202 in the second direction Y. The first portion 202_1 of the lower channel region 202 may overlap with the first upper channel region 204 in the third direction Z, and the second portion 202_2 of the lower channel region 202 may overlap with the second upper channel region 206 in the third direction Z. The third portion 202_3 of the lower channel region 202 may not overlap the first upper channel region 204 and the second upper channel region 206 in the third direction Z.

[0069] The second power line P2 may be spaced apart from the first power line P1 in the second direction Y. The first standard cell SC1 is a double height cell, and therefore the lower channel region 202 and the first upper channel region 204 and the second upper channel region 206 may not overlap with the first power line P1 in the third direction Z. The lower channel region 202 may include a central portion (e.g., a third portion 202_3) in the second direction Y, which is spaced apart from each first power line P1 by an equal distance in the second direction Y. The first upper channel region 204 may include a central portion in the second direction Y, which is spaced apart from one of the first power lines P1 and the second power line P2 by an equal distance in the second direction Y. The second upper channel region 206 may include a central portion in the second direction Y, which is spaced apart from another of the first power lines P1 and the second power line P2 by an equal distance in the second direction Y.

[0070] The lower transistor of the stacked FET may include a merged or single lower channel region 202 such that it extends longitudinally in the second direction Y and overlaps the second power line P2 in the third direction Z. Therefore, the effective channel width of the lower transistor in the second direction Y may be increased, thereby improving the performance of the integrated circuit device. In addition, due to the increase in the effective channel width of the lower transistor, the first standard cell SC1 may have improved timing synchronization.

[0071] Figure 4A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG. Figure 4B and Figure 4C According to some embodiments, Figure 4A 4 is a cross-sectional view of the first standard cell SC1 taken along lines Y1 - Y1 ′ and Y2 - Y2 ′. Figure 4A , Figure 4B and Figure 4C The first standard cell SC1 can be similar to the reference Figure 3A , Figure 3B and Figure 3C The first standard cell SC1 described herein is described, and therefore repeated description of similar elements will be omitted. Figure 4A Only some elements included in the first standard cell SC1 are shown.

[0072] Reference Figure 4A , Figure 4B and Figure 4C , the first standard cell SC1 may include a first lower channel region 330 and a second lower channel region 332 (also referred to as a pair of lower channel regions) and an upper channel region 328 on a portion of the substrate 214 between the trench isolation layers 216 .

[0073] In some embodiments, each of the first and second lower channel regions 330 and 332 and the upper channel region 328 may include a plurality of channel regions stacked in the third direction Z, and the channel regions may be spaced apart from each other in the third direction Z. Figure 4C It is shown that each of the first lower channel region 330 and the second lower channel region 332 and the upper channel region 328 includes two channel regions stacked in the third direction Z, but the present disclosure is not limited thereto. In some embodiments, each of the first lower channel region 330 and the second lower channel region 332 and the upper channel region 328 may include more or less than two channel regions stacked in the third direction Z.

[0074] The first and second lower channel regions 330, 332, and the upper channel region 328 may extend through the gate electrode 224 in the first direction X, and a gate insulator may be disposed between the gate electrode 224 and each of the first and second lower channel regions 330, 332, and the upper channel region 328 to provide insulation between the gate electrode 224 and each of the first and second lower channel regions 330, 332, and the upper channel region 328. The gate insulator may contact each of the first and second lower channel regions 330, 332, and the upper channel region 328 and / or the gate electrode 224. The gate insulator may separate the gate electrode 224 from the first and second lower channel regions 330, 332, and the upper channel region 328. Although not shown in FIG. Figure 4A , but the gate electrode 224 may extend longitudinally in the second direction Y to intersect the first and second lower channel regions 330 and 332 and the upper channel region 328 .

[0075] The first standard cell SC1 may include a first pair of lower source / drain regions 336 (e.g., a first lower source / drain region 336a and a second lower source / drain region 336b), a second pair of lower source / drain regions 338 (e.g., a third lower source / drain region 338a and a fourth lower source / drain region 338b), and a pair of upper source / drain regions 334 (e.g., a first upper source / drain region 334a and a second upper source / drain region 334b). Although Figure 4A Although not shown, the gate electrode 224 may be disposed between the first pair of lower source / drain regions 336 in the first direction X, between the second pair of lower source / drain regions 338 in the first direction X, and between the pair of upper source / drain regions 334 in the first direction X. Figure 4A, a pair of upper source / drain regions 334 may respectively contact the back-opposite side surfaces of the upper channel region 328 in the first direction X. Similarly, a first pair of lower source / drain regions 336 may respectively contact the back-opposite side surfaces of the first lower channel region 330 in the first direction X, and a second pair of lower source / drain regions 338 may respectively contact the back-opposite side surfaces of the second lower channel region 332 in the first direction X.

[0076] Each of the first lower channel region 330 and the second lower channel region 332 and the upper channel region 328 may include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, each of the first lower channel region 330 and the second lower channel region 332 and the upper channel region 328 may be a nanosheet that may have a thickness in the range of 1 nm to 100 nm in the third direction Z, or may be a nanowire that may have a circular cross-section with a diameter in the range of 1 nm to 100 nm.

[0077] Although not shown, in some embodiments, one or more of the first lower channel region 330, the second lower channel region 332, and the upper channel region 328 may be shaped as a fin. When the first lower channel region 330, the second lower channel region 332, and / or the upper channel region 328 are nanosheets or nanowires, the gate electrode 224 may surround the first lower channel region 330, the second lower channel region 332, and / or the upper channel region 328 on four sides thereof. When the first lower channel region 330, the second lower channel region 332, and / or the upper channel region 328 have a fin shape, the gate electrode 224 may surround the first lower channel region 330, the second lower channel region 332, and / or the upper channel region 328 on two, three, or four sides thereof.

[0078] Each of the first pair of lower source / drain regions 336, the second pair of lower source / drain regions 338, and the pair of upper source / drain regions 334 may include a semiconductor layer (e.g., a silicon (Si) layer and / or a silicon germanium (SiGe) layer), and may additionally include a dopant in the semiconductor layer. In some embodiments, each of the first pair of lower source / drain regions 336, the second pair of lower source / drain regions 338, and the pair of upper source / drain regions 334 may include a metal layer including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru).

[0079] The first lower transistor may include a first lower channel region 330, a first pair of lower source / drain regions 336, and "a portion of the gate electrode 224". The second lower transistor may include a second lower channel region 332, a second pair of lower source / drain regions 338, and "a portion of the gate electrode 224". The upper transistor may include an upper channel region 328, a pair of upper source / drain regions 334, and "a portion of the gate electrode 224".

[0080] In some embodiments, according to the specifications of the first standard cell SC1, the first and second lower transistors may be PMOSFETs and the upper transistor may be NMOSFETs, or vice versa. The first and second lower transistors and the upper transistor may together constitute a stacked FET.

[0081] In some embodiments, Figure 4C As shown in , the gate electrode 224 may be a common gate layer. A first portion of the gate electrode 224 may be a first gate electrode of an upper transistor including an upper channel region 328, a second portion of the gate electrode 224 may be a second gate electrode of a first lower transistor including a first lower channel region 330, and a third portion of the gate electrode 224 may be a third gate electrode of a second lower transistor including a second lower channel region 332. Since the gate electrode 224 is shared by the first and second lower transistors and the upper transistor, the input of the first standard cell SC1 may be commonly applied through the gate electrode 224. Although Figure 4C The gate electrode 224 is shown to be shared by the first lower transistor and the second lower transistor and the upper transistor, but the present disclosure is not limited thereto. In some embodiments, the lower portion of the gate electrode 224 may be separated and spaced apart from the upper portion of the gate electrode 224. For example, an insulating layer may be between the lower portion and the upper portion of the gate electrode 224, and the lower portion of the gate electrode 224 may be separated from the upper portion of the gate electrode 224. In this case, the lower portion of the gate electrode 224 may be the first gate electrode of the first lower transistor and the second lower transistor, and the upper portion of the gate electrode 224 may be the second gate electrode of the upper transistor.

[0082] In some embodiments, each of the first lower transistor and the second lower transistor and the upper transistor may be a 3D-FET (such as an MBCFET). In some embodiments, one or more of the first lower transistor and the second lower transistor and the upper transistor may have a structure different from that shown. For example, one or more of the first lower transistor and the second lower transistor and the upper transistor may be a GAAFET or a FinFET including a single channel region.

[0083] The first and second lower transistors and the upper transistor may be disposed in the interlayer insulating layer 218. Specifically, the first and second lower channel regions 330 and 332, the upper channel region 328, the first pair of lower source / drain regions 336, the second pair of lower source / drain regions 338, the pair of upper source / drain regions 334, and the gate electrode 224 may be disposed in the interlayer insulating layer 218.

[0084] The first power line P1 and the second power line P2 may each be electrically connected to a drain voltage having a predetermined voltage (eg, drain voltage V DD or source voltage V SS ), the predetermined voltage is used to power the first pair of lower source / drain regions 336, the second pair of lower source / drain regions 338, and / or the pair of upper source / drain regions 334. For example, the first power line P1 and the second power line P2 may be electrically connected to the first pair of lower source / drain regions 336, the second pair of lower source / drain regions 338, and / or the pair of upper source / drain regions 334 through conductive vias and / or contact structures.

[0085] The insulating layer 340 may extend between the first lower channel region 330 and the second lower channel region 332. The insulating layer 340 may separate the first lower channel region 330 from the second lower channel region 332 in the second direction Y. For example, the insulating layer 340 may include an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boronitride, and / or a low-k material). Although the insulating layer 340 is shown as a single layer, in some embodiments, the insulating layer 340 may include a plurality of layers.

[0086] The upper channel region 328 may be formed such that it extends longitudinally in the second direction Y and overlaps the second power line P2 in the third direction Z. In other words, the second power line P2 and the cell boundary CB defined by the second power line P2 may overlap the upper channel region 328 in the third direction Z. For example, the upper channel region 328 may include a central portion (e.g., a third portion 328_3) in the second direction Y that overlaps the second power line P2 along the third direction Z.

[0087] The upper channel regions 328 may be electrically connected to a pair of upper source / drain regions 334 on opposite sides thereof in the first direction X, respectively. The pair of upper source / drain regions 334 may extend longitudinally in the second direction Y, and may overlap the second power line P2 in the third direction Z. For example, each of the pair of upper source / drain regions 334 may include a central portion in the second direction Y overlapping the second power line P2 along the third direction Z.

[0088] The upper channel region 328 may be on the first lower channel region 330 and the second lower channel region 332. The first lower channel region 330 and the second lower channel region 332 may be between the substrate 214 and the upper channel region 328. The first lower channel region 330 and the second lower channel region 332 may not be merged or formed as a single unit, and may not overlap the second power line P2 in the third direction Z. That is, the first lower channel region 330 and the second lower channel region 332 may not overlap the second power line P2 and the cell boundary CB defined by the second power line P2 in the third direction Z.

[0089] The first lower channel regions 330 may be electrically connected to the first pair of lower source / drain regions 336 on opposite sides thereof in the first direction X, respectively. The second lower channel regions 332 may be electrically connected to the second pair of lower source / drain regions 338 on opposite sides thereof in the first direction X, respectively. The first pair of lower source / drain regions 336 and the second pair of lower source / drain regions 338 may not overlap the second power line P2 and the cell boundary CB defined by the second power line P2 in the third direction Z.

[0090] The width of the upper channel region 328 in the second direction Y may be greater than the width of the first lower channel region 330 in the second direction Y. Similarly, the width of the upper channel region 328 in the second direction Y may be greater than the width of the second lower channel region 332 in the second direction Y. For example, the width of the upper channel region 328 in the second direction Y may be at least 1.5 times (i.e., at least 1.5 times) the width of each of the first lower channel region 330 and the second lower channel region 332 in the second direction Y. In some embodiments, the width of the upper channel region 328 in the second direction Y may be at least 2 times (i.e., at least 2 times) the width of each of the first lower channel region 330 and the second lower channel region 332 in the second direction Y. In some embodiments, the width of the upper channel region 328 in the second direction Y may be greater than the combined width of the first lower channel region 330 and the second lower channel region 332 in the second direction Y.

[0091] The corresponding width of the pair of upper source / drain regions 334 in the second direction Y may be greater than the corresponding width of the first pair of lower source / drain regions 336 in the second direction Y. Similarly, the corresponding width of the pair of upper source / drain regions 334 in the second direction Y may be greater than the corresponding width of the second pair of lower source / drain regions 338 in the second direction Y. For example, the corresponding width of the pair of upper source / drain regions 334 in the second direction Y may be at least 1.5 times (i.e., at least 1.5 times wider) of the corresponding width of the first pair of lower source / drain regions 336 in the second direction Y. Similarly, the corresponding width of the pair of upper source / drain regions 334 in the second direction Y may be at least 1.5 times (i.e., at least 1.5 times wider) of the corresponding width of the second pair of lower source / drain regions 338 in the second direction Y. In some embodiments, the corresponding width of the pair of upper source / drain regions 334 in the second direction Y may be at least 2 times (i.e., at least 2 times wider) of the corresponding width of the first pair of lower source / drain regions 336 in the second direction Y. Similarly, the respective widths of the pair of upper source / drain regions 334 in the second direction Y may be at least 2 times (ie, at least 2 times wider) than the respective widths of the second pair of lower source / drain regions 338 in the second direction Y.

[0092] In some embodiments, the width of the first upper source / drain region 334a in the second direction Y may be greater than the combined width of the first lower source / drain region 336a and the third lower source / drain region 338a in the second direction Y, and may also be greater than the combined width of the second lower source / drain region 336b and the fourth lower source / drain region 338b in the second direction Y. Similarly, the width of the second upper source / drain region 334b ​​in the second direction Y may be greater than the combined width of the first lower source / drain region 336a and the third lower source / drain region 338a in the second direction Y, and may also be greater than the combined width of the second lower source / drain region 336b and the fourth lower source / drain region 338b in the second direction Y.

[0093] The upper channel region 328 may overlap the first lower channel region 330 and the second lower channel region 332 in the third direction Z. The first upper source / drain region 334a may overlap the first lower source / drain region 336a and the third lower source / drain region 338a in the third direction Z. The second upper source / drain region 334b ​​may overlap the second lower source / drain region 336b and the fourth lower source / drain region 338b in the third direction Z.

[0094] The upper channel region 328 may include a first portion 328_1, a second portion 328_2, and a third portion 328_3 (see Figure 4C). The first portion 328_1 and the second portion 328_2 of the upper channel region 328 may not overlap with the second power line P2 in the third direction Z. The third portion 328_3 of the upper channel region 328 may be between the first portion 328_1 and the second portion 328_2, and may overlap with the second power line P2 in the third direction Z. For example, the first portion 328_1 of the upper channel region 328 may be on the first lower channel region 330, and the second portion 328_2 of the upper channel region 328 may be on the second lower channel region 332. The third portion 328_3 of the upper channel region 328 may be a central portion of the upper channel region 328 in the second direction Y. The first portion 328_1 of the upper channel region 328 may overlap with the first lower channel region 330 in the third direction Z, and the second portion 328_2 of the upper channel region 328 may overlap with the second lower channel region 332 in the third direction Z. The third portion 328_3 of the upper channel region 328 may not overlap the first and second lower channel regions 330 and 332 in the third direction Z.

[0095] The first standard cell SC1 is a double height cell, and therefore the upper channel region 328 and the first and second lower channel regions 330 and 332 may not overlap with the first power line P1 in the third direction Z. The upper channel region 328 may include a central portion (e.g., a third portion 328_3) in the second direction Y that is spaced an equal distance from each first power line P1 in the second direction Y. The first lower channel region 330 may include a central portion in the second direction Y that is spaced an equal distance from one of the first power lines P1 and the second power line P2 in the second direction Y. The second lower channel region 332 may include a central portion in the second direction Y that is spaced an equal distance from the other of the first power lines P1 and the second power line P2 in the second direction Y.

[0096] The upper transistor of the stacked FET may include a merged or single upper channel region 328 such that it extends longitudinally in the second direction Y and overlaps the second power line P2 in the third direction Z. Therefore, the effective channel width of the upper transistor in the second direction Y may be increased, thereby improving the performance of the integrated circuit device. In addition, due to the increase in the effective channel width of the upper transistor, the first standard cell SC1 may have improved timing synchronization.

[0097] Figure 5A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG. Figure 5B and Figure 5C According to some embodiments, Figure 5A 4 is a cross-sectional view of the first standard cell SC1 taken along lines Y1 - Y1 ′ and Y2 - Y2 ′. Figure 5A , Figure 5B and Figure 5C The first standard cell SC1 can be similar to the reference Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B and Figure 4C The first standard cell SC1 described herein is described, and therefore repeated description of similar elements will be omitted. Figure 5A Only some elements included in the first standard cell SC1 are shown.

[0098] Reference Figure 5A , Figure 5B and Figure 5C , the first standard cell SC1 may include reference Figure 3A , Figure 3B and Figure 3C The first standard cell SC1 may further include a lower channel region 202 and a pair of lower source / drain regions 208 as described above. Figure 4A , Figure 4B and Figure 4C An upper channel region 328 and a pair of upper source / drain regions 334 are depicted.

[0099] The lower channel region 202 and the upper channel region 328 may be on a portion of the substrate 214 between the trench isolation layers 216. The lower transistor may include the lower channel region 202, a pair of lower source / drain regions 208, and "a portion of the gate electrode 224". The upper transistor may include the upper channel region 328, a pair of upper source / drain regions 334, and "a portion of the gate electrode 224".

[0100] In some embodiments, according to the specifications of the first standard cell SC1, the lower transistor may be a PMOSFET and the upper transistor may be an NMOSFET, or vice versa. The lower transistor and the upper transistor may together constitute a stacked FET. In some embodiments, each of the lower transistor and the upper transistor may be a 3D-FET (such as an MBCFET). In some embodiments, one or more of the lower transistor and the upper transistor may have a structure different from that shown. For example, one or more of the lower transistor and the upper transistor may be a GAAFET or a FinFET including a single channel region.

[0101] Both the lower channel region 202 and the upper channel region 328 may be formed such that they extend longitudinally in the second direction Y and overlap with the second power line P2 in the third direction Z. In other words, the second power line P2 and the cell boundary CB defined by the second power line P2 may overlap with both the lower channel region 202 and the upper channel region 328 in the third direction Z. For example, each of the lower channel region 202 and the upper channel region 328 may include a central portion (e.g., the third portion 202_3 and the third portion 328_3, respectively) in the second direction Y that overlaps with the second power line P2 along the third direction Z.

[0102] The lower channel region 202 may be electrically connected to a pair of lower source / drain regions 208 on opposite sides thereof in the first direction X, respectively. The pair of lower source / drain regions 208 may extend longitudinally in the second direction Y and overlap the second power line P2 in the third direction Z. For example, each of the pair of lower source / drain regions 208 may include a central portion in the second direction Y overlapping the second power line P2 along the third direction Z.

[0103] The upper channel regions 328 may be electrically connected to a pair of upper source / drain regions 334 on opposite sides thereof in the first direction X, respectively. The pair of upper source / drain regions 334 may extend longitudinally in the second direction Y, and may overlap the second power line P2 in the third direction Z. For example, each of the pair of upper source / drain regions 334 may include a central portion in the second direction Y overlapping the second power line P2 along the third direction Z.

[0104] The lower channel region 202 may be between the substrate 214 and the upper channel region 328. The lower channel region 202 and the upper channel region 328 may overlap each other in the third direction Z. Similarly, a pair of lower source / drain regions 208 and a pair of upper source / drain regions 334 may overlap each other in the third direction Z. That is, the first lower source / drain region 208a may overlap with the first upper source / drain region 334a in the third direction Z, and the second lower source / drain region 208b may overlap with the second upper source / drain region 334b ​​in the third direction Z.

[0105] The lower channel region 202 may include a first portion 202_1, a second portion 202_2, and a third portion 202_3 (see Figure 5C). The first portion 202_1 and the second portion 202_2 of the lower channel region 202 may not overlap with the second power line P2 in the third direction Z. The third portion 202_3 of the lower channel region 202 may be between the first portion 202_1 and the second portion 202_2 of the lower channel region 202, and may overlap with the second power line P2 in the third direction Z. The third portion 202_3 of the lower channel region 202 may be a central portion of the lower channel region 202 in the second direction Y. Each of the first portion 202_1, the second portion 202_2, and the third portion 202_3 of the lower channel region 202 may overlap with the upper channel region 328 in the third direction Z.

[0106] The upper channel region 328 may include a first portion 328_1, a second portion 328_2, and a third portion 328_3 (see Figure 5C ). The first portion 328_1 and the second portion 328_2 of the upper channel region 328 may not overlap the second power line P2 in the third direction Z. The third portion 328_3 of the upper channel region 328 may be between the first portion 328_1 and the second portion 328_2 of the upper channel region 328, and may overlap the second power line P2 in the third direction Z. The third portion 328_3 of the upper channel region 328 may be a central portion of the upper channel region 328 in the second direction Y. Each of the first portion 328_1, the second portion 328_2, and the third portion 328_3 of the upper channel region 328 may overlap the lower channel region 202 in the third direction Z.

[0107] The first standard cell SC1 is a double height cell, and thus the lower channel region 202 and the upper channel region 328 may not overlap the first power line P1 in the third direction Z. The lower channel region 202 may include a central portion (e.g., a third portion 202_3) in the second direction Y that is spaced an equal distance from each of the first power lines P1 in the second direction Y. Similarly, the upper channel region 328 may include a central portion (e.g., a third portion 328_3) in the second direction Y that is spaced an equal distance from each of the first power lines P1 in the second direction Y.

[0108] The lower transistor of the stacked FET may include a merged or single lower channel region 202 such that it extends longitudinally in the second direction Y and overlaps with the second power line P2 in the third direction Z. Similarly, the upper transistor of the stacked FET may include a merged or single upper channel region 328 such that it extends longitudinally in the second direction Y and overlaps with the second power line P2 in the third direction Z. Therefore, the effective channel width of the lower transistor and the upper transistor in the second direction Y may be increased, thereby improving the performance of the integrated circuit device. In addition, due to the increase in the effective channel width of the lower transistor and the upper transistor, the first standard cell SC1 may have improved timing synchronization.

[0109] Fig. 6A According to some embodiments Figure 1 FIG. 1 is an enlarged schematic layout diagram of the first standard cell SC1 in FIG. Figure 6B According to some embodiments, Fig. 6A 4 is a cross-sectional view of the first standard cell SC1 taken along line Y2 - Y2 ′ in FIG. Fig. 6A and Figure 6B The first standard cell SC1 can be similar to the reference Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B and Figure 5C The first standard cell SC1 described herein is described, and therefore repeated description of similar elements will be omitted. Fig. 6A Only some elements included in the first standard cell SC1 are shown.

[0110] Reference Fig. 6A and Figure 6B , the standard cell SC1 may include reference Figure 3A , Figure 3B and Figure 3C A lower channel region 202 , a first upper channel region 204 and a second upper channel region 206 , a pair of lower source / drain regions 208 , a first pair of upper source / drain regions 210 and a second pair of upper source / drain regions 212 are depicted.

[0111] The first standard cell SC1 may include a first power line P1 and a second power line P2. The first power line P1 and the second power line P2 may be included in a BEOL structure 220 formed by a BEOL portion manufactured by a device. The first power line P1 and the second power line P2 may be on an interlayer insulating layer 218. The first power line P1 and the second power line P2 may each be electrically connected to a drain voltage V DD or source voltage V SS), the predetermined voltage is used to power a pair of lower source / drain regions 208, a first pair of upper source / drain regions 210, and / or a second pair of upper source / drain regions 212. For example, the first power line P1 and the second power line P2 may be electrically connected to the pair of lower source / drain regions 208, the first pair of upper source / drain regions 210, and / or the second pair of upper source / drain regions 212 through conductive vias and / or contact structures.

[0112] Despite Fig. 6A and Figure 6B 2, but in some embodiments, one or more of the first power line P1 and the second power line P2 may be included in the BEOL structure 220, and one or more of the first power line P1 and the second power line P2 may be included in the BSPDN 222. That is, the first power line P1 and the second power line P2 may be included in the BEOL structure 220 and / or the BSPDN 222.

[0113] Although Fig. 6A and Figure 6B Similar to reference Figure 3A , Figure 3B and Figure 3C The first standard cell SC1 described above will be understood, however, that one or more of the first power line P1 and the second power line P2 may also be included in the reference numeral SC1. Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B and Figure 5C The BEOL structure 220 in the first standard cell SC1 is depicted.

[0114] Figure 7 According to some embodiments, Figure 1 0 is a circuit diagram of an example logic circuit in the first standard cell SC1 in FIG.

[0115] Reference Figure 7 , logic circuits can be designed as double-height cells and can be included in Figure 1 The logic circuit may include two P-type transistors 642 and 646 and a single N-type transistor 644. In some embodiments, the N-type transistor 644 may have a larger size than each of the two P-type transistors 642 and 646. For example, the N-type transistor 644 may include a channel region having a width greater than that of each of the two P-type transistors 642 and 646. For example, the logic circuit may correspond to the reference Figure 3A , Figure 3B and Figure 3C The first standard cell SC1 described or referred to Figure 4A , Figure 4B and Figure 4C A first standard cell SC1 is described.

[0116] The first power line P1 can transmit a first voltage (eg, drain voltage V DD ) is supplied to the P-type transistors 642 and 646 and the N-type transistor 644. The second power line P2 can supply the second voltage (eg, the source voltage V SS ) is supplied to P-type transistors 642 and 646 and N-type transistor 644.

[0117] Although Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B and Figure 7 The first standard cell SC1 is shown as a double-height standard cell, but it will be understood that the present disclosure is also applicable to other multiple-height standard cells (eg, a triple-height standard cell or a quadruple-height standard cell).

[0118] Figure 8 is a flow chart of a method of forming an integrated circuit device according to some embodiments. Figures 9 to 12 is a cross-sectional view illustrating a method of forming an integrated circuit device according to some embodiments. Specifically, Figures 9 to 11 is with Figure 3A The cross-sectional view corresponding to the line Y2-Y2', and Fig.12 is with Figure 3A The cross-sectional view corresponding to the line Y1-Y1'.

[0119] Reference Figure 8 and Fig. 9 , a lower channel region 202 may be formed on the substrate 214 (block 710). The lower channel region 202 may be alternately stacked with a portion of the sacrificial layer 850 in the third direction Z. A preliminary upper channel region 848 may be formed on the substrate 214 (block 720). The lower channel region 202 may be between the substrate 214 and the preliminary upper channel region 848. The preliminary upper channel region 848 may be alternately stacked with a portion of the sacrificial layer 850 in the third direction Z. Although the sacrificial layer 850 is shown as a single layer, in some embodiments, the sacrificial layer 850 may include a plurality of layers alternately stacked with the lower channel region 202 and the preliminary upper channel region 848. The lower channel region 202 and the preliminary upper channel region 848 may be on a portion of the substrate 214 between the trench isolation layers 216.

[0120] The sacrificial layer 850 may include a material having an etching selectivity relative to the lower channel region 202 and the preliminary upper channel region 848. The sacrificial layer 850 may include, for example, a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the sacrificial layer 850 may include a SiGe layer.

[0121] Reference Figure 8 and Fig.10 , a portion of the preliminary upper channel region 848 may be removed to form the first upper channel region 204 and the second upper channel region 206. (Block 730). For example, a central portion of the preliminary upper channel region 848 in the second direction Y may be removed to form the first upper channel region 204 and the second upper channel region 206. The portion of the preliminary upper channel region 848 may be removed, for example, by an etching process (e.g., a dry etching process and / or a wet etching process). As a result of removing a portion of the preliminary upper channel region 848, a recess 952 may be formed in the sacrificial layer 850. When a portion of the preliminary upper channel region 848 is removed, a portion of the sacrificial layer 850 may also be removed.

[0122] Reference Fig.11 , the sacrificial layer 850 may be removed and replaced with the gate electrode 224 and the gate insulator. For example, the sacrificial layer 850 may have an etching selectivity with respect to the lower channel region 202 and the first and second upper channel regions 204 and 206, and thus the sacrificial layer 850 may be selectively removed by an etching process (e.g., a dry etching process and / or a wet etching process) without removing the lower channel region 202 and the first and second upper channel regions 204 and 206.

[0123] The work function layer 226 may be disposed between the gate electrode 224 and the gate insulator. In some embodiments, the work function layer 226 may extend between the gate electrode 224 and the gate insulator, and may separate the gate electrode 224 from the gate insulator.

[0124] An interlayer insulating layer 218 may be formed on the gate electrode 224 and may extend between the first upper channel region 204 and the second upper channel region 206. The interlayer insulating layer 218 may separate the first upper channel region 204 from the second upper channel region 206 in the second direction Y.

[0125] Reference Figure 8 and 12, a pair of lower source / drain regions 208 may be formed (block 740). The pair of lower source / drain regions 208 may be formed by performing an epitaxial growth process using the lower channel region 202 as a seed layer. Specifically, the pair of lower source / drain regions 208 may be grown from opposite side surfaces of the lower channel region 202 in the first direction X, respectively, by an epitaxial growth process. The first lower source / drain region 208a may be grown from a first side surface of the lower channel region 202, and the second lower source / drain region 208b (see Figure 3A ) may grow from a second side surface of the lower channel region 202 opposite to the first side surface in the first direction X.

[0126] A first pair of upper source / drain regions 210 and a second pair of upper source / drain regions 212 may be formed (block 750). The first pair of upper source / drain regions 210 may be formed by performing an epitaxial growth process using the first upper channel region 204 as a seed layer. Specifically, the first pair of upper source / drain regions 210 may be grown from opposite side surfaces of the first upper channel region 204 in the first direction X, respectively, by an epitaxial growth process. The first upper source / drain region 210a may be grown from a first side surface of the first upper channel region 204, and the second upper source / drain region 210b (see FIG. 2 ) may be grown from a first side surface of the first upper channel region 204. Figure 3A ) may be grown from a second side surface of the first upper channel region 204 opposite to the first side surface in the first direction X. The second pair of upper source / drain regions 212 may be formed by performing an epitaxial growth process using the second upper channel region 206 as a seed layer. Specifically, the second pair of upper source / drain regions 212 may be grown from opposite side surfaces of the second upper channel region 206 in the first direction X, respectively, by an epitaxial growth process. The third upper source / drain region 212a may be grown from the first side surface of the second upper channel region 206, and the fourth upper source / drain region 212b (see Figure 3A ) may grow from a second side surface of the second upper channel region 206 opposite to the first side surface in the first direction X.

[0127] Return to reference Figure 3A , Figure 3B and Figure 3C BEOL structure 220 may be formed by a BEOL portion of device manufacturing. BSPDN 222 including first power line P1 and second power line P2 may also be formed. A central portion of each of first power line P1 and second power line P2 in the second direction Y may define a cell boundary CB.

[0128] It will be understood that, including with reference to Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A and Figure 6B The standard cell SC1 in the integrated circuit device 100 described above can be obtained by referring to Figures 8 to 12 The methods described are similarly formed with appropriate modifications thereto.

[0129] For example, in reference Figure 4A , Figure 4B and Figure 4C In the first standard cell SC1 described above, a portion of the preliminary lower channel region may be removed to form a first lower channel region 330 and a second lower channel region 332. An insulating layer 340 may fill a recess generated by removing a portion of the preliminary lower channel region. The insulating layer 340 may extend between the first lower channel region 330 and the second lower channel region 332, and may separate the first lower channel region 330 from the second lower channel region 332 in the second direction Y.

[0130] For example, in reference Figure 5A , Figure 5B and Figure 5C In the described first standard cell SC1 , portions of the lower channel region 202 and the upper channel region 328 may not be removed so that both the lower channel region 202 and the upper channel region 328 may be merged to extend longitudinally in the second direction Y and overlap with the second power line P2 in the third direction Z.

[0131] For example, in reference Fig. 6A and Figure 6B In the depicted first standard cell SC1 , the power lines P1 and P2 may be formed by the BEOL portion of device fabrication in the BEOL structure 220 rather than during the formation of the BSPDNS 222 .

[0132] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that the present disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always represent the same elements.

[0133] Example embodiments are described herein with reference to schematic diagrams as idealized embodiments and cross-sectional views of intermediate structures of example embodiments. Thus, variations in the shapes of the diagrams, such as those caused by manufacturing techniques and / or tolerances, will be anticipated. Therefore, the embodiments herein should not be construed as being limited to the specific shapes shown herein, but may include deviations in shapes, such as those caused by manufacturing. Although elements are shown as single layers in the accompanying drawings, elements may include multiple layers.

[0134] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their contextual meaning in the relevant art, and will not be interpreted in an idealized or overly formal manner.

[0135] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that the terms "comprise" and / or "comprising" when used in this specification specify the presence of narrated features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or their groups.

[0136] It will be understood that when an element is referred to as being "connected to" or "on" another element, it can be directly connected to or on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected to" or "directly on" another element, there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or" It will be understood that although the terms "first", "second", etc. may be used to describe various elements herein, these elements should not be limited by these terms. These terms are only used to separate one element from another element region. Therefore, without departing from the teachings of the present embodiment, the first element may be referred to as the second element.

[0137] For ease of description, spatially relative terms (such as, "below," "below," "below," "above," and "above," etc.) may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as "below" or "below" other elements or features will be "located above" the other elements or features. Therefore, the term "below" may include both the orientation of "above" and the orientation of "below." The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0138] In conjunction with the above description and the accompanying drawings, many different embodiments have been disclosed herein. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0139] The subject matter disclosed above is considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. An integrated circuit device comprising: an upper transistor including an upper channel region on the substrate; A lower transistor, between the substrate and the upper transistor, the lower transistor including a lower channel region; as well as a power line extending longitudinally in a first horizontal direction, wherein at least one of the upper channel region and the lower channel region extends longitudinally in a second horizontal direction transverse to the first horizontal direction, and The at least one of the upper channel region and the lower channel region overlaps the power supply line in the thickness direction.

2. The integrated circuit device according to claim 1, wherein: The at least one of the upper channel region and the lower channel region is electrically connected to a source / drain region overlapping the power supply line in the thickness direction.

3. The integrated circuit device according to claim 1, wherein: The at least one of the upper channel region and the lower channel region includes a central portion in the second horizontal direction, the central portion overlapping the power supply line in the thickness direction.

4. The integrated circuit device according to claim 1, wherein: The lower channel region overlaps the power supply line in the thickness direction, and the upper channel region does not overlap the power supply line in the thickness direction.

5. The integrated circuit device according to claim 4, wherein: A width of the lower channel region in the second horizontal direction is at least twice a width of the upper channel region in the second horizontal direction.

6. The integrated circuit device according to claim 4, wherein: the upper transistor is a first upper transistor, and the upper channel region is a first upper channel region, The integrated circuit device further includes: a second upper transistor including a second upper channel region spaced apart from the first upper channel region in a second horizontal direction, and The lower channel region overlaps the first upper channel region and the second upper channel region in a thickness direction.

7. The integrated circuit device according to claim 1, wherein: The upper channel region overlaps the power supply line in the thickness direction, and the lower channel region does not overlap the power supply line in the thickness direction.

8. The integrated circuit device according to claim 7, wherein: A width of the upper channel region in the second horizontal direction is at least twice a width of the lower channel region in the second horizontal direction.

9. The integrated circuit device according to claim 1, wherein: Both the upper channel region and the lower channel region overlap the power supply line in the thickness direction.

10. The integrated circuit device according to any one of claims 1 to 9, wherein: The power cord is the first power cord, The integrated circuit device further includes: a second power line and a third power line spaced apart from each other in a second horizontal direction, wherein the first power line is between the second power line and the third power line, and The at least one of the upper channel region and the lower channel region includes a portion spaced apart from the second power line and the third power line by an equal distance in the second horizontal direction.

11. An integrated circuit device comprising: A first transistor including a first channel region on a substrate; as well as a pair of second transistors including a pair of second channel regions spaced apart from each other in a first horizontal direction, The first channel region overlaps with the pair of second channel regions in a thickness direction.

12. The integrated circuit device according to claim 11, wherein: The first channel region is between the substrate and the pair of second channel regions.

13. The integrated circuit device according to claim 11, wherein: The pair of second channel regions are between the substrate and the first channel region.

14. The integrated circuit device according to claim 11, wherein: The first channel region includes: a first portion overlapping a first channel region of the pair of second channel regions in a thickness direction; a second portion overlapping the second channel region of the pair of second channel regions in the thickness direction; and The third portion is between the first portion and the second portion and does not overlap the pair of second channel regions in the thickness direction.

15. The integrated circuit device according to claim 11, further comprising: The power line extends longitudinally in a second horizontal direction transverse to the first horizontal direction, wherein the first channel region overlaps the power line in a thickness direction.

16. The integrated circuit device according to claim 15, wherein: The pair of second channel regions do not overlap the power supply line in the thickness direction.

17. An integrated circuit arrangement according to any one of claims 11 to 16, wherein: A width of the first channel region in the first horizontal direction is wider than a combined width of the pair of second channel regions in the first horizontal direction.

18. An integrated circuit arrangement according to any one of claims 11 to 16, wherein: The first channel region is electrically connected to the first source / drain region, One of the pair of second channel regions is electrically connected to the second source / drain region, and the other of the pair of second channel regions is electrically connected to the third source / drain region, and The first source / drain region overlaps the second source / drain region and the third source / drain region in a thickness direction.

19. A method of forming an integrated circuit device, the method comprising: forming a lower transistor and an upper transistor on a substrate, the lower transistor including a lower channel region and the upper transistor including an upper channel region; as well as forming a power supply line extending longitudinally in a first horizontal direction, wherein at least one of the upper channel region and the lower channel region extends longitudinally in a second horizontal direction transverse to the first horizontal direction, and The at least one of the upper channel region and the lower channel region overlaps the power supply line in the thickness direction.

20. The method according to claim 19, further comprising: A source / drain region is formed, the source / drain region being electrically connected to the at least one of the upper channel region and the lower channel region and overlapping the power supply line in the thickness direction.

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