Integrated circuit bus I2C slave device, system and awakening method

Abstract

The invention relates to an integrated circuit bus (I2C) slave device, an I2C master device and a wake-up method, when the I2C slave device is in a low-power-consumption state, the I2C master device initiates a read / write access operation, and partial wake-up enable configured by an I2C communication module is closed, and after the I2C communication module receives matching of a device address, or the partial wake-up enable configured by the I2C communication module is started, the I2C slave device and the I2C master device are started. When the I2C communication module receives the device address, the address is matched, and the received register access address is greater than or equal to the wake-up address configured by the I2C communication module, a wake-up signal is generated and output to the system control module and the SoC, the system clock is recovered, and the SoC quits the low power consumption mode after receiving the wake-up signal. The I2C slave device can enter a low-power-consumption state during idle, power consumption is saved, the I2C slave device can be awakened in a non-inductive and selective mode during I2C communication, and data transmission can be completed in the low-power-consumption state.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an integrated circuit bus I2C slave device, system and wake-up method. Background Art

[0002] The slave device system based on the integrated circuit bus I2C, when idle, after receiving the instruction for indicating entering the low power state, the entire system enters the low power state to save power. In the low power state, the master device initiates I2C communication to wake up the system. When the wake-up signal for indicating exiting the low power state is generated, the entire system exits the low power state. There are mainly two methods for waking up the system based on I2C communication in the prior art: 1. During the communication process, after the slave device detects the I2C start signal, it generates a wake-up signal to wake up the system. 2. During the communication process, after the slave device receives the device address and the device address matches, it generates a wake-up signal to wake up the system.

[0003] In the first wake-up method of the prior art, if there are multiple slave devices on the integrated circuit bus I2C, as long as the master device initiates communication, each slave device will detect the start signal and all slave devices will be awakened. In the second wake-up method, each time the communication is carried out, as long as the slave device receives a matching device address, the system will be awakened. In addition, in the process of waking up the system in these two methods of the prior art, the slave device needs to adopt the clock extension mechanism in the I2C protocol to keep the serial clock line SCL in a low level state, thereby lengthening the clock cycle and forcing the master device to suspend data transmission to ensure that the slave device has enough time to wake up the system. After the slave device system wakes up and the clock is restored, the serial clock line SCL is released and data transmission can continue.

[0004] The existing technology cannot meet the needs of the I2C master device to selectively wake up the slave device system when the slave device system is in a low-power state; secondly, the existing technology needs to pull down the serial clock line SCL of the integrated circuit bus I2C during the system wake-up process, forcing the master device to suspend data transmission and wait for the slave device to wake up the system and restore the clock before continuing communication. In addition, in the I2C protocol, the clock stretching function is optional, and most devices may not support this function. The existing technology needs to use this function, and the slave device needs to implement the clock stretching function and must constrain the master device to also support this function or have a corresponding processing mechanism, otherwise it will cause communication failure and data loss. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an integrated circuit bus I2C slave device, system and wake-up method to solve the deficiencies of the prior art.

[0006] The object of the present invention is achieved by the following technical solutions: an integrated circuit bus I2C slave device, which is connected to a power supply, and the I2C slave device includes a system on chip SoC, a system control module, an I2C communication module and an I2C interface; The system on chip SoC enters a low power consumption mode after receiving an instruction for instructing to enter a low power consumption state, and transmits a low power consumption mode signal to a system control module; After receiving the low power mode signal, the system control module turns off the unnecessary system clock, generates a low power state signal and outputs it to the power supply to make it enter the low power mode, and after receiving the wake-up signal, restores the clock signal and cancels the low power state signal of the power supply to restore the normal working mode, and makes the system on chip SoC exit the low power mode; The I2C communication module is provided with two configuration signals, partial wake-up enable and wake-up address, and different configuration signals are used to select whether to wake up the I2C slave device during I2C communication and the timing of generating the wake-up signal, and the I2C communication is realized in an asynchronous manner, that is, the serial clock line SCL is used as the clock to complete the transmission of the serial data SDA, so as to complete the data read / write access in a low power consumption state without a system clock; The I2C interface is connected for communication with external devices.

[0007] The method of selecting whether to wake up the I2C slave device during I2C communication and the timing of generating the wake-up signal by using different configuration signals includes: Partial wake-up enable is turned off, the system is woken up after receiving a matching device address, otherwise the system is not woken up and communication is not continued; Partial wake-up is enabled. After receiving a matching device address, the system will not be woken up immediately. Instead, the system will be woken up only after receiving a register access address that is greater than or equal to the configured wake-up address. Otherwise, the system will not be woken up, but communication will continue, that is, data transmission is performed in a low power state.

[0008] The I2C slave device also includes a glitch filtering circuit, which is connected to the I2C interface and the I2C communication module respectively; the glitch filtering circuit filters high-level glitches and low-level glitches on the serial clock line SCL and serial data SDA on the integrated circuit bus I2C in the absence of a system clock, so as to ensure that the I2C communication implemented in an asynchronous manner can reliably transmit data.

[0009] The I2C slave device also includes a memory, and uses the serial clock line SCL as a clock to access data, and data access can be completed without the participation of a system clock.

[0010] An integrated circuit bus I2C system, the system includes an I2C master device and an I2C slave device; the I2C master device is communicatively connected with an I2C interface, the I2C master device initiates a read / write access operation to the I2C slave device, wakes up the system imperceptibly or completes data transmission in a low power consumption state.

[0011] A method for waking up an I2C slave device, the method comprising: When the I2C slave device is in a low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured by the I2C communication module is turned off, the I2C communication module generates a wake-up signal after receiving a device address match and outputs it to the system control module and the system on chip SoC. The system control module recovers the system clock, and the system on chip SoC exits the low power mode after receiving the wake-up signal, and the entire system exits the low power state; Alternatively, when the I2C slave device is in a low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured by the I2C communication module is turned on, the I2C communication module generates a wake-up signal and outputs it to the system control module and the system on chip SoC when it receives the device address and the address matches, and the received register access address is greater than or equal to the wake-up address configured by the I2C communication module. The system control module restores the system clock, and the system on chip SoC exits the low power mode after receiving the wake-up signal, and the entire system exits the low power state.

[0012] The awakening method further includes: When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured by the I2C communication module is turned on, the I2C communication module receives the device address and the address matches, and the received register access address is less than the wake-up address configured by the I2C communication module. At this time, no wake-up signal is generated, and the I2C communication module continues to complete data transmission in the low power state.

[0013] The awakening method further includes: When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, but the device address received by the I2C slave device does not match. Regardless of whether the partial wake-up enable configured in the I2C communication module is turned on, it will neither wake up nor continue to transmit data, and the communication ends.

[0014] The present invention has the following advantages: an integrated circuit bus I2C slave device, system and wake-up method can enter a low power consumption state when idle to save power consumption, can wake up the I2C slave device system imperceptibly and selectively during I2C communication, and can also complete data transmission in a low power consumption state; when the I2C slave device is in a low power consumption state, each read / write access operation initiated by the I2C master device to the slave device is normal data transmission for the I2C slave device, thereby improving transmission efficiency; the I2C communication module uses an asynchronous method to implement I2C communication, that is, the serial clock line SCL is used as a clock to complete data transmission. Combined with the above configuration, it can meet the needs of completing data transmission without waking up the system when reading / writing access to certain memories that do not require a system clock. Flexibility is improved and power consumption is saved at the same time. Secondly, in the process of waking up the system, it is not necessary to suspend the I2C communication by pulling down the serial clock line SCL, and the master device does not need to be forced to wait for the slave device clock to recover before continuing to complete the communication, so that both the master device and the slave device do not need to support the clock extension function, simplifying the design and enhancing the applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of the present invention; Figure 2 A schematic diagram of a data transmission format for an I2C read / write access operation of the present invention; Figure 3 This is the I2C communication timing diagram; Figure 4 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0017] like Figure 1As shown, one embodiment of the present invention relates to an integrated circuit bus I2C slave device system, which includes a system on chip SoC, a system control module, a memory, an I2C communication module, a glitch filtering circuit and an I2C interface.

[0018] Among them, after the SoC receives the instruction to enter the low power state, the SoC enters the low power mode and outputs the low power mode signal to the system control module. After the wake-up signal is generated, the system control module turns on the clock, and the SoC exits the low power mode after receiving the wake-up signal.

[0019] The system control module is used to shut down the system clocks that are not needed by the SoC and other modules after receiving the signal that the SoC enters the low-power mode, and generate a low-power state signal to output to the power supply to make it enter the low-power mode. After receiving the wake-up signal, the system control module restores the clocks of the SoC and other modules, cancels the low-power state signal of the power supply, and restores the power supply to the normal working mode.

[0020] The I2C communication module is equipped with two configuration signals: partial wake-up enable and wake-up address. Different configurations can be used to select whether to wake up the I2C slave device during I2C communication and when the wake-up signal is generated. That is, the system will be woken up only when needed, rather than every time communication occurs, to save power consumption.

[0021] At the same time, the I2C communication module uses an asynchronous method to implement I2C communication, that is, the serial clock line SCL is used as the clock to complete the transmission of serial data SDA. In this way, data read / write access can be completed in a low-power state without a system clock. Figure 3 As shown in the figure, the communication starts with the start bit (S) and ends with the stop bit (P). When the communication is in the idle state, the serial clock line SCL and the serial data line SDA are both in the high level state. Each SCL clock corresponds to one bit of SDA data, and the jump of SDA data always occurs at the low level of the SCL clock. Therefore, the transmission of serial data SDA can be realized without relying on the system clock, only using the serial clock SCL as the clock.

[0022] The glitch filtering circuit can filter out high-level glitches and low-level glitches on the serial clock line SCL and the serial data line SDA on the integrated circuit bus I2C in the absence of a system clock, thereby ensuring reliable data transmission for the I2C communication implemented in an asynchronous manner.

[0023] The memory uses the serial clock line SCL as the clock to access data, and can complete data access without the participation of the system clock. The memory form is not limited, it can be a register or a whole storage module.

[0024] The I2C interface includes a serial clock SCL port and a serial data SDA port. Only two signal lines are needed to connect the master and slave devices to complete data transmission, saving valuable I / O resources.

[0025] Another embodiment of the present invention relates to an integrated circuit bus I2C system, which includes the I2C slave device and the I2C master device of the previous embodiment, the I2C master device is connected to the I2C interface in the I2C slave device for communication, and can enter a low power consumption state when idle to save power consumption. During I2C communication, the I2C slave device system can be awakened imperceptibly and selectively, and data transmission can also be completed in a low power consumption state.

[0026] That is, the system is in a low-power state. At this time, when the I2C master device accesses the slave device, the I2C communication is a normal read / write access operation for the slave device, and the system is woken up during the access process. During the entire I2C communication process, the slave device does not need to pull down the serial clock line SCL for clock stretching, nor does the master device need to suspend data transmission to wait for system wake-up and clock recovery. Data transmission can still be completed. In addition, the timing of generating a wake-up signal can be selectively specified by configuring partial wake-up enable and wake-up address. Communications before this will not wake up the system, so that the memory that does not require the system clock can still be accessed normally when the system is in a low-power state.

[0027] like Figure 4 As shown, another embodiment of the present invention relates to a method for waking up an integrated circuit bus I2C slave device system, which specifically includes the following contents: After the SoC receives the instruction for instructing to enter the low power consumption state, the SoC enters the low power consumption mode, and the system control module turns off the system clock and instructs the power supply to enter the low power consumption mode.

[0028] The I2C communication module is equipped with two configuration signals: partial wake-up enable and wake-up address. These two configuration signals are used to select whether to generate a wake-up signal and when to generate the wake-up signal.

[0029] When the I2C slave device system is in low power consumption state, when the I2C master device reads / writes the memory of the slave device, it is a normal data transmission operation for the I2C slave device. Through the above configuration, the system can be woken up without feeling during the data transmission process.

[0030] When the system is in low power state, the I2C master device initiates a read / write access operation, but the device address received by the slave device does not match. Regardless of whether the partial wake-up enable is turned on, the system is neither woken up nor the transmission continues, and the communication ends.

[0031] When the system is in low power consumption state, the I2C master device initiates a read / write access operation, and the partial wake-up enable is turned off, the I2C communication module of the slave device receives a device address match and generates a wake-up signal to output to the system control module and SoC. The system control module recovers the system clock, and the SoC exits the low power consumption mode after receiving the wake-up signal, and the entire system exits the low power consumption state.

[0032] When the system is in low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable is turned on, the slave receives the device address and the address matches, and then the received register access address is greater than or equal to the configured wake-up address, and generates a wake-up signal to output to the system control module and SoC. The system control module recovers the system clock, and the SoC exits the low power mode after receiving the wake-up signal, and the entire system exits the low power state.

[0033] When the system is in low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable is turned on, the slave receives the device address and the address matches, but the received register access address is less than the configured wake-up address, then no wake-up signal is generated, and the I2C communication module continues to complete data transmission in the low power state.

[0034] During the system wake-up process, the I2C slave device does not need to pull down the serial clock line SCL for clock stretching to wait for the system to wake up, and the master device does not need to suspend data transmission. The I2C communication module continues to communicate normally.

[0035] The data transmission format of the I2C communication module read / write access is transmitted in bytes, and each byte is followed by an acknowledge signal (A). Figure 2 As shown in the figure, the data transmission format for read / write access includes the transmission of the device address and the register access address. Each transmission starts with a start bit (S), followed by a 7-bit device address, followed by a 1-bit read / write (R / ¯W) indication signal, "0" for write and "1" for read. Then the N-byte register access address is transmitted. The stop bit (P) is used to end the transmission.

[0036] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used for various other combinations, modifications and improvements, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. An integrated circuit bus I2C slave device connected to a power supply, characterized in that: The I2C slave device includes a system on chip SoC, a system control module, an I2C communication module and an I2C interface; The system on chip SoC enters a low power consumption mode after receiving an instruction for instructing to enter a low power consumption state, and transmits a low power consumption mode signal to a system control module; After receiving the low power mode signal, the system control module turns off the unnecessary system clock, generates a low power state signal and outputs it to the power supply to make it enter the low power mode, and after receiving the wake-up signal, restores the clock signal and cancels the low power state signal of the power supply to restore the normal working mode, and makes the system on chip SoC exit the low power mode; The I2C communication module is provided with two configuration signals, partial wake-up enable and wake-up address, and different configuration signals are used to select whether to wake up the I2C slave device during I2C communication and the timing of generating the wake-up signal, and the I2C communication is realized in an asynchronous manner, that is, the serial clock line SCL is used as the clock to complete the transmission of the serial data SDA, so as to complete the data read / write access in a low power consumption state without a system clock; The I2C interface is connected for communication with external devices.

2. An integrated circuit bus I2C slave device according to claim 1, characterized in that: The method of selecting whether to wake up the I2C slave device during I2C communication and the timing of generating the wake-up signal by using different configuration signals includes: Partial wake-up enable is turned off, the system is woken up after receiving a matching device address, otherwise the system is not woken up and communication is not continued; Partial wake-up is enabled. After receiving a matching device address, the system will not be woken up immediately. Instead, the system will be woken up only after receiving a register access address that is greater than or equal to the configured wake-up address. Otherwise, the system will not be woken up, but communication will continue, that is, data transmission is performed in a low power state.

3. An integrated circuit bus I2C slave device according to claim 1, characterized in that: The I2C slave device also includes a glitch filtering circuit, which is connected to the I2C interface and the I2C communication module respectively; the glitch filtering circuit filters high-level glitches and low-level glitches on the serial clock line SCL and serial data SDA on the integrated circuit bus I2C in the absence of a system clock, so as to ensure that the I2C communication implemented in an asynchronous manner can reliably transmit data.

4. The integrated circuit bus I2C slave device according to claim 1, characterized in that: The I2C slave device also includes a memory, and uses the serial clock line SCL as a clock to access data, and data access can be completed without the participation of a system clock.

5. An integrated circuit bus I2C system, characterized in that: The system includes an I2C master device and an I2C slave device as described in any one of claims 1 to 4; the I2C master device is communicatively connected to an I2C interface, and the I2C master device initiates a read / write access operation to the I2C slave device to wake up the system imperceptibly or complete data transmission in a low power consumption state.

6. A method for waking up an I2C slave device according to any one of claims 1 to 4, characterized in that: The wake-up method comprises: When the I2C slave device is in a low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured by the I2C communication module is turned off, the I2C communication module generates a wake-up signal after receiving a device address match and outputs it to the system control module and the system on chip SoC. The system control module recovers the system clock, and the system on chip SoC exits the low power mode after receiving the wake-up signal, and the entire system exits the low power state; Alternatively, when the I2C slave device is in a low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured by the I2C communication module is turned on, the I2C communication module generates a wake-up signal and outputs it to the system control module and the system on chip SoC when it receives the device address and the address matches, and the received register access address is greater than or equal to the wake-up address configured by the I2C communication module. The system control module restores the system clock, and the system on chip SoC exits the low power mode after receiving the wake-up signal, and the entire system exits the low power state.

7. A wake-up method according to claim 6, characterized in that: The awakening method further includes: When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, and the partial wake-up enable configured by the I2C communication module is turned on, the I2C communication module receives the device address and the address matches, and the received register access address is less than the wake-up address configured by the I2C communication module. At this time, no wake-up signal is generated, and the I2C communication module continues to complete data transmission in the low power state.

8. A wake-up method according to claim 6, characterized in that: The awakening method further includes: When the I2C slave device is in low power state, the I2C master device initiates a read / write access operation, but the device address received by the I2C slave device does not match. Regardless of whether the partial wake-up enable configured in the I2C communication module is turned on, it will neither wake up nor continue to transmit data, and the communication ends.

Images