Thermal simulation analysis method of three-dimensional chip, computer device and readable storage medium

Abstract

The invention provides a thermal simulation analysis method of a three-dimensional chip, a computer device and a storage medium, and the method comprises the steps: obtaining a design file of the three-dimensional chip, the design file comprising line design information of each stacked layer of the three-dimensional chip; moreover, inputting a design file into a simulation program, setting grid division information for each stack layer, and performing grid division on each stack layer according to the grid division information by applying the simulation program to obtain metal density, via holes and medium information corresponding to each grid of each stack layer; power information of the three-dimensional chip is obtained, the power information is input into a simulation program, the simulation program calculates heat distribution information of the three-dimensional chip according to the power information and the metal density information of the grids of the stacked layers, and a temperature distribution cloud picture of the three-dimensional chip is formed based on the heat distribution information. The computer device and the storage medium can realize the method. The thermal simulation analysis cost of the three-dimensional chip can be reduced, and the thermal simulation analysis efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of analysis of three-dimensional stacked chips, and in particular to a thermal simulation analysis method for three-dimensional chips, and a computer device and a computer-readable storage medium for implementing the method. Background Art

[0002] With the development of integrated circuit technology, three-dimensional chips are widely used in large-capacity storage and high-speed signal processors due to their advantages such as high density, high speed, multi-function and low power consumption. Since a large number of devices are integrated inside a three-dimensional chip and the density of the devices is very high, a large amount of heat will be generated when the three-dimensional chip is working. For this reason, it is usually necessary to perform thermal simulation on the three-dimensional chip to identify the heat distribution when the three-dimensional chip is working. If the heat distribution of the three-dimensional chip is too uneven, it will easily lead to excessive heat accumulation in a certain area, affecting the device performance and service life of the device in that area.

[0003] The existing thermal analysis method for 3D chips mainly includes three steps. The first step is to perform system-level thermal analysis to find the hottest chip in the system. The second step is to perform package-level thermal analysis, which requires finding the hot spot area of ​​the 3D chip, that is, finding the area with the most concentrated heat in the 3D chip. The third step is to perform chip-level thermal analysis to optimize the hot spot temperature of the area by adjusting the RDL (Redistribution Layer) routing and vias of the 3D chip.

[0004] At present, the method for chip-level thermal analysis is mainly to first obtain the design file of the three-dimensional chip, and then obtain the routing, via and other information of each stacking layer of the three-dimensional chip based on the design file, and then model the three-dimensional chip based on the design file. Figure 1 Since the simulation program needs to model the three-dimensional chip to generate the specific structure of each stacking layer of the three-dimensional chip, for example, it is necessary to generate the specific positions of each routing and via of each stacking layer 11, 12, 13 in the three-dimensional chip 10.

[0005] The stacked structure 20 (BEOL, Back end of line) inside the three-dimensional chip is a structure that connects transistors and pads. The stacked structure 20 is mainly composed of metal wires, dielectric materials, and vias. With the improvement of the manufacturing process of three-dimensional chips, the size of metals is getting smaller and smaller, and coupled with the low thermal conductivity of dielectric materials, the thermal resistance of the stacked structure 20 becomes the main thermal resistance in the three-dimensional chip. For this reason, when modeling a three-dimensional chip, the traditional thermal analysis method is to accurately calculate the specific structure of the stacked structure 20, and then perform thermal analysis based on the accurately calculated model.

[0006] However, since the amount of data in the constructed model is very large, the amount of calculation required for thermal analysis based on the constructed model is also very large. This causes the simulation program to place extremely high demands on the computer's computing power, resulting in a very long simulation time for thermal analysis and high calculation costs. Summary of the invention

[0007] The first object of the present invention is to provide a thermal simulation analysis method for a three-dimensional chip which has low requirements on the computing power of a computer device and reduces the simulation analysis time.

[0008] A second object of the present invention is to provide a computer device for implementing the thermal simulation analysis method of the above-mentioned three-dimensional chip.

[0009] A third object of the present invention is to provide a readable storage medium for implementing the thermal simulation analysis method of the above-mentioned three-dimensional chip.

[0010] To achieve the first purpose of the present invention, the thermal simulation analysis method of a three-dimensional chip provided by the present invention includes obtaining a design file of the three-dimensional chip, the design file including circuit design information of each stacked layer of the three-dimensional chip; and, inputting the design file into a simulation program, and setting grid division information for each stacked layer, applying the simulation program to grid each stacked layer according to the grid division information, and obtaining metal density, vias, medium and other information corresponding to each grid of each stacked layer; obtaining power information of the three-dimensional chip, and inputting the power information into the simulation program, the simulation program calculates the thermal distribution information of the three-dimensional chip based on the power information and the metal density, vias, and medium information of each grid of each stacked layer, and forms a temperature distribution cloud map of the three-dimensional chip based on the thermal distribution information.

[0011] It can be seen from the above scheme that by dividing each stacked layer of the three-dimensional chip into multiple grids, and calculating the metal density information of each grid, thermal analysis is performed based on the metal density information of each grid. In this way, it is not necessary to model the three-dimensional chip during the thermal analysis process, nor is it necessary to perform thermal analysis based on the modeled model. Since each grid only records the metal density, vias, dielectric and other information of the grid, that is, only a 100% value is recorded, compared with the model of the three-dimensional chip, the amount of data of the metal density information of the grid is very small, so the computing power requirement is low, and a lot of time does not need to be spent on calculations during the simulation process, which can improve the simulation efficiency of thermal analysis.

[0012] A preferred solution is that the metal density information corresponding to each grid of each stacked layer calculated by the simulation program includes the metal content information of each grid.

[0013] It can be seen that by calculating the metal content information of each grid, when performing thermal simulation, the thermal distribution information is calculated based on the metal content information of each grid. Since the thermal resistance of the three-dimensional chip mainly comes from the metal, the thermal distribution information of the three-dimensional chip can be accurately calculated by calculating the metal content of each grid.

[0014] A further solution is that when the simulation program is used to mesh the stacked layers according to the meshing information, the simulation program also obtains the metal material information and thickness information of each stacked layer.

[0015] It can be seen that in addition to obtaining the metal content information of each grid, the metal material information and thickness information of each stacked layer are also obtained, which is conducive to accurately calculating the thermal distribution information of the three-dimensional chip.

[0016] A further solution is that, in the grid division information set for each stacking layer, the number of grid divisions of each stacking layer is equal.

[0017] An optional solution is that, in the grid division information set for each stacking layer, the number of grid divisions of at least one stacking layer is different from the number of grid divisions of another stacking layer.

[0018] It can be seen that, depending on the situation of the three-dimensional chip, the number of grids divided for different stacking layers can be equal or unequal to meet the simulation requirements of different three-dimensional chips.

[0019] A further solution is that when setting the grid division information for each stacking layer, each stacking layer is grid-divided in an array manner, and the area of ​​each grid is equal.

[0020] It can be seen that when the areas of each grid are equal, it is beneficial to calculate the metal density of each grid. Since the areas of each grid are equal, there is no need to consider whether the areas of the grids are equal in the subsequent thermal distribution calculation. Each grid is calculated as a reference unit, thereby improving the efficiency of thermal distribution information calculation.

[0021] A further solution is to obtain power information of the three-dimensional chip including the location of the heat source and the power intensity information.

[0022] Since heat sources may be distributed in different locations, the specific location and power intensity of the heat source are also considered when calculating the thermal distribution information. The heat distribution of each grid can be accurately calculated, thereby obtaining the thermal distribution information of the three-dimensional chip.

[0023] A further solution is that the thermal distribution information of the three-dimensional chip calculated by the simulation program includes the heat distribution information of each grid.

[0024] To achieve the second objective mentioned above, the computer device provided by the present invention includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, each step of the thermal simulation analysis method of the three-dimensional chip is implemented.

[0025] To achieve the third objective mentioned above, a storage medium provided by the present invention stores a computer program, and when the computer program is executed by a processor, each step of the thermal simulation analysis method of the three-dimensional chip mentioned above is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the structure of a three-dimensional chip.

[0027] Figure 2 It is a flow chart of an embodiment of a thermal simulation analysis method for a three-dimensional chip of the present invention.

[0028] Figure 3 It is a schematic diagram of dividing a stacking layer of a three-dimensional chip into grids in an embodiment of the thermal simulation analysis method for a three-dimensional chip of the present invention.

[0029] Figure 4 It is a distribution diagram of metal density information of each grid of a stacking layer of a three-dimensional chip in an embodiment of the thermal simulation analysis method of a three-dimensional chip of the present invention.

[0030] Figure 5 It is a temperature distribution cloud diagram obtained by simulation in the embodiment of the thermal simulation analysis method for a three-dimensional chip of the present invention.

[0031] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0032] The present invention simulates the thermal distribution of a three-dimensional chip, especially the thermal distribution of each stacking layer of a three-dimensional stacked chip, realizes simulation calculation with less computing power, and improves simulation efficiency. The computer device of the present invention has a processor and a memory, the memory is a readable storage medium of the present invention, and a computer program is stored on the memory. When the computer program is executed by the processor, the above-mentioned thermal simulation analysis method of the three-dimensional chip is realized.

[0033] Thermal simulation analysis method embodiment of a three-dimensional chip: This embodiment is used to simulate and analyze the heat distribution of three-dimensional stacked chips. Figure 2In this embodiment, step S11 is first performed to obtain the design file of the three-dimensional chip. For example, in the three-dimensional chip design stage, the developer will design the routing, vias and other information of each stacking layer of the three-dimensional chip. These routing and vias have specific positions on each stacking layer. Usually, the developer needs to edit the circuit design information of each stacking layer to form a GDS.map file for each stacking layer. Therefore, in step S11, the GDS.map file of each stacking layer needs to be obtained.

[0034] Then, step S12 is executed to input the design file into the simulation program. In this embodiment, the simulation program used is an existing program for three-dimensional chip thermal simulation, which is not limited here. When the design information of the three-dimensional chip is input into the simulation program, the GDS file of the wafer needs to be input into the simulation program.

[0035] Next, each stacked layer needs to be gridded. The main idea of ​​this embodiment is to only record the metal density, vias, dielectric and other information corresponding to each grid after each stacked layer is gridded. The metal density information is only represented by numerical values, and there is no need to model the three-dimensional chip. The subsequent thermal simulation process is based on the metal density information for thermal distribution analysis, instead of using the model of the three-dimensional chip for thermal distribution analysis. Therefore, the work of modeling the three-dimensional chip and using the model for thermal analysis can be omitted, and the computing power requirements for the computer are relatively low. While reducing the cost of thermal simulation, it can also improve the efficiency of thermal simulation.

[0036] Therefore, in step S12, it is necessary to set the grid division situation for each stacking layer, for example, the developer can manually input the number of grids for each stacking layer in the simulation program. Preferably, the simulation program grids the stacking layer in an array manner, for example, the stacking layer is divided into a grid of multiple rows and columns, so the developer only needs to input the number of rows and columns of the grid to be divided in the simulation program, and the total number of grids can be set. Moreover, the size of each grid divided by the simulation program is equal, that is, the stacking layer is divided into multiple rows and columns in an equal manner, and the size of each row is equal, and the size of each column is also equal. Of course, if the stacking layer is not a regular rectangle, an irregular shape will be formed at the boundary, but it does not affect the subsequent thermal analysis, so irregularly shaped grids are allowed to exist at the boundary.

[0037] Developers can flexibly set the number of grids in each stacking layer according to the situation of each stacking layer. For example, the number of grids in a certain stacking layer is set to 5×5, and the number of grids in another stacking layer is set to 10×10. That is to say, the number of grid divisions in each stacking layer may be unequal. Since the areas of each stacking layer of the three-dimensional chip are equal, when the number of grids in the stacking layers is unequal, the areas of individual grids in different stacking layers are unequal. Of course, the number of grids in each stacking layer can also be equal, that is, the number of grids in each stacking layer of the three-dimensional chip is equal, so the size and area of ​​each grid are also equal. In addition, when dividing the grid, the number of rows and columns of the grid can be equal or unequal. Therefore, developers can flexibly set the number of grids required to divide each stacking layer according to the actual situation of each stacking layer.

[0038] Then, step S13 is executed, and the simulation program divides each stack layer into grids according to the number of grid division rows and columns input by the developer. Assuming that the number of grids divided by the developer for a certain stack layer is 4×5, the grid division of the simulation program for the stack layer is as follows: Figure 3 As shown, the numbers in the figure are the serial numbers of each grid.

[0039] After the simulation program obtains the grid distribution of each stacked layer, it calculates the metal density information of each grid and obtains the via, dielectric and other information in the grid. Since the design file of the simulation program contains the routing information and via information of each stacked layer, usually, the via is filled with metal. Therefore, the simulation program can calculate the metal density information in each grid according to the specific location of the routing and via of each stacked layer. For example, the calculated metal density information of multiple grids of a certain stacked layer is as follows: Figure 4 As shown, Figure 4 The number in each grid represents the metal content of the grid, that is, the proportion of the volume of the metal in the grid to the volume of the grid. Since the thermal resistance generated by metal is the main thermal resistance of the three-dimensional chip, the metal content of each grid in each stacking layer is calculated, and the distribution of the metal in the stacking layer can be determined based on the metal content of each grid, thereby calculating the thermal distribution of the three-dimensional chip.

[0040] Next, execute step S14, and the simulation program obtains the power information of the three-dimensional chip. Since the developer will set the power information of the three-dimensional chip in advance according to the actual use of the three-dimensional chip, for example, including the heat source position and specific power of the three-dimensional chip. Usually, the heat source position of the three-dimensional chip can be located at the top or bottom of the three-dimensional chip, and, according to the use of the three-dimensional chip, the heat source position and power data are pre-set. Therefore, the developer only needs to input the pre-set heat source position and power information into the simulation program, and the simulation program can execute step S15 to calculate the thermal distribution of the three-dimensional chip based on the acquired power information and information on the heat source position, the metal density of each grid of each stacked layer, vias, media and other information, thereby forming the thermal distribution information of the three-dimensional chip.

[0041] Since step S13 has obtained the metal density information of each grid in each stacked layer, including data such as the metal content of each grid, and step S14 has obtained information such as the heat source and power, step S15 can quickly calculate the heat generated by each grid based on information such as the position and power of the heat source and the metal content of each grid, thereby forming a temperature distribution cloud map of the three-dimensional chip.

[0042] Finally, step S16 is executed to form a temperature distribution cloud map of the three-dimensional chip based on the thermal distribution information of the three-dimensional chip, such as Figure 5 As shown in the figure, the red area indicates the area with higher temperature of the 3D chip, that is, the area with more concentrated heat. Based on this, the temperature distribution cloud map of the 3D chip can be calculated. After the simulation program displays the generated temperature distribution cloud map on the display interface, developers can very intuitively and clearly understand the heat distribution of each area of ​​the 3D chip, so as to know which areas are the areas with more concentrated heat, and according to the distribution of the internal devices of the 3D chip, determine whether the devices, routings, vias, etc. of the 3D chip need to be adjusted to avoid excessive heat concentration in a certain area inside the 3D chip, which may affect the performance of the 3D chip.

[0043] It can be seen that this embodiment does not need to model the three-dimensional chip during the process of thermal simulation and analysis of the three-dimensional chip, especially does not need to model the wiring, vias, etc. inside the three-dimensional chip, which can reduce a lot of modeling time. In addition, since this embodiment only divides the stacked layers into grids, and calculates the metal density information such as the metal content of the grid, and then analyzes the thermal distribution based on the metal density information. Since the metal density and other information of the grid are only expressed in numerical values, the amount of calculation required to calculate the metal density information of each grid is small, the computing power requirements of the computer are low, and the computing efficiency is high, and the analysis and calculation of the thermal distribution can be completed in a shorter time, thereby reducing the cost and time of thermal analysis of the three-dimensional chip.

[0044] Computer device embodiment: The computer device of this embodiment can be various types of electronic devices, such as smart terminal devices, which have a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the above-mentioned information processing method. When the processor executes the computer program, each step of the thermal simulation analysis method of the above-mentioned three-dimensional chip is implemented.

[0045] For example, a computer program may be divided into one or more modules, one or more modules are stored in a memory and executed by a processor to complete each module of the present invention. One or more modules may be a series of computer program instruction segments capable of completing a specific function, and the instruction segments are used to describe the execution process of the computer program in a terminal device.

[0046] It should be noted that the terminal device may be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The terminal device may include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that the schematic diagram of the present invention is only an example of a terminal device and does not constitute a limitation on the terminal device. The terminal device may include more or fewer components than shown in the figure, or may combine certain components, or different components. For example, the terminal device may also include an input / output device, a grid access device, a bus, etc.

[0047] The processor referred to in the present invention may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.

[0048] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created according to the use of the mobile phone, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (FlashCard), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0049] Storage medium embodiment: If the computer program stored in the computer device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement each step of the above-mentioned three-dimensional chip thermal simulation analysis method.

[0050] Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form, etc. Computer readable media may include: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer readable media do not include electric carrier signals and telecommunication signals.

[0051] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. Thermal simulation analysis method for three-dimensional chips, including: Acquire a design file of a three-dimensional chip, wherein the design file includes circuit design information of each stacked layer of the three-dimensional chip; Features: Input the design file into a simulation program, set grid division information for each stacked layer, apply the simulation program to grid each stacked layer according to the grid division information, and obtain metal density, vias, and dielectric information corresponding to each grid of each stacked layer; The power information of the three-dimensional chip is obtained and input into the simulation program. The simulation program calculates the thermal distribution information of the three-dimensional chip according to the power information and the metal density, vias, and dielectric information of each grid of each stacked layer, and forms a temperature distribution cloud map of the three-dimensional chip based on the thermal distribution information.

2. The thermal simulation analysis method of a three-dimensional chip according to claim 1, characterized in that: The metal density information corresponding to each of the grids of each of the stacked layers calculated by the simulation program includes metal content information of each of the grids.

3. The thermal simulation analysis method of a three-dimensional chip according to claim 2, characterized in that: When the simulation program is used to perform mesh division on the stacked layers according to the mesh division information, the simulation program also obtains metal material information and thickness information of each of the stacked layers.

4. The thermal simulation analysis method for a three-dimensional chip according to any one of claims 1 to 3, characterized in that: In the grid division information set for each of the stacking layers, the number of grid divisions of each of the stacking layers is equal.

5. The thermal simulation analysis method for a three-dimensional chip according to any one of claims 1 to 3, characterized in that: In the grid division information set for each of the stacked layers, the number of grid divisions of at least one layer of the stacked layers is different from the number of grid divisions of another layer of the stacked layers.

6. The thermal simulation analysis method for a three-dimensional chip according to any one of claims 1 to 3, characterized in that: When setting the grid division information for each stacking layer, each stacking layer is grid-divided in an array manner, and the area of ​​each grid is equal.

7. The thermal simulation analysis method for a three-dimensional chip according to any one of claims 1 to 3, characterized in that: The acquiring of the power information of the three-dimensional chip includes heat source position and power intensity information.

8. The thermal simulation analysis method for a three-dimensional chip according to any one of claims 1 to 3, characterized in that: The thermal distribution information of the three-dimensional chip calculated by the simulation program includes the heat distribution information of each of the grids.

9. A computer device, characterized in that The method comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, each step of the thermal simulation analysis method for a three-dimensional chip as claimed in any one of claims 1 to 8 is implemented.

10. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step of the thermal simulation analysis method for a three-dimensional chip as claimed in any one of claims 1 to 8 is implemented.

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