High-frequency high-power packaging module and mixed substrate

Abstract

The invention discloses a high-frequency high-power packaging module which comprises at least three semiconductor power devices and a driver. The semiconductor power devices are arranged on the same plane; the driver provides a driving signal for each semiconductor power device, and the projection of the driver on the plane partially coincides with the projection of each semiconductor power device on the plane. On the other hand, the invention discloses a mixed substrate which comprises a high-heat-conduction area and a low-heat-conduction area. The high heat conduction area and the low heat conduction area are arranged in the horizontal direction. The heat conductivity coefficient of the high-heat-conductivity area is larger than that of the low-heat-conductivity area. According to the invention, the heat dissipation capability is guaranteed, the loop inductance is greatly reduced, high power and high frequency are realized, the advantages of a third-generation semiconductor are fully played, and an application basis is provided for the upgrading of the performance of the third-generation semiconductor.

Description

[0001] This application is a divisional application with application number 202310266865.1, application date March 17, 2023, and invention name “A high-frequency, high-power packaging module and a method for manufacturing the module”. Technical Field

[0002] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a high-frequency and high-power packaging module and a hybrid substrate. Background Art

[0003] As the third-generation semiconductor GaN / SiC gradually matures, its application is becoming more and more extensive. Compared with traditional silicon devices, its equivalent internal resistance is greatly reduced, which greatly increases the applicable power of a single semiconductor power device. At the same time, the third-generation semiconductor also has better switching characteristics, its switching loss is greatly reduced, and it is easier to work at high frequencies. However, due to the shortcomings of existing packaging technology, it is difficult to obtain the above two advantages at the same time.

[0004] like Figure 1 As shown in the figure, due to the small area and high heat density of the semiconductor power devices Q1 and Q2, a thick copper ceramic substrate is required to achieve insulation and heat conduction. However, the thick copper leads to poor wiring accuracy of the ceramic substrate, and small pitch SMD operations cannot be achieved. Therefore, the back side (i.e., the top side) of the semiconductor power device is usually welded to the ceramic board for heat dissipation, and the front side of the semiconductor power device is wired through wirebond to lead out the high-precision electrical arrangement on the semiconductor power device. Due to the existence of wirebond, the loop inductance increases significantly, which limits the increase in switching speed, and thus limits the increase in frequency.

[0005] Therefore, how to significantly reduce the loop inductance while ensuring heat dissipation capabilities so that high power and high frequency can be achieved and the advantages of third-generation semiconductors can be fully utilized is an urgent problem to be solved. Summary of the invention

[0006] In view of this, one of the purposes of the present invention is to provide a high-frequency and high-power packaging module, which ensures the heat dissipation capability while greatly reducing the loop inductance, so that high-power and high-frequency can be achieved, giving full play to the advantages of the third-generation semiconductors and providing an application basis for the upgrading of their performance.

[0007] Another object of the present invention is to provide a hybrid substrate for the above-mentioned high-frequency and high-power packaging module.

[0008] The high-frequency and high-power in the high-frequency and high-power packaging module of the present invention refers to: the power of the converter using the module exceeds 10KW, and the operating frequency is higher than 100KHz; or the operating frequency of the converter using the module is higher than 300KHz, and the power exceeds 1KW; wherein, the converter using the module preferably has a power of more than 10KW and an operating frequency of more than 300KHz. Of course, this is only a preferred application scenario, not a limitation of the present invention.

[0009] To achieve the above-mentioned object, the present invention discloses a high-frequency and high-power packaging module, comprising at least three semiconductor power devices and a driver;

[0010] The semiconductor power devices are arranged on the same plane;

[0011] The driver provides a driving signal for each of the semiconductor power devices, and a projection on the plane partially overlaps with a projection of each of the semiconductor power devices on the plane.

[0012] Preferably, it further comprises a circuit layer, wherein the circuit layer comprises a first surface and a second surface opposite to each other; the semiconductor power device is arranged on the first surface, and the driver is arranged on the second surface.

[0013] Preferably, the wiring distance from each of the semiconductor power devices to the corresponding driving signal terminal of the driver is the same.

[0014] Preferably, it also includes at least one high-frequency capacitor, an insulating heat-conducting plate and a plastic package;

[0015] The insulating heat-conducting plate comprises an insulating heat-conducting layer, and an upper metal layer and a lower metal layer respectively arranged on the upper and lower surfaces of the insulating heat-conducting layer;

[0016] The plastic package fills the gap area between the second surface of the circuit layer and the upper surface of the insulating heat-conducting plate, and an external electrode is arranged on the second surface or the side edge of the circuit layer, and the external electrode is electrically connected to the power conversion bridge arm;

[0017] The front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating heat-conducting plate;

[0018] The high-frequency capacitor is connected in parallel with the power conversion bridge arm to form a high-frequency loop, the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the insulating heat-conducting plate, and at least one electrode of the high-frequency capacitor is electrically connected to at least one electrode of at least one semiconductor power device through an inner electrical connection layer;

[0019] The wiring distance from each of the semiconductor power devices to the corresponding driving signal terminal of the driver is the same.

[0020] Preferably, it also includes a heat-conducting column, which is connected to the upper surface of the circuit layer through a high thermal conductivity interconnection, and the heat-conducting column is used for liquid cooling and heat dissipation.

[0021] Preferably, the thermally conductive column is a carbon fiber tube, and the high thermal conductivity interconnect is sintered silver.

[0022] Preferably, the high thermal conductivity interconnect is sintered silver, and the thermal conductive column includes a metal shell and an ultra-high thermal conductivity filler, wherein the ultra-high thermal conductivity filler is arranged inside the metal shell, and the ultra-high thermal conductivity filler is a carbon fiber tube, a graphene sheet or a phase change liquid.

[0023] Preferably, the heat-generating semiconductor device is a third-generation semiconductor power device, and the thermal density of the third-generation semiconductor power device is at least 2 W / mm2.

[0024] Another aspect of the present invention discloses a hybrid substrate, comprising a high thermal conductivity region and a low thermal conductivity region; the hybrid substrate has an upper surface and a lower surface opposite to each other;

[0025] The high thermal conductivity area and the low thermal conductivity area are arranged in a horizontal direction;

[0026] The high thermal conductivity area is used to set a heat-generating semiconductor device, and the heat-generating semiconductor device is specifically set on the lower surface;

[0027] The thermal conductivity of the high thermal conductivity region is greater than the thermal conductivity of the low thermal conductivity region;

[0028] The upper surface of the hybrid substrate is used for assembling a heat dissipation device.

[0029] Preferably, the thermal conductivity of the high thermal conductivity region is greater than twice the thermal conductivity of the low thermal conductivity region.

[0030] Preferably, the high thermal conductivity region is a high thermal conductivity particle array, or the high thermal conductivity region is a mixture of a high thermal conductivity particle array and a low thermal conductivity material.

[0031] Preferably, it further comprises an upper metal layer and a lower metal layer respectively arranged on the upper surface and the lower surface, and the materials of the high thermal conductivity area and the low thermal conductivity area are both insulating materials.

[0032] Preferably, the heat dissipation device comprises a heat-conducting column, the heat-conducting column and the upper surface of the hybrid substrate are connected via a high thermal conductivity interconnection, and the heat-conducting column is used for liquid cooling and heat dissipation.

[0033] Preferably, the thermally conductive column is a carbon fiber tube, and the high thermal conductivity interconnect is sintered silver.

[0034] Preferably, the high thermal conductivity interconnect is sintered silver, and the thermal conductive column includes a metal shell and an ultra-high thermal conductivity filler, wherein the ultra-high thermal conductivity filler is arranged inside the metal shell, and the ultra-high thermal conductivity filler is a carbon fiber tube, a graphene sheet or a phase change liquid.

[0035] Preferably, the heat-generating semiconductor device is a third-generation semiconductor power device, and the heat density of the third-generation semiconductor power device is at least 2W / mm 2 .

[0036] On the other hand, the present invention discloses a high-frequency high-power packaging module, characterized in that it includes at least one power conversion bridge arm, a circuit layer, an insulating heat-conducting plate and a packaging body;

[0037] The power conversion bridge arm includes at least two semiconductor power devices connected in series;

[0038] The circuit layer comprises a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path, wherein the inner electrical connection layer is electrically connected to the first surface via at least one vertical electrical connection path; an external electrode is disposed on the second surface of the circuit layer, and the external electrode is electrically connected to the power conversion bridge arm;

[0039] The insulating heat-conducting plate comprises an insulating heat-conducting layer;

[0040] The front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating heat-conducting plate;

[0041] The packaging body fills the gap area between the first surface of the circuit layer and the lower surface of the insulating heat conductive plate;

[0042] The semiconductor power device is a semiconductor wafer.

[0043] Preferably, the side of the high-frequency high-power packaging module is provided with a step-shaped structure for increasing the creepage distance, or the second surface of the circuit layer is provided with an insulating pin bracket and the side of the insulating pin bracket is provided with a step-shaped structure for increasing the creepage distance.

[0044] Preferably, the packaging body is formed by plastic packaging.

[0045] Preferably, an upper metal layer and a lower metal layer are respectively provided on two surfaces of the insulating heat-conducting layer.

[0046] Preferably, it further comprises a high-frequency capacitor, and the power conversion bridge arm is electrically connected to the high-frequency capacitor to form a high-frequency loop.

[0047] Preferably, a metal layer is provided on the lower surface of the insulating heat conducting plate, and the metal layer is an electrostatic potential.

[0048] Preferably, the packaging body fills a gap area between the second surface of the circuit layer and the lower surface of the insulating heat-conducting plate.

[0049] Preferably, the external electrodes are surface mount electrodes, and the surface mount electrodes are used to electrically interconnect the high-frequency and high-power packaging module with the system board through a surface mount process.

[0050] Preferably, the step-shaped body is a plastic package.

[0051] Preferably, the front side of the semiconductor power device is directly connected to the first surface of the circuit layer by welding, or directly connected by electroplated vias.

[0052] Preferably, a metal layer is provided on the lower surface of the insulating heat-conducting plate, and the front surface of the semiconductor power device is electrically connected to the first surface of the circuit layer through the metal layer on the lower surface of the insulating heat-conducting plate.

[0053] Preferably, it also includes an electrical connection device, through which at least one electrode on the front side of the semiconductor power device is led out to the outside of the high-frequency high-power packaging module and is electrically connected to at least one electrode of a high-frequency capacitor.

[0054] Preferably, it also includes a cross-ceramic layer electrical connection component and a common-mode suppression capacitor; one electrode of the common-mode suppression capacitor is electrically connected to the upper metal layer through the cross-ceramic layer electrical connection component, and the other electrode of the common-mode suppression capacitor is electrically connected to a DC end of a power conversion bridge arm.

[0055] Preferably, the external electrodes include at least one pair of DC-end external electrodes, at least one pair of AC-end external electrodes and at least one pair of signal-end external electrodes; the signal-end external electrodes are arranged between the DC-end external electrodes and the AC-end external electrodes.

[0056] Preferably, it also includes a buffer external pin, which is electrically connected to the circuit layer and is used to electrically connect the high-frequency and high-power packaging module to the customer's mainboard.

[0057] A high-frequency and high-power packaging module disclosed in the present invention ensures heat dissipation capability while significantly reducing loop inductance, thereby enabling high-power and high-frequency to be achieved, giving full play to the advantages of third-generation semiconductors, and providing an application basis for the upgrading of their performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 is a schematic diagram of a third generation semiconductor packaging structure in the prior art;

[0060] FIG. 2A to FIG. 2I A schematic diagram of the structure of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0061] FIG. 3A to FIG. 3C A schematic structural diagram of a high-frequency and high-power packaging module disclosed in another embodiment of the present invention;

[0062] FIG. 4A to FIG. 4C A schematic structural diagram of a high-frequency and high-power packaging module disclosed in another embodiment of the present invention;

[0063] FIG. 4D to FIG. 4E A schematic structural diagram of a high-frequency and high-power packaging module disclosed in another embodiment of the present invention;

[0064] Figure 5A A schematic diagram of the structure of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0065] Figure 5B An equivalent circuit diagram of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0066] FIG. 5C to FIG. 5E It is a schematic diagram of the structure of the packaging module of semiconductor power devices with different thicknesses;

[0067] Fig. 5F An equivalent circuit diagram of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0068] Figure 5G to Figure 5J It is a structural schematic diagram of a high-frequency, high-power packaging module with a thermal conductive column;

[0069] Figure 5K It is a structural schematic diagram of a high-frequency and high-power package module with a driver;

[0070] Figure 5L A schematic structural diagram of a high-frequency and high-power packaging module disclosed in another embodiment of the present invention;

[0071] Figure 6 Another structural schematic diagram of the high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0072] 7A to 7E A schematic diagram of the structure of a high-frequency capacitor, a multi-layer circuit board, a power conversion bridge arm and an insulating heat-conducting plate of a high-frequency high-power packaging module disclosed in an embodiment of the present invention at different heights;

[0073] FIG. 8A to FIG. 8F A schematic flow chart of a method for manufacturing a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0074] Fig. 9 A schematic structural diagram of a high-frequency and high-power packaging module disclosed in another embodiment of the present invention;

[0075] Fig.10 A schematic structural diagram of an electrode arrangement method for a semiconductor power device of a high-frequency, high-power packaging module disclosed in an embodiment of the present invention;

[0076] Fig.11 A schematic diagram of the structure of a high-frequency, high-power packaging module disclosed in an embodiment of the present invention provided with a high-heat capacity element;

[0077] FIG. 12A to FIG. 12D It is a structural schematic diagram of the buffer external pins of the high-frequency high-power packaging module disclosed in an embodiment of the present invention when they are arranged on the second surface of the multi-layer circuit board;

[0078] FIG. 13A to FIG. 13D It is a structural schematic diagram of a high-frequency high-power packaging module disclosed in an embodiment of the present invention when the buffer outer pins are arranged on the side edge of a multi-layer circuit board;

[0079] FIG. 13E to FIG. 13F A schematic diagram of the structure of other configurations of the buffer external pins of the high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0080] FIG. 14A to FIG. 14E A schematic flow chart of a method for manufacturing a buffer external pin of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0081] FIG. 15A to FIG. 15D A schematic diagram of a structure in which the buffer external pins of the high-frequency and high-power packaging module disclosed in an embodiment of the present invention are led out through a rewiring structure;

[0082] Fig.16A A schematic diagram of the structure of directly SMDing the packaged components of the high-frequency and high-power packaging module disclosed in an embodiment of the present invention to the second surface of the multi-layer circuit board;

[0083] Fig. 16B A schematic diagram of the structure of the multi-layer circuit board of the high-frequency and high-power packaging module disclosed in the embodiment of the present invention, after components are placed and interconnected on the second surface, and then the entire surface is plastic-sealed;

[0084] Fig. 16CA schematic diagram of the structure of the multilayer circuit board of the high-frequency and high-power packaging module disclosed in the embodiment of the present invention, in which components are placed on the second surface and interconnected, and then fixed and protected by the COB process;

[0085] FIG. 16D to FIG. 16F It is a structural schematic diagram of a high-frequency high-power packaging module disclosed in an embodiment of the present invention when a second surface protection member is provided;

[0086] FIG. 17A to FIG. 17E It is a schematic structural diagram of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention using double-sided plastic packaging;

[0087] Fig.18 A schematic structural diagram of an electrode arrangement method for a semiconductor power device of a high-frequency, high-power packaging module disclosed in an embodiment of the present invention;

[0088] Fig.19A An equivalent circuit diagram when the semiconductor power device of the high-frequency high-power packaging module disclosed in the embodiment of the present invention includes a normally-open third-generation semiconductor sub-power device and a low-voltage normally-closed semiconductor sub-power device;

[0089] FIG. 19B to FIG. 19D A schematic diagram of the structure of the semiconductor power device of the high-frequency high-power packaging module disclosed in the embodiment of the present invention includes a normally open third-generation semiconductor sub-power device and a low-voltage normally closed semiconductor sub-power device;

[0090] Fig. 20A An equivalent circuit diagram of a high-frequency, high-power packaging module disclosed in an embodiment of the present invention when a plurality of power conversion bridge arms are provided;

[0091] FIG. 20B to FIG. 20D It is a structural schematic diagram of a PIN surface when a high-frequency high-power packaging module disclosed in an embodiment of the present invention is provided with a plurality of power conversion bridge arms;

[0092] FIG. 21A to FIG. 21B A schematic diagram of a structure in which the side edge of the plastic package body of the high-frequency high-power packaging module disclosed in an embodiment of the present invention is in a stepped shape;

[0093] FIG. 22A to FIG. 22B A schematic diagram of the structure of an electrically insulating pin support of a high-frequency, high-power packaging module disclosed in an embodiment of the present invention;

[0094] Fig.23 This is a schematic diagram of the structure of the high-frequency and high-power packaging module disclosed in an embodiment of the present invention when it is installed vertically to the customer's mainboard;

[0095] FIG. 24A to FIG. 24D A schematic diagram of the heat dissipation of the high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0096] FIG. 25A to FIG. 25EA schematic flow chart of a secondary packaging process of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0097] FIG. 26A to FIG. 26C A schematic diagram of preventing electromagnetic interference of a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0098] FIG. 27A to FIG. 27C A schematic diagram of suppressing common mode noise by a high-frequency and high-power packaging module disclosed in an embodiment of the present invention;

[0099] FIG. 27D to FIG. 27G A structural schematic diagram of a configuration method of a common-mode suppression capacitor of a high-frequency, high-power packaging module disclosed in an embodiment of the present invention;

[0100] FIG. 28A to FIG. 28D The present invention is a flowchart of another method for manufacturing a high-frequency and high-power packaging module disclosed in an embodiment of the present invention.

[0101] FIG. 29A to FIG. 29C A schematic structural diagram of a high-frequency and high-power packaging module disclosed in another embodiment of the present invention;

[0102] in:

[0103] 1 high-frequency capacitor; 2 multi-layer circuit board; 3 insulating thermal conductive layer; 3a hybrid substrate; 4 upper metal layer; 5 lower metal layer; 6 heat sink; 7 / 70 plastic package; 8 customer mainboard; 9 electrical insulation sheet; 10 conductive component; 11 external electrode; 12 thermal resistance electrical connection layer; 13 high thermal capacity component; 14 buffer external pin; 15 insulating fixed frame; 16 metal spring; 17 circuit board through hole; 18 rewiring structure; 19 shell; 20 sealant; 21 silicone filler; 22 customer daughter board; 23 high-frequency decoupling capacitor; 24 common mode suppression capacitor; 25 cross-ceramic layer electrical connection component; 26 side edge electrical interconnection; 27 through-type electrical interconnection; 28 conductive coating; 29 support platform; 30 heating plate; 31 low loop pad; 32 fixing column; 101 bonding material; 102 bonding wire; 103 vertical connection; 104 electrochemical metal hole; 105 metal conductive bridge; 106 protrusion structure; 107 shielding layer; 108 large diameter vertical conductive part; 110 gate bonding wire; 111 source bonding wire; 112 power bond 121 electrical connection hole; 130 vertical electrical connection path; 131 / 132 protrusion structure; 133 thermal / electrical conductive interconnection material; 134 metal ball; 135 thermal conductive column; 135a top of thermal conductive column; 135b bottom of thermal conductive column; 136 flow guide device; 137 high thermal conductivity area; 138 low thermal conductivity area; 139 gate lead; 141 ceramic material; 142 high thermal conductivity electrical insulation particles; 143 shell; 144 high thermal conductivity interconnection; 145 ultra-high thermal conductivity filler; 151 fixed frame; 2 00 switch element; 201 first surface of multilayer circuit board; 202 second surface of multilayer circuit board; 301 upper surface of insulating heat-conducting layer; 302 lower surface of insulating heat-conducting layer; 400 electrode; 601 mounting hole; 602 copper pillar; 603 pad; 611 large deep countersunk hole; 612 small via; 621 power pin; 622 signal pin; 631 copper pillar; 632 copper-clad layered electrode; 641 / 642 area; 643 electrically insulating pin bracket; 644 thermally conductive and electrically insulating material; A / B / C pin position; Bottom semiconductor power device front; C1 / C2 capacitor; Cbus bus capacitor; Ccer ceramic equivalent capacitor; Cth distributed capacitor; Cy1 external Y capacitor; Cy2 integrated Y capacitor; D1-D4 vertical connector; DBC insulating thermal conductive plate; Drain drain; Driver driver; Gate / G1-G4 gate; H1 distance from the first surface to the top surface; H2 distance from the first surface to the bottom surface; H3 distance from the first surface to the top surface; H4 distance from the second surface to the bottom surface; HC high-frequency capacitor height; Icom common mode current; L1 module thickness; L2 insulation distance; L3 air gap; Line_G wiring ground; Lloop loop parasitic inductance; Lth distributed inductance; Q1 / Q2 / Q3 / Q4 / Q1-1 / Q1-2 / Q1-3 / Q2-1 / Q2-2 / Q2-3 semiconductor power device; Q10 power semiconductor chip with high thermal density;Rin damping; Rth contact resistance; Source / S1-S4 source; Top semiconductor power device back; V1-V4 vertical connector; x module length axis; y module width axis; z module height axis. ; DETAILED DESCRIPTION

[0104] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0105] like Figure 2A As shown, an embodiment of the present invention discloses a high-frequency and high-power packaging module, including: a multi-layer circuit board 2, an insulating heat-conducting plate, a plastic package body 7, at least one power conversion bridge arm and at least one high-frequency capacitor 1; the multi-layer circuit board 2 here is the circuit layer, which is not limited to an independent multi-layer circuit board, and can also refer to a wiring layer of a multi-layer circuit, or a wiring layer with the same function formed in a module process, and is hereinafter referred to as a multi-layer circuit board; the x-axis and y-axis here represent the length direction and width direction of the module, and the x-axis and y-axis constitute the horizontal plane of the module, and the z-axis represents the height of the module, and the same applies hereinafter.

[0106] The power conversion bridge arm includes at least two semiconductor power devices Q1 and Q2 connected in series, and the high-frequency capacitor 1 is connected in parallel with the power conversion bridge arm to form a high-frequency loop. At least one power conversion bridge arm is arranged on the insulating heat-conducting plate, and the plastic package 7 fills the gap area between the multi-layer circuit board and the insulating heat-conducting plate.

[0107] The front sides of the semiconductor power devices Q1 and Q2 are electrically connected to the multilayer circuit board, and the back sides of the semiconductor power devices Q1 and Q2 are thermally or electrically connected to the lower surface of the insulating heat-conducting plate.

[0108] The multilayer wiring board at least partially overlaps the semiconductor power devices Q1 and Q2 of the high-frequency circuit to which it belongs in the projection direction.

[0109] like Figure 2AAs shown, the semiconductor power device is bonded to the insulating heat conductive plate DBC through a bonding material 101, and its front electrode is electrically connected to the wiring layer of the insulating heat conductive plate by means of a bonding wire 102. The multilayer circuit board 2 is stacked on the insulating heat conductive plate, and the multilayer circuit board 2 is equipped with a high-frequency capacitor 1. The insulating heat conductive plate can be a direct bonded copper clad plate (DBC for short, DBC is also used to refer to the insulating heat conductive plate below), including an insulating heat conductive layer 3, an upper metal layer 4 and a lower metal layer 5, wherein the upper metal layer 4 is arranged on the upper surface of the insulating heat conductive layer 3, and the lower metal layer 5 is arranged on the lower surface of the insulating heat conductive layer 3. The insulating heat conductive plate can be a ceramic insulating plate or a printed circuit board, but is not limited thereto. The multilayer circuit board 2 and the insulating heat conductive plate are electrically connected through a vertical connector 103. The multilayer circuit board 2 and the insulating heat conductive plate are mechanically connected and electrically insulated through a plastic encapsulation material 7, and the environmental protection capability is effectively improved. The bonding material 101 of the embodiment of the present invention includes but is not limited to solder, silver, copper or other sintering materials. The material of the upper metal layer 4 and the lower metal layer 5 of the embodiment of the present invention is copper.

[0110] like Figure 2B As shown, in the current loop of the high-frequency capacitor 1, the current passing through the adjacent vertical connecting members 103 is set in reverse, so the loop inductance can be controlled at a lower level.

[0111] In other embodiments, Figure 2C As shown, the electrical connection between the insulating heat-conducting plate and the multi-layer circuit board 2 can also be achieved through the electrochemical metal hole 104.

[0112] like Figure 2D As shown, the front electrode of the semiconductor power device is interconnected with the multilayer circuit board 2 through the metal conductive bridge 105. Compared with the bonding wire 102, the metal conductive bridge 105 can have a smaller connection impedance. The connection material between the metal conductive bridge 105 and the semiconductor power device includes but is not limited to solder, silver or copper and other sintering materials.

[0113] like Figure 2E As shown, the front electrode of the semiconductor power device can be directly connected to the multi-layer circuit board 2 through the vertical connector 103, and can also be directly interconnected with the multi-layer circuit board through the protrusion structure 106 set on the metal conductive bridge.

[0114] like Figure 2F As shown, the multilayer circuit board 2 can be electroplated and etched on the surface of the plastic package 7, reducing the material matching requirements and improving reliability.

[0115] like Figure 2G As shown, the multilayer circuit board 2 can place components on both sides to integrate more functions.

[0116] In some other embodiments, such as Figure 2H As shown, a shielding layer 107 is provided in the envelope region of the high-frequency loop composed of the high-frequency capacitor 1 and the semiconductor power device, and the shielding layer 107 can be connected to a fixed potential. Fig.2I As shown, the shielding layer 107 may not be connected to other potentials, for example, the shielding layer 107 is arranged inside the multi-layer circuit board. In this embodiment, the parasitic inductance of the loop can be further reduced by arranging the shielding layer 107.

[0117] like Figure 3A As shown, a half-bridge circuit formed by two switch elements 200 connected in series is arranged on the insulating heat-conducting plate. The two switch elements 200 are respectively composed of three semiconductor power devices (such as Q1-1, Q1-2 and Q1-3 or Q2-1, Q2-2 and Q2-3) connected in parallel. In actual use, the number of semiconductor power devices constituting each switch element is not limited to this and can be freely adjusted as needed. The gates of the parallel chips are independently increased with gate-level resistance (not shown in the figure) to improve the dynamic and static current sharing between the parallel chips. Vertical connectors 103 are arranged on the insulating heat-conducting plate as needed to achieve electrical connection with the multilayer circuit board 2. Figure 3B The schematic diagram of the stacked multilayer circuit board is shown in FIG. 1 . The projection of the wiring Vbus+ or Vbus- connected to both ends of the high-frequency capacitor 1 on the multilayer circuit board in the horizontal direction at least overlaps with the projection of the semiconductor power device in the horizontal direction to obtain the minimum loop inductance. Figure 3A It can be further seen that between parallel chips, such as Q1-1, Q1-2 and Q1-3, vertical connectors 103, such as D1-D4, V1-V4, can be distributed on the outside of the peripheral chips Q1 and Q3 and the wiring layer of the insulating heat-conducting layer to construct multiple high-frequency loops. Make the high-frequency loop impedances of (Q1-1, Q2-1 group) (Q1-2, Q2-2 group) (Q1-3, Q2-3 group) approximately the same. This has a lower and more uniform high-frequency loop impedance than the traditional planar layout, which can not only reduce the voltage stress of the switching device but also further improve the high-frequency current sharing characteristics of the module. Reference Figure 3C The high-frequency current passing through the high-frequency capacitor 1 actually passes through a 3D loop. The current loop in the projection direction of the horizontal plane is shown in the loop in the reference diagram. Since the high-frequency capacitor 1 can be distributed in the middle of the (Q1-1, Q2-1 group), the magnetic fields formed by the two high-frequency currents on both sides are opposite, which can effectively reduce the interference to external components and improve the reliability of the system.

[0118] In other embodiments, FIG. 4A to FIG. 4C As shown, the circuit topology C1 / Q1 / Q2 / Q3 forms a high-frequency loop, and C2 / Q3 / Q2 / Q4 forms another high-frequency loop. Figure 4B Wiring diagram for the insulated thermally conductive plate. Figure 4CSchematic diagram after stacking multilayer circuit boards, the wiring on the multilayer circuit board connected to the two ends of the high-frequency capacitor 1 overlaps at least partially with the semiconductor power device related to the high-frequency circuit to which it belongs in the horizontal projection direction to obtain the minimum loop inductance. In this embodiment, some of the vertical conductors used to connect the insulating heat-conducting plate DBC and the multilayer circuit board 2 can adopt different diameters, for example, large-diameter vertical conductors 108 (i.e., first vertical connectors) are arranged at the positions of the four side angles of DBC, so that the parallelism of the insulating heat-conducting plate DBC and the multilayer circuit board 2 can be ensured, and the difficulty of subsequent assembly can be reduced. For example, during the plastic packaging process, the difference in parallelism between the insulating heat-conducting plate DBC and the multilayer circuit board 2 will cause glue overflow, and the use of large-diameter vertical conductors 108 can solve similar problems. Furthermore, at least one large-diameter vertical conductor 108 and at least one power terminal have the same electrical properties, and the projection of the large-diameter vertical conductor 108 on the vertical plane overlaps with the power terminal, so that the parasitic impedance in the circuit where the large-diameter vertical conductor 108 is located is reduced, thereby improving the electrical performance of the product.

[0119] Furthermore, refer to Figure 3A and Figure 4B , the gates of multiple parallel semiconductor chips are all independently controlled. After the gate bonding wire 110, source bonding wire 111 and power bonding wire 112 are bonded, each semiconductor chip can be tested separately. When a failed chip is found, the corresponding vertical conductive column between the insulating heat conductive board DBC and the multi-layer circuit board 2 can be removed to isolate the failed chip from the parallel connection of multiple semiconductor chips; similarly, the power electrode of each semiconductor chip can also be isolated separately on the insulating heat conductive board DBC and connected to the multi-layer circuit board 2 through the corresponding vertical conductive member 103. Therefore, before installing the multi-layer circuit board 2, the Die Bond and Wire Bond of the insulating heat conductive board DBC are first completed, and then the complete characteristics of each Die are completed. After further screening, the multi-layer circuit board 2 is installed. Compared with the process of testing after the module is completed, the waste of various materials can be avoided.

[0120] like Figure 4D As shown, the electrode of the semiconductor chip (i.e., semiconductor power device Q1 or Q2) facing the side of the multilayer circuit board 2 can be formed by drilling holes in the multilayer circuit board 2 and the plastic packaging material 7, and depositing metal, such as copper, through a metallization process to form an electrical connection hole 121 to achieve electrical connection between the semiconductor chip and the multilayer circuit board 2. The drilling process of the electrical connection hole 121 can be achieved by mechanical and laser processing. In order to avoid damage to the front electrode of the semiconductor chip during the drilling process, it can be as follows Figure 4DAs shown, a metal layer (such as a copper layer) is bonded on the surface of the semiconductor chip on one side facing the multilayer circuit board 2 by solder, sintered silver, etc., and the thickness of the bonded metal layer is greater than 50um, preferably greater than 200um. On the other hand, a thicker metal layer can also be directly metallized on the surface of the semiconductor chip. In this embodiment, when testing the insulating thermal conductive board DBC at the assembly stage, the failed chip can be isolated by not setting the corresponding electrical connection holes; or after the electrical connection holes are set, the failed samples found when the module is tested can also be removed by mechanical, laser, chemical and other methods to isolate the failed samples.

[0121] Furthermore, if Figure 4E As shown, the electrodes on one side of the semiconductor chip facing the multi-layer circuit board are all connected by drilling holes in the multi-layer circuit board 2 and the plastic packaging material 7, and metal is deposited through a metallization process to achieve interconnection between the electrodes and the multi-layer circuit board, which can more completely isolate the failed chip.

[0122] like Figure 5A and Figure 5B As shown, another embodiment of the present invention further discloses a high-frequency, high-power packaging module, including at least one power conversion bridge arm and at least one high-frequency capacitor 1, the power conversion bridge arm includes at least two semiconductor power devices connected in series, and the high-frequency capacitor 1 is connected in parallel with the power conversion bridge arm. In order to reduce the switching loss of the conversion and pursue the extreme high speed of the switching elements, it is necessary to reduce the loop inductance formed by the above three elements, wherein the two poles of the high-frequency capacitor 1 are respectively the Vbus+ and Vbus- poles of the DC bus. The semiconductor power devices Q1 and Q2 described in the present invention include but are not limited to third-generation semiconductor power devices, such as GaN devices, SiC devices, etc.

[0123] Taking GaN devices as an example, planar devices are commonly used, that is, the three electrodes of its Pure Die are on the same surface (Top surface). Therefore, the PAD on its Top surface is very dense. In order to reduce the interconnection resistance and inductance, the present invention directly electrically interconnects the chip-sized GaNTop surface PAD to the first surface 201 of a high-precision multi-layer circuit board 2 (PCB), wherein at least one of the Vbus+ or Vbus- poles is interconnected through the inner electrical connection layer (Via) to the first surface 201 and the second surface 202, so that the loop inductance becomes extremely small through the coupling of the two layers.

[0124] Compared to Figure 1The traditional package has a loop inductance of nearly 10nH, which is suitable for supporting applications below 100KHz. The present invention has the opportunity to achieve a loop inductance below 1nH, which is sufficient to support MHz-level applications. The effect can be imagined. In this way, the loop inductance is guaranteed, providing a basis for high-frequency high-speed switching. Obviously, in order to achieve a low loop, at least one of the two semiconductor power devices Q1 and Q2 has at least two electrodes, such as the source Source and the gate Gate, which are welded to the multi-layer circuit board.

[0125] At the same time, the reverse side of the GaN device is thermally interconnected to an insulating heat conducting board (DBC), such as a ceramic substrate, through a material with a high thermal conductivity. The DBC includes an insulating heat conducting layer 3, and an upper metal layer 4 and a lower metal layer 5 respectively arranged on the upper and lower surfaces of the insulating heat conducting layer 3. The insulating heat conducting layer 3 can not only conduct heat to the surface of the module, but also play the role of electrical insulation, which is convenient for installing a heat sink 6 (see Figure 6 As shown in the heat sink 6). Since the two semiconductor power devices Q1 and Q2 are preferentially soldered to the high-density circuit board, the back height of the semiconductor power devices Q1 and Q2 is not easy to be flush, so the thickness of the material with high thermal conductivity needs to be relatively thick, such as 50um or even more than 200um. Therefore, the top surface of the two semiconductor power devices Q1 and Q2 is connected to the DBC, and it is best to have only one large-area PAD, such as the drain or source, to reduce the requirements for connection accuracy.

[0126] like Figure 5C As shown, in electronic circuits, different types of semiconductor chips are usually required, especially vertically structured semiconductor chips, whose thickness is closely related to the performance of the semiconductor chips. In order to assemble semiconductor chips of different thicknesses, in this embodiment, protrusion structures 131 and 132 (such as copper pillars) of different thicknesses are used to achieve this. In other embodiments, such as Figure 5D As shown, the lower metal layer 5 of the insulating heat conducting board DBC is partially thinned to adapt to semiconductor chips of different thicknesses. In addition, because the height of the protruding structure 131 or 132 on the surface of the semiconductor chip is usually between 50um and 300um, and the thickness of the metal layer of the DCB is between 100um and 500um, the range of the thickness tolerance absorbed by the protruding structure and the metal layer is limited. Figure 5EIn the embodiment shown, the problem of thickness tolerance is solved by implanting metal balls 134 on the surface of the semiconductor chip. The diameter of the metal ball 134 is between 100um and 1mm, and the diameter can be adjusted according to actual needs, so that the ability to absorb thickness tolerance is further enhanced. In this embodiment, the material of the metal ball 134 can be metal, such as copper, iron, nickel, iron-nickel alloy or solder ball. These metal balls 134 not only have different resistivities, but also have different magnetic conductivity properties, which can be used to achieve different resistances and inductances. Furthermore, the same semiconductor chip can be equipped with different alloy balls at different positions to match the requirements of different parasitic parameters (i.e. resistance or inductance) of the local area of ​​the same semiconductor chip, so as to improve the consistency of dynamic and static characteristics at different positions inside the same semiconductor chip. Furthermore, the metal balls 134 of different materials can be used to arrange them differently between multiple parallel semiconductor chips, so as to improve the consistency of dynamic and static characteristics between multiple parallel chips. In addition, the electrodes on one side of all semiconductor chips in the module can be realized and connected to the outside by metal balls, which can further reduce the cost and development cycle of directly forming copper pillars on the chip surface metallization. Therefore, this embodiment can further shorten the product development cycle and reduce costs.

[0127] like Fig. 5F In order to further reduce the parasitic capacitance between the module and the heat sink, the parasitic capacitance causes common-mode noise under the jump voltage, so the electrostatic potential electrode source Source of the semiconductor chip is connected to the wiring layer of DBC. At the same time, in order to reduce the thermal resistance from the semiconductor chip to the top surface of DBC, it is necessary to increase the connection area between the semiconductor chip and DBC as much as possible. Taking Q2 as an example, the copper plating area corresponding to the source Source of Q2 and DBC needs to be as large as possible. The gate Gate and source Source of Q2 are located on the top surface of the semiconductor device Q2. When the semiconductor chip is assembled with DBC, the gate Gate is easily short-circuited with the source Source. Therefore, glue is applied to the connection solder joints between the gate lead 139 and the gate to protect the solder joints between the gate lead and the gate from being affected by the assembly of the source Source.

[0128] In this embodiment, the high-frequency capacitor 1 is disposed on the first surface 201 of the circuit board 2, but it is not limited thereto. The high-frequency capacitor 1 can also be disposed on the second surface 202 of the circuit board 2. The gate can also be disposed on the DBC by welding, such as Figure 5GHowever, the thickness of the lower metal layer 5 and the upper metal layer 4 of the DBC cannot be too thick, for example, thinner than 0.1 mm, which will reduce the horizontal heat diffusion capacity of the plane direction formed by the x-axis and y-axis of the two metal layer surfaces of the DBC, and it is necessary to increase the heat dissipation capacity of the vertical heat dissipation channel of the semiconductor chip in the z-axis direction. In order to better solve the heat dissipation problem in the vertical direction, as Figure 5G As shown, a heat-conducting column 135 is provided on the outer surface of the insulating heat-dissipating layer 3 (i.e., the upper metal layer 4) corresponding to the semiconductor chip in the vertical direction, which can be used for liquid cooling or for use in a liquid cooling device, such as Figure 5H As shown. Because the heat conduction in the horizontal direction can be ignored, the number of heat-conducting pillars 135 can be reduced at the position outside the horizontal plane projection of the semiconductor chip, and it is only used to adjust the direction of the liquid flow; it is even unnecessary to set the heat-conducting pillars 135; that is, the number density of the heat-conducting pillars 135 within the horizontal plane projection of the semiconductor chip is greater than the number density of the heat-conducting pillars 135 outside the horizontal plane projection of the semiconductor chip. Because the copper layer of the upper metal layer 4 and the lower metal layer 5 is very thin, the insulating heat-conducting layer 3 can only be made of copper electroplated on the surface of the insulating heat-conducting material.

[0129] In another embodiment, if Fig.5I As shown, the hybrid substrate 3a includes two thermally conductive materials. The projected portion of the semiconductor chip on the hybrid substrate 3a (i.e., the high thermal conductivity area 137) can be made of high thermal conductivity material, and the remaining portion of the hybrid substrate 3a (i.e., the low thermal conductivity area 138) can be made of low thermal conductivity material with relatively low thermal conductivity. Furthermore, the thermal conductivity of the high thermal conductivity material is greater than twice the thermal conductivity of the low thermal conductivity material. Specifically, the high thermal conductivity material can be high thermal conductivity particles, such as an array of high-purity diamond particles, especially an array formed by mixing neatly arranged diamond particles with ceramic materials. Because the thermal conductivity of diamond is dozens of times that of ceramic materials, as long as the proportion of diamond in this area is greater than 10% or greater than 20%, the equivalent thermal conductivity can be greatly improved. The structure of the hybrid substrate 3a disclosed in this embodiment is applicable to all embodiments disclosed in the present invention, and is also applicable to thick copper DBC solutions and other traditional packaging solutions. On the other hand, because this embodiment is a three-dimensional structure, that is, one side of the insulating heat conductive plate is used for heat dissipation, and the other side is used for electrical connection, it is impossible to upgrade the heat dissipation capacity by double-sided heat dissipation. It is necessary to further process the heat dissipation surface to improve the heat dissipation capacity, such as Fig.5I The Die Bond of the semiconductor chip shown can also use a sintered silver process to improve the high junction temperature operation capability and further improve the heat dissipation capability.

[0130] An application example of the hybrid substrate 3a is as follows: Figure 5JAs shown, the hybrid substrate 3a may also include an upper metal layer 4 and a lower metal layer 5, wherein the bottom surface of the lower metal layer 5 is connected to the power semiconductor chip Q10 with high thermal density via a high thermal conductivity interconnect 144, and the high thermal conductivity interconnect 144 may be sintered silver, and the power semiconductor chip Q10 with high thermal density is fixed to the hybrid substrate 3a by sintering; the top surface of the hybrid substrate 3a is connected to the thermally conductive column 135 via the high thermal conductivity interconnect 144, and the thermally conductive column 135 is generally made of copper material, and its thermal conductivity is 400W / (m·K). When a high thermal conductivity hybrid substrate is used (the thermal conductivity of diamond is higher than 2000W / (m·K)), and because the height of the thermally conductive column is greater than the thickness of the hybrid substrate, the copper thermally conductive column becomes a bottleneck for heat dissipation. Therefore, in Figure 5J In the illustrated embodiment, the thermally conductive column 135 is made of a carbon fiber tube or a composite. The composite here can be a metal shell 143 with high thermal conductivity coated with an ultra-high thermal conductive filler 145. The metal shell 143 can be made of copper material, and the ultra-high thermal conductive filler 145 can be a carbon fiber tube, a graphene sheet or a phase change liquid (heat pipe). Figure 5J The structure shown conducts the heat generated by the high heat density power semiconductor chip to the outer surface of the module, and then is conducted to the surface of the heat-conducting column by a plurality of high thermal conductivity heat-conducting columns 135. The surface of the heat-conducting column exchanges heat with the cooling liquid to achieve efficient heat dissipation. The hybrid substrate disclosed in the present invention can be applied to all embodiments disclosed in the present invention, and can also be applied to other embodiments, as long as the above technical features are met.

[0131] In addition, the present invention also discloses an embodiment of connecting multiple chips in parallel under high power application, such as Figure 5K As shown. Traditionally, multiple chips are connected in parallel, and the packaging structure of multiple chips and their drivers is usually arranged on the same plane, so that the distance between the driver and each chip is unequal, so that the driving signal received by each chip is inconsistent, resulting in uneven current after multiple chips are connected in parallel. The present invention discloses a three-dimensional packaging of multiple chips in parallel, which can solve the consistency problem of multi-chip parallel driving. Figure 5K As shown in the bottom view and side view, four chips are arranged in a 2x2 arrangement on the first surface 201 of the multilayer circuit board, and the gates of each semiconductor chip are arranged close to each other; the driver is arranged on the second surface 202 of the multilayer circuit board, and the lower metal layer 5 of the DBC is attached to the top surface of the four chips. Figure 5KIn the bottom view schematic diagram shown, the multilayer circuit board 2 is removed, and the driver Driver is set at the center of the four chips arranged in 2x2, that is, the projection of the driver on the first surface and the projection of each semiconductor chip on the first surface partially overlap, so that the routing distance between each drive output pin and the gate Gate of the corresponding chip is equal and the distance is the shortest; the wiring layer of the multilayer circuit board 2 can also be evenly wired to improve the consistency of each drive circuit; current equalization between each chip can be achieved, and high-speed driving can also be achieved.

[0132] Combined with the above-mentioned optimized heat dissipation structure, high-frequency and high-power applications can be realized. A large current driver Driver can be used to drive multiple semiconductor chips, or each semiconductor chip can be driven by its own driver. For the solution with multiple drivers, the current of each semiconductor chip can also be sampled at the same time, and the sampled current information can be fed back to the driver, and the drive of each semiconductor chip can be adjusted in real time and differentiated to achieve active current sharing control. The multiple semiconductor chips here are not limited to four, but can also be three or more, as long as the projection of the driver on the first surface 201 of the multi-layer circuit board and the projection of each semiconductor chip on the first surface 201 of the multi-layer circuit board partially overlap.

[0133] As above Fig. 5F As shown, by staggeredly welding the pins of two semiconductor chips, for example, the source of one semiconductor chip and the drain of another semiconductor chip are set on the circuit board, and the drain Drain (static potential) of one semiconductor chip and the source Source (static potential) of another semiconductor chip are set on the lower metal layer 5, low common-mode interference is achieved, which greatly reduces the demand for common-mode inductance in system applications, reduces costs, and reduces volume. Figure 5L The embodiment shown discloses another technical solution to achieve the same effect. In this embodiment, the semiconductor wafer uses an LD MOS whose substrate potential can be flexibly set, such as a low-voltage GaN MOS, or a GaN MOS with an electrically insulating material such as ceramic (sapphire) as a substrate. The substrate of this type of semiconductor wafer is thermally connected to the lower metal layer of the DBC, and the pins thermally connected to the lower metal layer are set to an electrostatic potential, such as Vbus+ or Vbus- or power GND, etc.

[0134] The high-frequency high-power packaging module disclosed in the embodiment of the present invention also includes a plastic package 7, the thinnest of which can be controlled between the upper surface of the insulating heat conductive plate DBC and the first surface 201 of the multilayer circuit board 2, and achieves safety insulation capability. Figure 6As shown, the plastic package 7 fills the gap area between the first surface 201 of the multilayer circuit board and the upper surface of the insulating heat conductive plate, the upper surface of the insulating heat conductive plate is exposed, the second surface 202 and the side edge of the multilayer circuit board are exposed, and the second surface 202 or the side edge of the multilayer circuit board is provided with an external electrode 11, and the external electrode 11 is electrically connected to the power conversion bridge arm. This embodiment greatly improves the mechanical strength and can support thinner DBCs, such as 0.4mm or even less insulation thickness. Figure 1 The silicone package, with a thickness of at least 0.6mm, can achieve lower thermal resistance, down more than 30%, and support greater power.

[0135] The front side (i.e., the bottom side) of the semiconductor power device of the high-frequency, high-power packaging module disclosed in the embodiment of the present invention is electrically connected to the first surface 201 of the multilayer circuit board, and the back side (i.e., the top side) of the semiconductor power device is thermally or electrically connected to the lower surface 302 of the insulating heat-conducting plate. The semiconductor power device and the DBC are thermally interconnected preferably by welding. Therefore, the back side of the semiconductor power device is preferably metallized.

[0136] The high-frequency capacitor 1 is electrically connected to the first surface 201 of the multilayer circuit board or the second surface 202 of the multilayer circuit board or the lower surface of the insulating heat-conducting plate, and at least one electrode of the high-frequency capacitor 1 is electrically connected to at least one electrode of at least one semiconductor power device through an inner electrical connection layer. It should be noted that the bottom surface and top surface of the semiconductor power device referred to in the present invention are only relative concepts, and do not specifically refer to a certain surface as the front surface or the back surface.

[0137] As an example, Figure 6 As shown, since the present invention pursues ultra-thinness, and uses the second surface 201 of the multi-layer circuit board as a surface mount pad (SMD PAD), which is electrically interconnected to the customer's mainboard 8, the thinnest overall system of the customer is achieved, or the module of the present invention occupies as little space as possible in the customer's system. When the module thickness L1 is thinner than a certain degree, such as 5mm, and its thickness is thinner than the creepage distance required for safety insulation (usually greater than 6mm), the radiator 6 can be in contact with the insulating heat sink DBC only to ensure the heat dissipation effect, and there is an air gap of not less than 1mm between the plastic packaging material and the edge of the module to increase the insulation distance L2, that is, there is an air gap L3 between the upper surface of the plastic packaging body 7 and the radiator 6, and the air gap L3 is greater than 1mm. In other embodiments, an electrical insulating sheet 9 can be provided between the upper surface of the plastic packaging body 7 and the radiator 6 to increase the insulation effect, such as Figure 6 shown.

[0138] In order to achieve smaller loop inductance, it is advisable for high-frequency capacitor 1 to be integrated on the module, and high-frequency capacitor 1 should be as close to semiconductor power devices Q1 and Q2 as possible. In practical applications, there are two reasons why high-frequency capacitors and semiconductor power devices are not easy to get close to each other. First, high power often means high voltage applications above 200V, such as 400V Vbus, which requires a 630V ceramic capacitor. Capacitors for such high-voltage applications often require a higher height to achieve the required capacity, such as 1mm and above. Secondly, in order to achieve lower thermal resistance, the thickness of semiconductor power devices Q1 and Q2 should be as thin as possible, which causes high-frequency capacitor 1 to be blocked by DBC. Here, high-frequency capacitor 1 is taken as an example, but in fact it also applies to other higher components.

[0139] like Fig. 7A As shown, the higher components are soldered on the multi-layer circuit board 2. In order to help the semiconductor power devices Q1 and Q2 to diffuse heat and increase the heat capacity, and enhance the transient and steady-state thermal management capabilities, the DBC is covered with thick copper on both sides, namely the upper metal layer 4 and the lower metal layer 5 of the insulating thermal conductive layer 3. Then, the lower metal layer 5 above the high-frequency capacitor 1 can be thinned or removed to make room so that the high-frequency capacitor 1 can be placed between the insulating thermal conductive layer 3 and the multi-layer circuit board 2. That is, the high-frequency capacitor 1 is electrically connected to the first surface 201 of the multi-layer circuit board, and the height Hc of the high-frequency capacitor 1 meets the following conditions:

[0140] H1≤Hc<H2;

[0141] Among them, H1 is the distance from the first surface 201 of the multilayer circuit board to the top surface of the semiconductor power devices Q1 and Q2, and H2 is the distance from the first surface 201 of the multilayer circuit board to the lower surface 302 of the insulating thermal conductive layer; the insulating thermal conductive plate extends to the top of the high-frequency capacitor 1, and the lower metal layer 5 located between the high-frequency capacitor 1 and the insulating thermal conductive plate is isolated from the high-frequency capacitor 1 by thinning or removal.

[0142] like Figure 7B As shown, the higher component is welded on the multilayer circuit board 2. When the height Hc of the high-frequency capacitor 1 is higher than the height between the lower surface 302 of the insulating heat-conducting layer and the first surface 201 of the multilayer circuit board, the entire insulating heat-conducting plate can be retracted so that only the plastic encapsulation material is between the top of the high-frequency capacitor 1 and the upper surface of the module. The thickness of the plastic encapsulation material is preferably above 0.4 mm to ensure electrical insulation strength. That is, the high-frequency capacitor 1 is electrically connected to the first surface 201 of the multilayer circuit board, and the height Hc of the high-frequency capacitor 1 meets the following conditions:

[0143] H2≤Hc<H3;

[0144] H2 is the distance from the first surface 201 of the multilayer circuit board to the lower surface 302 of the insulating thermal conductive layer 3, and H3 is the distance from the first surface 201 of the multilayer circuit board to the upper surface 301 of the insulating thermal conductive layer. The insulating thermal conductive plate 3 is only located above the semiconductor power devices Q1 and Q2.

[0145] like Figure 7C As shown in the figure, since the high-frequency capacitor 1 is highly limited, in order to pursue the ultimate thermal performance, the thickness of the insulating heat conductive plate DBC is made as thin as possible. Figure 7B The thickness of the plastic encapsulation material on the high-frequency capacitor 1 may not meet the safety requirements, and may even be exposed. Figure 7C The solution is to place the high-frequency capacitor 1 on the second surface 202 of the multi-layer circuit board. Not only can the loop be reduced, but also the size of the module can be reduced. That is, the high-frequency capacitor 1 is electrically connected to the second surface 202 of the multi-layer circuit board, and the two electrodes of the high-frequency capacitor 1 are electrically connected to the inner electrical connection layer and the first surface 201 of the multi-layer circuit board through the vertical electrical connection path 130.

[0146] Fig.7D and Fig. 7E In the scheme, these higher components are welded on the lower surface 302 of the insulating heat-conducting layer, and the corresponding part of the insufficient space is thinned or removed in the local area of ​​the multilayer circuit board 2. The lower metal layer 5 of the insulating heat-conducting layer 3 can also be thinned. That is, the high-frequency capacitor 1 is electrically connected to the lower surface 302 of the insulating heat-conducting layer, at least one electrode of the high-frequency capacitor 1 is electrically connected to the inner electrical connection layer through an electrical connector (not shown in the figure), and the height Hc of the high-frequency capacitor 1 meets the following conditions:

[0147] H1≤Hc<H4;

[0148] Among them, H1 is the distance from the first surface 201 of the multilayer circuit board to the top surface of the semiconductor power device, and H4 is the distance from the second surface 202 of the multilayer circuit board to the lower surface 302 of the insulating thermal conductive layer; the multilayer circuit board 2 located below the high-frequency capacitor 1 is isolated from the high-frequency capacitor 1 by thinning or removal.

[0149] As an example, Figures 8A to 8FAs shown, in high-frequency situations, the internal circuit of the module should be small, but due to limited space and limited internal capacitance, the upper capacitor of the customer's mainboard 8 and the high-frequency capacitor 1 inside the module need to be placed close to each other. Therefore, modules for different application scenarios, including modules with different powers and different internal circuits, require the most optimized packaging form and pin arrangement, which means that there will be a wide variety of packages. Plastic packaging is different from silicone packaging, and the cost of the mold is very high. This embodiment discloses a method for making a high-frequency, high-power packaging module to effectively circumvent the problem of very high mold costs. It can not only retain the performance of the finished module of the present invention, but also reduce costs by sharing one mold for multiple types of modules, and can also achieve automated mass production to further reduce costs. The steps are as follows:

[0150] Step 1 Sa1: Place the semiconductor power devices Q1, Q2 and other necessary components of multiple modules on the corresponding partitions of the PCB Panel; if necessary, the PCB can be double-sided SMD components, such as Fig. 8A shown.

[0151] Step 2 Sa2: Optionally, pre-encapsulate the area between the semiconductor power devices Q1, Q2 and the first surface 201 of the multilayer circuit board to form a thermal resistance electrical connection layer 12 to enhance the strength of the semiconductor power devices Q1, Q2 and eliminate bottom bubbles, such as Figure 8B shown.

[0152] Step 3 Sa3: Bond / weld the DBC of each module to the corresponding semiconductor power device Q1, Q2Top surface; if Fig.8D and Fig. 8E and Fig.29C If the DBC is thermally connected to the semiconductor power devices Q1 and Q2, the necessary components such as high-frequency capacitor 1 and common-mode suppression capacitor 24 are first soldered, such as Figure 8C shown.

[0153] Step 4 Sa4: The periphery of the PCB Panel is used as a plastic sealing area to prevent the plastic sealing from overflowing, and the upper part of the PCB is effectively plastic sealed to form a plastic sealing body 7, such as Fig.8D shown.

[0154] Step 5 Sa5: Optionally, polish one side of the upper metal layer 4 of the DBC to remove the overflow glue, improve the flatness of the insulating heat conducting plate DBC, reduce the thickness of the heat dissipation glue installed later, improve the thickness consistency of each module, and reduce the thickness of the heat dissipation glue installed later for multiple modules, such as Fig. 8E shown.

[0155] Step 6: Cut and separate each module from the Panel. Fig.8F shown.

[0156] The module made by this embodiment or in the process of making the module has a feature that the cutting and separation can make the periphery of the module side and the side of the plastic package 7 flush with the side of the multilayer circuit board. Since a large panel is cut into multiple modules, as long as the internal size of the large panel meets the size of the combination of multiple modules, the same mold can be used, that is, one mold can make multiple types of modules.

[0157] In other embodiments, Fig. 9 As shown, the semiconductor power device can be embedded in a multi-layer circuit board 2, and its electrodes 400 are led out through vias and electroplating, and then electrically interconnected with the insulating heat conductive plate and the pins. This can save welding and wire bonding processes, and has higher reliability.

[0158] As an example, Fig.10 As shown, for planar devices such as GaN, the top surface electrode of the semiconductor power device often needs to be connected to a suitable potential, such as its source or gate. Since its top surface is connected to the DBC, the top surface electrode of the semiconductor power device needs to be electrically connected to the first surface 201 of the multilayer circuit board through the lower metal layer 5 and the conductive component 10 in sequence, connecting it from the DBC to the multilayer circuit board 2. However, this electrical connection is only for the semiconductor power device to obtain the necessary potential, and no large current is required, so thick copper does not need to be laid on the DBC.

[0159] When using a vertical device such as SiC, its power electrodes are placed on the upper and lower surfaces of the device, and its top surface electrode is often an electrostatic potential electrode. Therefore, its drain Drain needs to be electrically connected to the first surface 201 of the multi-layer circuit board through the lower metal layer 5 and the conductive component 10, and the lower metal layer 5 is a thick copper layer.

[0160] As an example, refer to Figure 5A As shown, the height of the conductive component 10 between the multilayer circuit board 2 and the DBC, as well as the height precision of the semiconductor power devices Q1 and Q2, are very high, which will cause high cost and complex process problems. Since it is only for the purpose of stabilizing the electrical properties of the semiconductor power device base, a better approach is to connect the base to the required electrode, such as the source, through the conductive through hole inside the semiconductor power device, so that the challenges and costs at the packaging level can be eliminated.

[0161] As an example, Fig.11As shown, due to the trend of electric vehicles, the application of SiC / GaN in automotive applications is becoming more and more popular, especially in the drive of electric motors. According to the particularity of the car, there is often acceleration in seconds, that is, high power output in seconds. Then, in the module, it is most effective and economical to set a heat capacity in seconds for the semiconductor power devices Q1 and Q2. Since the semiconductor power devices Q1 and Q2 are very thin, their lateral thermal resistance is very large, and it is difficult to do anything. The top surface of the semiconductor power devices Q1 and Q2 has been connected to DBC. Under the premise that the packaging stress allows, the thickest DBC copper will be used as much as possible to obtain low thermal resistance and high thermal capacity in seconds. Therefore, opportunities can only be found from the TOP layer of the semiconductor power devices Q1 and Q2. However, due to the requirements of electrical routing, the surface copper thickness of the TOP layer is limited, and it is difficult to obtain a sufficiently large heat capacity in seconds. Therefore, the present invention chooses to bury a low thermal resistance and large heat capacity object, such as thick copper, in the inner electrical connection layer of the circuit board directly below the TOP surface of the semiconductor power devices Q1 and Q2. Through the high-density arrangement of high-heat-capacity components 13, the first surface 201, the second surface 202 of the multilayer circuit board 2 and the inner electrical connection layer are interconnected, and low thermal resistance interconnection is achieved. This not only achieves high-precision electrical interconnection of the surface layer, but also enables the semiconductor power devices Q1 and Q2 to obtain additional low thermal resistance and high thermal capacity, providing support for the transient high-power impact of the module.

[0162] like Figure 6 As shown, the module is installed on the customer's mainboard 8 through the SMD process. However, this also has disadvantages in some applications. For example, when multiple modules are installed on the same heat sink 6 at the same time, due to the module thickness tolerance and the SMD process tolerance, the heat dissipation surface heights of multiple modules are often different, and thicker thermal grease is required to buffer the tolerance. Thick thermal grease increases the thermal resistance of the module and limits the power. Therefore, an embodiment is required to buffer the tolerance.

[0163] As an example, Figures 12A to 12D As shown in FIG. 1 , a buffer external pin 14 (Pin) is implanted on the module SMD PAD. Fig. 12A It is a direct plug soldering pin, which is soldered to the customer's mainboard 8 and electrically connected by solder; Fig. 12B For direct insertion of crimp pins, the external pins 14 are crimped into the through holes of the customer's mainboard 8, and the contact force is formed by the buffering elasticity of the pin to make an electrical connection; Fig. 12C For surface contact crimping pins, the elastic Pin is crimped to the SMD Pad of the customer's mainboard 8; Fig.12D The pins are soldered to the surface contacts and the elastic pins are soldered to the SMD pad of the customer's mainboard 8. When installing multiple modules, the thickness tolerance is buffered by the elasticity of the pins or the difference in insertion depth, so that the thinnest thermal grease can be used to obtain the lowest thermal resistance and ensure maximum power.

[0164] As an example, FIG. 13A to FIG. 13EAs shown, the required electrodes are guided to the side edge of the multilayer circuit board 2 inside the multilayer circuit board, that is, the outer pins of the multilayer circuit board on the side of the module are formed, and then the buffer outer pins 14 are implanted. Fig.13A It is a direct plug soldering pin, which is soldered to the customer's mainboard 8 and electrically connected by solder; Fig. 13B It is a direct-insert crimp pin, which is crimped into the PCB through-hole, and relies on the buffer elasticity of the pin to form contact force and make electrical connection; Fig. 13C For surface contact crimping pins, the elastic Pin is crimped to the SMD Pad of the customer's mainboard 8; Fig.13D The surface contact soldering pins are soldered to the SMDPad of the customer's mainboard 8. When installing multiple modules, the thickness tolerance is buffered by the elasticity of the pin or the difference in insertion depth, so that the thinnest thermal grease can be used to obtain the lowest thermal resistance and ensure maximum power.

[0165] As an example, Figures 13A to 13D As shown, in order to reduce the size of the plastic package 7 of the module as much as possible and improve the production capacity, the mounting hole 601 for fixing the module to the radiator 6 may not be set in the plastic package 7. Then, an insulating fixing frame 15 can be added to the plastic package 7. The cross-sectional view of the insulating fixing frame 15 is L-shaped, and one side of the L-shape is glued to the side of the plastic package 7 by glue for mechanical reinforcement and electrical insulation reinforcement. The other side of the L-shape has a screw mounting hole 601 for mounting the fixing frame 15 to the radiator 6.

[0166] As an example, Fig.13E As shown, a Z-shaped elastic insulating fixed frame 15 is used, one end of the elastic insulating fixed frame 15 is a partial fixed frame 151 of insulating material, which is pressed on the outer edge of the module multilayer circuit board 2; the other end of the elastic insulating fixed frame 15 is a metal spring 16 (i.e., elastic member), which is pressed on the heat sink 6 by screws; the metal spring 16 is molded in the partial fixed frame 151. The pressure of the metal spring 16 is transmitted to the module through the partial fixed frame 151 to form an installation force. The plastic part ensures the insulation requirements.

[0167] As an example, Fig.13F As shown, an L-shaped insulating fixing frame 15 is used. The insulating fixing frame 15 has a certain elasticity to balance the thickness tolerance balancing force. One end of the insulating fixing frame 15 is pressed on the outer edge of the module circuit board, and the screws lock the insulating fixing frame 15, the module, and the heat sink 6 together to form a balanced pressure.

[0168] Fig.13E and Fig.13F It also shows Figure 7CThe output method of the technical solution shown is to make full use of the gap between the insulating fixing frame 15 and the second surface 202 of the multilayer circuit board, and set SMD components, such as Cbus, Driver and other necessary components, on the second surface 202 of the multilayer circuit board. It not only makes full use of the space, but also greatly reduces the module size, reduces the cost and improves the yield rate. Fig.13E and Fig.13F The buffer external pin 14 of the illustrated solution is electrically connected to an external electrode disposed on the second surface 202 of the multilayer circuit board. It should be noted that the buffer external pin 14 may also be directly electrically connected to the circuit structure inside the circuit board.

[0169] In the previous embodiments, the module is implanted with a buffer external pin 14, and the simplest method is to reflow and weld it, whether on the side or the bottom. However, since the plastic package 7 is hard-cured, all different materials need to be hard-connected together. The internal stress of the plastic package 7 caused by reflow can easily destroy the structural stability and cause reliability problems. This embodiment proposes a technical solution of implanting the pin before plastic packaging, which effectively solves this problem. The detailed technical solution is shown in the figure. FIG. 14A to FIG. 14E shown.

[0170] Step 1 Sb1: Reserve soldering space at the pin placement on the PCB Panel. Fig.14A shown.

[0171] Step 2 Sb2: Mechanically implant the Pin into the through hole 17 of the circuit board. It is preferred that the top of the Pin does not exceed the first surface 201 of the multilayer circuit board. Fig. 14B shown.

[0172] Step 3 Sb3: Before reflowing the SMD components on the multi-layer circuit board 2, place enough solder paste on the top of the pin. After reflowing, the solder not only reliably connects the pin to the PCB, but also fully fills the gap between the pin and the multi-layer circuit board to prevent overflow during plastic sealing. Fig. 14C shown.

[0173] Step 4 Sb4: Reflow SMD soldering other components on multilayer circuit board 2. Fig.14D shown.

[0174] Step 5 Sb5: Plastic encapsulation to form a plastic encapsulation body 7, such as Fig.14E As shown, the subsequent process is FIG. 8A to FIG. 8F similar.

[0175] At this point, each implanted buffer external pin 14 can refer to Fig. 12A Direct welding method, Fig. 12B Direct plug-in crimping method shown, Fig. 12CThe surface crimping method shown and Fig.12D The surface welding method shown is used to make a fixed electrical connection with the customer's mainboard 8. The plastic package 7 does not need to be subjected to high temperature reflow, making the module more reliable. In addition, the pin can be designed according to actual needs, thereby reducing the lateral diffusion resistance of the internal circuit of the multilayer circuit board 2, greatly improving the utilization rate of the multilayer circuit board and the electrical performance of the module.

[0176] like FIG. 15A to FIG. 15D As shown, through the rewiring structure 18, each pin is uniformly output to the required position, which is convenient for customers to use. At the same time, the pin output flexibility of the circuit board inside the module is taken into account to ensure the internal performance of the circuit board.

[0177] As an example, FIG. 16A to FIG. 16F As shown, Fig.13F and Fig.13F A derivative of the solution. In order to better improve the performance of the module, it is often necessary to place Cbus, drive or control IC and its peripheral circuits nearby. If they are placed on the same surface of the multi-layer circuit board 2 with the semiconductor power devices Q1 and Q2, firstly, the area of ​​the circuit board will increase, thereby increasing the volume of the module; secondly, it will cause the parasitic parameters in the high-frequency circuit to increase, affecting the high-frequency performance of the module; thirdly, the temperature of the IC and capacitor will be high, affecting the performance and reliability of other components in the module. In this embodiment, some components, such as Cbus, drive IC or control IC and its peripheral circuits, are placed on the second surface 202 of the multi-layer circuit board, away from heat sources, thereby solving the above three problems and simplifying the convenience of customers using the module. Fig.16A , use packaged IC and other components to directly SMD to the second surface 202 of the multilayer circuit board; Fig. 16C The semiconductor power devices Q1 and Q2 are Die Bonded on the second surface 202 of the multilayer circuit board, and then wired to the PAD of the second surface 202 of the multilayer circuit board through wirebond, and then fixed and protected by COB or other processes; or Fig. 16B After the components are placed and interconnected on the second surface 202 of the multilayer circuit board, the entire surface is plastic-sealed, filled with silicone, COB or sprayed with three-conformal paint for enhanced protection. This is because without protection, whether it is waterproof and dustproof, or electrical withstand voltage insulation spacing, there will be a great sacrifice, affecting the module size and reliability.

[0178] Fig.16D for Fig. 16CThe improvement of the above method is to add a filling component (i.e., a second surface protection component) to the outer edges of both sides of the module PCB. The filling component includes a shell 19, a sealant 20, and a filling body 21. The shell 19 is fixed and covered on the second surface 202 of the multilayer circuit board by the sealant 20. The filling body 21 is filled between the shell 19 and the second surface 202 of the multilayer circuit board. The components on the second surface 202 of the multilayer circuit board are within the range defined by the filling component, so the filling body protects the electronic components. The filling body here can be silicone or plastic packaging material.

[0179] Fig.16E and 16F for Fig.16D Two different implementations of . Fig.16E It is a structural diagram formed by the silicone process flow for the independently formed plastic-encapsulated module. The so-called independently formed plastic-encapsulated module refers to a single module obtained by dividing the board after plastic encapsulation, and the second surface 202 of the multi-layer circuit board in the module has been installed with corresponding electronic components, such as resistors, capacitors, driver IC pins, etc.

[0180] First, an independently formed packaging module is completed; a sealant 20 is set at the boundary of the range to be filled with silicone; the housing 19 is installed, and the housing 19 is fixed to the module through the sealant 20; then silicone is poured, and the relevant electronic components are protected by silicone inside the module housing 19 to form a silicone filling body 21. Since an independently formed plastic-encapsulated module is installed, the filling component can be provided with screw holes, taking into account the module's installation function for the radiator 6.

[0181] Fig.16F It is a structural diagram of a multi-module plastic-sealed panel that has been plastic-sealed but not yet divided into boards. The corresponding electronic components of each module, such as resistors, capacitors, driver IC pins, etc., have been installed on the second surface 202 of the multi-layer circuit board of the multi-module plastic-sealed panel. First, complete the multi-module plastic-sealed panel; set sealant 20 at the boundary of the silicone filling range in each module; install the corresponding shell 19 of each module, and the shell 19 is fixed to the module through the sealant 20; fill each module area with silicone, and protect the relevant electronic components with silicone inside the module shell 19 to form a silicone filling body 21; then divide the boards. The advantage of this is that the efficiency of silicone filling can be greatly improved. However, the size of the filling component is smaller than the module, so it is not easy to independently assume the function of fixing the finished module to the radiator 6. Fig.16F The solution is suitable for the screw holes for fixing the module to the heat sink 6 to be arranged on the plastic package body 7, that is, a screw hole is arranged on each side of the plastic package body 7, which can be a full hole, or a half hole to save space.

[0182] Fig. 16BThe pins are connected through the side of the multi-layer circuit board, and the current is collected horizontally through the multi-layer circuit board 2, resulting in a large current loss. As an embodiment of double-sided plastic packaging, a copper column is embedded perpendicular to the plastic packaging body 7, and a via hole is formed on the embedded copper column, and the top of the copper column is used as a pad; or a via hole and a pad are formed by electroplating; or a copper column is embedded, and then a large-area pad is electroplated on the top.

[0183] like Fig.17A , welding the pins on a plane, the welding strength is a great challenge, or burying the copper pillar 602 in the plastic package 7 or the silicone filler, and then electroplating the surface of the plastic package 7 near the copper pillar 602 to form a pad 603, which will only increase the cost and the process is relatively complicated. Fig. 17B and Fig. 17C A large deep countersunk hole 611 plus a plurality of small vias 612 are used. The large deep countersunk hole is formed by a silicone filler or a plastic package body concave toward the second surface of the circuit board. The surface of the large deep countersunk hole and the surface of the adjacent plastic package body 7 or silicone filler are electroplated to form a pad. A plurality of small vias 612 are arranged at the bottom of the large deep countersunk hole 611, and the pad and the circuit board are electrically connected to form a multiplexed pad for welding of a large current power pin 621. Since the small vias 612 are numerous and have a short stroke, the resistance is small; the large deep countersunk hole 611 has a large surface area and a large diameter, the pin welding strength is large, and the resistance is small.

[0184] like Fig.17D , as a new pin design for the module. Because there are many signal pins 622, in the previous embodiments, the signal pins 622 often require customers to use through holes. If the spacing is large, the floor space is large, and if the spacing is small, it is not easy to align during installation. In this embodiment, the signal pins 622 are designed to be pressure-contacted, and they are in contact with the flat pads on the surface of the customer's motherboard, while the power pins 621 still use through-hole design to ensure high current capacity. In this way, very convenient installation can be achieved in a very small size.

[0185] like Fig.17E , the power pin 621 is set as a thread, and a screw is used to guide it to a distant place through a cable. The signal pin 622 is guided to a distant place through a cable. This is because in high-power applications, the magnetic components and capacitor components are very large, and it is difficult to match their electrical connection positions with the power module with their sizes, which brings great challenges to system design. This embodiment can ensure high frequency and high power of the module body while allowing the power pins and signal pins to be interconnected through cables.

[0186] As an example, Fig.18As shown, during the plastic encapsulation, the mold flow requires a certain gap to more reliably remove bubbles. If the semiconductor power devices Q1 and Q2 are directly soldered to the multi-layer circuit board of the module, because the metal layer on the surface of the semiconductor power devices Q1 and Q2 is very thin, usually thinner than 10um, it means that the gap between the semiconductor power devices Q1 and Q2 and the PCB is only less than 10um at the thinnest, and reliable exhaust cannot be caused, which will cause reliability problems such as insufficient withstand voltage. A feasible solution is to plant copper pillars 631 on the surface of the bottom surface electrode of the semiconductor power devices Q1 and Q2, and raise the above gap to more than 30um to help the mold flow to reliably exhaust. Another feasible solution is to first encapsulate the semiconductor power devices Q1 and Q2, such as the embedded process or fanout process, and the thick copper electrode formed by the encapsulation is used to raise the air gap using the thick copper on the surface of the encapsulation. The thick copper is preferably thicker than 30um. The top surface of the semiconductor power devices Q1 and Q2 is directly covered with copper over a large area to form a copper layer or a copper-clad layered electrode 632 formed by encapsulation to ensure that the thermal resistance of the top surface of the semiconductor power devices Q1 and Q2 is not significantly affected.

[0187] As an example, Figures 19A to 19D As shown, since some power devices such as GaN / SiC are normally on, such as GaN D Mode and SiC JFET. Such devices have better performance, cost and reliability advantages. However, since they are normally on, a low-voltage normally closed (Normal off) device such as low-voltage SiMOS or E-Mode GaN FET is usually required to be cascaded to form the semiconductor power devices Q1 and Q2 of the embodiment of the present invention. Due to the cascade structure, there are both power loops and drive loops. In order to obtain the best performance, both should be as small as possible.

[0188] A preferred embodiment is to cascade a normally-on third-generation semiconductor sub-power device Normal On GaN / SiC and a low-voltage normally-off semiconductor sub-power device Normal off SiMOS, and form semiconductor power devices Q1 and Q2 by stacking the normally-on third-generation semiconductor sub-power device and the low-voltage normally-off semiconductor sub-power device. That is, the drain of the low-voltage normally-off semiconductor sub-power device is directly welded to the source of the high-voltage device Source and then packaged. The top surface of the package body transfers the heat generated by the high-voltage device to the top surface of the package body through low thermal resistance, and leads out or interconnects each electrode and low loop inductance. In this way, both high power and high frequency can be achieved on the Normal On device.

[0189] As a further embodiment, at least one semiconductor power device is a normally-on power device Normal OnGaN / SiC, the normally-on power device is provided with a low-voltage normally-off semiconductor power device Normal off SiMOS, the normally-on power device is cascaded with the low-voltage normally-off semiconductor power device, the low-voltage normally-off semiconductor power device is provided on the second surface 202 of the multilayer circuit board, and the setting position of the low-voltage normally-off semiconductor power device corresponds to the position of the normally-on power device. That is, the low-voltage normally-off semiconductor power device and the normally-on power device are SMDed on the second surface 202 and the first surface 201 of the module multilayer circuit board respectively, and are interconnected through the circuit board. It is equivalent to realizing high-power and high-frequency interconnection without adding any process links. If the low-voltage normally-off semiconductor power device is Vertical MOS, Die Bond and Wirebond processes can be directly performed on the circuit board for interconnection. If the low-voltage normally-off semiconductor power device is LateralMOS, SMD can be performed directly on the circuit board to interconnect the low-voltage semiconductor power devices.

[0190] As an example, FIG. 20A to FIG. 20D As shown, a high-power converter often requires multiple power conversion bridge arms, that is, multiple high-current and high-frequency voltage output pins, such as Fig. 20A Pin A, Pin B and Pin C in the module. As the two pins of Vbus, Vbus+ and Vbus-, in order to reduce the demand for internal capacitors of the module, Vbus+ and Vbus- can be designed as a plurality of pairs, so that customers can place corresponding capacitors on the mainboard to minimize the loop inductance between the capacitors of the mainboard 8 and the high-frequency capacitor 1 inside the module.

[0191] like Fig. 20B As shown, Vbus+ and Vbus- are placed on one side as DC pins, and AC Pins A / B / C are placed on the other side, which is convenient for customers to set high-power bulk capacitors and AC magnetic or capacitive components.

[0192] Since the present invention can make the module size very small, in some high-voltage occasions, the spacing between the high-voltage power pins (DC pins, AC pins) is tight, and there is no space to place signal pins, such as drive signals. Due to the use of the multi-layer circuit board 2, the pin positions can be flexibly set, so Fig. 20C The embodiment can take into account the voltage resistance processing between the module pins and can also facilitate the layout when the customer uses it.

[0193] Fig. 20CThe power pins (DC pins Vbus+ and Vbus- and AC pins Pin A / B / C) are placed on the upper and lower sides respectively, and the signal pin 622 is placed in the middle of the two rows of power pins. In this way, the signal pin 622 will not occupy the spacing position of the power pins, so that the module size can be smaller by reducing the spacing, or the module can be adapted to higher working voltage scenarios by increasing the spacing.

[0194] When the customer uses it, the circuit board resources of the customer mainboard above and below the module can be used for the DC power pin and the AC power pin respectively, so that the high current path is unobstructed. The signal pin 622 can be led out from the left or right side of the module, such as Fig.20D As shown, the signal pin 622 and the power pin do not interfere with each other.

[0195] As a preference, the minimum spacing between the drive pin and the power pin must be more than 4mm to achieve a withstand voltage greater than 2KV. That is, the module integrates a driver IC that isolates the signal from the drive output. This allows customers to achieve the function of isolating the drive power semiconductor without the need for external isolation components. This is because traditional modules cannot achieve high power and isolation drive at the same time in such a small size scenario, such as 6cm×4cm area.

[0196] Preferably, multiple drive pins are pre-integrated into a strip to reduce the footprint and are compatible with customers soldering or connectors to lead out the signal pins 622. This is because the drive pin current is small, but if each signal pin 622 is planted separately, the area required for soldering is large, resulting in a larger spacing between the drive signal pins.

[0197] As a preferred embodiment, the signal pin 622 may be led out as a flat wire of a flexible circuit board, so as to achieve a smaller size and better anti-interference capability.

[0198] As an example, Fig.21A and Fig. 21B As shown in the figure, when the module is SMD pinned, the creepage distance is insufficient because the module is very thin. Fig.21A The area 641 shown in the figure is used to grind the plastic package body 7 into a step, or as shown in the figure Fig. 21B In the area 642 shown, a portion of the multilayer circuit board 2 and the plastic package 7 are ground away to form a step shape to increase the creepage distance.

[0199] As an example, Fig.22A and Fig. 22BAs shown, as customers' requirements for safety factors increase, the creepage distance d between the module power pin 621 and the heat sink 6 is required to be as large as possible, often reaching 6mm or even more than 12mm. If it is achieved by relying solely on the thickness of the module, it is obviously uneconomical and impractical. The present invention can shrink the power pin 621 inward, make full use of the surface distance of the circuit board 2, and even the surface distance of the electrically insulating pin bracket 643 to expand the creepage distance. To achieve an equivalent creepage distance d, the shrinkage avoidance space and the air distance from the surface of the insulating material to another surface must have a certain degree, such as a spacing of d1 of more than 0.5mm to facilitate customers to insert insulating sheets, or more than 1mm can be directly filled with air.

[0200] like Fig. 22B As mentioned above, blindly shrinking the pins will result in a smaller pin size. Therefore, the outer side of the electrically insulating pin bracket 643 is set to be stepped, and the air distance d2 between the upper side of the step and the circuit board and the air distance d1 between the lower side of the step and the customer's main board 8 are both set to be greater than 0.5 mm, so that the customer can insert an insulating sheet; or d1 and d2 are both set to be greater than 1 mm, and can be directly filled with air. The number of steps can be adjusted and increased as needed.

[0201] As an example, as shown in FIG25, the previous examples all install the module parallel to the client motherboard 8. There are also many occasions where the module needs to be installed perpendicular to the client motherboard 8, which is beneficial for installing the module and the heat sink 6 separately to obtain the best heat dissipation performance. It is just that the module output pin needs to be adjusted from the original perpendicular to the module heat dissipation surface to parallel.

[0202] like Fig.23 As shown, the pins perpendicular to the surface of the module are used to connect to the customer daughter board 22 nearby. The customer daughter board 22 can be provided with a high-frequency decoupling capacitor 23, as well as system control components such as a high-voltage isolation driver or controller. One side of the customer daughter board 22, such as the upper side, is connected to the high-frequency pins of the power magnetic component, that is, one or all of Pin A, Pin B, and Pin C; the other side of the customer daughter board 22, such as the lower side, is connected to the customer main board 8, and the bulk capacitor is connected through the main board. In this way, the respective paths are short to achieve connection, and there is no interference with each other, which can achieve higher efficiency and power density.

[0203] As an example, FIG. 24A to FIG. 24D As shown in the figure, the maximum operating temperature of capacitors and driver ICs is often lower than that of SiC / GaN. For example, the maximum operating temperature of SiC is 175°C, while the maximum operating temperature of high-frequency capacitor 1 is only 125°C. Therefore, if not specially handled, the performance and reliability of high-frequency capacitors will be affected due to excessive temperature.

[0204] like Fig.24AWhen these components are arranged on the outside of the multi-layer circuit board 2 of the module, a heat-conducting and electrically insulating material 644 can be added between these components and the customer mainboard 8 to help these components reduce heat.

[0205] like Fig. 24B as well as Fig.24C and Fig.24D As shown, not only capacitors and other components, but also high-density multi-layer circuit boards often have lower thermal limits, such as 145°C. Then, when the temperature of semiconductor power devices Q1 and Q2 reaches 175°C, if the temperature of the multi-layer circuit board needs to be controlled at 145°C, the multi-layer circuit board 2 needs to have its own heat dissipation channel (ie, thermal path) Rth_PCBtoCase, that is, the total equivalent thermal resistance value from the multi-layer circuit board 2 to the surrounding environment. And there needs to be a certain thermal resistance Rth_DietoPCB between the semiconductor power devices Q1 and Q2. Then, the relationship between these thermal resistances, plus the power consumption Pdie of the Die and the thermal resistance Rth_DietoCase from the Die to the outer surface of the DBC, i.e., the module Case, must satisfy a certain relationship, so that the heat conducted away by the semiconductor power devices Q1 and Q2 through the multi-layer circuit board 2 forms a temperature difference on the thermal resistance Rth_DietoPCB, which is close to or even greater than the maximum tolerable temperature difference between the Die and the multi-layer circuit board. That is, when the semiconductor power devices Q1 and Q2 reach the highest temperature TdieMAX, the temperature of the multilayer circuit board must be less than or equal to the highest temperature resistance value TpcbMAX. That is, (Tcase+(TdieMAX-Tcase)×Rth_PCBtoCase / (Rth_PCBtoCase+Rth_DietoPCB))≤TpcbMax. It can be seen that a proper increase in Rth_DietoPCB is conducive to controlling the temperature of the circuit board. Since copper with a resistance of 1mOhm is equivalent to a thermal resistance of approximately 150K / W. If you want 10W of heat to form a temperature difference of more than 30°C from Die to PCB, then the thermal resistance is Rth_DietoPCB≥3K / W, that is, the parallel resistance of all copper connected from the Die to the multilayer circuit board must be greater than 0.02mOhm.

[0206] As an example, FIG. 25A to FIG. 25E As shown, in order to solve the problem that the mold flow is difficult to control in the previous embodiment because only one plastic sealing is performed, this embodiment performs two plastic sealings according to the particularity of the structure of this case.

[0207] Step 1 Sc1: As needed, solder corresponding components on one or both sides of the multilayer circuit board 2, such as semiconductor power devices Q1, Q2, high-frequency capacitor 1, copper pillars connecting DBC / circuit board, etc. Fig.25A shown.

[0208] Step 2 Sc2: Plastic-encapsulate the first surface 201 of the circuit board 2 and one side of the semiconductor power devices Q1 and Q2 to form a plastic encapsulation body 7. After plastic encapsulation, keep the top surface of the semiconductor power devices Q1 and Q2 exposed, and when necessary, keep the exposed semiconductor power devices Q1 and Q2 solderable. For example, during plastic encapsulation, add a protective film to the exposed soldering surface; or after plastic encapsulation, grind it flat and plate a metal layer. Since the plastic encapsulation cavity is small, the mold flow is easier to control as needed, such as Fig.25B shown.

[0209] Step 3 Sc3: Weld or bond the DBC to ensure good thermal conductivity between the DBC and the semiconductor power devices Q1 and Q2, and electrical conductivity when necessary, such as Fig.25C shown.

[0210] Step 4 Sc4: Based on the first plastic packaging, the DBC and the first plastic packaging body 7 are plastic packaged for a second time to form a plastic packaging body 70. Similarly, it is determined whether to polish after the plastic packaging is completed according to the needs, such as Fig.25D shown.

[0211] Step Sc5: Divide the boards into corresponding modules, such as Fig.25E shown.

[0212] As an example, FIG. 26A to FIG. 26C As shown, since the present invention is suitable for high-frequency and high-voltage occasions, it means that the problem of high-voltage and high-frequency jumps is prone to occur. In order to better dissipate heat, a plastic packaging structure is used to reduce the thickness of the insulating thermal conductive layer 3, such as below 0.4mm, or even below 0.3mm, so that the parasitic capacitance between the upper metal layer 4 and the lower metal layer 5 on both sides of the insulating thermal conductive layer 3 is very large. The upper metal layer 4 is connected to the heat sink 6 and thus grounded. If the potential of the lower metal layer 5 is a high-frequency and high-voltage jump, then the common-mode current will be very large, resulting in an increase in the electromagnetic interference of the system.

[0213] like Fig.26A As shown in the figure, the two ends of each power conversion bridge arm are DC voltages, and the potentials of Vbus+ and Vbus- are relatively calm, which is not easy to cause large electromagnetic interference. The midpoints of the power conversion bridge arms, such as points A, B, and C, are high-frequency and high-voltage jump potentials, and most of the electromagnetic interference of the system comes from this type of potential. Fig.26B The conventional processing method is shown, that is, the upper and lower power switches, such as Q1 and Q2, have their heat dissipation surfaces as drain electrodes, corresponding to Fig.26A , which are Vbus+ and A potential respectively, so the Drain of Q2, i.e. A potential, will cause great electromagnetic interference.

[0214] like Fig.26CAs shown, this embodiment uses bridge arm switches with different heat dissipation surfaces. If the power current of SiC / MOS / IGBT vertically penetrates the upper and lower surfaces of semiconductor power devices Q1 and Q2, the heat dissipation surface of the upper tube Q1 is the Drain electrode, and the heat dissipation surface of the lower tube Q2 is the Source electrode. That is, the potentials connected to DBC are respectively static potentials, such as Vbus+ and Vbus-, which greatly reduces common-mode electromagnetic interference.

[0215] If the power current flows on the same side of the semiconductor power devices Q1 and Q2, such as GaN, the heat dissipation surface of the upper tube Q1 is the Drain electrode, and the heat dissipation surface of the lower tube Q2 is the Source or Gate electrode. That is, the potentials connected to DBC are respectively the electrostatic potential, such as Vbus+ and Vbus- or Vbus+ and Vgs, which greatly reduces the common-mode electromagnetic interference. Because the jump voltage and the electrostatic potential are relative, the electrostatic potential can be defined as the Vds voltage of the bridge arm power device, that is, less than one-tenth of the A voltage. For occasions where the A voltage amplitude is usually greater than 400V, a driving voltage below 20V can be regarded as the electrostatic potential.

[0216] As an example, FIG. 27A to FIG. 27C As shown, the common-mode suppression capacitor 24 (Y capacitor) for suppressing common-mode noise is integrated in the module nearby, so that the common-mode noise, especially the high-frequency common-mode noise, is suppressed inside the module.

[0217] like Fig.27A As shown, the midpoint of the power conversion bridge arm, i.e., the high-frequency and high-voltage jump VA, is often the Drain pole of Q2 in the SiC case and the Source pole of Q1 in the GaN case, which is electrically connected to the lower metal layer 5 of the DBC, thereby forming a large parasitic common-mode capacitor Cc with the upper metal layer 4 of the DBC through the insulating thermal conductive layer 3. The capacitor is short-circuited to the heat sink 6, thereby connecting to the ground GND. That is, the voltage source VA forms a large common-mode current Icom through Cc and the impedance between the ground and the power ground GND_pw.

[0218] The actual system is much more Fig.27A Complex, such as Fig.27B, the heat sink 6 itself is a combination of multiple parasitic inductors and multiple pairs of parasitic capacitances to the earth. Even if the system adds Y capacitor Cy1 and common mode inductor Lcom between the earth and the power ground, the complexity of its parasitic circuit greatly reduces the suppression effect, or requires larger common mode inductors and capacitors for suppression. The present invention proposes to integrate Y capacitor Cy2 and integrated damping Rin nearby inside the module, that is, before the complex parasitic circuit, the common mode energy is suppressed inside the module, so that the entire heat sink 6 has almost no voltage drop. Here, Line_G is the wiring ground connected to the earth, Ccer is the ceramic equivalent capacitor, Rth is the contact resistance between the external copper and the heat sink, Lth is the distributed inductance of the heat sink, and Cth is the distributed capacitance of the heat sink.

[0219] To achieve better results, you can add damping elements such as resistors or high-impedance beads to the built-in Y capacitor.

[0220] Fig.27C The specific structural implementation scheme is to set a Y capacitor inside the module, one electrode of the Y capacitor is electrically connected to the upper metal layer 4 through the cross-ceramic layer electrical connection component 25, and the other electrode of the Y capacitor is electrically connected to the top surface electrode of the first power device through the lower metal layer 5, so as to achieve Fig.29B equivalent effect.

[0221] like Figures 27D to 27G As shown, since the upper metal layer 4 of the DBC is to be mounted on the heat sink 6, the flatness requirement is very high. The cross-ceramic layer electrical connection component 25 interconnecting the Y capacitor to the upper metal layer 4 cannot exceed the upper metal layer 4. Fig.27D In the figure, the cross-ceramic layer electrical connection component 25 is a side edge electrical interconnection 26, which is arranged at the side edge of the insulating heat conductive plate, one end of the side edge electrical interconnection 26 is electrically connected to the upper metal layer 4, and the other end of the side edge electrical interconnection 26 is electrically connected to the Y capacitor through the lower metal layer 5; Fig.27E In the figure, the cross-ceramic layer electrical connection component 25 is a through-type electrical interconnection 27, which penetrates the insulating thermal conductive layer 3, one end of the through-type electrical interconnection 27 is electrically connected to the upper metal layer 4, and the other end of the through-type electrical interconnection 27 is electrically connected to the common-mode suppression capacitor 24 through the lower metal layer 5. Fig.27F and Figure 27G In the process, the copper wire welding process is complicated, and the current of the Y capacitor is small, so Fig.27F The solution shown can interconnect the upper metal layer 4 and the lower metal layer 5 of the DBC using a conductive coating 28, such as a silver paste coating. Fig.27C As shown, due to the large height of the Y capacitor, not only is the first surface of the circuit board grooved to make room, but the metal layer 5 under the DBC is also partially thinned. However, the local thinning of the copper layer requires additional processes, which can be Fig.27FBased on the scheme shown, a conductive coating 28 is further used to achieve the thinning effect, that is, Figure 27G The interconnection between the Y capacitor and the conductive coating 28 shown can be achieved directly by using the viscosity of the conductive coating 28, or by bonding with a conductive adhesive.

[0222] Since the above embodiments all complete the production of the module through multiple welding processes, there are many process flows, and it is necessary to make a thermal resistance electrical connection layer 12 at the bottom of the semiconductor power devices Q1 and Q2, which takes a long time and is costly. Therefore, a simplified production method is proposed, such as Figures 28A to 28D As shown, the details are as follows:

[0223] The first step Sd1: place the semiconductor power devices Q1 and Q2 on the first surface 201 of the multilayer circuit board, with welding material between the front of the semiconductor power devices Q1 and Q2 and the multilayer circuit board, and then place the multilayer circuit board 2 with the semiconductor power devices Q1 and Q2 on a support platform 29. The welding material can be printed on the multilayer circuit board 2 or pre-set on the front of the semiconductor power devices Q1 and Q2. In order to reduce the welding temperature difference, the support platform 29 below the multilayer circuit board 2 can also be a heating plate, such as Fig.28A shown.

[0224] Step 2 Sd2: Place DBC on the top surface of semiconductor power devices Q1 and Q2. There is welding material between the top surface of semiconductor power devices Q1 and Q2 and DCB. The welding material can be printed on DBC or pre-set on the top surface of semiconductor power devices Q1 and Q2. Fig.28B and Fig.28C shown.

[0225] Step 3 Sd3: Press a heating plate 30 onto the DBC and heat it. Since the DBC and the semiconductor power devices Q1 and Q2 are both good thermal conductors, heat can be quickly transferred to each solder joint. In order to reduce energy consumption and heating speed, the copper layer of the DBC can be heated by electric induction heating, such as Fig.28D shown.

[0226] In the above-mentioned embodiment, in order to meet the safety insulation requirements, the vertical electrical connection path 130 in the multilayer circuit board 2 is as close to the edge of the module as possible. In some applications that do not require safety insulation, such as 48V low-voltage electrode drive or rectifier inverter applications, or applications where the heat sink 6 is connected to the power ground instead of the earth, the thickness of the module can be further reduced because the withstand voltage requirement is relatively low and a large safety distance requirement is not required.

[0227] like Fig.29AAs shown, the low loop pad 31 is arranged on the second surface 202 of the multilayer circuit board, and the high frequency capacitor 1 can be welded to the second surface 202 of the circuit board 2 through the low loop pad 31. The vertical electrical connection path 130 is arranged as close to the low loop pad 31 as possible. The two electrodes of the high frequency capacitor 1 form a low loop with the semiconductor power device via the vertical electrical connection path 130, the internal wiring layer of the multilayer circuit board, and the first surface 201 of the multilayer circuit board. In the low loop, the transmission path of the high frequency signal is short, and the area enclosed by the loop is small, so the parasitic inductance and other parasitic parameters in the loop are small, thereby reducing the peak voltage and reducing the loss. Similar to the previous embodiment, the electrode arranged on the back of the semiconductor power device is connected to the insulating heat conductive plate through the heat conductive electrical insulating material 644, and the area of ​​the back of the semiconductor power device that exceeds 80% of the total area is set as an electrostatic potential to reduce common mode interference.

[0228] In another embodiment, if Fig.29B As shown, the module is set on one surface of the customer mainboard 8 by surface mount welding, and the high-frequency capacitor 1 is set on the other surface of the customer mainboard 8 corresponding to the module. The high-frequency capacitor is set adjacent to the low-loop pad 31 of the module, so that the wiring connecting the two poles of the high-frequency capacitor to the low-loop pad via the customer mainboard is as short as possible, thereby forming a low loop. Such a structure can achieve the same high-frequency effect, while reducing the number of internal components of the module, improving the module's yield rate, reducing the height of the module, and saving costs.

[0229] Reference Fig.29C ,exist Fig.29B Based on the application shown, a heat sink 6 is installed on the upper surface of the module, and the heat generated by the semiconductor chip is conducted to the heat sink 6 via the insulating heat conducting plate, and the heat sink 6 is connected and assembled with the customer mainboard 8 through the fixing column 32. While increasing the heat dissipation capacity of the module, the stability of the module is also enhanced.

[0230] The present invention strives to balance the ultimate loop reduction and excellent thermal conductivity, so as to realize the production of high-frequency and high-power packaging modules, and to achieve electrical insulation and good thermal conductivity from the heat dissipation surface. Therefore, the selection of insulating and thermally conductive materials for the DBC in this case is particularly important, and materials with high thermal conductivity coefficients, such as aluminum oxide, aluminum nitride, and silicon nitride materials are preferred; and the DBC in this case actually refers to an electrically insulating and good conductor substrate, and is not limited to the DBC body. The circuit board in this case actually refers to a multi-layer circuit wiring layer, which is not limited to an independent multi-layer circuit board, but can also be a wiring layer with the same function formed in the module process. The semiconductor power device in this case can also be a semiconductor wafer or a semiconductor chip, which are suitable for the technical solution disclosed in the present invention. The present invention proposes a high-frequency and high-power module solution that can cope with future demand trends, and proposes various improvement solutions to give full play to the potential of the present invention. Some of the improvement solutions are also applicable to other application scenarios and are not necessarily limited to those disclosed in the present invention.

[0231] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0232] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-frequency, high-power packaging module, characterized in that: It includes at least three semiconductor power devices and a driver; The semiconductor power devices are arranged on the same plane; The driver provides a driving signal for each of the semiconductor power devices, and a projection on the plane partially overlaps with a projection of each of the semiconductor power devices on the plane.

2. The high-frequency and high-power packaging module according to claim 1, characterized in that: It also includes a circuit layer, which includes a first surface and a second surface that are opposite to each other; the semiconductor power device is arranged on the first surface, and the driver is arranged on the second surface.

3. The high-frequency and high-power packaging module according to claim 1, characterized in that: The wiring distance from each of the semiconductor power devices to the corresponding driving signal terminal of the driver is the same.

4. The high-frequency and high-power packaging module according to claim 2, characterized in that: It also includes at least one high-frequency capacitor, an insulating heat-conducting plate and a plastic package; The insulating heat-conducting plate comprises an insulating heat-conducting layer, and an upper metal layer and a lower metal layer respectively arranged on the upper and lower surfaces of the insulating heat-conducting layer; The plastic package fills the gap area between the second surface of the circuit layer and the upper surface of the insulating heat-conducting plate, and an external electrode is arranged on the second surface or the side edge of the circuit layer, and the external electrode is electrically connected to the power conversion bridge arm; The front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating heat-conducting plate; The high-frequency capacitor is connected in parallel with the power conversion bridge arm to form a high-frequency loop, the high-frequency capacitor is electrically connected to the first surface of the circuit layer or the second surface of the circuit layer or the lower surface of the insulating heat-conducting plate, and at least one electrode of the high-frequency capacitor is electrically connected to at least one electrode of at least one semiconductor power device through an inner electrical connection layer; The wiring distance from each of the semiconductor power devices to the corresponding driving signal terminal of the driver is the same.

5. The high-frequency and high-power packaging module according to claim 4, characterized in that: It also includes a heat-conducting column, which is connected to the upper surface of the circuit layer through a high thermal conductivity interconnection, and the heat-conducting column is used for liquid cooling and heat dissipation.

6. The high-frequency and high-power packaging module according to claim 5, characterized in that: The thermally conductive column is a carbon fiber tube, and the high thermal conductivity interconnect is sintered silver.

7. The high-frequency and high-power packaging module according to claim 5, characterized in that: The high thermal conductivity interconnect is sintered silver, and the thermal conductive column includes a metal shell and an ultra-high thermal conductivity filler, wherein the ultra-high thermal conductivity filler is arranged inside the metal shell, and the ultra-high thermal conductivity filler is a carbon fiber tube, a graphene sheet or a phase change liquid.

8. The high-frequency and high-power packaging module according to claim 4, characterized in that: The heat-generating semiconductor device is a third-generation semiconductor power device, and the heat density of the third-generation semiconductor power device is at least 2W / mm 2 .

9. A hybrid substrate, characterized in that: The hybrid substrate comprises a high thermal conductivity region and a low thermal conductivity region; the hybrid substrate has an upper surface and a lower surface opposite to each other; The high thermal conductivity area and the low thermal conductivity area are arranged in a horizontal direction; The high thermal conductivity area is used to set a heat-generating semiconductor device, and the heat-generating semiconductor device is specifically set on the lower surface; The thermal conductivity of the high thermal conductivity region is greater than the thermal conductivity of the low thermal conductivity region; The upper surface of the hybrid substrate is used for assembling a heat dissipation device.

10. The hybrid substrate according to claim 9, characterized in that: The thermal conductivity of the high thermal conductivity region is greater than twice the thermal conductivity of the low thermal conductivity region.

11. The hybrid substrate according to claim 9, characterized in that: The high thermal conductivity region is a high thermal conductivity particle array, or the high thermal conductivity region is a mixture of a high thermal conductivity particle array and a low thermal conductivity material.

12. The hybrid substrate according to claim 9, characterized in that: It also includes an upper metal layer and a lower metal layer respectively arranged on the upper surface and the lower surface, and the materials of the high thermal conductivity area and the low thermal conductivity area are both insulating materials.

13. The hybrid substrate according to claim 9, characterized in that: The heat dissipation device comprises a heat-conducting column, wherein the heat-conducting column and the upper surface of the hybrid substrate are connected via a high thermal conductivity interconnection, and the heat-conducting column is used for liquid cooling and heat dissipation.

14. The hybrid substrate according to claim 13, characterized in that: The thermally conductive column is a carbon fiber tube, and the high thermal conductivity interconnect is sintered silver.

15. The hybrid substrate according to claim 13, characterized in that: The high thermal conductivity interconnect is sintered silver, and the thermal conductive column includes a metal shell and an ultra-high thermal conductivity filler, wherein the ultra-high thermal conductivity filler is arranged inside the metal shell, and the ultra-high thermal conductivity filler is a carbon fiber tube, a graphene sheet or a phase change liquid.

16. The hybrid substrate according to claim 9, characterized in that: The heat-generating semiconductor device is a third-generation semiconductor power device, and the heat density of the third-generation semiconductor power device is at least 2W / mm 2 .

17. A high-frequency, high-power packaging module, characterized in that: It includes at least one power conversion bridge arm, a circuit layer, an insulating heat-conducting plate and a packaging body; The power conversion bridge arm includes at least two semiconductor power devices connected in series; The circuit layer comprises a first surface, an inner electrical connection layer, a second surface and a vertical electrical connection path, wherein the inner electrical connection layer is electrically connected to the first surface via at least one vertical electrical connection path; an external electrode is disposed on the second surface of the circuit layer, and the external electrode is electrically connected to the power conversion bridge arm; The insulating heat-conducting plate comprises an insulating heat-conducting layer; The front side of the semiconductor power device is electrically connected to the first surface of the circuit layer, and the back side of the semiconductor power device is thermally or electrically connected to the lower surface of the insulating heat-conducting plate; The packaging body fills the gap area between the first surface of the circuit layer and the lower surface of the insulating heat conductive plate; The semiconductor power device is a semiconductor wafer.

18. The high-frequency and high-power packaging module according to claim 17, characterized in that: The side of the high-frequency high-power packaging module is provided with a step shape for increasing the creepage distance, or the second surface of the circuit layer is provided with an insulating pin bracket and the side of the insulating pin bracket is provided with a step shape for increasing the creepage distance.

19. The high-frequency and high-power packaging module according to claim 17, characterized in that: The packaging body is formed by plastic packaging.

20. The high-frequency and high-power packaging module according to claim 17, characterized in that: An upper metal layer and a lower metal layer are respectively arranged on two surfaces of the insulating heat-conducting layer.

21. The high-frequency and high-power packaging module according to claim 17, characterized in that: It also includes a high-frequency capacitor, and the power conversion bridge arm is electrically connected to the high-frequency capacitor to form a high-frequency loop.

22. The high-frequency and high-power packaging module according to claim 17, characterized in that: A metal layer is disposed on the lower surface of the insulating heat-conducting plate, and the metal layer is an electrostatic potential.

23. The high-frequency and high-power packaging module according to claim 17, characterized in that: The packaging body fills the gap area between the second surface of the circuit layer and the lower surface of the insulating heat-conducting plate.

24. The high-frequency and high-power packaging module according to claim 17, characterized in that: The external electrodes are surface mount electrodes, which are used to electrically interconnect the high-frequency and high-power packaging module with the customer's mainboard through a surface mount process.

25. The high-frequency and high-power packaging module according to claim 18, characterized in that: The step shape is a plastic package body.

26. The high-frequency and high-power packaging module according to claim 17, characterized in that: The front side of the semiconductor power device is directly connected to the first surface of the circuit layer by welding, or directly connected by electroplated vias.

27. The high-frequency and high-power packaging module according to claim 17, characterized in that: A metal layer is provided on the lower surface of the insulating heat-conducting plate, and the front surface of the semiconductor power device is electrically connected to the first surface of the circuit layer through the metal layer on the lower surface of the insulating heat-conducting plate.

28. The high-frequency and high-power packaging module according to claim 17, characterized in that: It also includes an electrical connection device, through which at least one electrode on the front side of the semiconductor power device is led out to the outside of the high-frequency high-power packaging module and is electrically connected to at least one electrode of a high-frequency capacitor.

29. The high-frequency and high-power packaging module according to claim 20, characterized in that: It also includes a cross-ceramic layer electrical connection component and a common-mode suppression capacitor; one electrode of the common-mode suppression capacitor is electrically connected to the upper metal layer through the cross-ceramic layer electrical connection component, and the other electrode of the common-mode suppression capacitor is electrically connected to a DC end of a power conversion bridge arm.

30. The high-frequency and high-power packaging module according to claim 17, characterized in that: The external electrodes include at least one pair of DC-end external electrodes, at least one pair of AC-end external electrodes and at least one pair of signal-end external electrodes; the signal-end external electrodes are arranged between the DC-end external electrodes and the AC-end external electrodes.

31. The high-frequency and high-power packaging module according to claim 17, characterized in that: It also includes a buffer external pin, which is electrically connected to the circuit layer and is used to electrically connect the high-frequency and high-power packaging module to the customer's mainboard.

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