Power factor correction package device and electronic apparatus

Abstract

The invention discloses a power factor correction packaging device and electronic equipment. The power factor correction packaging device comprises a substrate, a first booster circuit, a second booster circuit, a strong current pin and a weak current pin, the strong current pin and the weak current pin are located on the two opposite sides of the substrate respectively, and the first booster circuit and the second booster circuit are both connected with the strong current pin and the weak current pin. According to the power factor correction packaging device, the first booster circuit and the second booster circuit are integrated to form the power factor correction packaging device, so that the number of devices is reduced, installation and wiring are facilitated, the occupied space can be saved, the production cost is remarkably reduced, and the power factor correction packaging device is suitable for large-scale popularization and application. And the strong current pin and the weak current pin are respectively positioned on two opposite sides of the substrate, so that electromagnetic interference can be reduced, and stable work is ensured.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a power factor correction package device and electronic equipment. Background Art

[0002] Power factor correction (PFC) technology can effectively reduce grid current harmonics, reduce interference to the grid, and improve the stability and reliability of the entire system. As the system power increases, a multi-channel interleaved Boost PFC topology is often used in related technologies. The multi-channel interleaved Boost PFC topology can reduce the current stress of the inductor and switch, and can also reduce the ripple current of the capacitor. However, there are many devices in the multi-channel interleaved Boost PFC topology, which is inconvenient to route and install, and is prone to electromagnetic interference. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application needs to provide a power factor correction package device and an electronic device.

[0004] The power factor correction packaged device of the embodiment of the present application includes a substrate and a first boost circuit, a second boost circuit, a high-current pin and a low-current pin packaged on the substrate; the high-current pin and the low-current pin are respectively located on two opposite sides of the substrate, and the first boost circuit and the second boost circuit are both connected to the high-current pin and the low-current pin.

[0005] In some embodiments, the strong current pin includes a first input pin and an output pin, the weak current pin includes a first control pin and a first ground pin, and the first boost circuit includes:

[0006] a first switch transistor, wherein a first electrode of the first switch transistor is connected to the first ground pin, and a control electrode of the first switch transistor is connected to the first control pin;

[0007] a first diode, wherein an anode of the first diode is connected to a first electrode of the first switch transistor, and a cathode of the first diode is connected to a second electrode of the first switch transistor;

[0008] A second diode, wherein an anode of the second diode is connected to the second electrode of the first switch transistor and the first input pin, and a cathode of the second diode is connected to the output pin.

[0009] In some embodiments, the first switch transistor includes one of a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

[0010] In certain embodiments, the second diode includes one of a silicon fast recovery diode or a silicon carbide Schottky diode.

[0011] In some embodiments, the strong current pin includes a second input pin and an output pin, the weak current pin includes a second control pin and a second ground pin, and the second boost circuit includes:

[0012] a second switch transistor, wherein a first electrode of the second switch transistor is connected to the second ground pin, and a control electrode of the second switch transistor is connected to the second control pin;

[0013] a third diode, wherein an anode of the third diode is connected to the first electrode of the second switch transistor, and a cathode of the third diode is connected to the second electrode of the second switch transistor;

[0014] A fourth diode, wherein an anode of the fourth diode is connected to the second electrode of the second switch transistor and the second input pin, and a cathode of the fourth diode is connected to the output pin.

[0015] In some embodiments, the second switch transistor includes one of a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

[0016] In certain embodiments, the fourth diode includes one of a silicon fast recovery diode or a silicon carbide Schottky diode.

[0017] In some embodiments, the weak current pin further includes a first detection pin and a second detection pin, and the power factor correction package device further includes:

[0018] The thermistor is packaged on the substrate and connected to the first detection pin and the second detection pin respectively.

[0019] In some embodiments, the first boost circuit, the second boost circuit, the high-voltage pin, and the low-voltage pin are packaged on the substrate by a dual in-line package process.

[0020] The electronic device according to the embodiment of the present application includes the power factor correction package device according to any of the above embodiments.

[0021] In the power factor correction packaged device and electronic device of the embodiment of the present application, a device is formed by packaging the first boost circuit and the second boost circuit integrated on a substrate. In this way, the number of devices is reduced while ensuring power factor correction, which is convenient for installation and routing, and can save space and significantly reduce production costs. The high-current pins and the low-current pins are located on opposite sides of the substrate, respectively, which can avoid the crossover of strong and weak electricity, thereby reducing electromagnetic interference and ensuring the stability of operation.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 It is a circuit diagram of a power factor correction package device according to an embodiment of the present application.

[0025] Figure 2 Schematic diagram of the temperature relationship between thermistor and IGBT in one embodiment of the present application.

[0026] Description of main component symbols:

[0027] 100-power factor correction package device, 1-substrate, 10-first boost circuit, 101-first switch transistor, 102-first diode, 103-second diode, 20-second boost circuit, 201-second switch transistor, 202-third diode, 203-fourth diode, 30-strong current pin, PFC1-first input pin, PFC2-second input pin, P-output pin, 40-weak current pin, G1-first control pin, GND1-first ground pin, G2-second control pin, GND2-second ground pin, NTC1-first detection pin, NTC2-second detection pin, 301-thermistor; DETAILED DESCRIPTION

[0028] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0029] With the widespread use of electronic products, harmonic pollution in the power grid is becoming more and more serious. Power Factor Correction (PFC) technology can effectively reduce harmonic components and improve power factor, thereby reducing energy consumption, reducing the size and weight of power equipment, reducing the cross-sectional area of ​​wires, and reducing external radiation and conduction interference of power equipment.

[0030] Among them, Boost (boost) PFC is a more commonly used PFC topology. Boost PFC mainly includes switching devices and diodes. The switching device is used to control the on and off of the circuit, and the diode is used to provide a freewheeling path for the inductor when the switching device is turned off to ensure the stable operation of the circuit. In applications such as commercial air conditioning, as the system power increases, a multi-way interleaved Boost PFC topology is commonly used to achieve it. The multi-way interleaved Boost PFC topology works by using multiple Boost PFC converters in an interleaved parallel manner. In the interleaved parallel PFC circuit, it is composed of two or more Boost PFC converters in parallel. The switch tube of each Boost PFC converter is staggered, that is, the opening time in the switching cycle is delayed by a certain time (usually 180°) in sequence, so that the current flowing through each Boost PFC converter is also staggered. The advantage of this method is that it can significantly reduce the effective value of the input current ripple and the output capacitor ripple current, and improve the power level of the circuit. However, in a multi-channel interleaved Boost PFC topology, each Boost PFC includes multiple devices. The presence of multiple devices makes the wiring more complicated and prone to electromagnetic interference problems. In addition, multiple devices are inconvenient to install and occupy a large space.

[0031] In view of this, please refer to Figure 1 An embodiment of the present application provides a power factor correction packaged device 100, which includes a substrate 1 and a first boost circuit 10, a second boost circuit 20, a high-current pin 30 and a low-current pin 40 packaged on the substrate 1; the high-current pin 30 and the low-current pin 40 are respectively located on two opposite sides of the substrate 1, and the first boost circuit 10 and the second boost circuit 20 are both connected to the high-current pin 30 and the low-current pin 40.

[0032] In the power factor correction packaged device 100 of the embodiment of the present application, a device is formed by packaging and integrating the first boost circuit 10 and the second boost circuit 20 on the substrate 1. In this way, while achieving power factor correction, the number of devices is reduced, which is convenient for installation and routing, and can save space and significantly reduce production costs. The high-current pin 30 and the low-current pin 40 are respectively located on opposite sides of the substrate 1 to avoid the crossover of strong and weak electricity, thereby reducing electromagnetic interference and ensuring the stability of operation.

[0033] The substrate 1 may be made of ceramic, polymer, plastic or composite material, and the substrate 1 needs to have good thermal conductivity to facilitate heat dissipation.

[0034] Both the strong current pin 30 and the weak current pin 40 may include a plurality of them, and the specific number of the strong current pin 30 and the weak current pin 40 may be set according to the requirements of the first boost circuit 10 and the second boost circuit 20. The strong current pin 30 and the weak current pin 40 are respectively packaged on opposite sides of the substrate 1 and extend out of the substrate 1.

[0035] The strong current pin 30 is used to connect a circuit with a higher voltage level or a larger current level, wherein a higher voltage level refers to a voltage greater than 24 volts, for example, the strong current pin 30 can be connected to a 220 volt or 380 volt circuit, and a larger current level refers to a current usually measured in amperes (A) or kiloamperes (kA), for example, the strong current pin 30 can be connected to a circuit with 2 amperes or 5 amperes. The weak current pin 40 is used to connect a circuit with a lower voltage level or a smaller current level, wherein a lower voltage level refers to a voltage less than 24 volts, such as a DC voltage of 3 volts or 12 volts. A smaller current level refers to a current usually measured in milliamperes (mA) or microamperes (uA).

[0036] The first boost circuit 10 and the second boost circuit 20 can both be Boost PFC circuits, and the Boost PFC circuit is a switching DC boost circuit that adjusts the input voltage to achieve the desired output voltage by periodic switching. The first boost circuit 10 and the second boost circuit 20 are packaged on the substrate 1, and are both connected to the strong current pin 30 and the weak current pin 40, and the first boost circuit 10 and the second boost circuit 20 are connected to the external circuit through the strong current pin 30 and the weak current pin 40. The switch tubes of the first boost circuit 10 and the second boost circuit 20 can be staggered, that is, the opening moment in the switching cycle is delayed by a certain time (for example, 180°) in sequence, so that the current flowing through the first boost circuit 10 and the second boost circuit 20 also presents a staggered state. In this way, the effective value of the input current ripple and the output capacitor ripple current is significantly reduced, and the power level of the circuit is improved.

[0037] Furthermore, the first boost circuit 10 and the second boost circuit 20, the strong current pin 30 and the weak current pin 40 can be packaged on the substrate 1 using epoxy resin-based plastic packaging materials to form a device. In addition, it should be noted that during packaging, the back side of the substrate 1 needs to be exposed for heat dissipation. In this way, the first boost circuit 10 and the second boost circuit 20 are guaranteed to operate within the specified temperature range, thereby improving the stability and reliability of the power factor correction packaged device 100. The packaging process can adopt a dual in-line package (DIP) process, for example, a DIP24 packaging process.

[0038] Please refer to Table 1, which is a comparison table of the dual-path interleaved Boost PFC structure in the related art and the power factor correction package device 100 of the present application. From Table 1, it can be seen that the total occupied area of ​​the dual-path interleaved Boost PFC structure in the related art is 1957 square millimeters, and the occupied area of ​​the power factor correction package device 100 of the present application is 719 square millimeters. It can be seen that the present application can significantly reduce the occupied area.

[0039]

[0040] Table 1

[0041] Please refer to further Figure 1 In some embodiments, the strong current pin 30 includes a first input pin PFC1 and an output pin P, the weak current pin 40 includes a first control pin G1 and a first ground pin GND1, and the first boost circuit 10 includes a first switch transistor 101, a first diode 102, and a second diode 103. Among them, the first electrode of the first switch transistor 101 is connected to the first ground pin GND1, and the control electrode of the first switch transistor 101 is connected to the first control pin G1; the positive electrode of the third diode 202 is connected to the first electrode of the first switch transistor 101, the negative electrode of the third diode 202 is connected to the second electrode of the first switch transistor 101, the positive electrode of the second diode 103 is connected to the second electrode of the first switch transistor 101 and the first input pin PFC1, and the negative electrode of the second diode 103 is connected to the output pin P.

[0042] It should be noted that each type of pin may include one or more pins. When there are multiple pins of the same type, the multiple pins of the same type are arranged adjacent to each other. It can be understood that multiple pins of the same type can improve the current carrying capacity. For example, the first input pin PFC1 and the output pin P may each include two pins, two first input pins PFC1 are arranged adjacent to each other, and two output pins P are arranged adjacent to each other.

[0043] The first switch transistor 101 is used to control the on and off of the first boost circuit 10. The first switch transistor 101 can be switched at a certain frequency in the first boost circuit 10 to achieve voltage increase and power factor correction. The first switch transistor 101 can be a metal-oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). For example, in some examples, the first switch transistor 101 can be a MOSFET, and for another example, in some examples, the first switch transistor 101 can be an IGBT.

[0044] The first electrode of the first switch transistor 101 is a collector, the second electrode of the first switch transistor 101 is an emitter, and the control electrode of the first switch transistor 101 is a gate. That is, the collector of the first switch transistor 101 is connected to the first ground pin GND1, the emitter of the first switch transistor 101 is connected to the anode of the second diode 103, and the gate of the first switch transistor 101 is connected to the first control pin G1.

[0045] The first diode 102 is used to prevent the reverse voltage from damaging the first switch transistor 101 . It should be noted that when the first switch transistor 101 is a MOSFET, the first diode 102 is a parasitic body diode of the first switch transistor 101 .

[0046] The second diode 103 can play an isolation role to prevent current backflow and reduce the energy loss of the first switch transistor 101 during operation. The second diode 103 includes a silicon fast recovery diode (Silicon Fast Recovery Diode, Si-FRD) or a silicon carbide Schottky diode (SiC Schottky Diode, SSD). For example, in some examples, the second diode 103 can be a silicon fast recovery diode, and in other examples, the second diode 103 can be a silicon carbide Schottky diode.

[0047] It should be noted that the silicon fast recovery diode is a semiconductor device designed for high-speed switching applications, with good switching characteristics and short reverse recovery time, which can significantly improve the efficiency of the power supply. The silicon carbide Schottky diode is a metal-semiconductor device made by the rectification characteristics of the contact barrier formed between the metal and the N-type semiconductor, with the advantages of high voltage tolerance, high temperature stability, and fast switching speed.

[0048] In this way, by configuring the first switch transistor 101 , the first diode 102 and the second diode 103 , the power factor correction function of the first boost circuit 10 can be achieved.

[0049] Please refer to further Figure 1In some embodiments, the strong current pin 30 includes a second input pin PFC2 and an output pin P, the weak current pin 40 includes a second control pin G2 and a second ground pin GND2, and the second boost circuit 20 includes a second switch transistor 201, a third diode 202, and a fourth diode 203. Among them, the first electrode of the second switch transistor is connected to the second ground pin GND2, and the control electrode of the second switch transistor 201 is connected to the second control pin G2; the positive electrode of the third diode 202 is connected to the first electrode of the second switch transistor 201, and the negative electrode of the third diode 202 is connected to the second electrode of the second switch transistor 201. The positive electrode of the fourth diode 203 is connected to the second electrode of the second switch transistor 201 and the second input pin PFC2, and the negative electrode of the fourth diode 203 is connected to the output pin P.

[0050] Specifically, the second switch transistor 201 is used to control the on and off of the second boost circuit 20. The second switch transistor 201 can be switched at a certain frequency in the second boost circuit 20 to achieve voltage increase and power factor correction. The second switch transistor 201 can be a metal-oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). For example, in some examples, the second switch transistor 201 can be a MOSFET, and for another example, in some examples, the second switch transistor 201 can be an IGBT.

[0051] The first electrode of the second switch transistor 201 is a collector, the second electrode of the second switch transistor 201 is an emitter, and the control electrode of the second switch transistor 201 is a gate. That is, the collector of the second switch transistor 201 is connected to the second ground pin GND2, the emitter of the second switch transistor 201 is connected to the anode of the fourth diode 203, and the gate of the second switch transistor 201 is connected to the second control pin G2.

[0052] The third diode 202 is used to prevent the reverse voltage from damaging the second switch transistor 201 . It should be noted that when the second switch transistor 201 is a MOSFET, the third diode 202 is a parasitic body diode of the second switch transistor 201 .

[0053] The fourth diode 203 can play an isolation role to prevent current backflow and reduce the energy loss of the second switch transistor 201 during the switching process. The fourth diode 203 includes a silicon fast recovery diode or a silicon carbide Schottky diode. For example, in some examples, the fourth diode 203 can be a silicon fast recovery diode, and in other examples, the fourth diode 203 can be a silicon carbide Schottky diode.

[0054] In this way, by configuring the second switch transistor 201 , the third diode 202 and the fourth diode 203 , the power factor correction function of the second boost circuit 20 can be achieved.

[0055] like Figure 1 As shown, in some embodiments, the low-voltage pin 40 also includes a first detection pin NTC1 and a second detection pin NTC2, and the power factor correction packaged device 100 also includes a thermistor 301, which is packaged on the substrate 1 and connected to the first detection pin NTC1 and the second detection pin NTC2 respectively.

[0056] The thermistor 301 is used to monitor the temperature of the power factor correction package device 100. It can be understood that when the first boost circuit 10 and the second boost circuit 20 are working, the first switch transistor 101 and the second switch transistor 201 need to perform switching operations at a certain frequency, which causes the temperature of the entire power factor correction package device to rise. Therefore, the setting of the thermistor 301 can monitor the temperature of the power factor correction package device 100 in real time, thereby avoiding damage to the first boost circuit 10 or the second circuit due to high temperature.

[0057] For example, in some examples, the first switch transistor 101 and the second switch transistor 201 are both IGBTs, and the temperature read by the thermistor 301 is linearly related to the IGBT junction temperature Tj (eg, Figure 2 As shown). Thus, the IGBT junction temperature can be prevented from exceeding the rated maximum value by reading the temperature of the thermistor 301.

[0058] The electronic device according to the embodiment of the present application includes the power factor correction package device 100 according to any one of the above embodiments.

[0059] In the electronic device of the embodiment of the present application, a device is formed by packaging and integrating the first boost circuit 10 and the second boost circuit 20 on the substrate 1. In this way, the number of components is reduced while ensuring power factor correction, which is convenient for installation and routing, and can save space and significantly reduce production costs. The high-current pin 30 and the low-current pin 40 are respectively located on opposite sides of the substrate 1 to avoid the crossover of strong and weak electricity, thereby reducing electromagnetic interference and ensuring the stability of operation.

[0060] The electronic device of the present application may be an electric power device such as an air conditioning device.

[0061] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0062] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A power factor correction package device, characterized in that: It includes a substrate and a first boost circuit, a second boost circuit, a strong current pin and a weak current pin packaged on the substrate; the strong current pin and the weak current pin are respectively located on two opposite sides of the substrate, and the first boost circuit and the second boost circuit are both connected to the strong current pin and the weak current pin.

2. The power factor correction package device according to claim 1, characterized in that: The strong current pin includes a first input pin and an output pin, the weak current pin includes a first control pin and a first ground pin, and the first boost circuit includes: a first switch transistor, wherein a first electrode of the first switch transistor is connected to the first ground pin, and a control electrode of the first switch transistor is connected to the first control pin; a first diode, wherein an anode of the first diode is connected to a first electrode of the first switch transistor, and a cathode of the first diode is connected to a second electrode of the first switch transistor; A second diode, wherein an anode of the second diode is connected to the second electrode of the first switch transistor and the first input pin, and a cathode of the second diode is connected to the output pin.

3. The power factor correction package device according to claim 2, characterized in that: The first switch transistor includes one of a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

4. The power factor correction package device according to claim 2, characterized in that: The second diode includes one of a silicon fast recovery diode and a silicon carbide Schottky diode.

5. The power factor correction package device according to claim 1, characterized in that: The strong current pin includes a second input pin and an output pin, the weak current pin includes a second control pin and a second ground pin, and the second boost circuit includes: a second switch transistor, wherein a first electrode of the second switch transistor is connected to the second ground pin, and a control electrode of the second switch transistor is connected to the second control pin; a third diode, wherein an anode of the third diode is connected to the first electrode of the second switch transistor, and a cathode of the third diode is connected to the second electrode of the second switch transistor; A fourth diode, wherein an anode of the fourth diode is connected to the second electrode of the second switch transistor and the second input pin, and a cathode of the fourth diode is connected to the output pin.

6. The power factor correction package device according to claim 5, characterized in that: The second switch transistor includes one of a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

7. The power factor correction package device according to claim 5, characterized in that: The fourth diode includes a silicon fast recovery diode or a silicon carbide Schottky diode.

8. The power factor correction package device according to claim 1, characterized in that: The weak current pin includes a first detection pin and a second detection pin, and the power factor correction package device also includes: The thermistor is packaged on the substrate and connected to the first detection pin and the second detection pin respectively.

9. The power factor correction package device according to claim 1, characterized in that: The first boost circuit, the second boost circuit, the strong current pin and the weak current pin are packaged on the substrate by a dual in-line packaging process.

10. An electronic device, characterized in that: A power factor correction package device comprising any one of claims 1 to 9.

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