Four-section thickness quantization system and method applied to analog-to-digital conversion of image sensor

Abstract

The invention discloses a four-section thickness quantization system and method applied to analog-to-digital conversion of an image sensor, and belongs to the technical field of image communication. The system comprises a slope generator, a comparator, a coarse and fine quantization interval separation circuit, a high-frequency clock, a low-frequency clock, a digital processing circuit, a coarse quantization circuit and a fine quantization circuit. According to the invention, fine quantization compensation is carried out on four sections of intervals of coarse quantization rising and falling edges of two counting stages, so that compared with a traditional double-slope double-channel clock up-down counting structure, clock edge inconsistency caused by clock delay introduced by long-distance transverse arrangement of multiple columns of quantization circuits is eliminated; and the physical quantity corresponding to the counting result does not contain an extra fixed voltage physical value, so that the accuracy of analog-to-digital conversion is improved.

Description

Technical Field

[0001] The present invention relates to a four-stage coarse and fine quantization system and method applied to analog-to-digital conversion of an image sensor, belonging to the technical field of image communication. Background Art

[0002] The analog-to-digital converter quantization structures that can be used in the column-parallel readout circuit of CMOS image sensors include ramp type, successive approximation type, and cyclic type structures. Among them, the ramp type structure is usually selected for the micron-level small pixel readout circuit, including single ramp, such as Figure 1 The dual slope single clock counting up and down is shown as Figure 2 The dual slope single clock counting up is shown as Figure 3 The structure shown is dual slope dual clock up and down counting.

[0003] The traditional dual-slope single-channel clock up and down counting and the single-channel clock up and up counting are counted in the corresponding counting intervals, and a high-speed counting clock is used to meet the full counting interval to achieve full-scale counting.

[0004] Traditional dual-slope, dual-channel clock up / down counting uses two different clock signals, high and low frequencies, to count in corresponding working intervals. Within the counting working interval, the low-frequency clock is used for most of the working interval. The high-speed clock is used for supplementary counting in the interval that is less than one low-speed clock cycle and outside the working interval interval, which is an integer number of low-speed clocks apart. At the same time, because the end position of the second counting interval is after the flip point, the second low-speed counting interval uses subtraction counting. A high-frequency clock counter needs to be compatible with both up-counting and down-counting functions. The high-frequency clock counts at the left edge of the first counting interval and the right edge of the second counting interval. The counting circuit trigger position is the falling edge of the low-speed clock and the rising edge of the high-speed clock.

[0005] The corresponding relationship between the traditional double-slope up and down counting code value and the physical quantity is: The first stage counting result is , the second stage counting result is .in, is the voltage difference between the highest and lowest points of the ramp signal in the first stage, is the highest point voltage value of the ramp signal in the two stages, is the reset voltage value of the image sensor pixel, is the voltage value of the light signal of the image sensor pixel. The corresponding relationship between the traditional double-slope up-down counting code value and the physical quantity is: The first stage counting result is , the second stage counting result is The corresponding relationship between the traditional dual-slope dual-channel clock up and down counting code values ​​and physical quantities is: The first stage counting result is , the second stage counting result is .

[0006] The final counting results of the three structures are traditional dual slope up-down counting, traditional dual slope up-up counting and traditional dual slope dual clock up-down counting. The results of this goal all contain an additional fixed physical value, which has the defect of the physical value of the base voltage. Summary of the Invention

[0007] The technical problem solved by the present invention is: to overcome the shortcomings of the existing technology, and to propose a four-segment coarse and fine quantization system and method for analog-to-digital conversion of image sensors, in which fine quantization compensation is performed on the four intervals of the coarse quantization rising and falling edges in the two counting stages, and the physical quantity corresponding to the counting result does not contain additional fixed voltage physical values, thereby improving data accuracy.

[0008] The technical solution of the present invention is: A four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors, including a ramp generator, a comparator, a coarse and fine quantization interval separation circuit, a high-frequency clock, a low-frequency clock, a digital processing circuit, a coarse quantization circuit, and a fine quantization circuit; A ramp generator generates a ramp signal based on a periodic analog signal output by the image sensor, which is composed of an alternating arrangement of a reset signal and a light signal. The period of the ramp signal is the same as that of the periodic analog signal. Within each period, the ramp signal includes a short ramp signal and a long ramp signal with different amplitudes, both of which are signals that monotonically decrease from an initial voltage to an end voltage. The period in which the short ramp signal exists is recorded as the first stage. During the first stage, the periodic analog signal remains as the reset signal, the amplitude of the short ramp signal covers the swing of the reset signal, the initial voltage is higher than the maximum value of the reset signal, and the end voltage is lower than the minimum value of the reset signal. The period in which the long ramp signal exists is recorded as the second stage. During the second stage, the periodic analog signal remains as the light signal, the amplitude of the long ramp signal covers the swing of the light signal, the initial voltage is higher than the maximum value of the light signal, and the end voltage is lower than the minimum value of the light signal. a comparator, for comparing the ramp signal generated by the ramp generator with the periodic analog signal, and outputting the signal to the coarse and fine quantization interval separation circuit; The coarse-fine quantization interval separation circuit separates the comparator output signal into two coarse-quantization interval signals and four fine-quantization interval signals; wherein the four rising and falling edges of the two coarse-quantization interval signals correspond to the positions of the four fine-quantization interval signals, thus forming a four-segment coarse-fine quantization structure; The coarse quantization circuit counts the number of low-frequency clocks corresponding to the coarse quantization interval signal based on the low-frequency clock; The fine quantization circuit counts the number of high-frequency clocks corresponding to the fine quantization interval signal based on the high-frequency clock; The digital processing circuit processes the counting results of the coarse quantization circuit and the counting results of the fine quantization circuit into a final quantization result.

[0009] Furthermore, the comparator compares the ramp signal generated by the ramp generator with the periodic analog signal and outputs two signals, namely an UP-UP signal and an UP-DOWN signal; The UP-UP signal is as follows: the signal is initially low; at the starting point of the short ramp signal and the long ramp signal, the signal flips from low to high; when the short ramp signal and the long ramp signal are decreasing and their amplitudes do not reach the corresponding reset signal and optical signal amplitudes in the periodic analog signal, the signal remains high; when the short ramp signal and the long ramp signal amplitudes drop to the corresponding reset signal and optical signal amplitudes in the periodic analog signal, the signal flips from high to low, forming a pulse; The UP-DOWN signal is as follows: in the first stage, the UP-DOWN signal and the UP-UP signal are the same pulse signal; in the second stage, the UP-DOWN signal and the UP-UP signal are inverted signals.

[0010] Furthermore, the coarse and fine quantization interval separation circuit includes a D flip-flop, a logic XOR gate circuit and a logic AND gate circuit; wherein, the input of the D flip-flop is the UP-UP signal output by the comparator and the low-frequency clock, and the UP-UP signal is sampled using the rising edge of the low-frequency clock to output a coarse quantization interval signal; the coarse quantization interval signal and the UP-UP signal are input into the logic XOR gate circuit for XOR operation; the signal output by the logic XOR gate circuit and the UP-DOWN signal are then input into the logic AND gate circuit for logic AND operation to obtain a fine quantization interval signal.

[0011] Furthermore, the high-frequency signal and the low-frequency signal are two signals with a frequency difference of 32 times.

[0012] Furthermore, the coarse quantization circuit counts the number of coarse quantization interval signals based on the low-frequency clock. The counting method is: the coarse quantization interval signals adopt downward decreasing counting in the first stage and upward increasing counting in the second stage.

[0013] Furthermore, the fine quantization circuit counts the number of fine quantization interval signals based on the high-frequency clock, and the counting method is: the fine quantization interval signal adopts downward reduction counting in the first pulse segment, upward increment counting in the second pulse segment, upward increment counting in the third pulse segment, and downward reduction counting in the fourth pulse segment; wherein, the first pulse segment and the second pulse segment are in the first stage, and the third pulse segment and the fourth pulse segment are in the second stage.

[0014] Furthermore, the digital processing circuit performs quantization in the following way: the downward reduction count is equivalent to the subtraction of the count value, and the upward increment count is equivalent to the addition of the count value; the physical quantity corresponding to the counting result in the first stage is , the physical quantity corresponding to the second stage counting result is , the physical quantity corresponding to the final quantization result is ;in, is the voltage difference between the highest and lowest points of the ramp signal in the first stage, is the highest point voltage value of the ramp signal in the two stages, is the reset voltage value of the image sensor pixel, is the voltage value of the image sensor pixel light signal.

[0015] A method for performing analog-to-digital conversion based on a four-stage coarse-fine quantization system applied to analog-to-digital conversion of an image sensor includes: Processing the output signal of the image sensor's photosensitive device into a periodic analog signal in which a reset signal and a light signal are alternately arranged; generating a ramp signal based on a periodic analog signal; comparing the ramp signal with the periodic analog signal; The signals output after comparison are separated and processed to obtain two coarse quantization interval signals and four fine quantization interval signals; wherein the four rising and falling edges of the two coarse quantization interval signals correspond to the positions of the four fine quantization interval signals, thus forming a four-segment coarse and fine quantization structure; Counting the number of low-frequency clocks corresponding to the coarse quantization interval signal; counting the number of high-frequency clocks corresponding to the fine quantization interval signal; The obtained coarse quantization interval signal count value and fine quantization interval signal count value are processed to obtain a final quantization result.

[0016] Furthermore, the ramp signal is compared with the periodic analog signal, and an UP-UP signal and an UP-DOWN signal are output; The output UP-UP signal is as follows: the signal is initially low; at the starting point of the short ramp signal and the long ramp signal, the signal flips from low to high; when the short ramp signal and the long ramp signal are decreasing and their amplitudes do not reach the corresponding reset signal and optical signal amplitudes in the periodic analog signal, the signal remains high; when the short ramp signal and the long ramp signal amplitudes drop to the corresponding reset signal and optical signal amplitudes in the periodic analog signal, the signal flips from high to low, forming a pulse; The output UP-DOWN signal is: in the first stage, the UP-DOWN signal and the UP-UP signal are the same pulse signal; in the second stage, the UP-DOWN signal and the UP-UP signal are inverted signals.

[0017] Furthermore, the method for separating and processing the signal output after comparison is: using the rising edge of a low-frequency clock to sample the UP-UP signal and output a coarse quantization interval signal; performing an XOR operation on the coarse quantization interval signal and the UP-UP signal and then performing a logical AND operation with the UP-DOWN signal to obtain a fine quantization interval signal.

[0018] The advantages of the present invention compared with the prior art are: (1) The present invention overcomes the defects of the three structures of traditional dual-slope up-down counting, traditional dual-slope up-up counting and traditional dual-slope dual-channel clock up-down counting in that the physical quantity corresponding to the final counting result has the physical value of the base voltage. The physical quantity corresponding to the final counting result of the present invention is , there is no additional fixed voltage physical value.

[0019] (2) The present invention performs fine quantization compensation on the four intervals of the coarse quantization rising and falling edges of the two counting stages. Compared with the traditional dual-slope dual-path clock up and down counting structure, it eliminates the clock edge inconsistency caused by the clock delay introduced by the long-distance horizontal arrangement of multiple column quantization circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings: Figure 1 This is the dual slope up and down counting timing diagram; Figure 2 This is the dual slope up-down counting timing diagram; Figure 3 This is the traditional dual-slope dual-channel clock up and down counting timing diagram; Figure 4 This is a timing diagram of the four-stage coarse and fine quantization dual-slope dual-channel clock up and down counting according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a coarse and fine quantization interval separation module according to an embodiment of the present invention; Figure 6 This is a block diagram of the four-stage coarse and fine quantization structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0022] The present invention proposes a four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors, such as Figure 6 As shown, it includes a ramp generator, a comparator, a coarse and fine quantization interval separation circuit, a high-frequency clock, a low-frequency clock, a digital processing circuit, a coarse quantization circuit and a fine quantization circuit.

[0023] The output signal of the image sensor's photosensitive device is processed by the analog front-end circuit into a periodic analog signal in which a reset signal and a light signal are alternately arranged.

[0024] The ramp generator generates a ramp signal that monotonically decreases from an initial voltage to an ending voltage. The initial voltage is higher than the maximum value of the periodic analog signal, and the ending voltage is lower than the minimum value of the periodic analog signal. The amplitude of the ramp signal can cover the swing of the periodic analog signal, and the period is the same as the period of the periodic analog signal. The ramp signal includes short ramp intervals and long ramp intervals. The amplitude of the short ramp signal can cover the swing of the reset signal, and the amplitude of the long ramp signal can cover the swing of the optical signal. During the short ramp signal interval, the periodic analog signal remains as the reset signal, and during the long ramp signal interval, the periodic analog signal remains as the optical signal.

[0025] The comparator's two inputs are a periodic analog signal and a ramp signal. Its operating principle is as follows: at the start of the short and long ramps, the comparator switches from a low level to a high level. While the ramp signal is falling and before reaching the reset signal and the optical signal of the periodic analog signal, the comparator output remains high. When the ramp signal reaches the reset signal and the optical signal, the comparator output switches from a high level to a low level. Specifically, in this embodiment, the comparator output is low by default. At the start of the short ramp, the comparator switches from a low level to a high level. While the short ramp signal is falling and before reaching the reset signal, the comparator output remains high. When the short ramp signal reaches the reset signal, the comparator output switches from a high level to a low level. This pulse represents the reset signal interval. Subsequently, at the start of the long ramp, the comparator switches from a low level to a high level. While the long ramp signal is falling and before reaching the optical signal, the comparator output remains high. When the long ramp signal reaches the optical signal, the comparator output switches from a high level to a low level. This pulse represents the optical signal interval.

[0026] The coarse and fine quantization interval separation module separates the output signal of the comparator into two coarse quantization intervals and four fine quantization intervals, such as Figure 5As shown, the coarse-fine quantization interval separation module consists of a D-type flip-flop, a logic XOR gate, and a logic AND gate. The coarse-fine quantization function involves two signals, a high-frequency signal and a low-frequency signal, with frequencies that differ by 32 times. The UP-UP and UP-DOWN signals are the outputs of the comparator. In the first stage, the UP-UP and UP-DOWN signals are identical pulse signals. In the second stage, the UP-UP and UP-DOWN signals are inverted signals. The D-type flip-flop samples the UP-UP signal using the rising edge of the low-frequency clock. The output of the D-type flip-flop is the coarse quantization interval. The coarse quantization interval is XORed with the UP-UP signal and then logically ANDed with the UP-DOWN signal to produce the fine quantization interval. The four rising and falling edges of the two coarse quantization intervals correspond to the positions of the four fine quantization intervals. To characterize this structure, it is called a four-stage coarse-fine quantization structure.

[0027] The coarse quantization circuit completes the counting of the number of low-frequency clock signals in the coarse quantization interval, and the fine quantization circuit completes the counting of the number of high-frequency clock signals, such as Figure 4 As shown in the figure, the coarse quantization interval uses downward counting in the first phase (i.e., the reset signal phase) and upward counting in the second phase (i.e., the optical signal phase). The fine quantization interval signal uses downward counting in the first pulse segment, upward counting in the second pulse segment, upward counting in the third pulse segment, and downward counting in the fourth pulse segment. The first and second pulse segments correspond to the first phase of the coarse quantization interval signal, while the third and fourth pulse segments correspond to the second phase of the coarse quantization interval signal.

[0028] The digital processing circuit processes the coarse and fine quantization counts into the final quantization result. Among them, the downward reduction count is equivalent to the subtraction of the count value, and the upward increment count is equivalent to the addition of the count value. The physical quantity corresponding to the first stage counting result is , the physical quantity corresponding to the second stage counting result is , the physical quantity corresponding to the final counting result is , there is no additional fixed voltage physical value.

[0029] In a counting structure system, the count value corresponds to the voltage value. The counting process is the process of analog-to-digital conversion, which converts the reset signal and light signal of the image sensor pixel into a digital code value. The conversion process is a linear conversion. The present invention separates the coarse and fine quantization intervals and uses fine quantization to compensate for the accuracy of coarse quantization, thereby achieving accurate conversion of the reset signal and light signal.

[0030] The method for analog-to-digital conversion based on this system is: The output signal of the image sensor's photosensitive device is processed into a periodic analog signal in which a reset signal and a light signal are alternately arranged.

[0031] Based on the periodic analog signal, a ramp signal is generated. The ramp signal includes a short ramp signal and a long ramp signal with different amplitudes. Both are signals that monotonically decrease from an initial voltage to a final voltage. The amplitude of the short ramp signal covers the swing of the reset signal, and the amplitude of the long ramp signal covers the swing of the optical signal. In the time zone where the short ramp signal exists, the periodic analog signal remains as a reset signal; in the time zone where the long ramp signal exists, the periodic analog signal remains as an optical signal.

[0032] The ramp signal is compared with the periodic analog signal: the UP-UP signal output after comparison is initially low. At the starting points of the short and long ramp signals, the comparator output signal flips from low to high. While the short and long ramp signals are decreasing and their amplitudes do not reach the corresponding reset and optical signal amplitudes in the periodic analog signal, the comparator output signal remains high. When the short and long ramp signals' amplitudes drop to the corresponding reset and optical signal amplitudes in the periodic analog signal, the comparator output signal flips from high to low, forming a pulse. The output UP-DOWN signal is: in the first stage, the UP-DOWN signal and the UP-UP signal are identical pulse signals; in the second stage, the UP-DOWN signal and the UP-UP signal are inverted signals.

[0033] The compared output signals are separated and processed. Based on the compared output signals and the low-frequency clock, the UP-UP signal is sampled using the rising edge of the low-frequency clock to output the coarse quantization interval signal. The coarse quantization interval signal is XORed with the UP-UP signal and then logically ANDed with the UP-DOWN signal to obtain the fine quantization interval signal. The four rising and falling edges of the two coarse quantization interval signals correspond to the positions of the four fine quantization interval signals, forming a four-segment coarse and fine quantization structure.

[0034] The number of low-frequency clocks corresponding to the coarse quantization interval signal is counted.

[0035] The number of high-frequency clocks corresponding to the fine quantization interval signal is counted.

[0036] The obtained coarse quantization interval signal count value and fine quantization interval signal count value are processed to obtain a final quantization result.

[0037] The above-described embodiments are only preferred specific implementations of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A four-stage coarse-fine quantization system for analog-to-digital conversion of image sensors, characterized in that: It includes a ramp generator, a comparator, a coarse and fine quantization interval separation circuit, a high-frequency clock, a low-frequency clock, a digital processing circuit, a coarse quantization circuit and a fine quantization circuit; A ramp generator generates a ramp signal based on a periodic analog signal composed of a reset signal and an optical signal alternately arranged and output by an image sensor, wherein the period of the ramp signal is the same as that of the periodic analog signal; within each period, the ramp signal includes a short ramp signal and a long ramp signal with different amplitudes, both of which are signals that monotonically decrease from an initial voltage to an end voltage; a period in which the short ramp signal exists is recorded as a first stage, during which the periodic analog signal remains as a reset signal, the amplitude of the short ramp signal covers the swing of the reset signal, the initial voltage is higher than the highest value of the reset signal, and the end voltage is lower than the lowest value of the reset signal; a period in which the long ramp signal exists is recorded as a second stage, during which the periodic analog signal remains as an optical signal, the amplitude of the long ramp signal covers the swing of the optical signal, the initial voltage is higher than the highest value of the optical signal, and the end voltage is lower than the lowest value of the optical signal; A comparator compares the ramp signal generated by the ramp generator with the periodic analog signal and outputs the signal to a coarse and fine quantization interval separation circuit; The coarse and fine quantization interval separation circuit separates the comparator output signal into two coarse quantization interval signals and four fine quantization interval signals; wherein the four rising and falling edges of the two coarse quantization interval signals correspond to the positions of the four fine quantization interval signals, that is, a four-segment coarse and fine quantization structure is formed; The coarse quantization circuit counts the number of low-frequency clocks corresponding to the coarse quantization interval signal based on the low-frequency clock; A fine quantization circuit counts the number of high-frequency clocks corresponding to the fine quantization interval signal based on the high-frequency clock; The digital processing circuit processes the counting result of the coarse quantization circuit and the counting result of the fine quantization circuit into a final quantization result.

2. The four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors according to claim 1, characterized in that: The comparator compares the ramp signal generated by the ramp generator with the periodic analog signal, and outputs two signals, namely, an UP-UP signal and an UP-DOWN signal; The UP-UP signal is as follows: the signal is initially at a low level; at the starting point of the short ramp signal and the long ramp signal, the signal flips from a low level to a high level; during the falling process of the short ramp signal and the long ramp signal and when the amplitude does not reach the corresponding reset signal and optical signal amplitude in the periodic analog signal, the signal remains at a high level; when the amplitude of the short ramp signal and the long ramp signal drops to the corresponding reset signal and optical signal amplitude in the periodic analog signal, the signal flips from a high level to a low level, forming a pulse; The UP-DOWN signal is as follows: in the first stage, the UP-DOWN signal and the UP-UP signal are the same pulse signal; in the second stage, the UP-DOWN signal and the UP-UP signal are inverted signals.

3. The four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors according to claim 2, characterized in that: The coarse and fine quantization interval separation circuit includes a D flip-flop, a logic XOR gate circuit and a logic AND gate circuit; wherein the input of the D flip-flop is the UP-UP signal output by the comparator and the low-frequency clock, the UP-UP signal is sampled using the rising edge of the low-frequency clock, and a coarse quantization interval signal is output; the coarse quantization interval signal and the UP-UP signal are input into the logic XOR gate circuit for XOR operation; the signal output by the logic XOR gate circuit and the UP-DOWN signal are then input into the logic AND gate circuit for logic AND operation to obtain a fine quantization interval signal.

4. The four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors according to claim 3, characterized in that: The high-frequency signal and the low-frequency signal are two signals whose frequencies differ by 32 times.

5. The four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors according to claim 1, characterized in that: The coarse quantization circuit counts the number of coarse quantization interval signals based on the low-frequency clock. The counting method is: the coarse quantization interval signal adopts downward reduction counting in the first stage and upward increment counting in the second stage.

6. The four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors according to claim 1, characterized in that: The fine quantization circuit counts the number of fine quantization interval signals based on a high-frequency clock, and the counting method is: the fine quantization interval signal adopts downward reduction counting in the first pulse segment, upward increment counting in the second pulse segment, upward increment counting in the third pulse segment, and downward reduction counting in the fourth pulse segment; wherein, the first pulse segment and the second pulse segment are in the first stage, and the third pulse segment and the fourth pulse segment are in the second stage.

7. The four-stage coarse and fine quantization system for analog-to-digital conversion of image sensors according to claim 5 or 6, characterized in that: The method of quantization by the digital processing circuit is: the downward reduction count is equivalent to the subtraction of the count value, and the upward increment count is equivalent to the addition of the count value; the physical quantity corresponding to the counting result in the first stage is , the physical quantity corresponding to the second stage counting result is , the physical quantity corresponding to the final quantization result is ;in, is the voltage difference between the highest and lowest points of the ramp signal in the first stage, is the highest point voltage value of the two-stage ramp signal, is the reset voltage value of the image sensor pixel, is the voltage value of the image sensor pixel light signal.

8. A method for performing analog-to-digital conversion based on the four-stage coarse-fine quantization system for analog-to-digital conversion of image sensors according to claim 1, characterized in that: include: Processing the output signal of the photosensitive device of the image sensor into a periodic analog signal in which a reset signal and a light signal are alternately arranged; Based on the periodic analog signal, a ramp signal is generated; comparing the ramp signal with the periodic analog signal; The signals output after comparison are separated and processed to obtain two coarse quantization interval signals and four fine quantization interval signals; wherein the four rising and falling edges of the two coarse quantization interval signals correspond to the positions of the four fine quantization interval signals, that is, a four-segment coarse and fine quantization structure is formed; Counting the number of low-frequency clocks corresponding to the coarse quantization interval signal; counting the number of high-frequency clocks corresponding to the fine quantization interval signal; The obtained coarse quantization interval signal count value and fine quantization interval signal count value are processed to obtain a final quantization result.

9. The method for performing analog-to-digital conversion according to claim 8, characterized in that: Compare the ramp signal with the periodic analog signal, and output UP-UP signal and UP-DOWN signal; The output UP-UP signal is: the signal is initially at a low level; at the starting point of the short ramp signal and the long ramp signal, the signal flips from a low level to a high level; when the short ramp signal and the long ramp signal are decreasing and the amplitude does not reach the corresponding reset signal and optical signal amplitude in the periodic analog signal, the signal remains at a high level; when the short ramp signal and the long ramp signal amplitude decrease to the corresponding reset signal and optical signal amplitude in the periodic analog signal, the signal flips from a high level to a low level to form a pulse; The output UP-DOWN signal is: in the first stage, the UP-DOWN signal and the UP-UP signal are the same pulse signal; in the second stage, the UP-DOWN signal and the UP-UP signal are anti-phase signals.

10. The method for performing analog-to-digital conversion according to claim 9, characterized in that: The method for separating and processing the signal output after comparison is: using the rising edge of a low-frequency clock to sample the UP-UP signal and output a coarse quantization interval signal; performing an XOR operation on the coarse quantization interval signal and the UP-UP signal and then performing a logical AND operation with the UP-DOWN signal to obtain a fine quantization interval signal.

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