Communication chip

Abstract

The invention provides a communication chip, which works based on a hardware circuit and comprises a bus communication pin, a first local output pin, a second local output pin and a local signal input pin. And the first local output pin is used for decoding a twisted pair bus signal into a signal 0 or 1. And the second local output pin decodes 01 of the first local output pin into 0 and decodes 11 of the first local output pin into 1. And the bus communication pin is used for coding a signal 0 of the local signal input pin into 01 and coding 1 into 11. According to the configuration, encoding and decoding are carried out in a hardware decoding mode, software encoding and decoding do not need to be carried out in the MCU or other logic control devices, the calculation burden of the MCU or other logic control devices is relieved, the universality of the communication chip is improved, and a hardware basis is provided for implementation of other anti-interference functions. The communication chip can improve the long-distance communication effect, and solves the problems in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chips, and in particular to a communication chip. Background Art

[0002] In industrial applications such as commercial air conditioning, master-slave communication usually uses the HBS communication protocol (Home Bus System), which is a concept jointly proposed by Japanese companies: Hitachi, Mitsubishi, Panasonic, Toshiba, etc., and formulated by the HBS Standards Committee of the Japan Electronics Industry Federation / Wireless Engineering Electronics Association. The HBS protocol supports the use of a pair of twisted pair cables for communication and power supply between master and slave machines. The signal reception and transmission processing uses AMI encoding. The signals on the two transmission lines are differential signals (that is, both lines transmit signals, the two signals have the same amplitude and opposite phases; the signal receiving end compares the difference between the two voltages to determine the logical state sent by the sending end). The maximum communication distance is generally within 1000m, and the communication rate is generally 9600bps.

[0003] However, with the development of technology, there are more nodes in the communication network, the communication distance is longer, and the communication rate is also higher. In the more complex communication network, traditional solutions and communication chips face problems such as high bit error rate and slow device response speed. The communication effect of traditional solutions and communication chips is not good.

[0004] The specific analysis is as follows: the longer the communication distance and the higher the communication rate, the more serious the interference of the bus parasitic parameters on the signal transmitted on the bus will be, and there will be adverse phenomena such as signal oscillation or distortion. In order to ensure the accuracy of signal transmission on the bus, the previous solution is to add a matching resistor with a lower resistance between the buses of the farthest node in the communication network to reduce signal reflection and avoid oscillation, so as to achieve the purpose of improving signal quality. However, as the communication distance becomes longer and the communication rate becomes higher, the adverse effects caused by the bus parasitic parameters are more obvious. Some remote nodes close to the terminal resistor can still maintain a good communication effect, but most of the nodes far away from the terminal resistor may have abnormal communication. If you choose to add matching resistors between the buses at multiple nodes, it will cause the impedance between the buses to decrease and the bus current to increase. In severe cases, it will cause the signal amplitude to be pulled down and communication cannot be achieved. Therefore, it is not possible to improve the communication of each node by adding matching resistors between the buses at each node. A new communication solution and chip are needed to improve the communication of each node and reduce the influence of bus parasitic parameters on bus signals to meet more communication nodes, longer communication distances, and higher communication rates.

[0005] In short, for existing communication solutions, the impact caused by bus parasitic parameter interference is difficult to further improve or effectively avoid, and it cannot be applied to scenarios with longer communication distances and higher communication rates. Specific products may also be restricted and cannot be upgraded. Therefore, a new solution or communication chip is needed to ensure the quality of the bus signal and improve the communication effect. Summary of the invention

[0006] The object of the present invention is to provide a communication chip to solve the technical problem in the prior art of ensuring the quality of bus signals and improving communication effects.

[0007] In order to solve the above technical problems, the present invention provides a communication chip for HBS protocol communication, the communication chip works based on a hardware circuit, the communication chip comprises: a bus communication pin and an MCU communication pin, the MCU communication pin comprises a first local output pin, a second local output pin and a local signal input pin.

[0008] The first local output pin is used to output a signal 0 or 1 based on a differential value of the twisted pair bus signal received by the bus communication pin.

[0009] The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and to synchronously output signal 1 when the first local output pin outputs signal 11.

[0010] The bus communication pin is used to synchronously output a signal 01 when the signal of the local signal input pin is 0, and to synchronously output a signal 11 when the signal of the local signal input pin is 1.

[0011] Optionally, the communication chip also includes a PWM modulation signal pin, which is used to receive a PWM signal. The communication chip determines a duration of the signal between the bus communication pin and the first local output pin based on half a cycle of the PWM signal, and determines a duration of the signal between the second local output pin and the local signal input pin based on a cycle of the PWM signal.

[0012] Optionally, the communication chip further includes an impedance switching switch and a dynamic impedance matching pin, the bus communication pin includes two bus output pins, and in at least one connection mode of the communication chip, the dynamic impedance matching pin is used to externally connect a matching resistor.

[0013] The communication chip is used to connect the matching resistor between the two bus output pins through the impedance switching switch when the output signal of the bus output pin drops from a high level to an intermediate level or rises from a low level to an intermediate level, and is used to disconnect the matching resistor from the bus output pin through the impedance switching switch when the duration after connection reaches a preset time.

[0014] Optionally, the bus communication pin includes a bus output pin, and a voltage regulator tube for enhancing ESD protection capability is provided at the bus output pin.

[0015] Optionally, the communication chip further includes a signal pulse width correction pin, the bus communication pin includes a bus output pin, and the signal pulse width correction pin is used to externally connect a correction resistor.

[0016] In at least one connection relationship, the correction resistor is used to eliminate the influence of bus parasitic parameters to compensate for the high-level output pulse width of the bus output pin.

[0017] Optionally, in at least another connection relationship, the correction resistor is also used to actively adjust the high-level output pulse width of the bus output pin to adapt to different communication rates.

[0018] Optionally, the communication chip includes a decoding and error correction module for filtering out oscillations of bus signals, and the bus communication pin includes a bus input pin, and the bus input pin is connected to the MCU communication pin through the decoding and error correction module.

[0019] Optionally, the decoding error correction module includes a signal detection unit, a signal judgment unit, a reference potential providing unit and an output unit.

[0020] The signal detection unit is used for converting the twisted pair bus signal received by the bus input pin into two-channel first intermediate signals.

[0021] The reference potential providing unit is used to provide a reference voltage.

[0022] The signal determination unit is used to compare the first intermediate signal with the reference voltage. When any one of the first intermediate signals is greater than the reference voltage, the signal determination unit outputs a first level, otherwise, the signal determination unit outputs a second level.

[0023] The output unit is used to change its own output signal accordingly based on the output signal of the signal determination unit.

[0024] Among them, the signal detection unit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first constant current source, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode and an eighth triode.

[0025] The first end of the first resistor is used to receive one of the twisted pair bus signals, and the first end of the seventh resistor is used to receive the other of the twisted pair bus signals.

[0026] The first end of the first resistor is connected to the first ends of the second resistor, the fifth resistor and the seventh resistor in sequence, and the connection point between the second resistor and the fifth resistor is also connected to a working voltage.

[0027] The third transistor is an NPN transistor, the emitter of the third transistor is used to connect to a power supply, the base of the third transistor is connected to its collector, and the collector of the third transistor is connected to the second end of the first resistor.

[0028] The fourth transistor is an NPN transistor, the collector of the fourth transistor is connected to the power supply through the third resistor, the base of the fourth transistor is connected to the second end of the first resistor, and the collector of the fourth transistor is used to output one of the first intermediate signals.

[0029] The eighth transistor is an NPN transistor, the emitter of the eighth transistor is used to connect to a power supply, the base of the eighth transistor is connected to its own collector, and the collector of the eighth transistor is connected to the second end of the seventh resistor.

[0030] The sixth transistor is an NPN transistor, the collector of the sixth transistor is connected to the power supply through the sixth resistor, the base of the sixth transistor is connected to the second end of the seventh resistor, and the collector of the sixth transistor is used to output another path of the first intermediate signal.

[0031] The emitter of the fourth transistor is connected to the emitter of the sixth transistor through the fourth resistor.

[0032] The first transistor is an NPN transistor, the input end of the first constant current source is used to connect to a power source, the output end of the first constant current source is connected to the collector of the first transistor, and the emitter of the first transistor is used to be grounded.

[0033] The second transistor is an NPN transistor, the collector of the second transistor is used to connect to a power supply, the base of the second transistor is connected to the collector of the first transistor, and the emitter of the second transistor is connected to the base of the first transistor.

[0034] The fifth transistor is an NPN transistor, the collector of the fifth transistor is connected to the emitter of the fourth transistor, the base of the fifth transistor is connected to the base of the first transistor, and the emitter of the fifth transistor is grounded.

[0035] The seventh transistor is an NPN transistor, the collector of the seventh transistor is connected to the emitter of the sixth transistor, the base of the seventh transistor is connected to the base of the first transistor, and the emitter of the seventh transistor is used for grounding.

[0036] Optionally, the reference potential providing unit includes an eighth resistor, a second constant current source, a ninth triode, a tenth triode, an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode and a sixteenth triode.

[0037] The ninth transistor is an NPN transistor, the base of the ninth transistor is connected to the base of the first transistor, and the emitter of the ninth transistor is grounded.

[0038] The thirteenth transistor is an NPN transistor, the collector of the thirteenth transistor is connected to the collector of the ninth transistor, and the emitter of the thirteenth transistor is used for grounding.

[0039] The thirteenth transistor is an NPN transistor, the input end of the second constant current source is used to connect to a power supply, the output end of the second constant current source is connected to the collector of the thirteenth transistor, the collector of the thirteenth transistor is connected to its own base, the base of the thirteenth transistor is connected to the base of the thirteenth transistor, and the emitter of the thirteenth transistor is used for grounding.

[0040] The sixteenth transistor is an NPN transistor, the collector of the sixteenth transistor is connected to the collector of the thirteenth transistor, the emitter of the sixteenth transistor is used for grounding, and the base of the sixteenth transistor is used for receiving a second intermediate signal, and the second intermediate signal and the output signal of the output unit change simultaneously.

[0041] The first end of the eighth resistor is used to connect to a power source, and the second end of the eighth resistor is connected to the collector of the ninth transistor.

[0042] The eleventh transistor is an NPN transistor, the collector of the eleventh transistor is used to connect to a power supply, the base of the eleventh transistor is connected to the second end of the eighth resistor, and the emitter of the eleventh transistor is used to output the reference voltage.

[0043] The twelfth transistor is an NPN transistor, the collector of the twelfth transistor is connected to the emitter of the eleventh transistor, the emitter of the twelfth transistor is used for grounding, and the base of the twelfth transistor is connected to the base of the first transistor.

[0044] The fourteenth transistor is an NPN transistor, the collector of the fourteenth transistor is used to connect to a power supply, the base of the fourteenth transistor is connected to the second end of the eighth resistor, and the emitter of the fourteenth transistor is used to output the reference voltage.

[0045] The fifteenth transistor is an NPN transistor, the collector of the fifteenth transistor is connected to the emitter of the fourteenth transistor, the emitter of the fifteenth transistor is used for grounding, and the base of the fifteenth transistor is connected to the base of the first transistor.

[0046] Optionally, the signal judgment unit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twenty-third transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor and a thirty-third transistor.

[0047] The seventeenth triode, the eighteenth triode, the twenty-third triode, the twenty-second triode, the twenty-third triode, the twenty-fourth triode, the twenty-sixth triode, the twenty-eighth triode, the twenty-ninth triode and the thirty-third triode are all NPN triodes; the nineteenth triode, the twenty-first triode, the twenty-fifth triode and the twenty-seventh triode are all PNP triodes.

[0048] The collector of the seventeenth transistor is used to connect to a power supply, the collector of the eighteenth transistor is connected to the emitter of the seventeenth transistor, the base of the eighteenth transistor is connected to the base of the first transistor, the first end of the ninth resistor is used to connect to a power supply, the second end of the ninth resistor is connected to the emitter of the nineteenth transistor, the base of the nineteenth transistor is connected to the emitter of the seventeenth transistor, the collector of the twenty-third transistor is connected to the collector of the nineteenth transistor, the collector of the twenty-third transistor is also connected to its own base, and the second The emitter of the triode is used for grounding, the second end of the ninth resistor is also connected to the emitter of the twenty-first triode, the base of the twenty-first triode is used to obtain the reference voltage, the collector of the twenty-second triode is connected to the collector of the twenty-first triode, the emitter of the twenty-second triode is used for grounding, the base of the twenty-third triode is connected to the collector of the twenty-first triode through the tenth resistor, the emitter of the twenty-third triode is used for grounding, and the collector of the twenty-third triode is configured as the output end of the signal judgment unit.

[0049] The collector of the twenty-ninth transistor is used to connect to a power supply, the collector of the thirty-third transistor is connected to the emitter of the twenty-ninth transistor, the base of the thirty-third transistor is connected to the base of the first transistor, the first end of the twelfth resistor is used to connect to a power supply, the second end of the twelfth resistor is connected to the emitter of the twenty-seventh transistor, the base of the twenty-seventh transistor is connected to the emitter of the twenty-ninth transistor, the collector of the twenty-eighth transistor is connected to the collector of the twenty-seventh transistor, and the collector of the twenty-eighth transistor is also connected to its own base. The emitter of the twenty-eighth transistor is used for grounding, the second end of the twelfth resistor is also connected to the emitter of the twenty-fifth transistor, the base of the twenty-fifth transistor is used to obtain the reference voltage, the collector of the twenty-sixth transistor is connected to the collector of the twenty-fifth transistor, the emitter of the twenty-sixth transistor is used for grounding, the base of the twenty-fourth transistor is connected to the collector of the twenty-fifth transistor through the eleventh resistor, the emitter of the twenty-fourth transistor is used for grounding, and the collector of the twenty-fourth transistor is connected to the collector of the twenty-third transistor.

[0050] The base of the twenty-ninth transistor is used to receive one path of the first intermediate signal, and the base of the seventeenth transistor is used to receive the other path of the one intermediate signal.

[0051] Optionally, the output unit includes a thirteenth resistor, a fourteenth resistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, a forty-third transistor, a forty-first transistor and a forty-second transistor.

[0052] The thirty-first transistor is a PNP transistor, and the emitter of the thirty-first transistor is used to connect to a power supply.

[0053] The thirty-second transistor is an NPN transistor, the collector of the thirty-second transistor is connected to the collector of the thirty-first transistor, the emitter of the thirty-second transistor is used for grounding, and the collector of the thirty-second transistor is used to output a second intermediate signal, the second intermediate signal and the output signal of the output unit change simultaneously, and the second intermediate signal is used to provide a basis for logical judgment for other units of the decoding and error correction module.

[0054] The thirty-third transistor is a PNP type transistor, the emitter of the thirty-third transistor is used to connect to a power supply, the base of the thirty-third transistor is connected to the base of the thirty-first transistor, and the collector of the thirty-third transistor is connected to the base of the thirty-second transistor.

[0055] The thirty-fourth transistor is an NPN transistor, the collector of the thirty-fourth transistor is connected to the collector of the thirty-third transistor, and the emitter of the thirty-fourth transistor is used for grounding.

[0056] The thirty-fifth transistor is a PNP type transistor, the emitter of the thirty-fifth transistor is used to connect to a power supply, the base of the thirty-fifth transistor is connected to the base of the thirty-first transistor, the collector of the thirty-fifth transistor is connected to the base of the thirty-fourth transistor through the thirteenth resistor, and the collector of the thirty-fifth transistor is also connected to the output end of the signal judgment unit.

[0057] The thirty-sixth transistor is a PNP transistor, the emitter of the thirty-sixth transistor is used to connect to a power supply, and the base of the thirty-sixth transistor is connected to the base of the thirty-first transistor.

[0058] The thirty-seventh transistor is an NPN transistor, the collector of the thirty-seventh transistor is connected to the collector of the thirty-sixth transistor, the base of the thirty-seventh transistor is connected to the collector of the thirty-fifth transistor through the fourteenth resistor, and the emitter of the thirty-seventh transistor is used for grounding.

[0059] The thirty-eighth transistor is a PNP transistor, the emitter of the thirty-eighth transistor is used to connect to a power supply, and the base of the thirty-eighth transistor is connected to the base of the thirty-first transistor.

[0060] The thirty-ninth transistor is an NPN transistor, the collector of the thirty-ninth transistor is connected to the collector of the thirty-eighth transistor, the base of the thirty-ninth transistor is connected to the collector of the thirty-sixth transistor, the emitter of the thirty-ninth transistor is used for grounding, and the collector of the thirty-ninth transistor is also configured as the output end of the output unit.

[0061] The forty-third transistor is a PNP transistor, the emitter of the forty-third transistor is connected to the base of the thirty-first transistor, and the collector of the forty-third transistor is used for grounding.

[0062] The forty-first transistor is a PNP transistor, the emitter of the forty-first transistor is used to connect to a power supply, and the collector of the forty-first transistor is connected to the base of the forty-third transistor.

[0063] The 42nd transistor is an NPN transistor, the collector of the 42nd transistor is connected to the collector of the 41st transistor, the base of the 42nd transistor is connected to the base of the first transistor, and the emitter of the 42nd transistor is used for grounding.

[0064] Optionally, the communication chip further includes at least one of the following pins: a bootstrap capacitor pin, a reset control input pin, a power input pin, and a ground pin.

[0065] Compared with the prior art, the communication chip provided by the present invention works based on a hardware circuit, and the communication chip includes: a bus communication pin and an MCU communication pin, and the MCU communication pin includes a first local output pin, a second local output pin and a local signal input pin. The first local output pin is used to output a signal 0 or 1 based on a differential value of the twisted pair bus signal received by the bus communication pin. The second local output pin is used to synchronously output a signal 0 when the first local output pin outputs a signal 01, and synchronously output a signal 1 when the first local output pin outputs a signal 11. The bus communication pin is used to synchronously output a signal 01 when the signal of the local signal input pin is 0, and synchronously output a signal 11 when the signal of the local signal input pin is 1. In this configuration, encoding and decoding are performed in a hardware decoding manner, and there is no need for software encoding and decoding inside the MCU or other logic control devices, which reduces the calculation burden of the MCU or other logic control devices, increases the versatility of the communication chip, and provides a hardware basis for the implementation of other anti-interference functions. The communication chip can improve the long-distance communication effect and solve the problems existing in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0067] Figure 1 is a connection diagram of a communication chip according to an embodiment of the present invention;

[0068] Figure 2 is a pin diagram of a communication chip according to an embodiment of the present invention;

[0069] Figure 3 is a signal timing sequence of a communication chip according to an embodiment of the present invention;

[0070] Figure 4 It is an abnormal waveform diagram of a communication chip without dynamic impedance matching in the prior art;

[0071] Figure 5 The waveform diagram of the communication chip of one embodiment of the present invention is shown in FIG. Figure 1 ;

[0072] Figure 6 The waveform diagram of the communication chip of one embodiment of the present invention is shown in FIG. Figure 2 ;

[0073] Figure 7 It is a waveform comparison diagram of a communication chip of the prior art and an embodiment of the present invention;

[0074] Figure 8It is an abnormal waveform diagram of a communication chip without decoding and error correction function in the prior art;

[0075] Fig. 9 The waveform diagram of the communication chip of one embodiment of the present invention is shown in FIG. Figure 3 ;

[0076] Fig.10 4 is a circuit diagram of a decoding and error correction module according to an embodiment of the present invention.

[0077] in:

[0078] 1-Signal detection unit; 2-Reference potential providing unit; 3-Signal judgment unit; 4-Output unit. DETAILED DESCRIPTION

[0079] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0080] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0081] The core idea of ​​the present invention is to provide a communication chip to solve the technical problem in the prior art of ensuring the quality of bus signals and improving communication effects.

[0082] The following description is given with reference to the accompanying drawings.

[0083] In order to solve the problems in the above DC carrier communication solution, this embodiment proposes a communication chip and an internal structure, such as Figure 1 As shown. The chip pins can be compatible with existing solutions in the existing technology to increase compatibility; and by further improving the integration, the functions of some pins are redefined; the effect is achieved: the chip can reduce bus parasitic parameter interference to improve communication effects, increase the communication rate to 200Kbps, and support various communication topologies.

[0084] Compared with the prior art, this embodiment has the following five new functions:

[0085] 1. Built-in encoding function, changes the signal TXD sent by MCU to this communication chip from "0" to "01" and "1" to "11". This part of the encoding work previously needed to be completed by MCU software coding. Now it is integrated into the chip without software coding, reducing the occupation of MCU resources.

[0086] 2. Built-in decoding function, which changes the bus signal received by this communication chip from "01" to "0" and "11" to "1". This part of the decoding work previously needed to be completed by MCU software decoding. Now it is integrated into the chip without software decoding, reducing the occupation of MCU resources; at the same time, the decoded waveform can be corrected through other pins to compensate for the problem of insufficient high-level pulse width caused by complex working conditions, thereby improving communication quality.

[0087] 3. Built-in dynamic impedance matching function. In the solution based on HBS communication protocol, only one device sends a signal at the same time. The dynamic impedance matching function in the communication chip is enabled when the chip sends a signal. The internal switch control of the chip quickly pulls the two bus potentials to be equal, so that the bus differential value is stabilized to 0 and the decoding is stabilized to 1. This function can solve the problem that the bus differential waveform on the transmission line is not "steep" enough or even oscillates when it changes from "low level to middle level" or "high level to middle level", ensuring the accuracy of the decoded signal. Because the dynamic impedance matching function of only one node is in effect at the same time, it will not produce the situation where multiple matching resistors are incorporated into the bus like in previous communication solutions, resulting in a decrease in the impedance between the buses. The intervention time of the dynamic impedance matching function can also be adjusted to further reduce the bus power consumption.

[0088] 4. Built-in signal correction function, through this function can compensate for the high-level pulse width of the decoding signal (referring to the RXD signal finally given to the MCU), improve the previous communication scheme under complex conditions such as long-distance communication, and ensure the communication quality.

[0089] 5. Built-in decoding error correction function. By building in the decoding error correction function in the bus signal receiving pin of the communication chip, the bit errors caused by bus interference or oscillation can be solved, and the decoding accuracy and stability can be improved.

[0090] Specifically, the communication chip is used for HBS protocol communication. The communication chip works based on a hardware circuit. The communication chip includes: a bus communication pin and an MCU communication pin. The MCU communication pin includes a first local output pin, a second local output pin and a local signal input pin.

[0091] Figure 1 In the figure, the numbers 1 to 16 represent the pin numbers, which are the abbreviations of PIN1 to PIN16, not the figure numbers. Figure 2 This should also be understood. Figure 1 XL1195 is the serial number of the communication chip.

[0092] In this embodiment, PIN9-OUT(A), PIN10-OUT(B), PIN15-IN2, and PIN16-IN1 are the bus communication pins; PIN1-DATA OUTA is the first local output pin, PIN2-DATA OUTB is the second local output pin, and PIN6-DATA IN is the local signal input pin. Figure 2 To understand.

[0093] The first local output pin is used to output a signal of 0 or 1 based on a differential value of the twisted pair bus signal received by the bus communication pin.

[0094] The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and to synchronously output signal 1 when the first local output pin outputs signal 11.

[0095] The bus communication pin is used to synchronously output a signal 01 when the signal of the local signal input pin is 0, and to synchronously output a signal 11 when the signal of the local signal input pin is 1.

[0096] It can be understood that the signal durations of the bus communication pin, the first local output pin, the second local output pin and the local signal input pin are not exactly the same, and their specific lengths and proportional relationships between them can be understood based on the above description.

[0097] The above logic can also refer to Figure 3 To understand, Figure 3 In the example, the signal output by the MCU is the initial signal. If there is no abnormality in the communication link, the signal of the local signal input pin is consistent with the initial signal. The internal encoding logic of the communication chip is to convert 0 to 01, 1 to 11, and then output the desired twisted pair bus signal on the bus. Figure 3 As shown, when the absolute value of the difference of the signal is larger, it is regarded as 1, otherwise it is regarded as 0. If necessary, the internal coding signal can also be output through the first local output pin and the second local output pin. The output logic has been described in the previous text. Its waveform is as follows Figure 3 shown.

[0098] Through the encoding and decoding of the internal hardware circuit of the communication chip, the chip has more powerful functions and higher integration, does not require software encoding and decoding, and reduces the occupation of MCU resources.

[0099] The communication chip also includes a PWM modulation signal pin, which is used to receive a PWM signal. The communication chip determines a duration of the signal between the bus communication pin and the first local output pin based on a half cycle of the PWM signal, and determines a duration of the signal between the second local output pin and the local signal input pin based on a cycle of the PWM signal. PIN7-PWM is the PWM modulation signal pin. The above logic can also refer to Figure 3 To understand.

[0100] The communication chip further includes an impedance switching switch and a dynamic impedance matching pin, the bus communication pin includes two bus output pins, and in at least one connection mode of the communication chip, the dynamic impedance matching pin is used to connect an external matching resistor. PIN8-RT is the dynamic impedance matching pin, and RT is the matching resistor.

[0101] The communication chip is used to connect the matching resistor between the two bus output pins through the impedance switching switch when the output signal of the bus output pin drops from a high level to an intermediate level or rises from a low level to an intermediate level, and is used to disconnect the matching resistor from the bus output pin through the impedance switching switch when the duration after connection reaches a preset time.

[0102] like Figure 4 As shown in the figure, under complex working conditions such as long-distance communication, due to the large parasitic parameters of the bus, the signal transmitted on the bus will be significantly interfered, causing it to oscillate when it turns to the intermediate level. The communication chip in the previous HBS communication solution cannot completely eliminate such interference under long-distance communication, which will cause abnormal decoding signals, a certain bit error rate in the communication equipment, slow response speed and even unsuccessful communication. The chip with dynamic impedance matching function has a communication effect such as Figure 5 As shown in the figure, the dynamic impedance matching function can be enabled at the rising edge of the signal after the internal encoding of DATA IN and PWM signal. The built-in matching resistor is connected in parallel to PIN9 (OUTA) and PIN10 (OUTB) through the internal switch to improve the signal transmitted on the bus, making its waveform steep and stable when it turns to the intermediate level. In addition, the dynamic impedance matching equalization time can be adjusted by adjusting the chip PIN8 (RT) resistance to reduce the bus power consumption. Figure 4 and Figure 5 The circled part is the main focus.

[0103] The dynamic impedance matching pin may also be connected to the PIN11-VCC pin when not in use.

[0104] Furthermore, the bus communication pin includes a bus output pin, and a voltage regulator is provided at the bus output pin to enhance the ESD (Electro-Static Discharge) protection capability. The bus output pins are PIN9-OUT (A) and PIN10-OUT (B). Since PIN9 and PIN10 are connected to the bus through capacitors, the interference voltage on the bus, especially high-voltage glitches such as coupled strong electric signals and lightning surges, will cause breakdown damage to the 9 and 10 pins of the chip; by adding a voltage regulator at the 9 and 10 pins (increasing the wafer area of ​​the voltage regulator to increase its instantaneous power bearing capacity) to absorb high-voltage, high-frequency, and high-energy glitches, the ESD protection capability is enhanced to protect the chip from being damaged by interference signals such as static electricity and glitches on the bus.

[0105] The communication chip further comprises a signal pulse width correction pin, the bus communication pin comprises a bus output pin, and the signal pulse width correction pin is used for externally connecting a correction resistor.

[0106] In at least one connection relationship, the correction resistor is used to eliminate the influence of bus parasitic parameters to compensate for the high-level output pulse width of the bus output pin. PIN14-RD is the signal pulse width correction pin, and RD is the correction resistor. In this embodiment, the correction resistor is used to compensate the output signal of PIN2-DATAOUTB. In other embodiments, other output signals can be compensated according to different pin settings.

[0107] In this embodiment, the pulse width correction function is bidirectional, and can make the high level pulse width of the DATAOUTB signal greater than 50% or less than 50%, so as to adapt to different communication rates and ensure that normal communication can be achieved within the range of 9.6-200Kbps without changing the hardware circuit. That is, in at least another connection relationship, the correction resistor is also used to actively adjust the high level output pulse width of the bus output pin to adapt to different communication rates.

[0108] like Figure 6 As shown in the figure, under complex working conditions such as long-distance communication, due to the large bus parasitic parameters, the signal transmitted on the bus will be significantly interfered. The bus signal is not fast and steep enough when turning to the intermediate level. The communication chip in the previous HBS communication solution cannot completely eliminate such interference under long-distance communication, which will lead to insufficient high-level pulse width of the decoded signal and affect the communication quality. The chip with signal correction function can compensate for the high-level pulse width of the DATA OUT (B) signal under complex working conditions by adjusting the PIN14 (RD) resistance value, so that it is basically consistent with the DATAIN signal, ensuring the communication quality.

[0109] The communication chip includes a decoding error correction module, the bus communication pin includes a bus input pin, the bus input pin is connected to the MCU communication pin through the decoding error correction module, and the decoding error correction module is used to filter out the oscillation of the bus signal to ensure the accuracy of the output signal of the MCU communication pin. The bus input pins are PIN15-IN2 and PIN16-IN1.

[0110] In the past, HBS communication chips simply obtained logic "0" or "1" by judging the size of the bus signal differential value. For example, if the bus signal differential value was greater than a0 (a certain value), it would obtain logic "0", and if it was less than a0, it would obtain logic "1". However, the decoding signal flip point of the chip with decoding and error correction function is different. The flip start point (rising edge) of the decoding signal is VH, and the closing point (falling edge) is VL.

[0111] The schematic diagram of the decoding error correction function on the communication effect is as follows Figure 7 , Figure 8 , Fig. 9 shown. Figure 8 Combination Fig. 9 Content and Figure 7 The content is essentially the same, but Figure 8 and Fig. 9 It is a simulation result diagram, which is more convincing. Figure 8 and Fig. 9 In the figure, yellow and green represent one of the twisted pair bus signals respectively; pink: bus differential signal waveform; blue: DATA OUT waveform. Figure 7 to Figure 9 In the above description, DATA OUT should be understood as follows: when it represents the prior art, since there is only one local output pin in the prior art, it represents the signal of the local output pin; when it represents the present embodiment, it represents the signal of DATAOUT (A). For bus signal oscillation caused by the influence of bus parasitic parameters during long-distance communication, the chip with decoding and error correction function can use the principle of signal inversion decoding to suppress the interference signal received from the bus and ensure the accuracy of the decoded signal. In the past, the decoding signal of the HBS communication chip without decoding and error correction function will inevitably have certain signal anomalies, resulting in signal errors.

[0112] from Figure 7 to Figure 9 It can be seen from the content that when there is no decoding error correction module, the communication chip is prone to decoding signal errors, while when there is a decoding error correction module, the communication chip is not prone to decoding signal errors.

[0113] Specifically, please refer to Fig.10 The decoding error correction module includes a signal detection unit 1, a signal judgment unit 3, a reference potential providing unit 2 (also can be understood as an error correction unit) and an output unit 4.

[0114] The signal detection unit 1 is used to convert the twisted pair bus signal received by the bus input pin into two first intermediate signals (ie, output signals at points A and B in the figure).

[0115] The reference potential providing unit 2 is used to provide a reference voltage (ie, the voltage at points F1 and F2 in the figure).

[0116] The signal determination unit 3 is used to compare the first intermediate signal with the reference voltage. When any one of the first intermediate signals is greater than the reference voltage, the signal determination unit 3 outputs a first level, otherwise, it outputs a second level.

[0117] The output unit 4 is used to change its own output signal accordingly based on the output signal of the signal determination unit 3 .

[0118] Among them, the signal detection unit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first constant current source IS1, a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4, a fifth triode Q5, a sixth triode Q6, a seventh triode Q7 and an eighth triode Q8.

[0119] The first end of the first resistor is used to receive one of the twisted pair bus signals, and the first end of the seventh resistor is used to receive the other of the twisted pair bus signals.

[0120] The first end of the first resistor is connected to the first ends of the second resistor, the fifth resistor and the seventh resistor in sequence, and the connection point between the second resistor and the fifth resistor is also connected to a working voltage.

[0121] The third transistor is an NPN transistor, the emitter of the third transistor is used to connect to a power supply, the base of the third transistor is connected to its collector, and the collector of the third transistor is connected to the second end of the first resistor.

[0122] The fourth transistor is an NPN transistor, the collector of the fourth transistor is connected to the power supply through the third resistor, the base of the fourth transistor is connected to the second end of the first resistor, and the collector of the fourth transistor is used to output one of the first intermediate signals.

[0123] The eighth transistor is an NPN transistor, the emitter of the eighth transistor is used to connect to a power supply, the base of the eighth transistor is connected to its own collector, and the collector of the eighth transistor is connected to the second end of the seventh resistor.

[0124] The sixth transistor is an NPN transistor, the collector of the sixth transistor is connected to the power supply through the sixth resistor, the base of the sixth transistor is connected to the second end of the seventh resistor, and the collector of the sixth transistor is used to output another path of the first intermediate signal.

[0125] The emitter of the fourth transistor is connected to the emitter of the sixth transistor through the fourth resistor.

[0126] The first transistor is an NPN transistor, the input end of the first constant current source is used to connect to a power source, the output end of the first constant current source is connected to the collector of the first transistor, and the emitter of the first transistor is used to be grounded.

[0127] The second transistor is an NPN transistor, the collector of the second transistor is used to connect to a power supply, the base of the second transistor is connected to the collector of the first transistor, and the emitter of the second transistor is connected to the base of the first transistor.

[0128] The fifth transistor is an NPN transistor, the collector of the fifth transistor is connected to the emitter of the fourth transistor, the base of the fifth transistor is connected to the base of the first transistor, and the emitter of the fifth transistor is grounded.

[0129] The seventh transistor is an NPN transistor, the collector of the seventh transistor is connected to the emitter of the sixth transistor, the base of the seventh transistor is connected to the base of the first transistor, and the emitter of the seventh transistor is used for grounding.

[0130] The reference potential providing unit 2 includes an eighth resistor R8, a second constant current source IS2, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15 and a sixteenth transistor Q16.

[0131] The ninth transistor is an NPN transistor, the base of the ninth transistor is connected to the base of the first transistor, and the emitter of the ninth transistor is grounded.

[0132] The thirteenth transistor is an NPN transistor, the collector of the thirteenth transistor is connected to the collector of the ninth transistor, and the emitter of the thirteenth transistor is used for grounding.

[0133] The thirteenth transistor is an NPN transistor, the input end of the second constant current source is used to connect to a power supply, the output end of the second constant current source is connected to the collector of the thirteenth transistor, the collector of the thirteenth transistor is connected to its own base, the base of the thirteenth transistor is connected to the base of the thirteenth transistor, and the emitter of the thirteenth transistor is used for grounding.

[0134] The sixteenth transistor is an NPN transistor, the collector of the sixteenth transistor is connected to the collector of the thirteenth transistor, the emitter of the sixteenth transistor is used for grounding, and the base of the sixteenth transistor is used for receiving a second intermediate signal, and the second intermediate signal and the output signal of the output unit change simultaneously.

[0135] The first end of the eighth resistor is used to connect to a power source, and the second end of the eighth resistor is connected to the collector of the ninth transistor.

[0136] The eleventh transistor is an NPN transistor, the collector of the eleventh transistor is used to connect to a power supply, the base of the eleventh transistor is connected to the second end of the eighth resistor, and the emitter of the eleventh transistor is used to output the reference voltage.

[0137] The twelfth transistor is an NPN transistor, the collector of the twelfth transistor is connected to the emitter of the eleventh transistor, the emitter of the twelfth transistor is used for grounding, and the base of the twelfth transistor is connected to the base of the first transistor.

[0138] The fourteenth transistor is an NPN transistor, the collector of the fourteenth transistor is used to connect to a power supply, the base of the fourteenth transistor is connected to the second end of the eighth resistor, and the emitter of the fourteenth transistor is used to output the reference voltage.

[0139] The fifteenth transistor is an NPN transistor, the collector of the fifteenth transistor is connected to the emitter of the fourteenth transistor, the emitter of the fifteenth transistor is used for grounding, and the base of the fifteenth transistor is connected to the base of the first transistor.

[0140] The signal judgment unit 3 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twenty-third transistor Q20, a twenty-first transistor Q21, a twenty-second transistor Q22, a twenty-third transistor Q23, a twenty-fourth transistor Q24, a twenty-fifth transistor Q25, a twenty-sixth transistor Q26, a twenty-seventh transistor Q27, a twenty-eighth transistor Q28, a twenty-ninth transistor Q29 and a thirty-third transistor Q30.

[0141] The seventeenth triode, the eighteenth triode, the twenty-third triode, the twenty-second triode, the twenty-third triode, the twenty-fourth triode, the twenty-sixth triode, the twenty-eighth triode, the twenty-ninth triode and the thirty-third triode are all NPN triodes; the nineteenth triode, the twenty-first triode, the twenty-fifth triode and the twenty-seventh triode are all PNP triodes.

[0142] The collector of the seventeenth transistor is used to connect to a power supply, the collector of the eighteenth transistor is connected to the emitter of the seventeenth transistor, the base of the eighteenth transistor is connected to the base of the first transistor, the first end of the ninth resistor is used to connect to a power supply, the second end of the ninth resistor is connected to the emitter of the nineteenth transistor, the base of the nineteenth transistor is connected to the emitter of the seventeenth transistor, the collector of the twenty-third transistor is connected to the collector of the nineteenth transistor, the collector of the twenty-third transistor is also connected to its own base, and the second The emitter of the triode is used for grounding, the second end of the ninth resistor is also connected to the emitter of the twenty-first triode, the base of the twenty-first triode is used to obtain the reference voltage, the collector of the twenty-second triode is connected to the collector of the twenty-first triode, the emitter of the twenty-second triode is used for grounding, the base of the twenty-third triode is connected to the collector of the twenty-first triode through the tenth resistor, the emitter of the twenty-third triode is used for grounding, and the collector of the twenty-third triode is configured as the output end of the signal judgment unit.

[0143] The collector of the twenty-ninth transistor is used to connect to a power supply, the collector of the thirty-third transistor is connected to the emitter of the twenty-ninth transistor, the base of the thirty-third transistor is connected to the base of the first transistor, the first end of the twelfth resistor is used to connect to a power supply, the second end of the twelfth resistor is connected to the emitter of the twenty-seventh transistor, the base of the twenty-seventh transistor is connected to the emitter of the twenty-ninth transistor, the collector of the twenty-eighth transistor is connected to the collector of the twenty-seventh transistor, and the collector of the twenty-eighth transistor is also connected to its own base. The emitter of the twenty-eighth transistor is used for grounding, the second end of the twelfth resistor is also connected to the emitter of the twenty-fifth transistor, the base of the twenty-fifth transistor is used to obtain the reference voltage, the collector of the twenty-sixth transistor is connected to the collector of the twenty-fifth transistor, the emitter of the twenty-sixth transistor is used for grounding, the base of the twenty-fourth transistor is connected to the collector of the twenty-fifth transistor through the eleventh resistor, the emitter of the twenty-fourth transistor is used for grounding, and the collector of the twenty-fourth transistor is connected to the collector of the twenty-third transistor.

[0144] The base of the twenty-ninth transistor is used to receive one path of the first intermediate signal, and the base of the seventeenth transistor is used to receive the other path of the one intermediate signal.

[0145] The output unit 4 includes a thirteenth resistor R13, a fourteenth resistor R14, a thirty-first transistor Q31, a thirty-second transistor Q32, a thirty-third transistor Q33, a thirty-fourth transistor Q34, a thirty-fifth transistor Q35, a thirty-sixth transistor Q36, a thirty-seventh transistor Q37, a thirty-eighth transistor Q38, a thirty-ninth transistor Q39, a forty-third transistor Q40, a forty-first transistor Q41, and a forty-second transistor Q42.

[0146] The thirty-first transistor is a PNP transistor, and the emitter of the thirty-first transistor is used to connect to a power supply.

[0147] The thirty-second transistor is an NPN transistor, the collector of the thirty-second transistor is connected to the collector of the thirty-first transistor, the emitter of the thirty-second transistor is used for grounding, and the collector of the thirty-second transistor is used to output a second intermediate signal, the second intermediate signal and the output signal of the output unit change simultaneously, and the second intermediate signal is used to provide a basis for logical judgment for other units of the decoding and error correction module.

[0148] The thirty-third transistor is a PNP type transistor, the emitter of the thirty-third transistor is used to connect to a power supply, the base of the thirty-third transistor is connected to the base of the thirty-first transistor, and the collector of the thirty-third transistor is connected to the base of the thirty-second transistor.

[0149] The thirty-fourth transistor is an NPN transistor, the collector of the thirty-fourth transistor is connected to the collector of the thirty-third transistor, and the emitter of the thirty-fourth transistor is used for grounding.

[0150] The thirty-fifth transistor is a PNP type transistor, the emitter of the thirty-fifth transistor is used to connect to a power supply, the base of the thirty-fifth transistor is connected to the base of the thirty-first transistor, the collector of the thirty-fifth transistor is connected to the base of the thirty-fourth transistor through the thirteenth resistor, and the collector of the thirty-fifth transistor is also connected to the output end of the signal judgment unit.

[0151] The thirty-sixth transistor is a PNP transistor, the emitter of the thirty-sixth transistor is used to connect to a power supply, and the base of the thirty-sixth transistor is connected to the base of the thirty-first transistor.

[0152] The thirty-seventh transistor is an NPN transistor, the collector of the thirty-seventh transistor is connected to the collector of the thirty-sixth transistor, the base of the thirty-seventh transistor is connected to the collector of the thirty-fifth transistor through the fourteenth resistor, and the emitter of the thirty-seventh transistor is used for grounding.

[0153] The thirty-eighth transistor is a PNP transistor, the emitter of the thirty-eighth transistor is used to connect to a power supply, and the base of the thirty-eighth transistor is connected to the base of the thirty-first transistor.

[0154] The thirty-ninth transistor is an NPN transistor, the collector of the thirty-ninth transistor is connected to the collector of the thirty-eighth transistor, the base of the thirty-ninth transistor is connected to the collector of the thirty-sixth transistor, the emitter of the thirty-ninth transistor is used for grounding, and the collector of the thirty-ninth transistor is also configured as the output end of the output unit.

[0155] The forty-third transistor is a PNP transistor, the emitter of the forty-third transistor is connected to the base of the thirty-first transistor, and the collector of the forty-third transistor is used for grounding.

[0156] The forty-first transistor is a PNP transistor, the emitter of the forty-first transistor is used to connect to a power supply, and the collector of the forty-first transistor is connected to the base of the forty-third transistor.

[0157] The 42nd transistor is an NPN transistor, the collector of the 42nd transistor is connected to the collector of the 41st transistor, the base of the 42nd transistor is connected to the base of the first transistor, and the emitter of the 42nd transistor is used for grounding.

[0158] Fig.10 In the embodiment, VDD and VCC are both power supplies, but with different voltage values. In one embodiment, VDD is 2.5V and VCC is 5V.

[0159] The working logic of the decoding error correction module is described as follows:

[0160] In the signal detection unit 1, VDD is a 2.5V constant voltage source, IS1 is a constant current source 1, and multiple 1:1 mirror currents are formed through Q1, Q5, Q7, Q9, Q12, Q15, Q18, etc.; constant current source IS2=0.1IS1, resistors R2=R5, R1=R7, R3=R6, (resistor R8 has a smaller resistance than R3, so that the current on resistors R8, R3 or R6 is the same, but the voltage drop is different) resistor R4 is used to adjust the base voltage difference of Q4 and Q6, that is, when the base voltage difference of Q4 and Q6 reaches a preset value, when the IC current difference of Q4 and Q6 reaches a preset value, the voltage at point A or B is lower than the voltage at point G. For example, when the voltage of IN2 is higher than the voltage of IN1 by a first preset value, the emitter current of Q6 is greater than the emitter current of Q4. Since the current drawn by Q7 is fixed, the excess current will flow to Q5 through R4. This current is defined as IR4. The difference between the base voltage of Q6 and the base voltage of Q4 is the product of IR4 and the resistance value of R4, which is the first preset value. Since the current flowing through Q4 is reduced, the potential at point A is raised (higher than the potential at point G), which can be considered as the output of the signal detection unit 1 at a high level. Similarly, if the potential of IN1 is higher than the potential of IN2 by a first preset value, the potential at point B will be higher than the potential at point G, which can be considered as the output of the signal detection unit 1 at a high level. When the voltage difference between the two is less than the first preset value, the emitter currents of Q4 and Q6 are not much different and are both near IS1, so the potentials at points A and B will be lower than the potential at point G, which can be considered as the output of the signal detection unit 1 module at a low level.

[0161] In the signal judgment unit 3, the voltage of point C is VBE lower than that of point B, and the voltage of point H is VBE lower than that of point A; points F1 and F2 are VBE lower than that of point G, and the potentials of A / B and G are compared, and the equivalent H / C is compared with F1 / F2. When point H is higher than F2, or point C is higher than F1, the output terminal point J of the signal judgment unit 3 is at a low potential; when point H is lower than point F2, and point C is lower than point F1, the output terminal point J of the signal judgment unit 3 is at a high potential.

[0162] The output unit 4, when the input terminal J is at a low potential, DATA OUTA outputs a low level, and QB is low, at this time I1 = IQ9 + IQ10; when the input terminal J is at a high level, DATA OUTA outputs a high level, and QB is high, at this time I1 = IQ9. It can be understood that in different embodiments, DATA OUTA can be used as the output pin of the communication chip, or indirectly connected to the first local output pin through other modules to output the signal. The signal at QB is also the second intermediate signal.

[0163] The reference potential providing unit 2, when the input terminal QB is at a low level, I1=IQ9+IQ10, when the input terminal QB is at a high level, I1=IQ9; since the G point voltage=VC-R8*I1, the corresponding G point voltage when QB is high is higher than when QB is low; this potential provides a reference potential to the comparator in the signal judgment unit 3, and due to the change of this potential, the corresponding flip points of IN1 and IN2 in the signal detection unit 1 will change, which can effectively filter out the burr signals at IN1 and IN2, and the four units together realize the signal decoding and error correction function.

[0164] The working process of the decoding and error correction module is as follows: The signal detection unit 1 is used to collect the difference signal between signals IN1 and IN2. When the absolute value of the difference in signal amplitude reaches and is greater than the first preset value, it outputs a high-level signal (either A is high or B is high, where this high is compared with the potential of point G). When the signal judgment unit 3 detects that A or B is a high-level signal (the high level is relative to the potential of point G), it outputs a low-level signal. When the output unit 4 detects that the input signal is low, DATAOUTA outputs a low-level signal, and at the same time, the QB signal is low. When the reference potential providing unit 2 detects that QB is low, the current I1 flowing through resistor R8 is I1 = IS1 + IS2, and the voltage at point G is G1 = VCC - I1 * R8. Conversely, when the absolute difference between IN1 and IN2 in the SATAGE1 module is less than the second preset value, the voltage values of output signals A and B are close, but both voltages are lower than the voltage at point G. Then the signal judgment unit 3 outputs a high level, DATA OUTA of the output unit 4 outputs a high level, and at this time, QB is also at a high level. QB conducts, pulling IS2 to ground. Then the current I1' on resistor R8 is I1' = IS1 (Q9 and Q1 form a 1:1 current mirror), and the voltage at point G is G2 = VCC - I1' * R8. Since I1 > I1', the voltage G1 < G2. Since DATAOUA flips once, the voltage at point G changes once, that is, the reference voltage of the signal judgment unit 3 also changes once. When the entire large module detects that the bus difference signal reaches and is greater than the first preset value, it starts to flip (realizing that the output DATAOUTA signal is low), and synchronously adjusts the preset voltage value. The preset value decreases (realizing the function that when DATAOUTA outputs a low level, the flip point is adjusted to the second preset value, and when DATAOUTA outputs a high level, the flip point is adjusted to the first preset value. The voltage of the first preset value is greater than the voltage of the second preset value; it can be understood as similar to a hysteresis function). In this way, each time the pressure difference between IN1 and IN2 is greater than the first preset value, it will flip and output, and the DATA OUTA signal will output low. This can avoid misinterpreting the oscillation signal on the bus. Compared with existing products, it will not output misinterpreted signals and realizes the decoding and error correction function. Existing products do not have this function. When the bus differential signal changes from high to low, there will be oscillations on the bus, resulting in low-level signals being mixed in the high-level output signal DATA OUTA, affecting the communication quality.

[0165] Please continue to refer to Figure 1 Or Figure 2 , the communication chip further includes the following pins: PIN3 - BC1, PIN4 - BC2 which are bootstrap capacitor pins, PIN5 - RESET which is a reset control input pin, PIN11 - VCC which is a power input pin, PIN13 - GND which is a ground pin, and PIN12 - NC which is a no - connection pin.

[0166] The external connection relationship of the communication chip can be referred to Figure 1 To understand, the parameters of external electrical components are also Figure 1 The external connection relationship of the communication chip is not limited to Figure 1 As shown in the example, the PIN5-RESET pin can be connected to a reset control output terminal of a host control chip to facilitate the reset of the entire system.

[0167] The beneficial effects of this embodiment are analyzed as follows: Problems existing in previous communication schemes: The longer the communication distance and the higher the communication rate, the more serious the interference of bus parasitic parameters on the signal transmitted on the bus will be, and signal oscillation or distortion will occur, resulting in abnormal decoding with high bit error rate, slow response of communication equipment or inability to communicate; although the bus signal can be improved by adding matching resistors between remote node buses, nodes far from the matching resistors will still have problems with inaccurate decoding signals and insufficient high-level pulse widths, and dynamic impedance matching resistors cannot be added to each node because the bus impedance will be lowered and communication will not be possible. The dynamic impedance matching technology proposed in this embodiment is only enabled when the node sends a signal, and other nodes are in a receiving state and will not affect the bus impedance. The bus signal when each node sends a signal is improved by dynamic impedance matching technology, thereby improving decoding accuracy;

[0168] At the same time, the chip for improving the communication effect in this embodiment can also adjust the high-level pulse width of the decoding signal through the signal correction function to avoid the problem of insufficient pulse width of the decoding signal caused by the interference of the bus parasitic parameters; the chip for improving the communication effect in this embodiment also has a decoding error correction function, using a new principle of decoding signal flipping to suppress the interference signal received from the bus; through the above multiple functions, the interference of the bus parasitic parameters is reduced from multiple aspects to ensure the communication quality; because the scheme using this communication chip is almost not affected by the bus parasitic parameters, it can be applied to a longer communication distance, a higher communication rate and more communication nodes, which is conducive to the upgrading of traditional communication schemes. The chip for improving the communication effect in this embodiment also integrates the encoding and decoding function, does not require software encoding and decoding, saves MCU resources, and the communication chip has a higher degree of integration and richer functions, so it has stronger market competitiveness and higher profit margins.

[0169] In summary, this embodiment provides a communication chip, which works based on a hardware circuit. The communication chip includes: a bus communication pin and an MCU communication pin, and the MCU communication pin includes a first local output pin, a second local output pin and a local signal input pin. The first local output pin is used to output a signal 0 or 1 based on a differential value of the twisted pair bus signal received by the bus communication pin. The second local output pin is used to synchronously output a signal 0 when the first local output pin outputs a signal 01, and synchronously output a signal 1 when the first local output pin outputs a signal 11. The bus communication pin is used to synchronously output a signal 01 when the signal of the local signal input pin is 0, and synchronously output a signal 11 when the signal of the local signal input pin is 1. In this configuration, encoding and decoding are performed in a hardware decoding manner, and there is no need for software encoding and decoding inside the MCU or other logic control devices, which reduces the calculation burden of the MCU or other logic control devices, increases the versatility of the communication chip, and provides a hardware basis for the implementation of other anti-interference functions. The communication chip can improve the long-distance communication effect and solve the problems existing in the prior art.

[0170] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A communication chip, characterized in that: Used for HBS protocol communication, the communication chip works based on hardware circuits, and the communication chip includes: a bus communication pin and an MCU communication pin, and the MCU communication pin includes a first local output pin, a second local output pin and an MCU signal input pin; The first local output pin is used to output a signal 0 or 1 based on a differential value of the twisted pair bus signal received by the bus communication pin; The second local output pin is used to synchronously output signal 0 when the first local output pin outputs signal 01, and synchronously output signal 1 when the first local output pin outputs signal 11; The bus communication pin is used to synchronously output a signal 01 when the signal of the local signal input pin is 0, and to synchronously output a signal 11 when the signal of the local signal input pin is 1.

2. The communication chip according to claim 1, characterized in that: The communication chip also includes a PWM modulation signal pin, which is used to receive a PWM signal. The communication chip determines a duration of the signal between the bus communication pin and the first local output pin based on half a cycle of the PWM signal, and determines a duration of the signal between the second local output pin and the local signal input pin based on a cycle of the PWM signal.

3. The communication chip according to claim 1, characterized in that: The communication chip further includes an impedance switching switch and a dynamic impedance matching pin, the bus communication pin includes two bus output pins, and in at least one connection mode of the communication chip, the dynamic impedance matching pin is used to connect an external matching resistor; The communication chip is used to connect the matching resistor between the two bus output pins through the impedance switching switch when the output signal of the bus output pin drops from a high level to an intermediate level or rises from a low level to an intermediate level, and is used to disconnect the matching resistor from the bus output pin through the impedance switching switch when the duration after connection reaches a preset time.

4. The communication chip according to claim 1, characterized in that: The bus communication pins include bus output pins, and the bus output pins are provided with voltage regulator tubes for enhancing ESD protection capability.

5. The communication chip according to claim 1, characterized in that: The communication chip further comprises a signal pulse width correction pin, the bus communication pin comprises a bus output pin, and the signal pulse width correction pin is used to connect an external correction resistor; In at least one connection relationship, the correction resistor is used to eliminate the influence of bus parasitic parameters to compensate for the high-level output pulse width of the bus output pin.

6. The communication chip according to claim 5, characterized in that: In at least another connection relationship, the correction resistor is also used to actively adjust the high level output pulse width of the bus output pin to adapt to different communication rates.

7. The communication chip according to claim 1, characterized in that: The communication chip includes a decoding error correction module for filtering out oscillations of bus signals, and the bus communication pin includes a bus input pin, and the bus input pin is connected to the MCU communication pin through the decoding error correction module.

8. The communication chip according to claim 7, characterized in that: The decoding error correction module includes a signal detection unit, a signal judgment unit, a reference potential providing unit and an output unit; The signal detection unit is used to convert the twisted pair bus signal received by the bus input pin into two-way first intermediate signals; The reference potential providing unit is used to provide a reference voltage; The signal determination unit is used to compare the first intermediate signal with the reference voltage. When any one of the first intermediate signals is greater than the reference voltage, the signal determination unit outputs a first level, otherwise, the signal determination unit outputs a second level. The output unit is used to change its own output signal accordingly based on the output signal of the signal determination unit.

9. The communication chip according to claim 1, characterized in that: The communication chip further includes at least one of the following pins: a bootstrap capacitor pin, a reset control input pin, a power input pin, and a ground pin.

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