Memory and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a memory and a manufacturing method thereof, and the manufacturing method of the memory comprises the following steps: providing a semiconductor substrate; at least one storage unit is prepared on a semiconductor substrate, the storage unit comprises at least one transistor, each transistor comprises a grid electrode, a grid medium, a semiconductor channel, an upper electrode and a lower electrode, the semiconductor channel at least surrounds the peripheral side of the grid electrode, the grid medium is formed between the semiconductor channel and the grid electrode, and the upper electrode is formed between the upper electrode and the lower electrode. The upper electrode and the lower electrode are both located on the outer side of the semiconductor channel and make contact with the semiconductor channel, and the lower electrode is arranged below the upper electrode in an insulated mode; and performing oxidation treatment on a to-be-oxidized region of an effective semiconductor channel in at least one transistor in the memory unit, so that the to-be-oxidized region forms an oxidized channel. According to the scheme, the control capability of the grid electrode on the semiconductor channel can be improved, and meanwhile, the contact resistance between the source electrode and the drain electrode and the semiconductor channel is reduced.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and particularly relates to a memory and a method for manufacturing the same. Background Art

[0002] With the miniaturization of technology nodes, capacitor-free memory has become a research hotspot. At present, the structure of capacitor-free memory tends to be three-dimensional. When using oxidation treatment to improve the defects of the channel of three-dimensional capacitor-free memory, it is easy to cause the entire channel to be oxidized, which will cause the overall resistance of the channel to increase, which is not conducive to improving electrical performance. Summary of the invention

[0003] The embodiments of the present disclosure provide a memory and a method for manufacturing the same, which can improve the control capability of a gate over a semiconductor channel while reducing the contact resistance between a source, a drain and a semiconductor channel.

[0004] The present disclosure provides a method for manufacturing a memory device, which comprises the following steps:

[0005] Providing a semiconductor substrate;

[0006] At least one memory cell is prepared on the semiconductor substrate, the memory cell includes at least one transistor, each of the transistors includes a gate, a gate dielectric, a semiconductor channel, an upper electrode and a lower electrode, the semiconductor channel at least surrounds the outer peripheral side of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is insulated and arranged below the upper electrode, one of the upper electrode and the lower electrode is a source electrode, and the other is a drain electrode;

[0007] An oxidation treatment is performed on a region to be oxidized of an effective semiconductor channel in at least one of the transistors in the storage unit so that the region to be oxidized is formed into an oxidized channel, wherein the region to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxidized channel; wherein the effective semiconductor channel is the portion of the semiconductor channel located between the upper electrode and the lower electrode.

[0008] A second aspect of the present disclosure provides a memory, comprising:

[0009] a semiconductor substrate; and

[0010] At least one memory cell is formed on the semiconductor substrate, the memory cell includes at least one transistor, each of the transistors includes a gate, a gate dielectric, a semiconductor channel, an upper electrode and a lower electrode, the semiconductor channel at least surrounds the outer peripheral side of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is insulated and arranged below the upper electrode, one of the upper electrode and the lower electrode is a source, and the other is a drain;

[0011] Wherein, in the memory cell: a partial area of ​​an effective semiconductor channel in at least one of the transistors is oxidized to form an oxidized channel, the effective semiconductor channel is a portion of the semiconductor channel located between the upper electrode and the lower electrode, and neither the upper electrode nor the lower electrode is in contact with the oxidized channel.

[0012] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0013] By only oxidizing the effective semiconductor channel between the source and drain in the semiconductor channel, the gate's control over the semiconductor channel is improved and the on-current is increased. At the same time, since the area in the semiconductor channel that is in contact with the source and drain is not oxidized, the contact resistance between the source and drain and the semiconductor channel can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0015] Figure 1 A schematic diagram of a structure formed in the corresponding step S100 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0016] Figure 2 A schematic diagram of a structure formed in the corresponding step S102 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0017] Figure 3 A schematic diagram of a structure formed in the corresponding step S104 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0018] Figure 4 A schematic diagram of the structure after the gas channel is formed in the manufacturing method of the memory described in the embodiment of the present disclosure is shown.

[0019] Figure 5 A schematic diagram of the structure after an oxidation channel is formed by introducing an oxidizing gas into a gas channel in a method for manufacturing a memory described in an embodiment of the present disclosure is shown.

[0020] Figure 6 A schematic diagram of the structure after partially filling a gas channel to form a filling body in the method for manufacturing a memory described in an embodiment of the present disclosure is shown.

[0021] Figure 7 A schematic structural diagram of a storage unit in a memory described in an embodiment of the present disclosure including a read transistor and a write transistor is shown.

[0022] Figure 8 A schematic diagram of the structure after only the to-be-oxidized region of the read transistor is oxidized to form an oxidation channel in the method for manufacturing the memory described in the embodiment of the present disclosure is shown.

[0023] Fig. 9 A schematic diagram of the structure after only the to-be-oxidized region of the write transistor is oxidized to form an oxidation channel in the method for manufacturing the memory described in the embodiment of the present disclosure is shown.

[0024] Fig.10 A schematic diagram of the structure after oxidation treatment is performed on the to-be-oxidized regions of the read transistor and the write transistor to form an oxidation channel in the method for manufacturing the memory described in the embodiment of the present disclosure is shown.

[0025] Fig.11 A schematic diagram of the structure after the gas channel is formed in the manufacturing method of the memory described in the first embodiment of the present disclosure is shown.

[0026] Fig.12 A schematic diagram of the structure after the first oxidation channel and the second oxidation channel are simultaneously formed by introducing an oxidizing gas into a gas channel in the method for manufacturing the memory described in the first embodiment of the present disclosure is shown.

[0027] Fig.13 A schematic diagram of the structure after the gas channel is completely filled to form a filling body in the manufacturing method of the memory described in the first embodiment of the present disclosure is shown.

[0028] Fig.14 A schematic diagram of the structure after partially filling a gas channel to form a filling body in the method for manufacturing the memory described in the first embodiment of the present disclosure is shown.

[0029] Fig.15 A schematic diagram of a structure formed in the corresponding step S200 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0030] Fig.16 and Fig.17 Schematic diagrams of the structure formed in the corresponding step S200 in the memory manufacturing method described in the embodiment of the present disclosure at different viewing angles are respectively shown.

[0031] Fig.18 A schematic diagram of a structure formed in the corresponding step S202 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0032] Fig.19 A schematic structural diagram of a read transistor formed in the method for manufacturing a memory according to an embodiment of the present disclosure is shown.

[0033] Fig. 20 A schematic diagram of a structure formed in the memory manufacturing method according to the embodiment of the present disclosure corresponding to step S2041 is shown.

[0034] Fig.21 Another structural schematic diagram formed in the corresponding step S2041 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0035] Fig. 22 Another structural schematic diagram formed in the memory manufacturing method according to the embodiment of the present disclosure corresponding to step S2041 is shown.

[0036] Fig.23 A schematic diagram of a structure formed in the memory manufacturing method according to the embodiment of the present disclosure corresponding to step S206 is shown.

[0037] Fig.24 Another structural schematic diagram formed in the memory manufacturing method according to the embodiment of the present disclosure corresponding to step S206 is shown.

[0038] Fig.25 A schematic diagram of a structure formed in the corresponding step S208 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0039] Fig.26 and Fig. 27 Schematic diagrams of the structure formed in step S208 in the memory manufacturing method described in the embodiment of the present disclosure at different viewing angles are respectively shown.

[0040] Fig.28 A schematic diagram of a structure formed in the corresponding step S210 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0041] Fig.29 A schematic structural diagram of a write transistor formed in the method for manufacturing a memory device described in an embodiment of the present disclosure is shown.

[0042] Fig.30 A schematic diagram of a structure formed in the corresponding step S2121 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0043] Fig.31 Another structural schematic diagram formed in the corresponding step S2121 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0044] Fig.32 A schematic diagram of a structure formed in the corresponding step S2131 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0045] Fig.33 and Fig.34 Schematic diagrams of the structure formed in the corresponding step S2132 in the memory manufacturing method described in the embodiment of the present disclosure at different viewing angles are respectively shown.

[0046] Fig.35 A schematic diagram of the structure formed in the corresponding step S2133 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0047] Fig.36 A schematic diagram of a structure formed in the corresponding step S214 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0048] Fig.37 Another structural schematic diagram formed in the memory manufacturing method according to the embodiment of the present disclosure corresponding to step S214 is shown.

[0049] Fig.38 A schematic diagram of the arrangement of the storage unit and the second part of the gas channel in the memory described in an embodiment of the present disclosure on a horizontal plane is shown.

[0050] Fig.39 A structural schematic diagram is shown corresponding to step S216 in the memory manufacturing method described in the embodiment of the present disclosure.

[0051] Fig.40 A schematic diagram of the structure after the second gas channel is formed in the manufacturing method of the memory described in the second embodiment of the present disclosure is shown.

[0052] Fig.41 A schematic structural diagram of the memory manufacturing method described in the second embodiment of the present disclosure after the first gas channel is formed is shown.

[0053] Fig.42 A schematic diagram of the structure after the second oxidation channel is formed in the manufacturing method of the memory described in the second embodiment of the present disclosure is shown.

[0054] Fig.43 A schematic structural diagram of the memory manufacturing method described in the second embodiment of the present disclosure after the second filling body is formed is shown.

[0055] Fig.44 A schematic diagram of the structure after the first oxidation channel is formed in the manufacturing method of the memory described in the second embodiment of the present disclosure is shown.

[0056] Fig.45 A schematic diagram of the structure after the first filling body is formed in the manufacturing method of the memory described in the second embodiment of the present disclosure is shown.

[0057] Fig.46 A schematic diagram of a structure formed corresponding to step S308 in the method for manufacturing a memory described in an embodiment of the present disclosure is shown.

[0058] Fig.47 A schematic diagram of the structure after partially filling the second gas channel to form a second filling body in the method for manufacturing the memory described in the second embodiment of the present disclosure is shown.

[0059] Fig.48 A schematic diagram of a structure formed in the corresponding step S406 in the memory manufacturing method described in the embodiment of the present disclosure is shown.

[0060] Fig.49 Another structural schematic diagram formed in the memory manufacturing method according to the embodiment of the present disclosure corresponding to step S406 is shown.

[0061] Fig.50 A schematic diagram of a structure formed corresponding to step S408 in the method for manufacturing a memory described in an embodiment of the present disclosure is shown.

[0062] Fig.51 A schematic diagram of the structure after partially filling the first gas channel to form a first filling body in the method for manufacturing the memory described in the second embodiment of the present disclosure is shown.

[0063] Description of reference numerals:

[0064] 10. Semiconductor substrate;

[0065] 11, transistor; 110, gate; 111, gate dielectric; 112, semiconductor channel; 1120, oxidation channel; 113, upper electrode; 114, lower electrode;

[0066] 11W, write transistor; 110W, first gate; 111W, first gate dielectric; 112W, first semiconductor channel; 1120W, first oxidation channel; 113W, first upper electrode; 114W, first lower electrode; 115W, upper conductive filling portion;

[0067] 11R, read transistor; 110R, second gate; 111R, second gate dielectric; 112R, second semiconductor channel; 1120R, second oxidation channel; 113R, second upper electrode; 114R, second lower electrode; 115R, lower conductive filling portion;

[0068] 12, gas channel; 12W, first gas channel; 12R, second gas channel; 120, first part; 120W, upper first part; 120R, lower first part; 121, second part;

[0069] 13, filling body; 13W, first filling body; 13R, second filling body;

[0070] 141R, lower sacrificial insulating film layer; 142R, lower isolating insulating film layer; 143R, first lower interlayer dielectric layer; 144R, second lower interlayer dielectric layer; 145R, second lower signal line; 146R, second lower isolating insulating portion; 147R, second upper signal line; 148R, second upper isolating insulating portion; 149R, lower through hole;

[0071] 151R, lower semiconductor film layer; 152R, lower gate dielectric film layer; 153R, lower gate film layer; 154R, lower conductive filling film layer;

[0072] 16. middle isolation insulating film layer; 160. middle via hole;

[0073] 171W, upper sacrificial insulating film layer; 172W, upper isolation insulating film layer; 173W, first upper interlayer dielectric layer; 174W, second upper interlayer dielectric layer; 175W, write bit line; 176W, first lower isolation insulating portion; 177W, upper through hole; 178W, fill isolation insulating portion; 179W, write word line;

[0074] 180, a first upper isolation insulating film layer; 180W, a first upper isolation insulating portion;

[0075] 181W, upper semiconductor film layer; 182W, upper gate dielectric film layer; 183W, upper gate film layer; 184W, upper conductive filling film layer;

[0076] 19. Covering insulation layer;

[0077] C, storage unit; X, first horizontal direction; Y, second horizontal direction; Z, vertical direction. DETAILED DESCRIPTION

[0078] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0079] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0080] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0081] The present disclosure provides a method for manufacturing a memory, which may include step S100, step S102, and step S104.

[0082] In step S100: a semiconductor substrate 10 is provided, referring to Figure 1 As shown; for example, the semiconductor substrate 10 may be a silicon (Si) substrate, but is not limited thereto, and may also be a germanium (Ge) substrate, etc., depending on the specific circumstances.

[0083] In step S102: at least one memory cell is prepared on the semiconductor substrate 10. The memory cell may include at least one transistor 11. Figure 2 As shown, the transistor 11 may be a three-dimensional structure. Specifically, each transistor 11 may include a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113 and a lower electrode 114. The semiconductor channel 112 at least surrounds the outer peripheral side of the gate 110, and the gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110 to avoid direct contact between the semiconductor channel 112 and the gate 110. The upper electrode 113 and the lower electrode 114 are both located on the outside of the semiconductor channel 112 and in contact with the semiconductor channel 112.

[0084] Among them, the lower electrode 114 is insulated and arranged below the upper electrode 113, that is, the lower electrode 114 is closer to the semiconductor substrate 10 than the upper electrode 113. It should be noted that one of the upper electrode 113 and the lower electrode 114 is a source and the other is a drain, and in the semiconductor channel 112: the portion located between the upper electrode 113 and the lower electrode 114 can be defined as an effective semiconductor channel.

[0085] For example, the number of storage units may be multiple and arranged on a horizontal plane to form a storage array structure. The storage array structure may have one layer or multiple layers stacked in a vertical direction. It should be understood that the horizontal plane mentioned in this embodiment refers to a plane parallel or approximately parallel to the semiconductor substrate 10, and the vertical direction refers to a direction perpendicular or approximately perpendicular to the semiconductor substrate 10.

[0086] In step S104: an oxidation treatment is performed on the to-be-oxidized region of the effective semiconductor channel in at least one transistor 11 in the memory cell, so that the to-be-oxidized region is formed into an oxidized channel 1120, referring to Figure 3 As shown; wherein the area to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode 113 nor the lower electrode 114 is in contact with the oxidized channel 1120.

[0087] In the present embodiment, only the effective semiconductor channel between the source and drain in the semiconductor channel 112 is oxidized so that the region between the source and drain in the semiconductor channel 112 forms an oxidized channel 1120 having oxygen vacancies. This improves the control capability of the gate 110 over the semiconductor channel 112 and increases the on-current. At the same time, since the region in contact with the source and drain in the semiconductor channel 112 is not oxidized, the contact resistance between the source and drain and the semiconductor channel 112 can be reduced.

[0088] It should be noted that step S104 of this embodiment may be a sub-step of step S102, but is not limited to this. Step S104 may also be a step performed after the entire storage unit preparation is completed in step S102. The specific description may be given later based on the actual preparation situation and will not be elaborated here.

[0089] Before the oxidation treatment is performed on the region to be oxidized in the semiconductor channel 112, the manufacturing method of this embodiment may further include preparing a gas channel 12, referring to Figure 4 As shown, the gas channel 12 may include a first portion 120 disposed around the periphery of the region to be oxidized, and a second portion 121 communicating with the first portion 120 and extending vertically upward; after the gas channel 12 is formed, an oxidizing gas may be introduced from above the second portion 121 to act on the region to be oxidized. That is, when the region to be oxidized in the semiconductor channel 112 is oxidized, Figure 5 As shown, an oxidizing gas can be introduced from the upper opening of the second portion 121, and the oxidizing gas flows through the second portion 121 and the first portion 120 in sequence to act on the area to be oxidized, so as to oxidize the area to be oxidized into an oxidized channel 1120, wherein: Figure 5 The bold dashed line with arrows in the middle gas channel 12 indicates the flow path of the oxidizing gas.

[0090] In this embodiment, by forming an oxidation channel 1120 in the effective semiconductor channel of the semiconductor channel 112, the electrical performance of the transistor 11 can be improved to design a threshold voltage that meets the requirements to control the semiconductor channel 112. For example, the oxidizing gas in this embodiment may include at least oxygen.

[0091] Among them, since the first portion 120 of the gas channel 12 is arranged around the outer periphery of the area to be oxidized, the oxidation channel 1120 formed in this embodiment can also be arranged in a ring shape, specifically, can be arranged around the gate 110 of the transistor 11.

[0092] In an optional embodiment, after forming the gas channel 12 and before introducing the target gas from above the second part 121, the manufacturing method of this embodiment may also include: introducing a repair agent from above the second part 121 to act on the area to be oxidized to repair the surface of the area to be oxidized.

[0093] For example, when the semiconductor channel 112 is made of metal oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide), the repair agent may at least include hydrogen, but is not limited thereto, and other types of repair agents may also be used, depending on actual conditions.

[0094] After the oxidation channel 1120 is formed, the manufacturing method of this embodiment may further include: filling the gas channel 12 with an insulating material to prevent subsequent processing from affecting the oxidation channel 1120 .

[0095] In some embodiments, the step of filling the gas channel 12 with an insulating material may include: completely filling the gas channel 12 with the insulating material to form a filling body 13 in the gas channel 12, referring to Figure 3 As shown; it should be understood that, since the gas channel 12 is completely filled, the first part 120 and the second part 121 of the gas channel 12 are filled with insulating materials, and this design can ensure the stability of the structure. Among them, the upper surface of the filling body 13 is flush with the upper surface of the gas channel 12 to ensure the flatness of the upper surface of the structure, which is conducive to the formation of other structural layers thereon.

[0096] It should be understood that the upper surface mentioned in the present disclosure refers to the surface of the object away from the semiconductor substrate 10, which will not be repeated later.

[0097] In some other embodiments, the step of filling the gas channel 12 with an insulating material may include: partially or completely filling the second portion 121 of the gas channel 12 with an insulating material to form a filling body 13 in the second portion 121, referring to Figure 6 As shown, the upper surface of the filling body 13 is flush with the upper surface of the gas channel 12 to ensure the flatness of the upper surface of the structure, which is conducive to the formation of other structural layers thereon.

[0098] refer to Figure 6 As shown, the gas channel 12 is a void region except for the region filled by the filler 13. For example, if the filler 13 only fills part of the second portion 121, the first portion 120 of the gas channel 12 and the portion of the second portion 121 of the gas channel 12 that is not filled by the filler 13 are both void regions. If the filler 13 completely fills the second portion 121, the first portion 120 of the gas channel 12 is a void region. That is, when the second portion 121 of the gas channel 12 is partially or completely filled with an insulating material to prevent subsequent processing from affecting the oxidation channel, the first portion 120 of the gas channel 12 can be formed as a void region. That is, there is a void between the upper electrode 113 and the lower electrode 114 of the transistor 11. Figure 6 As shown, this can reduce the parasitic capacitance between the upper electrode 113 and the lower electrode 114 in the transistor 11.

[0099] It should be noted that if the second portion 121 of the gas channel 12 is partially filled with an insulating material, the filled area should be the upper area of ​​the second portion 121. Figure 6 As shown, the upper surface of the filling body 13 is flush with the upper surface of the gas channel 12. Specifically, the filling body 13 can be formed by quickly sealing with insulating materials. The filling body 13 is formed in the upper area of ​​the second part 121, and the lower area of ​​the second part 121 and the first part 120 are both gap areas.

[0100] The manufacturing method of the memory is described in detail below in conjunction with the accompanying drawings and the specific structure of the memory cell. In the embodiment of the present disclosure, the memory cell may be a 2T0C structure, that is, the memory cell is a structure including two transistors 11 and no storage capacitor; wherein one of the two transistors 11 of each memory cell is a read transistor 11R and the other is a write transistor 11W.

[0101] To facilitate subsequent description, in the embodiment of the present disclosure, the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113 and lower electrode 114 of the write transistor 11W are respectively defined as the first gate 110W, the first gate dielectric 111W, the first semiconductor channel 112W, the first upper electrode 113W and the first lower electrode 114W; and the gate 110, gate dielectric 111, semiconductor channel 112, upper electrode 113 and lower electrode 114 of the read transistor 11R are respectively defined as the second gate 110R, the second gate dielectric 111R, the second semiconductor channel 112R, the second upper electrode 113R and the second lower electrode 114R.

[0102] refer to Figure 7 As shown, in the memory cell: the write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W of the write transistor 11W and the second gate 110R of the read transistor 11R are conductively connected.

[0103] Among them, the oxidation treatment of the to-be-oxidized region of the effective semiconductor channel in at least one transistor 11 in the storage unit mentioned in the aforementioned step S104 so that the to-be-oxidized region is formed into an oxidized channel, may specifically include: oxidation treatment of the to-be-oxidized region of the effective semiconductor channel of at least one of the write transistor 11W and the read transistor 11R, that is, the effective semiconductor channel of at least one of the write transistor 11W and the read transistor 11R includes an oxidized channel 1120.

[0104] In some embodiments, the manufacturing method of the memory disclosed in the present invention may include: oxidizing the to-be-oxidized area of ​​the effective semiconductor channel of one of the write transistor 11W and the read transistor 11R to form an oxidized channel 1120; wherein the gas channel 12 is prepared after the transistor 11 corresponding to the to-be-oxidized area is prepared, so that the inner side of the semiconductor channel 112 is protected by structures such as the gate dielectric 111 and the gate 110, thereby reducing damage to the semiconductor channel 112 during the preparation of the gas channel 12.

[0105] For example, reference Figure 8 As shown, in this embodiment, the step of oxidizing the area to be oxidized of the transistor 11 in the memory cell may include: only oxidizing the area to be oxidized of the read transistor 11R in the memory cell, so that the effective semiconductor channel of the read transistor 11R includes an oxidized channel 1120, wherein the gas channel 12 is prepared after the preparation of the read transistor 11R is completed, and the filling of the gas channel 12 is completed before the preparation of the write transistor 11W begins.

[0106] Alternatively, refer to Fig. 9As shown, in this embodiment, the step of oxidizing the area to be oxidized of the transistor 11 in the memory cell may include: only oxidizing the area to be oxidized of the write transistor 11W in the memory cell so that the effective semiconductor channel of the write transistor 11W includes an oxidized channel 1120, wherein the gas channel 12 is prepared after the preparation of the write transistor 11W is completed.

[0107] In some other embodiments, the manufacturing method of the present disclosure may include: performing oxidation treatment on the to-be-oxidized regions of the effective semiconductor channels in the write transistor 11W and the read transistor 11R, so that the to-be-oxidized regions of the write transistor 11W and the read transistor 11R are formed into oxidation channels 1120 .

[0108] Among them, for the convenience of subsequent description, the effective semiconductor channel of the first semiconductor channel 112W in the write transistor 11W can be defined as a first effective semiconductor channel, the region to be oxidized of the first effective semiconductor channel in the write transistor 11W can be defined as a first region to be oxidized, the effective semiconductor channel of the second semiconductor channel 112R in the read transistor 11R can be defined as a second effective semiconductor channel, and the region to be oxidized of the second effective semiconductor channel in the read transistor 11R can be defined as a second region to be oxidized.

[0109] Specifically, refer to Fig.10 As shown, the aforementioned step of oxidizing the to-be-oxidized regions of the effective semiconductor channels in the write transistor 11W and the read transistor 11R so that the to-be-oxidized regions of the write transistor 11W and the read transistor 11R are formed into oxidation channels 1120 may include: oxidizing the first to-be-oxidized region of the first effective semiconductor channel in the write transistor 11W so that the first to-be-oxidized region is formed into a first oxidation channel 1120W; and oxidizing the second to-be-oxidized region of the second effective semiconductor channel in the read transistor 11R so that the second to-be-oxidized region is formed into a second oxidation channel 1120R; by oxidizing the to-be-oxidized regions of the write transistor 11W and the read transistor 11R, the write transistor 11W and the read transistor 11R are both formed with oxidation channels 1120, so as to improve the electrical properties of the read transistor 11R and the write transistor 11W, thereby improving the storage performance of the storage unit.

[0110] In this embodiment, the implementation methods of performing oxidation treatment on the to-be-oxidized regions of the effective semiconductor channels in the write transistor 11W and the read transistor 11R may include the following:

[0111] Implementation Method 1

[0112] In the embodiment of the present disclosure, the first oxidation channel 1120W of the write transistor 11W and the second oxidation channel 1120R of the read transistor 11R can be formed simultaneously, that is, the first oxidation channel 1120W and the second oxidation channel 1120R can be formed in the same preparation step, which can improve the preparation efficiency and reduce the preparation cost.

[0113] If the first oxidation channel 1120W and the second oxidation channel 1120R need to be formed simultaneously, the gas channel 12 can be prepared after the preparation of the write transistor 11W is completed. In this embodiment, refer to Fig.11 As shown, the prepared first part 120 of the gas channel 12 may include an upper first part 120W and a lower first part 120R, wherein the upper first part 120W refers to an upper area of ​​the first part 120 away from the semiconductor substrate 10, and the upper first part 120W surrounds the outer peripheral side of the first area to be oxidized, and the lower first part 120R refers to a lower area of ​​the first part 120 close to the semiconductor substrate 10, and the lower first part 120R surrounds the outer peripheral side of the second area to be oxidized.

[0114] It should be understood that reference Fig.11 As shown, in this embodiment, the upper first portion 120W and the lower first portion 120R of the gas channel 12 are spaced apart in the vertical direction Z and are connected through the second portion 121; specifically, the second portion 121 vertically extends upward to the upper surface of the storage unit and connects the upper first portion 120W and the lower first portion 120R, so that the oxidizing gas introduced from above the second portion 121 acts on the first to-be-oxidized area and the second to-be-oxidized area for oxidation treatment at the same time, that is: Fig.12 As shown, the oxidizing gas can enter the second part 121 through the gas inlet of the second part 121, and a part of the oxidizing gas can be diverted to the upper first part 120W to act on the first area to be oxidized for oxidation treatment, and another part of the oxidizing gas can be diverted to the lower first part 120R to act on the second area to be oxidized for oxidation treatment, so that the first oxidation channel 1120W and the second oxidation channel 1120R are formed at the same time. It should be noted that Fig.12 The bold dashed line with an arrow in the middle indicates the flow path of the oxidizing gas.

[0115] For example, after the first oxidation channel 1120W and the second oxidation channel 1120R are simultaneously formed, referring to Fig.13As shown, the gas channel 12 can be completely filled with insulating material to form a filling body 13 in the gas channel 12. In other words, the upper first part 120W, the lower first part 120R and the second part 121 of the gas channel 12 are all filled with the filling body 13 made of insulating material to ensure the structural stability of the storage unit, wherein the upper surface of the filling body 13 can be flush with the upper surface of the storage unit to ensure that the upper surface of the storage array structure is flat, which is conducive to the preparation of subsequent structural layers.

[0116] It should be understood that after the first oxidation channel 1120W and the second oxidation channel 1120R are formed at the same time, the gas channel 12 is not limited to being filled in the aforementioned complete filling manner, and the gas channel 12 may also be filled in an incomplete filling manner, for example: the second portion 121 may be divided into an upper trunk region and a lower connecting region along the vertical direction Z, the upper trunk region extending from the upper surface of the storage unit to the upper first portion 120W and connected to the upper first portion 120W, the lower connecting region connecting the upper first portion 120W and the lower first portion 120R, wherein the insulating material may be filled in the upper trunk region by a quick sealing method to form a filling body 13 in the upper trunk region of the second portion 121, refer to Fig.14 As shown, the filling body 13 is flush with the upper surface of the storage unit. It should be noted that the filling body 13 can completely fill the upper trunk area of ​​the second part 121 or fill the upper half of the upper trunk area.

[0117] Among them, if the gas channel 12 is filled by the incomplete filling method mentioned above, refer to Fig.14 As shown, the upper first part 120W and the lower first part 120R are both gap areas that are not filled by the filler 13, that is, there are gaps between the first upper electrode 113W and the first lower electrode 114W, and between the second upper electrode 113R and the second lower electrode 114R, which can reduce the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W, and between the second upper electrode 113R and the second lower electrode 114R.

[0118] In a specific embodiment of the present disclosure, a method for manufacturing a gas channel 12 including an upper first part 120W, a lower first part 120R and a second part 121 may include at least steps S200, S202, S204, S206, S208, S210, S212, S214 and S216.

[0119] In step S200: a lower stacked film layer is formed on the semiconductor substrate 10, referring to Fig.15As shown, the lower stacked film layer includes at least a second lower electrode 114R, a lower sacrificial insulating film layer 141R, a second upper electrode 113R and a lower isolation insulating film layer 142R stacked in sequence along the vertical direction Z, wherein the material of the lower isolation insulating film layer 142R may be different from the material of the lower sacrificial insulating film layer 141R and the subsequent upper sacrificial insulating film layer to avoid the risk of removing the lower isolation insulating film layer 142R in the subsequent removal step of the upper sacrificial insulating film layer and the lower sacrificial insulating film layer 141R.

[0120] In some embodiments, reference Fig.15 As shown, the lower stacked film layer may also include a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, the first lower interlayer dielectric layer 143R being formed between the second upper electrode 113R and the lower sacrificial insulating film layer 141R, and the second lower interlayer dielectric layer 144R being formed between the second lower electrode 114R and the lower sacrificial insulating film layer 141R.

[0121] Among them, the materials of the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R are different from the materials of the lower sacrificial insulating film layer 141R, so as to avoid the risk of removing the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R in the subsequent removal step of the lower sacrificial insulating film layer 141R, so that the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R can be used to protect the second upper electrode 113R and the second lower electrode 114R.

[0122] For example, the insulating materials of the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R and the lower isolation insulating film layer 142R may be the same, for example, all silicon oxide, and the insulating material of the lower sacrificial insulating film layer 141R may be silicon nitride, silicon oxynitride or silicon carbon nitride, etc., but is not limited to this and can be determined according to actual conditions.

[0123] In some embodiments of the present disclosure, step S200 may specifically include step S2001, step S2002, step S2003 and step S2004.

[0124] In step S2001, a plurality of second lower signal lines 145R are formed on the semiconductor substrate 10, and are arranged at intervals in the first horizontal direction X and extend in the second horizontal direction Y. A second lower isolation insulating portion 146R is formed between adjacent second lower signal lines 145R. Fig.16 and Fig.17As shown; in this embodiment, the second lower isolation insulating portion 146R can insulate adjacent second lower signal lines 145R from each other; wherein the second lower signal lines 145R can be formed on the semiconductor substrate 10 before the second lower isolation insulating portion 146R, but is not limited to this, and the second lower isolation insulating portion 146R can also be formed first, and then a plurality of lower second lower signal lines 145R are formed.

[0125] It should be noted that the first horizontal direction X and the second horizontal direction Y mentioned anywhere in the present disclosure are defined as directions parallel or approximately parallel to the semiconductor substrate 10, wherein the first horizontal direction X intersects with the second horizontal direction Y; further, the first horizontal direction X and the second horizontal direction Y are perpendicular or approximately perpendicular to each other to reduce design difficulty and save space.

[0126] In step S2002, a second lower interlayer dielectric layer 144R, a lower sacrificial insulating film layer 141R and a first lower interlayer dielectric layer 143R are sequentially stacked along the vertical direction Z on the upper surface of the second lower signal line 145R and the second lower isolation insulating portion 146R (i.e., the surface away from the semiconductor substrate 10), and a second lower interlayer dielectric layer 144R, a lower sacrificial insulating film layer 141R and a first lower interlayer dielectric layer 143R are sequentially stacked along the vertical direction Z. Fig.16 and Fig.17 shown.

[0127] In step S2003: a plurality of second upper signal lines 147R are formed on the first lower interlayer dielectric layer 143R, which are arranged at intervals in the second horizontal direction Y and extend in the first horizontal direction X, and a second upper isolation insulating portion 148R is formed between adjacent second upper signal lines 147R. Fig.16 and Fig.17 As shown; in the present embodiment, the second upper isolation insulating portion 148R can insulate adjacent second upper signal lines 147R from each other; wherein, the second upper signal lines 147R can be formed on the first lower interlayer dielectric layer 143R before the second upper isolation insulating portion 148R, but is not limited thereto, and the second upper isolation insulating portion 148R can also be formed first, and then a plurality of lower second upper signal lines 147R are formed.

[0128] In the embodiment of the present disclosure, one of the second upper signal line 147R and the second lower signal line 145R is a read bit line, and the other is a read word line; Fig.16 and Fig.17 As shown, there is an overlapping area between the orthographic projections of the second upper signal line 147R and the second lower signal line 145R on the semiconductor substrate 10, wherein the portion of the second upper signal line 147R corresponding to the overlapping area can be defined as a second upper electrode 113R, and the portion of the second lower signal line 145R corresponding to the overlapping area can be defined as a second lower electrode 114R.

[0129] For example, the second upper signal line 147R and the second lower signal line 145R may include one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), polysilicon, etc., but is not limited to this. Other conductive materials may also be used as long as the performance of the second upper signal line 147R and the second lower signal line 145R can be guaranteed.

[0130] In step S2004: a lower isolation insulating film layer 142R is formed to entirely cover the second upper signal line 147R and the second upper isolation insulating portion 148R, and a lower isolation insulating film layer 142R is formed to entirely cover the second upper signal line 147R and the second upper isolation insulating portion 148R. Fig.16 and Fig.17 shown.

[0131] It should be noted that the lower isolation insulating film layer 142R and the second upper isolation insulating portion 148R may be integrally formed, but is not limited thereto, and may also be prepared separately, depending on the specific circumstances.

[0132] In some other embodiments, the lower stacked film layer may not include Figures 15 to 17 The first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R shown depend on specific circumstances.

[0133] In step S202: a lower through hole 149R is formed which at least penetrates the lower isolation insulating film layer 142R, the second upper electrode 113R and the lower sacrificial insulating film layer 141R. Fig.18 As shown, the second lower electrode 114R is exposed by the lower through hole 149R. It should be understood that since the second upper electrode 113R belongs to the portion of the second upper signal line 147R that overlaps with the second lower signal line 145R, the second lower electrode 114R belongs to the portion of the second lower signal line 145R that overlaps with the second upper signal line 147R. Therefore, it can be understood that the lower through hole 149R of this embodiment is opened in the corresponding overlapping area of ​​the second upper signal line 147R and the second lower signal line 145R.

[0134] Wherein, when the lower stacked film layer further includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, the lower through hole 149R may also penetrate the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R, referring to Fig.18 shown.

[0135] For example, the lower surface of the lower through hole 149R may extend into the second lower electrode 114R. Fig.18As shown, this can make the second lower electrode 114R more exposed to increase the subsequent contact area with the semiconductor channel 112. In addition, while ensuring that the second lower electrode 114R is exposed, the etching accuracy can be reduced, thereby reducing the etching cost. However, it should be understood that the lower surface of the lower through hole 149R is not limited to extending into the second lower electrode 114R, but can also just extend to the upper surface of the second lower electrode 114R, or the lower through hole 149R can pass through the second lower electrode 114R (that is, the lower surface of the lower through hole 149R is flush with or lower than the lower surface of the second lower electrode 114R), etc.

[0136] In step S204: a second semiconductor channel 112R, a second gate dielectric 111R and a second gate 110R are formed at the lower through hole 149R to form a read transistor 11R. Fig.19 As shown, the second region to be oxidized of the second semiconductor channel 112R corresponds to the lower sacrificial insulating film layer 141R, that is, the second region to be oxidized of the second semiconductor channel 112R is located at a position surrounded by the lower sacrificial insulating film layer 141R.

[0137] It should be noted that when the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, after executing step S204, the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R can both be arranged to surround the second effective semiconductor channel. Specifically, the first lower interlayer dielectric layer 143R can surround an area of ​​the second effective semiconductor channel that is above the second area to be oxidized, and the second lower interlayer dielectric layer 144R can surround an area of ​​the second effective semiconductor channel that is below the second area to be oxidized.

[0138] In some embodiments of the present disclosure, step S204 may include at least step S2041 and step S2042.

[0139] In step S2041: after forming the lower through hole 149R, a lower semiconductor film layer 151R, a lower gate dielectric film layer 152R and a lower gate film layer 153R are sequentially deposited on the lower stacked film layer, referring to Fig. 20 As shown, the lower semiconductor film layer 151R, the lower gate dielectric film layer 152R and the lower gate film layer 153R uniformly cover the lower stacked film layer, that is, the lower semiconductor film layer 151R, the lower gate dielectric film layer 152R and the lower gate film layer 153R can be deposited on the upper surface of the lower isolation insulating film layer 142R and deposited in the lower through hole 149R; wherein, the portion of the lower semiconductor film layer 151R and the lower gate dielectric film layer 152R located in the lower through hole 149R can be U-shaped, and the portion of the lower gate film layer 153R located in the lower through hole 149R can be U-shaped, refer to Fig. 20or the lower gate film layer 153R can also fill the lower through hole 149R, reference Fig.21 shown.

[0140] For example, the material of the lower semiconductor film layer 151R may be a semiconductor material such as IGZO, but is not limited to this, and may also be other semiconductor materials; the material of the lower gate dielectric film layer 152R may be a high dielectric insulating material such as silicon oxide, but is not limited to this, and may also be a low dielectric material, etc.; the material of the lower gate film layer 153R may be a conductive material with good gate control capability such as ZnO (zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), etc., but is not limited to this, and may also be other conductive materials.

[0141] It should be noted that the portion of the lower gate film layer 153R located in the lower through hole 149R is as follows: Fig. 20 When the U-shaped structure is shown, step S2041 may further include: after depositing the lower gate film layer 153R, depositing a lower conductive filling film layer 154R that completely covers the lower gate film layer 153R, referring to Fig. 22 As shown, the portion of the lower conductive filling film layer 154R located in the lower through hole 149R fully fills the lower through hole 149R. In this embodiment, the lower conductive filling film layer 154R can be made of a conductive material with good conductivity and lower cost than the lower gate film layer 153R.

[0142] In step S2042: the portions of the lower semiconductor film layer 151R, the lower gate dielectric film layer 152R and the lower gate film layer 153R that exceed the target distance value of the hole boundary of the lower through hole 149R are etched away to form a second semiconductor channel 112R, a second gate dielectric 111R and a second gate 110R at the lower through hole 149R, thereby forming a read transistor 11R, as shown in FIG. Fig.19 shown.

[0143] Among them, the value of the target distance value mentioned in step S2042 can be 0, that is, the portions of the lower semiconductor film layer 151R, the lower gate dielectric film layer 152R and the lower gate film layer 153R that exceed the boundary of the lower through hole 149R are all etched away, but not limited to this. The value of the target distance value mentioned in step S2042 can also be greater than 0, but it must be less than half of the distance between adjacent lower through holes 149R. In this way, in addition to the portion located in the lower through hole 149R, the second semiconductor channel 112R, the second gate dielectric 111R and the second gate 110R prepared have portions extending in a direction away from the hole axis and resting on the upper surface of the lower isolation insulating film layer 142R, as shown in FIG. Fig.19 As shown, when forming a plurality of read transistors 11R arranged in an array, the etching difficulty can be reduced and the product quality can be ensured.

[0144] It should be understood that if step S2041 includes a lower conductive filling film layer 154R that entirely covers the lower gate film layer 153R, then in step S2042, in the process of etching away the portions of the lower semiconductor film layer 151R, the lower gate dielectric film layer 152R and the lower gate film layer 153R that exceed the target distance value from the hole boundary, the portion of the lower conductive filling film layer 154R that exceeds the target distance value from the hole boundary is also included in the process, wherein the remaining unetched portion of the lower conductive filling film layer 154R is defined as a lower conductive filling portion 115R, and the lower conductive filling portion 115R may be included in the read transistor 11R, a portion of the lower conductive filling portion 115R fills the lower through hole 149R and contacts the second gate 110R, and another portion overlaps the upper surface of the second gate 110R; it should be noted that the upper surface of the second gate 110 mentioned in the present disclosure refers to the surface of the second gate 110 that is farthest from the semiconductor substrate 10.

[0145] In step S206: an intermediate isolation insulating film layer 16 is formed on the lower stacked film layer, referring to Fig.23 As shown, the intermediate isolation insulating film layer 16 at least covers the area on the upper surface of the lower isolation insulating film layer 142R that is not covered by the read transistor 11R, and at least a portion of the second gate 110R does not overlap with the positive projection of the intermediate isolation insulating film layer 16 on the semiconductor substrate 10, that is, at least a portion of the second gate 110R is not blocked by the intermediate isolation insulating film layer 16, so as to facilitate connection with the first lower electrode 114W of the write transistor 11W formed subsequently.

[0146] Among them, reference Fig.23 As shown, if the portion of the second gate 110R located in the lower through hole 149R is U-shaped, and the lower through hole 149R is fully filled with the lower conductive filling portion 115R, the upper surface of the intermediate isolation insulating film layer 16 can be higher than the upper surface of the lower conductive filling portion 115R, and the intermediate isolation insulating film layer 16 has a plurality of intermediate vias 160 corresponding to the lower conductive filling portions 115R, and the intermediate vias 160 expose at least a portion of the upper surface of the lower conductive filling portion 115R. Fig.24 As shown, if the second gate 110R is fully filled with the lower through hole 149R, the upper surface of the intermediate isolation insulating film layer 16 can be higher than the upper surface of the second gate 110R, and the intermediate isolation insulating film layer 16 has a plurality of intermediate vias 160 corresponding one by one to the second gate 110R of the read transistor 11R, and the intermediate vias 160 expose at least a portion of the upper surface of the second gate 110R.

[0147] In step S208: forming an upper stacked film layer, refer to Fig.25As shown, the upper stacked film layer includes at least a first lower electrode 114W, an upper sacrificial insulating film layer 171W, a first upper electrode 113W and an upper isolation insulating film layer 172W stacked in sequence along the vertical direction Z, the first lower electrode 114W is connected to the second gate 110R, and the upper surface of the first lower electrode 114W is flush with the upper surface of the intermediate isolation insulating film layer 16.

[0148] For example, the material of the upper isolation insulating film layer 172W is different from the materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R to avoid the risk of removing the upper isolation insulating film layer 172W in the subsequent removal step of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R.

[0149] In some embodiments, reference Fig.25 As shown, the upper stacked film layer may also include a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, wherein the first upper interlayer dielectric layer 173W is formed between the first upper electrode 113W and the upper sacrificial insulating film layer 171W, and the second upper interlayer dielectric layer 174W is formed between the middle isolation insulating film layer 16 and the upper sacrificial insulating film layer 171W.

[0150] For example, the materials of the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W are different from the materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R to avoid the risk of removing the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W in the subsequent removal step of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, so that the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W can be used to protect the first upper electrode 113W and the first lower electrode 114W.

[0151] For example, the insulating materials of the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W, the upper isolation insulating film layer 172W, the middle isolation insulating film layer 16 and the lower isolation insulating film layer 142R may be the same, for example, all are silicon oxide, and the insulating materials of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R may be the same, for example, all are silicon nitride, silicon oxynitride or silicon carbon nitride, etc. It should be understood that the insulating materials of each interlayer dielectric layer, isolation insulating film layer and sacrificial insulating film layer are not limited to the materials exemplified above, but may also be other insulating materials, depending on the specific circumstances.

[0152] In some embodiments of the present disclosure, step S208 may specifically include step S2081, step S2082 and step S2083.

[0153] In step S2081: a plurality of first lower electrodes 114W are formed and arranged in an array along the first horizontal direction X and the second horizontal direction Y. The first lower electrodes 114W correspond to each other in the middle via hole 160. That is, each first lower electrode 114W is connected to a second gate 110R. Fig.26 and Fig. 27 shown.

[0154] It should be understood that if the second gate 110R fills the lower through hole 149R, the lower surface of the first lower electrode 114W is in direct contact with the upper surface of the second gate 110R to achieve direct connection between the first lower electrode 114W and the second gate 110R; wherein, the first lower electrode 114W and the second gate 110R can be integrally formed, but not limited to this, and the second gate 110R and the first lower electrode 114W can also be prepared separately, that is: the preparation of the second gate 110R is completed first, and then the preparation of the first lower electrode 114W is carried out; in addition, the first lower electrode 114W and the second gate 110R can be prepared using the same conductive material, but not limited to this, and can also be prepared using different conductive materials, depending on the specific circumstances.

[0155] If the portion of the second gate 110R located in the lower through hole 149R is U-shaped, and the lower through hole 149R is fully filled with the lower conductive filling portion 115R, the lower surface of the first lower electrode 114W is in direct contact with the upper surface of the lower conductive filling portion 115R, so as to achieve indirect connection with the second electrode through the lower conductive filling portion 115R; wherein, the first lower electrode 114W can be integrally formed with the lower conductive filling portion 115R, but is not limited to this, and the lower conductive filling portion 115R and the first lower electrode 114W can also be prepared separately, that is: first complete the preparation of the lower conductive filling portion 115R, and then prepare the first lower electrode 114W; in addition, the first lower electrode 114W and the lower conductive filling portion 115R can be prepared using the same conductive material, but is not limited to this, and can also be prepared using different conductive materials, depending on the specific circumstances.

[0156] For example, if the first lower electrode 114W and the second gate 110R are integrally formed or the first lower electrode 114W and the lower conductive filling portion 115R are integrally formed, the intermediate isolation insulating film layer 16 may be selected as an integrally formed whole-layer structure, for example: after the first lower electrode 114W and the second gate 110R or the lower conductive filling portion 115R are integrally formed, step S206 may specifically include: first forming an intermediate isolation insulating film that entirely covers the lower isolation insulating film layer 142R, the second gate 110R (or the lower conductive filling portion 115R) and the first lower electrode 114W, and then, removing the portion of the intermediate isolation insulating film that is higher than the upper surface of the first lower electrode 114W as a whole to form an intermediate isolation insulating film layer 16, the upper surface of which is flush with the upper surface of the first lower electrode 114W.

[0157] It should be understood that if the first lower electrode 114W is prepared separately from the second gate 110R or separately from the lower conductive filling portion 115R, the intermediate isolation insulating film layer 16 may also be an integrally formed whole-layer structure, for example: after the second gate 110R or the lower conductive filling portion 115R is formed, and before the first lower electrode 114W is formed, step S206 may specifically include: first forming an intermediate isolation insulating film that covers the entire surface of the lower isolation insulating film layer 142R and the second gate 110R (or the lower conductive filling portion 115R), and then removing the portion of the intermediate isolation insulating film that is connected to the second gate 110R (or the lower conductive filling portion 115R) to form an intermediate isolation insulating film layer 16 including the intermediate via 160; then, executing step S2081; but not limited to this, if the first lower electrode 114W is prepared separately from the second gate 110R or separately from the lower conductive filling portion 115R, the intermediate isolation insulating film Layer 16 can also be prepared in two layers, for example: after the second gate 110R or the lower conductive filling part 115R is formed, a first intermediate insulating film that completely covers the lower isolation insulating film layer 142R and the second gate 110R (or the lower conductive filling part 115R) can be formed first, and then the portion of the first intermediate insulating film that is higher than the upper surface of the second gate 110R (or the lower conductive filling part 115R) is completely removed to form a first intermediate insulating film layer, which covers the area on the upper surface of the lower isolation insulating film layer 142R that is not covered by the read transistor 11R, and then a second intermediate insulating film that completely covers the second intermediate insulating film layer and the second gate 110R (or the lower conductive filling part 115R) is formed, and then the second intermediate insulating film is subjected to a hole opening treatment to form a second intermediate insulating film layer including an intermediate via, and the second intermediate insulating film layer and the first intermediate insulating film layer constitute the intermediate isolation insulating film layer 16.

[0158] It should be noted that the step of preparing the second intermediate insulating film layer can be performed after the step of preparing the first lower electrode 114W, or can be performed before the step of preparing the first lower electrode 114W, depending on the specific situation, and will not be elaborated herein.

[0159] In step S2082, a second upper interlayer dielectric layer 174W, an upper sacrificial insulating film layer 171W and a first upper interlayer dielectric layer 173W are sequentially stacked on the upper surfaces of the intermediate isolation insulating film layer 16 and the first lower electrode 114W. Fig.26 and Fig. 27 shown.

[0160] In step S2083: a plurality of write bit lines 175W are formed on the first upper interlayer dielectric layer 173W, which are arranged at intervals in the second horizontal direction Y and extend in the first horizontal direction X, and a first lower isolation insulating portion 176W is formed between adjacent write bit lines 175W. Fig.26 and Fig. 27 As shown, in this embodiment, the first lower isolation insulating portion 176W can insulate adjacent write bit lines 175W from each other; wherein the write bit lines 175W can be formed on the first upper interlayer dielectric layer 173W before the first lower isolation insulating portion 176W, but is not limited to this, and the first lower isolation insulating portion 176W can also be formed first, and then a plurality of write bit lines 175W are formed.

[0161] In the embodiment of the present disclosure, the write bit line 175W may include a first upper electrode 113 , and an orthographic projection of the first upper electrode 113 and a first lower electrode 114W on the semiconductor substrate 10 has an overlapping region.

[0162] In step S2084: an upper isolation insulating film layer 172W is formed to entirely cover the write bit line 175W and the first lower isolation insulating portion 176W, and a Fig.26 and Fig. 27 shown.

[0163] In some other embodiments, the upper stacked film layer may not include the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, depending on specific circumstances.

[0164] In step S210: an upper through hole 177W is formed which at least penetrates the upper isolation insulating film layer 172W, the first upper electrode 113W and the upper sacrificial insulating film layer 171W. Fig.28 As shown, the first lower electrode 114W is exposed by the upper through hole 177W, that is, the upper through hole 177W may be opened at the region where the first upper electrode 113W and the first lower electrode 114W overlap correspondingly.

[0165] For example, the orthographic projections of the upper through hole 177W and the lower through hole 149R on the semiconductor substrate 10 can overlap, so that the write transistor 11W and the read transistor 11R of the storage unit overlap as much as possible in the vertical direction Z. While ensuring the performance of the storage unit, the horizontal area occupied by the storage unit can be reduced, so that more storage units can be arranged in a unit area to improve the storage density of the memory.

[0166] In some embodiments, when the upper stacked film layer further includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, the upper through hole 177W may also penetrate the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, referring to Fig.28 shown.

[0167] For example, refer to Fig.28 As shown, the orthographic projection of the upper through hole 177W on the semiconductor substrate 10 can completely cover the orthographic projection of the first lower electrode 114W on the semiconductor substrate 10. At this time, the lower surface of the upper through hole 177W can just extend to the upper surface of the first lower electrode 114W to avoid poor etching due to the different materials of the first lower electrode 114W and the intermediate isolation insulating film layer 16.

[0168] It should be understood that the orthographic projection of the upper through hole 177W on the semiconductor substrate 10 may be located within the orthographic projection of the first lower electrode 114W on the semiconductor substrate 10. At this time, the lower surface of the upper through hole 177W may extend to the interior of the first lower electrode 114W, so that the exposed area of ​​the first lower electrode 114W can be larger to increase the subsequent contact area with the semiconductor channel 112. In addition, while ensuring that the first lower electrode 114W is exposed, the etching accuracy can also be reduced, thereby reducing the etching cost. However, it should be understood that the lower surface of the upper through hole 177W is not limited to extending into the first lower electrode 114W, but may also just extend to the upper surface of the first lower electrode 114W.

[0169] In step S212: a first semiconductor channel 112W, a first gate dielectric 111W and a first gate 110W are sequentially formed at the upper through hole 177W to form a write transistor 11W, referring to Fig.29 As shown; wherein, the first region to be oxidized of the first semiconductor channel 112W corresponds to the upper sacrificial insulating film layer 171W, that is: the first region to be oxidized of the first semiconductor channel 112W is located at a position surrounded by the upper sacrificial insulating film layer 171W.

[0170] It should be noted that when the upper stacked film layer includes the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, after executing step S212, refer to Fig.29 As shown, the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W can both be arranged around the first effective semiconductor channel. Specifically, the first upper interlayer dielectric layer 173W can surround the area of ​​the first effective semiconductor channel located above the first area to be oxidized, and the second upper interlayer dielectric layer 174W can surround the area of ​​the first effective semiconductor channel located below the first area to be oxidized.

[0171] In some embodiments of the present disclosure, step S212 may include at least step S2121 and step S2122.

[0172] In step S2121: after forming the upper through hole 177W, an upper semiconductor thin film layer 181W, an upper gate dielectric thin film layer 182W and an upper gate thin film layer 183W are sequentially deposited on the upper stacked film layer, referring to Fig.30As shown, the upper semiconductor film layer 181W, the upper gate dielectric film layer 182W and the upper gate film layer 183W uniformly cover the upper stacked film layer, that is, the upper semiconductor film layer 181W, the upper gate dielectric film layer 182W and the upper gate film layer 183W can be deposited on the upper surface of the upper isolation insulating film layer 172W and deposited in the upper through hole 177W.

[0173] The upper semiconductor film layer 181W and the upper gate dielectric film layer 182W may have a U-shape in the upper through hole 177W, and the upper gate film layer 183W may have a U-shape in the upper through hole 177W. Fig.31 As shown; or the upper gate film layer 183W can fill the upper through hole 177W, refer to Fig.30 shown.

[0174] For example, the material of the upper semiconductor film layer 181W may be a semiconductor material such as IGZO, but is not limited to this, and may also be other semiconductor materials; the material of the upper gate dielectric film layer 182W may be a high dielectric insulating material such as silicon oxide, but is not limited to this, and may also be a low dielectric material, etc.; the material of the upper gate film layer 183W may be a conductive material with good gate control capability such as ZnO (zinc oxide), ITO (indium tin oxide), IZO (indium zinc oxide), etc., but is not limited to this, and may also be other conductive materials.

[0175] In step S2122: portions of the upper semiconductor film layer 181W, the upper gate dielectric film layer 182W and the upper gate film layer 183W that exceed the target distance value of the hole boundary of the upper through hole 177W are etched away to form a first semiconductor channel 112W, a first gate dielectric 111W and a first gate 110W at the upper through hole 177W, thereby forming a write transistor 11W.

[0176] In the embodiment of the present disclosure, the target distance value mentioned in step S2122 may be 0, that is, the portions of the upper semiconductor film layer 181W, the upper gate dielectric film layer 182W and the upper gate film layer 183W that exceed the boundary of the upper through hole 177W are all etched away, but not limited to this. The target distance value in step S2122 may also be greater than 0, but it must be less than half of the distance between adjacent upper through holes 177W. In this way, in addition to the portions located in the upper through holes 177W, the first semiconductor channel 112W, the first gate dielectric 111W and the first gate 110W prepared have portions extending in a direction away from the axis of the hole and resting on the upper surface of the upper isolation insulating film layer 172W, as shown in FIG. Fig.29 As shown, when forming a plurality of array-arranged write transistors 11W, the etching difficulty can be reduced and the product quality can be ensured.

[0177] When the portion of the first gate 110W located in the upper through hole 177W is U-shaped, Fig.29 As shown, the write transistor 11W in this embodiment may further include an upper conductive filling portion 115W that at least fills the upper through hole 177W. In this embodiment, the upper conductive filling portion 115W may be made of a conductive material with good conductivity and lower cost than the first gate 110W.

[0178] For example, the upper conductive filling portion 115W of the present embodiment may be columnar, and the upper surface of the columnar upper conductive filling portion 115W may be flush with the upper surface of the first gate 110W; but not limited thereto, the upper conductive filling portion 115W may also be T-shaped, referring to Fig.29 As shown, the T-shaped upper conductive filling portion 115W can not only fill the upper through hole 177W, but also cover the upper surface of the first gate 110W. The upper surface of the first gate 110W can be the surface of the first gate 110W farthest from the semiconductor substrate 10 .

[0179] In some embodiments, the manufacturing method of the upper conductive filling portion 115W may include: in step S2121: after depositing the upper gate film layer 183W, referring to Fig.31 As shown, an upper conductive filling film layer 184W is also deposited to cover the entire surface of the upper gate film layer 183W. After that, in the process of executing step S2112 to etch away the portions of the upper semiconductor film layer 181W, the upper gate dielectric film layer 182W and the upper gate film layer 183W that exceed the target distance value of the hole boundary, the portion of the upper conductive filling film layer 184W that exceeds the target distance value of the hole boundary is also etched away to form a T-shaped upper conductive filling portion; wherein, if a columnar upper conductive filling portion is to be formed, after executing step S2112, the portion of the T-shaped upper conductive filling portion that exceeds the upper surface of the first gate 110W can be removed to form a columnar upper conductive filling portion.

[0180] It should be noted that the columnar upper conductive filling portion is not limited to being prepared in the aforementioned manner, but can also be prepared in the following manner. For example, after executing step S2122 to form the first gate 110W, the first gate dielectric 111W and the first semiconductor channel 112W of the write transistor 11W: first deposit an upper conductive filling film layer 184W, and this upper conductive filling film layer 184W not only covers the entire surface of the structural layer located therebelow, but also fills the upper through hole 177W; then, pattern the upper conductive filling film layer 184W to form a filled columnar upper conductive filling portion in each upper through hole 177W.

[0181] In some embodiments of the present disclosure, after the write transistor 11W is formed, step S212 may further include: step S2131 , step S2132 , and step S2133 .

[0182] In step S2131: a filled isolation insulating portion 178W is formed on the upper surface of the upper isolation insulating film layer 172W, referring to Fig.32 As shown, the filled isolation insulating part 178W can cover the upper surface of the upper isolation insulating film layer 172W that is not covered by the write transistor 11W. It should be noted that if the first gate 110W itself fills the upper through hole 177W or the prepared columnar upper conductive filling part fills the upper through hole 177W, the upper surface of the filled isolation insulating part 178W formed here can be flush with the upper surface of the first gate 110W and the columnar upper conductive filling part. If the prepared T-shaped upper conductive filling part fills the upper through hole 177W: the upper surface of the filled isolation insulating part 178W formed here can be flush with the upper surface of the T-shaped upper conductive filling part to ensure that the subsequent write line is formed on the flush surface.

[0183] In step S2132: forming a plurality of write word lines 179W arranged at intervals in the first horizontal direction X and extending in the second horizontal direction Y, and forming a first upper isolation insulating portion 180W located between adjacent write word lines 179W, combining Fig.33 and Fig.34 shown.

[0184] Among them, the write line 179W can be connected to the first gate 110W of a plurality of write transistors 11W arranged at intervals in the second horizontal direction Y, wherein, if the first gate 110W itself fills up the upper through hole 177W: the write line 179W can be in direct contact with the first gate 110W to achieve direct connection between the two; if the upper through hole 177W is filled up with a T-shaped upper conductive filling portion: the write line 179W can be in direct contact with the upper surface of the T-shaped upper conductive filling portion to achieve indirect connection with the first gate 110W through the T-shaped upper conductive filling portion; if the upper through hole 177W is filled up with a columnar upper conductive filling portion: the write line 179W can be in direct contact with the upper surfaces of the first gate 110W and the columnar upper conductive filling portion at the same time to achieve connection between the three.

[0185] In step S2133: a capping insulating layer 19 is formed to cover the entire surface. The capping insulating layer 19 covers the write word line 179W and the filling isolation insulating portion 178W. Fig.35 As shown, the upper surface of the capping insulating layer 19 is a plane parallel or approximately parallel to the semiconductor substrate 10 .

[0186] In this embodiment, adjacent write word lines 179W are insulated from each other by a first upper isolation insulating portion 180W; specifically, the write word lines 179W may be formed prior to the first upper isolation insulating portion 180W, but is not limited thereto, and the first upper isolation insulating portion 180W may be formed first, and then a plurality of write word lines 179W may be formed.

[0187] In some embodiments, if the write line 179W is formed first and the first upper isolation insulating portion 180W is formed later: the first upper isolation insulating portion 180W can be formed integrally with the capping insulating layer 19, but is not limited to this. The first upper isolation insulating portion 180W can also be prepared separately from the capping insulating layer 19, that is: the first upper isolation insulating portion 180W is formed first, and then the capping insulating layer 19 is prepared.

[0188] In other embodiments, if the first upper isolation insulating portion 180W is formed first and the write line 179W is formed later: the first upper isolation insulating portion 180W can be formed integrally with the filled isolation insulating portion 178W, but is not limited to this. The first upper isolation insulating portion 180W can also be prepared separately from the filled isolation insulating portion 178W, that is: the filled isolation insulating portion 178W is formed first, and then the first upper isolation insulating portion 180W is prepared.

[0189] It should be understood that the write word line 179W in the present disclosure is not limited to being formed after the first gate 110W or the upper conductive filling portion 115W, and can also be formed integrally with the first gate 110W or the upper conductive filling portion 115W, depending on the specific situation, and will not be described in detail here. In addition, the present disclosure is not limited to the write bit line 175W extending in the first horizontal direction X and the write word line 179W extending in the second horizontal direction Y, and the write bit line 175W can also extend in the second horizontal direction Y and the write word line 179W extends in the first horizontal direction X, as long as the extension direction of the write word line 179W intersects with the extension direction of the write bit line 175W.

[0190] In step S214: after forming the write transistor 11W, the second portion 121 of the gas channel 12 is formed, and the second portion 121 does not overlap with the orthographic projections of the lower through hole 149R and the upper through hole 177W on the semiconductor substrate 10, referring to Fig.36 and Fig.37 As shown, the second portion 121 at least penetrates the upper isolation insulating film layer 172W, the upper sacrificial insulating film layer 171W, the middle isolation insulating film layer 16 and the lower isolation insulating film layer 142R, and exposes the lower sacrificial insulating film layer 141R, wherein the second portion 121 of the gas channel 12 can extend along the vertical direction Z to the interior of the lower sacrificial insulating film layer 141R, so that while reducing the process difficulty, the exposed area of ​​the lower sacrificial insulating film layer 141R can also be increased, thereby speeding up the subsequent etching rate of the lower sacrificial insulating film layer 141R, but not limited to this, the second portion 121 of the gas channel 12 can also just extend to the upper surface of the lower sacrificial insulating film layer 141R, or penetrate the lower sacrificial insulating film layer 141R.

[0191] In some embodiments, reference Fig.36As shown, the second portion 121 of the gas channel 12 can be prepared after the capping insulating layer 19 is formed. At this time, the "upper surface of the storage unit" in the aforementioned "second portion 121 extends vertically upward to the upper surface of the storage unit" refers to the upper surface of the capping insulating layer 19. That is to say, after the capping insulating layer 19 is formed, hole etching is performed vertically downward from the upper surface of the capping insulating layer 19 until the lower sacrificial insulating film layer 141R is etched. By preparing the second portion 121 of the gas channel 12 after the capping insulating layer 19, the capping insulating layer 19 can be used to protect the write transistor 11W and the write word line 179W to avoid damage to the write transistor 11W and the write word line 179W during subsequent hole etching.

[0192] In some other embodiments, the second portion 121 of the gas channel 12 may also be prepared after the write transistor 11W (or the upper conductive filling portion 115W) is formed and before the write word line 179W is formed. If the write transistor 11W is protected in this case, refer to Fig.37 As shown, after forming the write transistor 11W (or forming the upper conductive filling portion 115W), a first upper isolation insulating film layer 180 covering the entire surface can be formed. At this time, the "upper surface of the memory cell" in the aforementioned "second portion 121 vertically extends upward to the upper surface of the memory cell" refers to the upper surface of the first upper isolation insulating film layer 180, and then hole etching is performed vertically downward from the upper surface of the first upper isolation insulating film layer 180 until the lower sacrificial insulating film layer 141R is etched, and then subsequent steps are performed, wherein, after the first oxidation channel 1120W and the second oxidation channel 1120R are formed and the second portion 121 of the gas channel 12 is partially or completely filled with insulating material, the first upper isolation insulating film layer 180 is etched to form a first upper isolation insulating portion 180W, and then the write line 179W and the capping insulating layer 19 are formed, and so on.

[0193] In some embodiments, reference Fig.36 and Fig.37 As shown, when the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, and the upper stacked film layer includes a first upper interlayer dielectric layer 173W and a second upper interlayer dielectric layer 174W, the second part 121 of the gas channel 12 can also penetrate the first upper interlayer dielectric layer 173W, the second upper interlayer dielectric layer 174W and the first lower interlayer dielectric layer 143R.

[0194] In some embodiments, reference Fig.38As shown, the second portion 121 of the gas channel 12 does not overlap with the orthographic projections of the write word line 179W, the write bit line 175W, the second lower signal line 145R, and the second upper signal line 147R on the semiconductor substrate 10, so as to ensure the performance of the write word line 179W, the write bit line 175W, the second lower signal line 145R, and the second upper signal line 147R. Among them, since the second portion 121 of the gas channel 12 does not overlap with the orthographic projections of the write word line 179W, the write bit line 175W, the second lower signal line 145R, and the second upper signal line 147R on the semiconductor substrate 10, the second portion 121 of the gas channel 12 can penetrate the first upper isolation insulating portion 180W, the first lower isolation insulating portion 176W, and the second upper isolation insulating portion 148R in addition to penetrating the aforementioned film layers, refer to Fig.36 shown.

[0195] In some embodiments, reference Fig.38 As shown, a plurality of second parts 121 of the gas channel 12 may be provided, and a plurality of second parts 121 may surround the periphery of each storage unit C. This not only accelerates the etching rate of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, but also ensures etching uniformity.

[0196] In step S216, an etchant is introduced into the second portion 121 to remove the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, thereby forming an upper first portion 120W disposed around the first region to be oxidized and a lower first portion 120R disposed around the second region to be oxidized. Fig.39 shown.

[0197] In the process of removing the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R by using an etchant, the first lower interlayer dielectric layer 143R, the second lower interlayer dielectric layer 144R, the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W are retained, that is, they are not etched by the etchant or are etched very little.

[0198] For example, the etchant of this embodiment may be a liquid, but is not limited to this, and may also be a gas; wherein, when the insulating material of the aforementioned interlayer dielectric layer, isolation insulating film layer, and isolation insulating portion is silicon oxide, and the insulating material of the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R is silicon nitride, silicon oxynitride or silicon carbon nitride, etc., this embodiment may use chlorine gas or liquid phosphoric acid to completely etch the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, but is not limited to this. This embodiment may also use other etchants to etch the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R, as long as the etchant can etch away the upper sacrificial insulating film layer 171W and the lower sacrificial insulating film layer 141R while having little or no effect on the aforementioned interlayer dielectric layer, isolation insulating film layer, and isolation insulating portion, so as to retain the aforementioned interlayer dielectric layer, isolation insulating film layer, and isolation insulating portion.

[0199] Implementation Method 2

[0200] In the embodiment of the present disclosure, the first oxidation channel 1120W of the write transistor 11W and the second oxidation channel 1120R of the read transistor 11R can be prepared separately. Specifically, the second oxidation channel 1120R of the read transistor 11R can be formed first, and then the first oxidation channel 1120W of the write transistor 11W can be formed, so that the quality of the first oxidation channel 1120W and the second oxidation channel 1120R can be guaranteed.

[0201] When the first oxidation channel 1120W of the write transistor 11W and the second oxidation channel 1120R of the read transistor 11R are formed by separate preparation, the aforementioned gas channel 12 needs to include two channels manufactured successively, that is, the gas channel 12 may include: Fig.41 The first gas channel 12W shown in FIG. Fig.40 As shown in the second gas channel 12R, the first gas channel 12W and the second gas channel 12R are prepared separately, and the second gas channel 12R is prepared before the first gas channel 12W.

[0202] Among them, reference Fig.40 As shown, the second gas channel 12R includes a first portion 120 disposed around the second region to be oxidized, and a second portion 121 communicating with the first portion 120 of the second gas channel 12 and extending vertically upward to the upper surface of the read transistor 11R, Fig.41 As shown, the first gas channel 12W includes a first portion 120 surrounding the first area to be oxidized, and a second portion 121 communicating with the first portion 120 of the first gas channel 12W and extending vertically upward to the upper surface of the storage unit.

[0203] Based on this, the manufacturing method of this embodiment includes: firstly, oxidizing the second to-be-oxidized region of the second effective semiconductor channel of the read transistor 11R to form a second oxidized channel 1120R, referring to Fig.42 After forming the second oxidation channel 1120R, the second gas channel 12R is filled with an insulating material to form a second filling body 13R, referring to Fig.43 As shown, the upper surface of the second filling body 13R can be flush with the upper surface of the second gas channel 12R to ensure the flatness of the upper surface of the structural layer, which is conducive to the preparation of the subsequent structural layer; then the first to-be-oxidized region of the first effective semiconductor channel of the write transistor 11W is oxidized to form a first oxidized channel 1120W, referring to Fig.44 After forming the first oxidation channel 1120W, the first gas channel 12W is filled with an insulating material to form a first filling body 13, reference Fig.45 As shown, the upper surface of the first filling body 13 is flush with the upper surface of the first gas channel 12W to ensure that the upper surface of the storage array structure is flat, which is beneficial to the preparation of subsequent structural layers.

[0204] In a specific embodiment of the present disclosure, the method for manufacturing the first gas channel 12W may include steps S300 , S302 , S304 , S306 , S308 , and S310 .

[0205] Among them, step S300 can refer to the description of the aforementioned step S200, step S302 can refer to the description of the aforementioned step S202, and step S304 can refer to the description of the aforementioned step S204. The contents of step S300, step S302 and step S304 will not be elaborated here.

[0206] In step S306: an intermediate isolation insulating film layer 16 is formed on the lower stacked film layer, and the intermediate isolation insulating film layer 16 at least covers the area on the upper surface of the lower isolation insulating film layer 142R that is not covered by the read transistor 11R; wherein, the intermediate isolation insulating film layer 16 formed in step S306 may also completely cover the read transistor 11R to protect the read transistor 11R. It should be understood that when a lower conductive filling portion 115R is formed at the read transistor 11, the intermediate isolation insulating film layer 16 formed in step S306 may also completely cover the read transistor 11 while also completely covering the lower conductive filling portion 115R to simultaneously protect the read transistor 11 and the lower conductive filling portion 115R, but is not limited thereto, and at least a portion of the second gate 110R or the lower conductive filling portion 115R may not be blocked by the intermediate isolation insulating film layer 16 to facilitate subsequent direct connection, indirect connection or integral molding of the first lower electrode 114W and the second gate 110R, depending on actual conditions.

[0207] In step S308: forming the second portion 121 of the second gas channel 12R, referring to Fig.46 As shown; the second portion 121 of the second gas channel 12R does not overlap with the orthographic projection of the lower through hole 149R on the semiconductor substrate 10, and the second portion 121 of the second gas channel 12R at least passes through the intermediate isolation insulating film layer 16 and the lower isolation insulating film layer 142R, and exposes the lower sacrificial insulating film layer 141R.

[0208] Among them, the second part 121 of the second gas channel 12R does not overlap with the orthographic projections of the read word line and the read bit line on the semiconductor substrate 10, so as to ensure the performance of the read word line and the read bit line. Since the second part 121 of the second gas channel 12R does not overlap with the orthographic projections of the read word line and the read bit line on the semiconductor substrate 10, the second part 121 of the second gas channel 12R can not only penetrate the aforementioned film layer, but also penetrate the second upper isolation insulating portion 148R; in addition, the lower stacked film layer includes a first lower interlayer dielectric layer 143R and a second lower interlayer dielectric layer 144R, and the second part 121 of the second gas channel 12R can also penetrate the first lower interlayer dielectric layer 143R.

[0209] It should be noted that the second portion 121 of the second gas channel 12R mentioned above extends vertically upward to the upper surface of the read transistor 11R, and the “upper surface of the read transistor 11R” here can be understood as the upper surface of the structural layer where the read transistor 11R is located, wherein the structural layer where the read transistor 11R is located includes a lower stacked film layer and an intermediate isolation insulating film layer 16 located above the lower stacked film layer. Therefore, the “upper surface of the read transistor 11R” can be understood as the upper surface of the intermediate isolation insulating film layer 16. In other words, the second portion 121 of the second gas channel 12R can extend vertically downward from the upper surface of the intermediate isolation insulating film layer 16 to the lower sacrificial insulating film layer 141R, refer to Fig.41 shown.

[0210] In some embodiments, the second portion 121 of the second gas channel 12R may extend along the vertical direction Z to the interior of the lower sacrificial insulating film layer 141R, so that while reducing the process difficulty, the exposed area of ​​the lower sacrificial insulating film layer 141R may be increased, thereby accelerating the subsequent etching rate of the lower sacrificial insulating film layer 141R, but is not limited thereto, refer to Fig.46 As shown, the second portion 121 of the second gas channel 12R may also just extend to the upper surface of the lower sacrificial insulating film layer 141R, or penetrate the lower sacrificial insulating film layer 141R.

[0211] In some embodiments, multiple second portions 121 of the second gas channel 12R may be provided, and each read transistor 11R may be surrounded by multiple second portions 121 of the second gas channel 12R. This can not only speed up the etching rate of the lower sacrificial insulating film layer 141R, but also ensure etching uniformity.

[0212] In step S310, an etchant is introduced into the second portion 121 of the second gas channel 12R to remove the lower sacrificial insulating film layer 141R, thereby forming a first portion 120 of the second gas channel 12R disposed around the second region to be oxidized. Fig.42 As shown. Among them, the limitation of the etching agent can be referred to the aforementioned contents, and will not be elaborated here.

[0213] After step S310 is performed, the oxidizing gas is introduced through the second portion 121 of the second gas channel 12R, and the oxidizing gas acts on the second region to be oxidized through the first portion 120 of the second gas channel 12R to oxidize the second region to be oxidized to form a second oxidation channel 1120R. After the second oxidation channel 1120R is formed, the second gas channel 12R is filled with an insulating material to form a second filling body 13R. Fig.43 As shown, the upper surface of the second filling body 13R can be flush with the upper surface of the intermediate isolation insulating film layer 16 to facilitate the subsequent formation of the write transistor 11W and the structural layer where it is located.

[0214] In some embodiments, when the second gas channel 12R is filled with insulating material, a complete filling method may be adopted, that is, referring to Fig.43 As shown, the formed second filling body 13R can completely fill the first part 120 and the second part 121 in the second gas channel 12R to ensure structural stability. However, it is not limited to this. In other embodiments, refer to Fig.47 As shown, an insulating material may also be used to fill a portion of the second gas channel 12R, that is, the formed second filling body 13R may partially or completely fill the second portion 121 of the second gas channel 12R; for example, a quick sealing method may be used to fill the insulating material in the second portion 121 of the second gas channel 12R to form a second filling body 13R in the second portion 121 of the second gas channel 12R.

[0215] It should be understood that when the second filling body 13R partially or completely fills the second portion 121 of the second gas channel 12R, the second gas channel 12R except the area filled by the second filling body 13R is a gap area. Fig.47As shown, at least the first portion 120 of the second gas channel 12R may be a void region not filled by the second filler 13R, which may reduce the parasitic capacitance between the second upper electrode 113R and the second lower electrode 114R in the read transistor 11R.

[0216] In a specific embodiment of the present disclosure, the method for manufacturing the first gas channel 12W may include step S400 , step S402 , step S404 , step S406 , and step S408 .

[0217] Among them, step S400 can refer to the description of the aforementioned step S208, step S402 can refer to the description of the aforementioned step S210, and step S404 can refer to the description of the aforementioned step S212. The contents of step S400, step S402 and step S404 will not be elaborated here.

[0218] In step S406: after forming the write transistor 11W, the second portion 121 of the first gas channel 12W is formed, referring to Fig.48 As shown; the second portion 121 of the first gas channel 12W does not overlap with the orthographic projection of the upper through hole 177W on the semiconductor substrate 10, and the second portion 121 of the first gas channel 12W at least penetrates the upper isolation insulating film layer 172W and exposes the upper sacrificial insulating film layer 171W.

[0219] The second portion 121 of the first gas channel 12W may extend along the vertical direction Z to the interior of the upper sacrificial insulating film layer 171W, thereby reducing the process difficulty and increasing the exposed area of ​​the upper sacrificial insulating film layer 171W, thereby accelerating the subsequent etching rate of the upper sacrificial insulating film layer 171W, but is not limited thereto, and reference is made to Fig.48 As shown, the second portion 121 of the first gas channel 12W may also just extend to the upper surface of the upper sacrificial insulating film, or penetrate the upper sacrificial insulating film.

[0220] In addition, multiple second portions 121 of the first gas channel 12W may be provided, and each write transistor 11W may be surrounded by multiple second portions 121 of the first gas channel 12W, which can not only accelerate the etching rate of the upper sacrificial insulating film layer 171W, but also ensure etching uniformity.

[0221] In some embodiments, the manufacturing method of the first gas channel 12W may further include step S4051, step S4052 and step S4053. Step S4051 may refer to the description of the aforementioned step S2131, step S4052 may refer to the description of the aforementioned step S2132, and step S4053 may refer to the description of the aforementioned step S2133. The contents of step S4051, step S4052 and step S4053 will not be elaborated herein.

[0222] Among them, the second part 121 of the first gas channel 12W may not overlap with the orthographic projections of the write word line 179W and the write bit line 175W on the semiconductor substrate 10 to ensure the performance of the write word line 179W and the write bit line 175W. Since the second part 121 of the first gas channel 12W does not overlap with the orthographic projections of the write word line 179W and the write bit line 175W on the semiconductor substrate 10, the second part 121 of the first gas channel 12W can not only penetrate the aforementioned film layers, but also penetrate the first upper isolation insulating part 180W and the first lower isolation insulating part 176W; in addition, the upper stacked film layers include the first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W, and the second part 121 of the first gas channel 12W can also penetrate the first upper interlayer dielectric layer 173W.

[0223] It should be noted that the second portion 121 of the first gas channel 12W mentioned above vertically extends upward to the upper surface of the storage unit. Here, "the upper surface of the storage unit" can be understood as the upper surface of the capping insulating layer 19. That is, after the capping insulating layer 19 is formed, Fig.49 As shown, hole etching is performed vertically downward from the upper surface of the capping insulating layer 19 until the upper sacrificial insulating film layer 171W is etched. By preparing the second part 121 of the first gas channel 12W after the capping insulating layer 19, the capping insulating layer 19 can be used to protect the write transistor 11W and the write word line 179W to avoid damage to the write transistor 11W and the write word line 179W during subsequent hole etching. However, it is not limited to this. The second part 121 of the first gas channel 12W can also be prepared after the write transistor 11W (or the upper conductive filling portion 115W) is formed and before the write word line 179W is formed. If the write transistor 11W is protected in this case, a first upper isolation insulating film layer 180 covering the entire surface can be formed after the write transistor 11W is formed (or the upper conductive filling portion 115W is formed). At this time, the "upper surface of the storage unit" mentioned above refers to the upper surface of the first upper isolation insulating film layer 180, and then refer to Fig.48 As shown, hole etching is performed vertically downward from the upper surface of the first upper isolation insulating film layer 180 until the upper sacrificial insulating film layer 171W is etched; and then subsequent steps are performed, wherein, after the first oxidation channel 1120W is formed and the first gas channel 12W is filled with insulating material, the first upper isolation insulating film layer 180 is etched to form a first upper isolation insulating portion 180W, and then the write line 179W and the capping insulating layer 19 are formed, and so on.

[0224] In step S408, an etchant is introduced into the second portion 121 of the first gas channel 12W to remove the upper sacrificial insulating film layer 171W, thereby forming a first portion 120 of the first gas channel 12W disposed around the first region to be oxidized. Fig.50 As shown; among them, regarding the limitation of the etchant, please refer to the aforementioned records and will not be elaborated here.

[0225] After step S408 is performed, the oxidizing gas is introduced through the second portion 121 of the first gas channel 12W, and the oxidizing gas acts on the first region to be oxidized through the first portion 120 of the first gas channel 12W to oxidize the first region to be oxidized to form a first oxidation channel 1120W. After the first oxidation channel 1120W is formed, the first gas channel 12W is filled with an insulating material to form a first filling body 13W. Fig.51 As shown, the upper surface of the first filling body 13W can be flush with the upper surface of the storage unit to facilitate the formation of subsequent structural layers. In some embodiments, when the first gas channel 12W is filled with an insulating material, a complete filling method can be adopted, that is, the formed first filling body 13W can completely fill the first part 120 and the second part 121 in the first gas channel 12W, referring to Fig.45 As shown, to ensure structural stability. However, it is not limited thereto. In other embodiments, insulating materials may also be used to fill a portion of the first gas channel 12W, that is, Fig.51 As shown, the formed first filling body 13W can partially or completely fill the second part 121 of the first gas channel 12W; for example, the insulating material can be filled in the second part 121 of the first gas channel 12W by a quick sealing method to form the first filling body 13W in the second part 121 of the first gas channel 12W.

[0226] It should be understood that when the first filling body 13W partially or completely fills the second portion 121 of the first gas channel 12W, the first gas channel 12W except the area filled by the first filling body 13W is a gap area. Fig.51 As shown, at least the first portion 120 of the first gas channel 12W may be a void region not filled by the first filler 13W, which may reduce the parasitic capacitance between the first upper electrode 113W and the first lower electrode 114W in the write transistor 11W.

[0227] The embodiment of the present disclosure also provides a memory, including a semiconductor substrate 10 and at least one memory cell. The memory cell is formed on the semiconductor substrate 10, and the memory cell includes at least one transistor 11, each transistor 11 includes a gate 110, a gate dielectric 111, a semiconductor channel 112, an upper electrode 113 and a lower electrode 114, the semiconductor channel 112 at least surrounds the outer peripheral side of the gate 110, the gate dielectric 111 is formed between the semiconductor channel 112 and the gate 110, the upper electrode 113 and the lower electrode 114 are both located outside the semiconductor channel 112 and in contact with the semiconductor channel 112, the lower electrode 114 is insulated and arranged below the upper electrode 113, and one of the upper electrode 113 and the lower electrode 114 is a source and the other is a drain.

[0228] Wherein: in the memory cell: a portion of the effective semiconductor channel in at least one transistor 11 is oxidized to form an oxidized channel, the effective semiconductor channel is the portion of the semiconductor channel 112 located between the upper electrode 113 and the lower electrode 114, and the upper electrode 113 and the lower electrode 114 are not in contact with the oxidized channel, reference Figure 8 , Fig. 9 or Fig.10 shown.

[0229] It should be understood that the memory of the embodiment of the present disclosure can be manufactured using the manufacturing method described in any of the aforementioned embodiments, and no further details will be given here; however, it is not limited to this, and the memory of the embodiment of the present disclosure can also be formed using other preparation methods.

[0230] In an embodiment of the present disclosure, there are a plurality of memory cells, which are arranged in a horizontal plane to form a memory array structure, and each memory cell includes two transistors 11, namely a read transistor 11R and a write transistor 11W. The write transistor 11W includes a first gate 110W, a first gate dielectric 111W, a first semiconductor channel 112W, a first upper electrode 113W, and a first lower electrode 114W; the read transistor 11R includes a second gate 110R, a second gate dielectric 111R, a second semiconductor channel 112R, a second upper electrode 113R, and a second lower electrode 114R; the write transistor 11W is located above the read transistor 11R, and the first lower electrode 114W is conductively connected to the second gate 110R; wherein a portion of the effective semiconductor channel 112 of at least one of the write transistor 11W and the read transistor 11R is oxidized to form an oxidized channel 1120, with reference to FIG. Figure 8 , Fig. 9 or Fig.10 shown.

[0231] In the storage array structure: a plurality of storage units are arranged in an array in a first horizontal direction X and a second horizontal direction Y, and the first horizontal direction X intersects with the second horizontal direction Y. Fig.38For example, the first horizontal direction X and the second horizontal direction Y are perpendicular or approximately perpendicular to each other.

[0232] Combination Fig.26 , Fig. 27 , Fig.33 , Fig.34 and Fig.38 As shown, the memory further includes a second lower signal line 145R, a second upper signal line 147R, a write word line 179W and a write bit line 175W; the second lower signal line 145R extends in the second horizontal direction Y, and a plurality of second lower signal lines 145R are provided and arranged at intervals in the first horizontal direction X, and each second lower signal line 145R is connected to a second lower electrode 114 of each read transistor 11R arranged in a row in the second horizontal direction Y; the second upper signal line 147R extends in the first horizontal direction X, and a plurality of second lower signal lines 145R are provided and arranged at intervals in the second horizontal direction Y, the second upper signal line 147R is located on a side of the second lower signal line 145R away from the semiconductor substrate 10, and each second upper signal line 147R is connected to a second upper electrode 114 of each read transistor 11R arranged in a row in the first horizontal direction X. The second upper signal line 147R and the second lower signal line 145R are connected to each other, one of which is a read word line and the other is a read bit line; a write bit line 175W is formed on a side of the second upper signal line 147R away from the semiconductor substrate 10, and a write word line 179W is formed on a side of the write bit line 175W away from the semiconductor substrate 10, wherein one of the write word line 179W and the write bit line 175W extends in the first horizontal direction X and a plurality of them are arranged at intervals in the second horizontal direction Y, and the other extends in the second horizontal direction Y and a plurality of them are arranged at intervals in the first horizontal direction X, each write bit line 175W is connected to a row of first upper electrodes 113 of each write transistor 11W arranged in the extension direction thereof, and each write word line 179W is connected to a row of first gates 110W of each write transistor 11W arranged in the extension direction thereof.

[0233] In some embodiments, a portion of the first effective semiconductor channel 112 of the write transistor 11W is oxidized to form a first oxidized channel 1120W, a first gap region is formed between the first upper electrode 113 and the first lower electrode 114, and the first gap region is arranged around the first oxidized channel 1120W. Fig.14 and Fig.51 shown.

[0234] Further, refer to Fig.14 and Fig.51As shown, a first upper interlayer dielectric layer 173W is formed between the first upper electrode 113 and the first gap region, and a second upper interlayer dielectric layer 174W is formed between the first lower electrode 114 and the first gap region. The first upper interlayer dielectric layer 173W and the second upper interlayer dielectric layer 174W are both arranged around the first effective semiconductor channel 112 and do not contact the first oxidation channel 1120W.

[0235] In some other embodiments, a portion of the first effective semiconductor channel 112 of the write transistor 11W is oxidized to form a first oxidized channel 1120W, a first insulating layer is formed between the first upper electrode 113 and the first lower electrode 114, the first insulating layer surrounds the first oxidized channel 1120W, and is seamlessly connected to the lower surface of the first upper electrode 113 and the upper surface of the first lower electrode 114, Fig. 9 , Fig.10 , Fig.13 or Fig.45 shown.

[0236] For example, the first insulating layer may be a composite film layer including a first upper interlayer dielectric layer 173W, a second upper interlayer dielectric layer 174W, and a first filler 13W.

[0237] In some embodiments, a portion of the second effective semiconductor channel 112 of the read transistor 11R is oxidized to form a second oxidized channel 1120R, a second gap region is formed between the second upper electrode 113 and the second lower electrode 114, and the second gap region is arranged around the second oxidized channel 1120R. Fig.14 or Figures 47 to 51 shown.

[0238] Furthermore, a first lower interlayer dielectric layer 143R is formed between the second upper electrode 113 and the second gap region, and a second lower interlayer dielectric layer 144R is formed between the second lower electrode 114 and the second gap region. Both the first lower interlayer dielectric layer 143R and the second lower interlayer dielectric layer 144R are arranged around the second effective semiconductor channel 112 and do not contact the second oxidation channel 1120R.

[0239] In other embodiments, a portion of the second effective semiconductor channel 112 of the read transistor 11R is oxidized to form a second oxidized channel 1120R, a second insulating layer is formed between the second upper electrode 113 and the second lower electrode 114, the second insulating layer surrounds the second oxidized channel 1120R, and is seamlessly connected to the lower surface of the second upper electrode 113 and the upper surface of the second lower electrode 114, Figure 8 , Fig.10 , Fig.13 or Fig.44 shown.

[0240] For example, the second insulating layer may be a composite film layer including a first lower interlayer dielectric layer 143R, a second lower interlayer dielectric layer 144R, and a second filler 13R.

[0241] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0242] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0243] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A method for manufacturing a memory, characterized in that: The following steps are involved: Providing a semiconductor substrate; At least one memory cell is prepared on the semiconductor substrate, the memory cell includes at least one transistor, each of the transistors includes a gate, a gate dielectric, a semiconductor channel, an upper electrode and a lower electrode, the semiconductor channel at least surrounds the outer peripheral side of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is insulated and arranged below the upper electrode, one of the upper electrode and the lower electrode is a source electrode, and the other is a drain electrode; An oxidation treatment is performed on a region to be oxidized of an effective semiconductor channel in at least one of the transistors in the storage unit so that the region to be oxidized is formed into an oxidized channel, wherein the region to be oxidized is at least a portion of the effective semiconductor channel, and neither the upper electrode nor the lower electrode is in contact with the oxidized channel; wherein the effective semiconductor channel is the portion of the semiconductor channel located between the upper electrode and the lower electrode.

2. The method for manufacturing a memory according to claim 1, characterized in that: After the region to be oxidized is oxidized, the method further comprises: heat treating the oxidized region to be oxidized; or While the oxidation treatment is being performed on the area to be oxidized, the method further includes: performing a heat treatment on the area to be oxidized.

3. The method for manufacturing a memory according to claim 1 or 2, characterized in that: Before the area to be oxidized is oxidized, the manufacturing method further includes preparing a gas channel, wherein the gas channel includes a first portion arranged around the outer peripheral side of the area to be oxidized, and a second portion connected to the first portion and extending vertically upward, so that the oxidizing gas introduced from above the second portion acts on the area to be oxidized.

4. The method for manufacturing a memory according to claim 3, characterized in that: After forming the oxidation channel, the manufacturing method further includes: filling the gas channel with an insulating material.

5. The method for manufacturing a memory according to claim 4, characterized in that: The step of filling the gas channel with insulating material comprises: completely filling the gas channel with insulating material to form a filling body in the gas channel, wherein the upper surface of the filling body is flush with the upper surface of the gas channel.

6. The method for manufacturing a memory according to claim 4, characterized in that: The step of filling the gas channel with insulating material includes: partially or completely filling the second part of the gas channel with insulating material to form a filling body in the second part, the upper surface of the filling body is flush with the upper surface of the gas channel, wherein the gas channel except the area filled with the filling body is a void area.

7. The method for manufacturing a memory according to claim 4, characterized in that: There are multiple storage cells, which are arranged on a horizontal plane to form a storage array structure, and each storage cell includes two transistors, namely a read transistor and a write transistor; The write transistor comprises: a first gate, a first gate dielectric, a first semiconductor channel, a first upper electrode and a first lower electrode; The read transistor includes: a second gate, a second gate dielectric, a second semiconductor channel, a second upper electrode, and a second lower electrode; The write transistor is located above the read transistor, and the first lower electrode and the second gate are conductively connected; The manufacturing method includes: performing oxidation treatment on a region to be oxidized of an effective semiconductor channel of at least one of the write transistor and the read transistor.

8. The method for manufacturing a memory according to claim 7, characterized in that: The manufacturing method comprises: performing oxidation treatment on a to-be-oxidized region of an effective semiconductor channel of one of the write transistor and the read transistor to form an oxidized channel; The gas channel is prepared after the transistor corresponding to the area to be oxidized is prepared.

9. The method for manufacturing a memory according to claim 7, characterized in that: The manufacturing method comprises: performing oxidation treatment on a first region to be oxidized of a first effective semiconductor channel in the write transistor, so that the first region to be oxidized forms a first oxidized channel; and An oxidation process is performed on a second region to be oxidized of a second effective semiconductor channel in the read transistor, so that the second region to be oxidized is formed into a second oxidized channel.

10. The method for manufacturing a memory according to claim 9, characterized in that: The first oxidation channel and the second oxidation channel are formed simultaneously, and the gas channel is prepared after the preparation of the write transistor is completed; Among them, the first part of the gas channel includes an upper first part surrounding the outer peripheral side of the first area to be oxidized and a lower first part surrounding the outer peripheral side of the second area to be oxidized, the upper first part and the lower first part are spaced apart in the vertical direction, and the second part extends vertically upward to the upper surface of the storage unit and connects the upper first part and the lower first part, so that the oxidizing gas introduced from above the second part acts on the first area to be oxidized and the second area to be oxidized at the same time for oxidation treatment.

11. The method for manufacturing a memory according to claim 10, characterized in that: The method for manufacturing the gas channel comprises: forming a lower stacked film layer on the semiconductor substrate, wherein the lower stacked film layer at least comprises the second lower electrode, a lower sacrificial insulating film layer, the second upper electrode and a lower isolating insulating film layer sequentially stacked in a vertical direction; forming a lower through hole at least penetrating the lower isolation insulating film layer, the second upper electrode and the lower sacrificial insulating film layer, wherein the second lower electrode is exposed by the lower through hole; forming the second semiconductor channel, the second gate dielectric and the second gate at the lower through hole to form the read transistor, wherein the second region to be oxidized of the second semiconductor channel is located at a position surrounded by the lower sacrificial insulating film layer; forming an intermediate isolation insulating film layer on the lower stacked film layer, wherein the intermediate isolation insulating film layer at least covers a region of an upper surface of the lower isolation insulating film layer that is not covered by the read transistor, and at least a portion of the second gate does not overlap with an orthographic projection of the intermediate isolation insulating film layer on the semiconductor substrate; forming an upper stacked film layer, the upper stacked film layer at least comprising the first lower electrode, an upper sacrificial insulating film layer, a first upper electrode and an upper isolating insulating film layer stacked in sequence along a vertical direction, the first lower electrode being connected to the second gate, and an upper surface of the first lower electrode being flush with an upper surface of the intermediate isolating insulating film layer; forming an upper through hole at least penetrating the upper isolation insulating film layer, the first upper electrode and the upper sacrificial insulating film layer, wherein the first lower electrode is exposed by the upper through hole; The first semiconductor channel, the first gate dielectric and the first gate are sequentially formed at the upper through hole to form the write transistor, wherein the first region to be oxidized of the first semiconductor channel is located at a position surrounded by the upper sacrificial insulating film layer; After forming the write transistor, forming the second portion of the gas channel, the second portion does not overlap with the orthographic projections of the lower through hole and the upper through hole on the semiconductor substrate, and the second portion at least penetrates the upper isolation insulating film layer, the upper sacrificial insulating film layer, the middle isolation insulating film layer and the lower isolation insulating film layer, and exposes the lower sacrificial insulating film layer; An etchant is introduced into the second portion to remove the upper sacrificial insulating film layer and the lower sacrificial insulating film layer to form an upper first portion surrounding the first region to be oxidized and a lower first portion surrounding the second region to be oxidized.

12. The method for manufacturing a memory according to claim 9, characterized in that: The gas channel includes a first gas channel and a second gas channel; the first gas channel includes a first portion surrounding the first region to be oxidized, and a second portion communicating with the first portion of the first gas channel and extending vertically upward to the upper surface of the memory cell; the second gas channel includes a first portion surrounding the second region to be oxidized, and a second portion communicating with the first portion of the second gas channel and extending vertically upward to the upper surface of the read transistor; wherein the manufacturing method includes: Firstly, the second to-be-oxidized region of the second effective semiconductor channel of the read transistor is oxidized to form a second oxidation channel, and after the second oxidation channel is formed, the second gas channel is filled with an insulating material to form a second filling body, wherein the upper surface of the second filling body is flush with the upper surface of the second gas channel; Then, the first to-be-oxidized region of the first effective semiconductor channel of the write transistor is oxidized to form a first oxidation channel, and after the first oxidation channel is formed, the first gas channel is filled with an insulating material to form a first filling body, wherein the upper surface of the first filling body is flush with the upper surface of the first gas channel.

13. The method for manufacturing a memory according to claim 12, characterized in that: The second filling body completely fills the first part and the second part of the second gas channel; Alternatively, the second filling body partially or completely fills the second portion of the second gas channel, wherein the second gas channel except the area filled by the second filling body is a void area.

14. The method for manufacturing a memory according to claim 12, wherein: The first filling body completely fills the first part and the second part in the first gas channel; Alternatively, the first filling body partially or completely fills the second portion of the first gas channel, wherein the first gas channel except the area filled by the first filling body is a void area.

15. The method for manufacturing a memory according to claim 12, characterized in that: The manufacturing method of the first gas channel comprises: forming a lower stacked film layer on the semiconductor substrate, wherein the lower stacked film layer at least comprises the second lower electrode, a lower sacrificial insulating film layer, the second upper electrode and a lower isolating insulating film layer stacked in sequence; forming a lower through hole at least penetrating the lower isolation insulating film layer, the second upper electrode and the lower sacrificial insulating film layer, wherein the second lower electrode is exposed by the lower through hole; forming the second semiconductor channel, the second gate dielectric and the second gate at the lower through hole to form the read transistor, wherein the second region to be oxidized of the second semiconductor channel is located at a position surrounded by the lower sacrificial insulating film layer; forming an intermediate isolation insulating film layer on the lower stacked film layer, wherein the intermediate isolation insulating film layer at least covers the area of ​​the upper surface of the lower isolation insulating film layer that is not covered by the read transistor; forming a second portion of a second gas channel, wherein the second portion of the second gas channel does not overlap with the orthographic projection of the lower through hole on the semiconductor substrate, and the second portion of the second gas channel at least penetrates the intermediate isolation insulating film layer and the lower isolation insulating film layer, and exposes the lower sacrificial insulating film layer; An etchant is introduced into the second portion of the second gas channel to remove the lower sacrificial insulating film layer, thereby forming a first portion of the second gas channel disposed around the second region to be oxidized.

16. The method for manufacturing a memory according to claim 15, characterized in that: The manufacturing method of the first gas channel comprises: forming an upper stacked film layer, wherein the upper stacked film layer at least comprises the first lower electrode, an upper sacrificial insulating film layer, a first upper electrode and an upper isolating insulating film layer stacked in sequence, wherein the first lower electrode is connected to the second gate electrode, and an upper surface of the first lower electrode is flush with an upper surface of the intermediate isolating insulating film layer; forming an upper through hole at least penetrating the upper isolation insulating film layer, the first upper electrode and the upper sacrificial insulating film layer, wherein the first lower electrode is exposed by the upper through hole; The first semiconductor channel, the first gate dielectric and the first gate are sequentially formed at the upper through hole to form the write transistor, wherein the first region to be oxidized of the first semiconductor channel is located at a position surrounded by the upper sacrificial insulating film layer; After forming the write transistor, forming the second portion of the first gas channel, the second portion of the first gas channel not overlapping with the orthographic projection of the upper through hole on the semiconductor substrate, and the second portion of the first gas channel at least penetrates the upper isolation insulating film layer to expose the upper sacrificial insulating film layer; An etchant is introduced into the second portion of the first gas channel to remove the upper sacrificial insulating film layer, thereby forming a first portion of the first gas channel disposed around the first region to be oxidized.

17. The manufacturing method according to claim 11 or 16, characterized in that: The lower stacked film layer further includes a first lower interlayer dielectric layer and a second lower interlayer dielectric layer made of a material different from that of the lower sacrificial insulating film layer, wherein the first lower interlayer dielectric layer is formed between the second upper electrode and the lower sacrificial insulating film layer and is disposed around the second effective semiconductor channel; the second lower interlayer dielectric layer is formed between the second lower electrode and the lower sacrificial insulating film layer and is disposed around the second effective semiconductor channel; The upper stacked film layer further includes a first upper interlayer dielectric layer and a second upper interlayer dielectric layer made of a material different from that of the upper sacrificial insulating film layer, wherein the first upper interlayer dielectric layer is formed between the first upper electrode and the upper sacrificial insulating film layer and is disposed around the first effective semiconductor channel; the second upper interlayer dielectric layer is formed between the first lower electrode and the upper sacrificial insulating film layer and is disposed around the first effective semiconductor channel; Wherein, in the process of removing the upper sacrificial insulating film layer and the lower sacrificial insulating film layer by using the etchant, the first lower interlayer dielectric layer, the second lower interlayer dielectric layer, the first upper interlayer dielectric layer and the second upper interlayer dielectric layer are retained.

18. A memory, characterized in that: include: Semiconductor substrate; as well as At least one memory cell is formed on the semiconductor substrate, the memory cell includes at least one transistor, each of the transistors includes a gate, a gate dielectric, a semiconductor channel, an upper electrode and a lower electrode, the semiconductor channel at least surrounds the outer peripheral side of the gate, the gate dielectric is formed between the semiconductor channel and the gate, the upper electrode and the lower electrode are both located outside the semiconductor channel and in contact with the semiconductor channel, the lower electrode is insulated and arranged below the upper electrode, one of the upper electrode and the lower electrode is a source, and the other is a drain; Wherein, in the memory cell: a partial area of ​​an effective semiconductor channel in at least one of the transistors is oxidized to form an oxidized channel, the effective semiconductor channel is a portion of the semiconductor channel located between the upper electrode and the lower electrode, and neither the upper electrode nor the lower electrode is in contact with the oxidized channel.

19. The memory according to claim 18, characterized in that: There are multiple storage cells, which are arranged on a horizontal plane to form a storage array structure, and each storage cell includes two transistors, namely a read transistor and a write transistor; The write transistor comprises: a first gate, a first gate dielectric, a first semiconductor channel, a first upper electrode and a first lower electrode; The read transistor includes: a second gate, a second gate dielectric, a second semiconductor channel, a second upper electrode, and a second lower electrode; The write transistor is located above the read transistor, and the first lower electrode and the second gate are conductively connected; A partial region of the effective semiconductor channel of at least one of the write transistor and the read transistor is formed into the oxidized channel through oxidation treatment.

20. The memory according to claim 19, characterized in that In the storage array structure: a plurality of the storage units are arranged in an array in a first horizontal direction and a second horizontal direction, and the first horizontal direction intersects with the second horizontal direction.

21. The memory according to claim 20, characterized in that The memory also includes: a plurality of second lower signal lines arranged at intervals in the first horizontal direction and extending in the second horizontal direction, each of the second lower signal lines being connected to a row of second lower electrodes of the read transistors arranged in the second horizontal direction; a plurality of second upper signal lines arranged at intervals in the second horizontal direction and extending in the first horizontal direction, the second upper signal lines being located on a side of the second lower signal lines away from the semiconductor substrate, and each of the second upper signal lines being connected to a row of second upper electrodes of the read transistors arranged in the first horizontal direction, one of the second upper signal line and the second lower signal line being a read word line, and the other being a read bit line; and A write word line and a write bit line, wherein the write bit line is formed on a side of the second upper signal line away from the semiconductor substrate, and the write word line is formed on a side of the write bit line away from the semiconductor substrate, wherein one of the write word line and the write bit line extends in a first horizontal direction and a plurality of lines are arranged at intervals in a second horizontal direction, and the other extends in the second horizontal direction and a plurality of lines are arranged at intervals in the first horizontal direction, each of the write bit lines is connected to a first upper electrode of each of the write transistors arranged in a row in the direction of its extension, and each of the write word lines is connected to a first gate of each of the write transistors arranged in a row in the direction of its extension.

22. The memory according to claim 19, characterized in that A partial region of the first effective semiconductor channel of the write transistor is oxidized to form a first oxidation channel, a first gap region is formed between the first upper electrode and the first lower electrode, and the first gap region is arranged around the first oxidation channel; A partial region of the second effective semiconductor channel of the read transistor is oxidized to form a second oxidation channel, a second gap region is formed between the second upper electrode and the second lower electrode, and the second gap region is arranged around the second oxidation channel.

23. The memory according to claim 22, characterized in that A first upper interlayer dielectric layer is formed between the first upper electrode and the first gap region, a second upper interlayer dielectric layer is formed between the first lower electrode and the first gap region, and the first upper interlayer dielectric layer and the second upper interlayer dielectric layer are both arranged around the first effective semiconductor channel and are not in contact with the first oxidation channel; A first lower interlayer dielectric layer is formed between the second upper electrode and the second gap region, and a second lower interlayer dielectric layer is formed between the second lower electrode and the second gap region. Both the first lower interlayer dielectric layer and the second lower interlayer dielectric layer are arranged around the second effective semiconductor channel and do not contact the second oxidation channel.

24. The memory according to claim 19, characterized in that A partial region of the first effective semiconductor channel of the write transistor is oxidized to form a first oxidation channel, a first insulating layer is formed between the first upper electrode and the first lower electrode, the first insulating layer is arranged around the first oxidation channel, and is seamlessly connected to the lower surface of the first upper electrode and the upper surface of the first lower electrode; A partial area of ​​the second effective semiconductor channel of the read transistor is formed into a second oxidation channel through oxidation treatment, and a second insulating layer is formed between the second upper electrode and the second lower electrode. The second insulating layer is arranged around the second oxidation channel and is seamlessly connected to the lower surface of the second upper electrode and the upper surface of the second lower electrode.

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