Multi-chip stacking packaging structure and manufacturing method thereof

Abstract

The present invention provides a multi-chip stacking packaging structure and a manufacturing method thereof, wherein a plurality of packaging units are stacked on a substrate in sequence along the longitudinal direction, and a plastic encapsulation layer II covers all the packaging units; the packaging unit includes a plastic encapsulation layer I, a memory chip and an interposer chip, the memory chip and the interposer chip are interconnected through a rewiring layer, and the packaging units are electrically connected through connection bumps. The present invention combines fan-out packaging technology with TSV technology, and does not require each packaging unit to include a substrate, thereby realizing a lightweight packaging structure, and the signal is vertically transmitted through the interposer chip, and it is not necessary to process TSV on the memory chip; the present invention also increases the number of connection points of the memory chip through the rewiring layer, so that the interconnection between the packaging units is easier and faster to achieve; and the present invention improves the structure of NCF, with the first film layer with low fluidity playing a supporting role to reduce the overflow of the adhesive film, and the second film layer with high fluidity is melted first, so that the connection bumps are easier to pass through and the cold solder joints are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a multi-chip stacking packaging structure and a manufacturing method thereof. Background Art

[0002] With the development of science and technology, the amount of data transmission is becoming increasingly huge, which leads to an increasing demand for the capacity of electronic device memory. In order to meet the needs of high data transmission capacity and large storage capacity, the memory also needs to have higher bandwidth and lower power consumption. In order to increase the bandwidth of the memory, multiple chips need to be stacked and packaged to increase the memory capacity.

[0003] In the chip stacking packaging process, there are currently two more common ways to achieve interconnection between stacked chips: one is to bond the stacked chips layer by layer through wires on four sides, such as the packaging process used by LPDDR; the other is to interconnect the stacked chips through TSV (through silicon via) technology, such as the packaging process used by HBM. However, the method of interconnecting chips through wire bonding is prone to long signal transmission delays and limited bandwidth due to the long total length of the wires and carrier circuits, and this bonding method is expensive and has poor heat dissipation. The method of interconnecting chips through TSV technology requires the preparation of through silicon vias (TSV, throughsilicon via) and micro copper pillars on the chip. Some chips have complex and high-density circuit structures and there is no space to design TSV. After stacking, wire bonding or vertical interconnect technology cannot be used.

[0004] Chinese patent CN110010589A discloses a stacked semiconductor packaging method and packaging structure, including preparing a plurality of packaging units, wherein the packaging units include a substrate and a semiconductor chip, and the substrate includes a circuit and a plurality of conductive plugs connected to the circuit. This patent has great defects: (1) Each packaging unit must include a substrate. The increase in the number of packaging units leads to an increase in the thickness of the corresponding number of substrates, making it difficult for the packaging structure to be extremely light and thin; (2) Each substrate must be processed with a connecting circuit, which is very costly; (3) The packaging units are bonded by ordinary adhesive layers, which are prone to cold solder joints, voids, and overflow of the adhesive layer, resulting in short circuits, excessive packaging volume, and other problems; (4) After multiple packaging units are stacked together, they are plastic-sealed, and the gaps between individual packaging units are difficult to be plastic-sealed properly, and the circuits are prone to short circuits, which reduces the yield rate of the packaging structure. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a multi-chip stacked packaging structure and a manufacturing method thereof, so as to solve the problems in the prior art that multi-chip packaging is difficult to balance transmission stability and lightness, and the adhesive layer is prone to cold solder joints, voids, and overflow of the adhesive layer.

[0006] To achieve the above objectives and other related objectives, the present invention provides the following technical solutions:

[0007] According to a first aspect of the present invention, a multi-chip stacked packaging structure is provided, comprising a substrate, a packaging unit and a plastic encapsulation layer II, wherein a plurality of packaging units are stacked in sequence on the substrate in the longitudinal direction, and the plastic encapsulation layer II covers the substrate and covers all the packaging units; the packaging unit comprises a plastic encapsulation layer I, a memory chip and an interposer chip, wherein at least one memory chip and at least one interposer chip with a through silicon via (TSV) are encapsulated in parallel in the plastic encapsulation layer I, a redistribution layer (RDL) and a connection bump are formed on the upper and lower surfaces of the packaging unit, respectively, the memory chip and the interposer chip are interconnected through the redistribution layer, and the packaging units are electrically connected through the connection bumps.

[0008] Furthermore, the substrate is inverted, and the packaging units are also inverted on the substrate in sequence along the longitudinal direction; that is, the memory chips and interposer chips in the substrate and the packaging units are all facing downward and facing upward.

[0009] Furthermore, the connection bumps on the upper surface and the connection bumps on the lower surface of the packaging unit correspond to each other. When the packaging units are stacked, the connection bumps on the upper and lower surfaces of adjacent packaging units are aligned and welded to achieve electrical connection between the packaging units.

[0010] Furthermore, a plurality of connection bumps are formed on the upper surface (ie, the back surface) of the substrate, and the connection bumps on the upper surface of the substrate correspond to the connection bumps on the lower surface (ie, the front surface) of the bottommost packaging unit.

[0011] In one embodiment of the present invention, the memory chip and the interposer chip in the package unit are interconnected with the memory chip and the interposer chip in the adjacent package unit through the redistribution layer and the connection bumps, respectively.

[0012] Furthermore, a non-conductive film (NCF) is filled between adjacent packaging units and between the bottom packaging unit and the substrate. The non-conductive film surrounds each connection bump and bonds the packaging units and the packaging units and the substrate.

[0013] In one embodiment of the present invention, the non-conductive adhesive film includes a first film layer and a second film layer, the first film layer has a groove or a through hole at a position corresponding to each connection bump, and the second film layer is arranged in the groove or the through hole. Under the same conditions, the fluidity of the second film layer is greater than the fluidity of the first film layer.

[0014] The melting point of the first film layer with low fluidity is greater than that of the second film layer with high fluidity. Therefore, the first film layer has lower fluidity and is less likely to be melted than the second film layer. In the subsequent hot pressing bonding process, the first film layer and the second film layer are melted and stacked. The first film layer has a certain supporting effect to prevent the NCF from overflowing, and the second film layer is melted first to enable the connection bumps to be bonded.

[0015] Furthermore, the content of filler in the first film layer is higher than the content of filler in the second film layer.

[0016] Furthermore, the first film layer includes 30-60 wt% of filler, and the second film layer includes 10-30 wt% of filler. The filler may include silica filler, but is not limited thereto.

[0017] The first film layer includes 30~60wt% filler, which has low fluidity and high support force, and will not cause too much non-conductive adhesive film to be squeezed out of the packaging unit, thus improving the problem of glue overflow and thus not affecting the stacking process of subsequent packaging units. The second film layer only includes 10~30wt% filler, which has high fluidity and is softened first during the hot pressing process, making it easier for the connection bumps to pass through the grooves or through holes, which will not affect the electrical connection of the connection bumps and improve the cold solder joints; and the second film layer at the groove or through hole position has less filler and lighter color, which can improve the recognition alignment, thereby improving the alignment accuracy between the NCF film and the connection bumps; in addition, the second film layer has higher fluidity, and after curing, it can fully fill the gaps between the connection bumps and reduce holes, and can also reduce protrusions and bulges after curing, ensuring the level of each layer of the packaging unit during the stacking process, increasing the number of stackable layers, and improving the quality of the packaging structure.

[0018] In a preferred embodiment of the present invention, the first film layer includes 30-60 wt % of filler, 5-15 wt % of curing agent, and 35-65 wt % of epoxy resin.

[0019] The curing agent is selected from at least one of alicyclic acid anhydride, aromatic amine curing agent, aliphatic amine curing agent, phenolic curing agent and latent curing agent. The amount of the curing agent added is equivalent to 10% to 20% of the epoxy resin.

[0020] In a preferred embodiment of the present invention, the second film layer includes 10-30 wt % of filler, 10-20 wt % of active diluent, 5-15 wt % of plasticizer, 5-20 wt % of curing agent, and 35-70 wt % of epoxy resin.

[0021] The curing agent of the second film layer is preferably an acid anhydride curing agent, which can increase the cross-linking density and strengthen the bonding strength between the packaging units.

[0022] Wherein, the active diluent is selected from at least one of bisphenol A epoxy resin diluent, polyether diluent, glycidyl ether diluent, glycidyl ester diluent and glycidyl amine diluent.

[0023] The plasticizer is selected from at least one of phthalate plasticizers, fatty acid ester plasticizers, polyester plasticizers, phosphate plasticizers, and epoxidized plasticizers.

[0024] The addition of appropriate amounts of active diluent and plasticizer can not only soften the second film layer system, which is conducive to the connection bumps penetrating the second film layer, but the active diluent can also cause a certain proportion of slight shrinkage in the second film layer during the curing process, so that the film at the connection bump position will not bulge, thereby ensuring the flatness of the film layer.

[0025] In one embodiment of the present invention, the groove or the through hole is disposed on the upper surface of the first film layer, and the second film layer is disposed in the groove or the through hole.

[0026] Furthermore, the height of the top surface of the second film layer is not higher than the height of the top surface of the first film layer.

[0027] Furthermore, the height of the top surface of the second film layer is consistent with the height of the top surface of the first film layer.

[0028] In another embodiment of the present invention, the groove is arranged on the lower surface of the first film layer, and the second film layer is arranged in the groove. That is, when the non-conductive film is processed, the groove is still opened on the upper surface of the first film layer, but when it is used, it is turned upside down so that the groove is located on the lower surface of the first film layer.

[0029] Furthermore, the height of the bottom surface of the second film layer is not lower than the height of the bottom surface of the first film layer.

[0030] Furthermore, the height of the bottom surface of the second film layer is higher than that of the bottom surface of the first film layer, so that the non-conductive film has a certain depression corresponding to the position of the connection bump, which facilitates the alignment of the non-conductive film with the packaging unit of the lower layer during the bonding process.

[0031] Furthermore, the substrate itself has through silicon vias (TSV) and redistribution layers (RDL).

[0032] Furthermore, the substrate is selected from a silicon adapter (passive component, pure interposer) or a logic chip with TSV / RDL (active component).

[0033] Furthermore, a plurality of lead-out solder balls are formed on the lower surface (front surface) of the substrate, and the lead-out solder balls are connected to the circuit of the substrate.

[0034] Furthermore, the lead solder ball may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, silver (Ag), zinc (Zn), lead (Pb) and / or alloys thereof. For example, the lead solder ball may include at least one of Sn, Pb, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn and Sn-Bi-Zn.

[0035] Furthermore, the memory chip is selected from at least one of DRAM, SRAM, flash memory, EEPROM, PRAM, MRAM and RPAM.

[0036] Furthermore, the interposer chip is manufactured separately, and there is no need to process TSV on the memory chip.

[0037] Furthermore, the plastic encapsulation layer I covers the memory chip and the intermediate layer chip to form the packaging unit; the plastic encapsulation layer II covers all the packaging units stacked together to form the multi-chip stacked packaging structure of the present application.

[0038] Furthermore, the material of the plastic sealing layer I / the plastic sealing layer II includes a thermosetting material, and the thermosetting material is selected from at least one of epoxy resin and silicone.

[0039] A second aspect of the present invention provides a method for manufacturing a multi-chip stacked packaging structure, comprising at least the following steps:

[0040] (1) Prepare several packaging units:

[0041] Feeding a carrier and coating a peeling layer, mounting the back sides of the memory chip and the interposer chip on the peeling layer in parallel, using a plastic encapsulation layer I to cover the memory chip and the interposer chip to form a package, grinding a pad on the front side of the package and making a front side redistribution layer (RDL) and connection bumps, then using a carrier coated with a peeling layer to temporarily glue the front side of the package, removing the carrier on the back side of the package, inverting it, making a back side redistribution layer (RDL) and connection bumps on the back side of the package, removing the carrier on the front side and cutting it to obtain the package unit;

[0042] (2) Preparation of substrate:

[0043] Feeding a wafer, making a front redistribution layer (RDL) and lead-out solder balls on the front side of the wafer, temporarily gluing the front side of the wafer with a carrier coated with a peeling layer, grinding a solder pad on the back side of the wafer after inverting it, making a back redistribution layer (RDL) and connection bumps on the back side of the wafer, and obtaining the substrate;

[0044] (3) Stacking of several packaging units:

[0045] A non-conductive film (NCF) is used to adhere several packaging units layer by layer to the upper surface (back side) of the substrate, and the substrate and the packaging units, and the packaging units are joined together through a thermal compression process, wherein the connection bumps between adjacent packaging units and the connection bumps between the substrate and the packaging units are aligned and joined, and a plastic encapsulation layer II is used to cover all the packaging units on the substrate. After removing the carrier, cleaning, and cutting, the multi-chip stacked packaging structure is obtained.

[0046] As described above, the multi-chip stacking packaging structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0047] 1. The present invention combines fan-out packaging technology with TSV technology to realize parallel packaging and interconnection of memory chips and interposer chips with through silicon vias (TSVs). It is not necessary for each packaging unit to include a substrate, nor is it necessary for each memory chip to have its own TSV, so that the chip's available area is more economical, the thickness of the packaging unit is thinner, the processing technology is simpler, and the cost is lower; the memory chip in each packaging unit is interconnected with the interposer chip through a rewiring layer to realize vertical transmission of signals and speed up transmission. It is not necessary to process TSV on the memory chip, so as to avoid chip damage due to processing; the memory chip in each packaging unit is also interconnected with adjacent stacked memory chips through a rewiring layer to realize multiple electrical connections, increase the number of connection points, enrich the connection network, and make the interconnection between packaging units easier and faster to realize.

[0048] 2. The non-conductive adhesive film of the present invention is composed of a first film layer and a second film layer. A groove or a through hole is opened at the position of the first film layer corresponding to each connecting bump, and a second film layer with high fluidity is injected therein. The first film layer has lower fluidity and is less likely to melt than the second film layer, and can play a good supporting role and reduce overflow of the adhesive film. The second film layer melts first, making it easier for the connecting bumps to pass through the grooves or through holes to prevent cold solder joints. The second film layer with high fluidity can fully fill the gaps between the connecting bumps, reduce holes, and reduce protrusions and bulges after curing. In addition, the present invention mainly adjusts the fluidity by adjusting the filler content in the NCF, so that the second film layer at the groove or through hole has a color difference, which can provide an identification and alignment basis to ensure the alignment of the NCF with the packaging unit.

[0049] 3. The present invention first coats each packaging unit with a plastic packaging layer I to ensure that each chip is fully plastic-sealed, effectively preventing electrical interference and short circuit problems between chips, and the thickness of the packaging unit is close to the thickness of the chip, without increasing the thickness of the packaging structure; after multiple packaging units are stacked, the entirety is plastic-sealed with a plastic packaging layer II, which can provide sufficient mechanical strength to protect the packaging structure from physical shock, vibration and stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 This is a schematic diagram of the structure of the multi-chip stacking packaging structure disclosed in Example 1 of the present invention.

[0051] Figure 2 It is a schematic diagram of the disassembly of the multi-chip stacking packaging structure disclosed in Example 1 of the present invention.

[0052] Figure 3a~3h This is a diagram of the preparation process of the packaging unit disclosed in Example 2 of the present invention.

[0053] Figure 4a~4e This is a diagram of the preparation process of the substrate disclosed in Example 2 of the present invention.

[0054] Figure 5a~5d This is a diagram of the assembly process of the packaging unit and the substrate disclosed in Example 2 of the present invention.

[0055] Figure 6 Schematic diagram of the structure of the non-conductive adhesive film disclosed in Example 3 of the present invention.

[0056] Figure 7 Schematic diagram of the structure of the non-conductive adhesive film disclosed in Example 5 of the present invention.

[0057] Figure 8 Schematic diagram of the structure of the non-conductive adhesive film disclosed in Example 6 of the present invention.

[0058] Fig. 9Schematic diagram of the structure of the non-conductive adhesive film disclosed in Example 7 of the present invention.

[0059] Component number description

[0060] 100, substrate; 110, lead-out solder balls; 200, packaging unit; 210, memory chip; 220, interposer chip; 230, redistribution layer; 240, connection bumps; 250, plastic encapsulation layer I; 300, non-conductive adhesive film; 310, first film layer; 320, second film layer; 400, plastic encapsulation layer II; 500, carrier; 510, peeling layer. DETAILED DESCRIPTION

[0061] The following specific embodiments illustrate the implementation of the present invention, and those familiar with the technology can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0062] Example 1

[0063] refer to Figure 1 , 2 The present embodiment provides a multi-chip stacking packaging structure, including a substrate 100, a packaging unit 200 and a plastic layer II 400, wherein four packaging units are stacked in sequence on the substrate in the longitudinal direction, and the plastic layer II covers the substrate and covers all the packaging units; the packaging unit includes a plastic layer I 250, a memory chip 210 and an interposer chip 220, wherein two memory chips 210 and one interposer chip 220 with a through silicon via (TSV) are encapsulated in parallel in the plastic layer I, and the interposer chip is located between the two memory chips; a rewiring layer 230 and a connection bump 240 are formed on the upper surface and the lower surface of the packaging unit, respectively, and the memory chip and the interposer chip are interconnected through the rewiring layer 230, and the packaging units and the packaging units and the substrate are electrically connected through the connection bump 240.

[0064] The connection bumps on the upper surface of the packaging unit correspond to the connection bumps on the lower surface. When the packaging units are stacked, the connection bumps on the upper and lower surfaces of adjacent packaging units are aligned for welding connection to achieve electrical connection between the packaging units.

[0065] The memory chip in any packaging unit is interconnected with the memory chip and the intermediate layer chip in the adjacent packaging unit through the rewiring layer and the connection bumps; the intermediate layer chip in any packaging unit is interconnected with the intermediate layer chip in the adjacent packaging unit through the rewiring layer and the connection bumps.

[0066] Among them, the substrate is inverted, and the four packaging units are also inverted in the longitudinal direction in sequence, that is, the memory chips and intermediate layer chips in the substrate and the packaging units are all facing downward and the back side is facing upward.

[0067] The upper surface (i.e., the back surface) of the substrate is formed with a plurality of connection bumps, which correspond to the connection bumps on the lower surface (i.e., the front surface) of the bottom package unit. The lower surface (front surface) of the substrate is also formed with a plurality of lead-out solder balls, which are connected to the circuit of the substrate.

[0068] A non-conductive adhesive film 300 is filled between adjacent packaging units and between the bottom packaging unit and the substrate. The non-conductive adhesive film surrounds each connection bump and connects the packaging units and the packaging units and the substrate.

[0069] The memory chip is selected from DRAM. The interposer chip is manufactured separately without processing TSV on the memory chip.

[0070] The substrate itself has through-silicon vias and redistribution layers.

[0071] The material of the plastic sealing layer I / plastic sealing layer II includes a thermosetting material, and the thermosetting material is selected from epoxy resin.

[0072] Example 2

[0073] This embodiment provides a method for manufacturing the multi-chip stacking packaging structure in Embodiment 1, comprising the following steps:

[0074] (1) Prepare several packaging units:

[0075] refer to Figure 3a , feeding a carrier 500 and coating a release layer 510;

[0076] refer to Figure 3b , mounting the back sides of the memory chip 210 and the interposer chip 220 side by side on the peeling layer;

[0077] refer to Figure 3c , the memory chip and the interposer chip are encapsulated with a plastic encapsulation layer I 250 to form a package, and pads are ground on the front of the package;

[0078] refer to Figure 3d , making a front rewiring layer 230 and connection bumps 240 on the front side of the package;

[0079] refer to Figure 3e , temporarily gluing the front side of the package using a carrier 500 coated with a peeling layer 510;

[0080] refer to Figure 3f , removing the carrier on the back side of the package;

[0081] refer to Figure 3g , after inverting, a backside rewiring layer 230 and connection bumps 240 are made on the backside of the package;

[0082] refer to Figure 3h , removing the carrier on the front side of the package and cutting it to obtain a package unit 200;

[0083] (2) Preparation of substrate:

[0084] refer to Figure 4a , feeding wafer;

[0085] refer to Figure 4b , manufacturing a front redistribution layer 230 and lead-out solder balls 110 on the front side of the wafer;

[0086] refer to Figure 4c , temporarily gluing the front side of the wafer using a carrier 500 coated with a release layer;

[0087] refer to Figure 4d , after inverting the wafer, grind the pads on the back side;

[0088] refer to Figure 4e , manufacturing a backside redistribution layer 230 and connection bumps 240 on the backside of the wafer to obtain the substrate 100;

[0089] (3) Stacking of several packaging units:

[0090] refer to Figure 5a , a plurality of packaging units 200 are laminated on the upper surface (back surface) of the substrate 100 layer by layer using a non-conductive adhesive film 300, and the substrate and the packaging units are bonded together and between the packaging units by a thermal compression process, wherein the connection bumps 240 between adjacent packaging units and the connection bumps 240 between the substrate and the packaging units are aligned and bonded;

[0091] refer to Figure 5b , using a plastic packaging layer II 400 to cover all the packaging units 200 on the substrate;

[0092] refer to Figure 5c After removing the carrier 500, cleaning and cutting, the following is obtained: Figure 5d The multi-chip stacking packaging structure shown.

[0093] Example 3

[0094] This embodiment provides a multi-chip stacking packaging structure, and the technical features provided by the structure include all the technical features disclosed in Embodiments 1 and 2, except that:

[0095] refer to Figure 6The non-conductive adhesive film 300 includes a first film layer 310 and a second film layer 320. The first film layer has a groove at a position corresponding to each connection bump. The groove is arranged on the upper surface of the first film layer, and the second film layer is arranged in the groove. Under the same conditions, the fluidity of the second film layer is greater than the fluidity of the first film layer.

[0096] The height of the top surface of the second film layer is consistent with the height of the top surface of the first film layer.

[0097] The first film layer includes 50wt% nano-silicon dioxide filler and the remainder is epoxy resin; the second film layer includes 20wt% nano-silicon dioxide filler and the remainder is epoxy resin.

[0098] Example 4

[0099] This embodiment provides a multi-chip stacking packaging structure, and the technical features provided by the structure include all the technical features disclosed in Embodiment 3, except that:

[0100] Among them, the first film layer includes 50wt% nano-silica filler, 5wt% aromatic amine curing agent, and the balance is epoxy resin; the second film layer includes 20wt% nano-silica filler, 15wt% glycidyl ether diluent, 10wt% phthalate plasticizer, 5wt% anhydride curing agent, and the balance is epoxy resin.

[0101] Example 5

[0102] This embodiment provides a multi-chip stacking packaging structure, and the technical features provided by the structure include all the technical features disclosed in Embodiment 3, except that:

[0103] refer to Figure 7 The groove is arranged on the lower surface of the first film layer, and the second film layer is arranged in the groove or through hole. When the non-conductive adhesive film is processed, the groove is still opened on the upper surface of the first film layer, but when it is used, it is turned upside down so that the groove is located on the lower surface of the first film layer.

[0104] The first film layer includes 60wt% of nano-silicon dioxide filler, and the balance is epoxy resin; the second film layer includes 30wt% of nano-silicon dioxide filler, and the balance is epoxy resin.

[0105] Example 6

[0106] This embodiment provides a multi-chip stacking packaging structure, and the technical features provided by the structure include all the technical features disclosed in Embodiments 1 and 2, except that:

[0107] refer to Figure 8The non-conductive adhesive film includes a first film layer and a second film layer. The first film layer has a through hole at a position corresponding to each connection bump, and the second film layer is arranged in the through hole. Under the same conditions, the fluidity of the second film layer is greater than the fluidity of the first film layer.

[0108] The height of the top surface of the second film layer is consistent with the height of the top surface of the first film layer.

[0109] The bottom height of the top surface of the second film layer is consistent with the height of the bottom surface of the first film layer.

[0110] Among them, the first film layer includes 50wt% nano-silica filler, 5wt% phenolic curing agent, and the balance is epoxy resin; the second film layer includes 20wt% nano-silica filler, 15wt% bisphenol A epoxy resin diluent, 10wt% epoxidized plasticizer, 5wt% anhydride curing agent, and the balance is epoxy resin.

[0111] Example 7

[0112] This embodiment provides a multi-chip stacking packaging structure, and the technical features provided by the structure include all the technical features disclosed in Embodiment 6, except that:

[0113] refer to Fig. 9 The height of the bottom surface of the second film layer is higher than that of the bottom surface of the first film layer, so that the non-conductive film has a certain depression corresponding to the position of the connection bump, which facilitates the alignment of the non-conductive film with the packaging unit of the lower layer during the bonding process.

[0114] In summary, the present invention combines fan-out packaging technology and TSV technology, and does not require each packaging unit to include a substrate, thereby realizing a lightweight and thin packaging structure. Signals are vertically transmitted through the intermediate layer chip, and TSV does not need to be processed on the memory chip. The memory chip is also interconnected with the adjacent stacked memory chips through the rewiring layer, increasing the number of connection points, making the interconnection between the packaging units easier and faster to achieve. In addition, the present invention improves the structure of the non-conductive adhesive film, and the first film layer with low fluidity plays a supporting role to reduce the overflow of the adhesive film, and the second film layer with high fluidity is melted first, making it easier to pass the connection bumps and reducing cold solder joints. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0115] Among them, the terms such as "upper", "lower", "left", "right", "front", "back", "middle" and "one" cited in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships should be regarded as the scope of implementation of the present invention without substantially changing the technical content.

[0116] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. All equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A multi-chip stacking packaging structure, characterized in that: It comprises a substrate, a packaging unit and a plastic encapsulation layer II, wherein a plurality of packaging units are stacked in sequence on the substrate in the longitudinal direction, and the plastic encapsulation layer II covers the substrate and covers all packaging units; the packaging unit comprises a plastic encapsulation layer I, a memory chip and an intermediate layer chip, and at least one memory chip and at least one intermediate layer chip with a through silicon via are encapsulated in parallel in the plastic encapsulation layer I, and a rewiring layer and a connection bump are formed on the upper surface and the lower surface of the packaging unit respectively, and the memory chip and the intermediate layer chip are interconnected through the rewiring layer, and the packaging units are electrically connected through the connection bumps; A non-conductive adhesive film is filled between adjacent packaging units and between the bottom packaging unit and the substrate. The non-conductive adhesive film surrounds each connection bump and connects the packaging units and the packaging units and the substrate. The non-conductive adhesive film includes a first film layer and a second film layer. The first film layer is provided with a groove or a through hole at a position corresponding to each connection bump, and the second film layer is arranged in the groove or the through hole. Under the same conditions, the fluidity of the second film layer is greater than the fluidity of the first film layer.

2. The multi-chip stacking packaging structure according to claim 1, characterized in that: The substrate is arranged inverted, and the packaging units are sequentially arranged inverted on the substrate along the longitudinal direction.

3. The multi-chip stacking packaging structure according to claim 1, characterized in that: The memory chip and the interposer chip in the packaging unit are interconnected with the memory chip and the interposer chip in the adjacent packaging unit through the rewiring layer and the connection bumps respectively.

4. The multi-chip stacking packaging structure according to claim 1, characterized in that: The content of filler in the first film layer is higher than the content of filler in the second film layer.

5. The multi-chip stacking packaging structure according to claim 4, characterized in that: The first film layer includes 30-60 wt % of filler; the second film layer includes 10-30 wt % of filler.

6. The multi-chip stacking packaging structure according to claim 5, characterized in that: The first film layer comprises 30-60wt% filler, 5-15wt% curing agent, and 35-65wt% epoxy resin; The second film layer includes 10-30wt% filler, 10-20wt% active diluent, 5-15wt% plasticizer, 5-20wt% curing agent, and 35-70wt% epoxy resin.

7. The multi-chip stacking packaging structure according to claim 1, characterized in that: The groove is arranged on the lower surface of the first film layer, and the second film layer is arranged in the groove.

8. A method for manufacturing a multi-chip stacking packaging structure according to any one of claims 1 to 7, characterized in that: At least the following steps are included: (1) Prepare several packaging units: Feeding a carrier and coating a peeling layer, mounting the backs of the memory chip and the interposer chip side by side on the peeling layer, using a plastic encapsulation layer I to cover the memory chip and the interposer chip to form a package, grinding a pad on the front side of the package and making a front rewiring layer and connection bumps, then using a carrier coated with a peeling layer to temporarily glue the front side of the package, removing the carrier on the back side of the package, inverting and making a back rewiring layer and connection bumps on the back side of the package, removing the carrier on the front side and cutting, and obtaining the package unit; (2) Preparation of substrate: Feeding a wafer, making a front rewiring layer and lead-out solder balls on the front side of the wafer, temporarily gluing the front side of the wafer with a carrier coated with a peeling layer, grinding a solder pad on the back side of the wafer after inverting it, making a back rewiring layer and connection bumps on the back side of the wafer, and obtaining the substrate; (3) Stacking of several packaging units: A plurality of packaging units are adhered layer by layer to the upper surface of a substrate using a non-conductive adhesive film, and the substrate and the packaging units are bonded together through a thermal compression process, wherein the connection bumps between adjacent packaging units and the connection bumps between the substrate and the packaging units are aligned and bonded, and a plastic encapsulation layer II is used to cover all the packaging units on the substrate. After removing the carrier, cleaning, and cutting, the multi-chip stacked packaging structure is obtained.

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