Terminal structure of semiconductor power device and preparation method thereof

Abstract

The invention provides a terminal structure of a semiconductor power device and a preparation method thereof. The terminal structure of the semiconductor power device comprises a substrate layer; the epitaxial layer is located on the substrate layer and comprises an active region and a terminal region surrounding the active region; the field limiting rings are arranged in the terminal area of the epitaxial layer at intervals and are sequentially arranged in the direction from the active area to the terminal area; the junction terminal extension region is located in the terminal region and comprises a first junction terminal extension region to an Mth junction terminal extension region, and the first junction terminal extension region to the Mth junction terminal extension region are sequentially arranged in the direction from the active region to the terminal region and surround the side walls of the field limiting rings; any mth junction terminal extension region comprises an mth sub-junction terminal extension region, and the concentration of the first sub-junction terminal extension region to the Mth sub-junction terminal extension region decreases progressively along the direction from the active region to the terminal region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a terminal structure of a semiconductor power device and a preparation method thereof. Background Art

[0002] Wide bandgap semiconductor silicon carbide has a large bandgap width, high thermal conductivity, high breakdown field strength, high electron saturation velocity and strong radiation resistance, which makes silicon carbide power semiconductor devices applicable to high temperature, high voltage, high frequency and strong radiation working environment. Therefore, silicon carbide has become an ideal material for high temperature and high power semiconductor devices. Due to the limited size of semiconductor devices, in order to alleviate the problem of semiconductor device breakdown caused by electric field concentration at the edge of semiconductor devices, a junction terminal structure for protecting semiconductor devices is usually set at the edge of semiconductor devices. Common semiconductor terminal structures mainly include field plates, field limiting rings, junction terminal extensions (JTE), etc. These terminal structures have been widely used in various semiconductor devices. Summary of the invention

[0003] The present invention provides a terminal structure of a semiconductor power device, comprising: a substrate layer; an epitaxial layer located on the substrate layer, the epitaxial layer comprising an active area and a terminal area surrounding the active area; a plurality of field limiting rings arranged at intervals in the terminal area of ​​the epitaxial layer, the plurality of field limiting rings being arranged in sequence along the direction from the active area to the terminal area; a junction terminal extension area located in the terminal area, the junction terminal extension area comprising a first junction terminal extension area to an Mth junction terminal extension area, M being an integer greater than or equal to 3, the first junction terminal extension area to the Mth junction terminal extension area being arranged in sequence along the direction from the active area to the terminal area and all surrounding the side walls of the plurality of field limiting rings; any mth junction terminal extension area comprising an mth subjunction terminal extension area, the concentrations of the first subjunction terminal extension area to the Mth subjunction terminal extension area decreasing along the direction from the active area to the terminal area, m being an integer greater than or equal to 1 and less than or equal to M.

[0004] Optionally, any m-th junction terminal extension region only includes an m-th sub-junction terminal extension region, and any m-th sub-junction terminal extension region surrounds side walls of a plurality of field limiting rings.

[0005] Optionally, any j-th subjunction terminal extension region is in contact with the j+1-th subjunction terminal extension region, where j is an integer greater than or equal to 1 and less than or equal to M-1.

[0006] Optionally, there is a contact gap between any j-th subjunction terminal extension region and any j+1-th subjunction terminal extension region; there is one or more field limiting rings between any j-th subjunction terminal extension region and any j+1-th subjunction terminal extension region; j is an integer greater than or equal to 1 and less than or equal to M-1; the epitaxial layer between the adjacent m-th subjunction terminal extension region and the field limiting ring constitutes an m-th current cutoff region, and the conductivity type of the m-th current cutoff region is opposite to the conductivity type of the field limiting ring and the m-th subjunction terminal extension region.

[0007] Optionally, the bottom surface of any m-th subjunction terminal extension region facing the substrate layer is flush with the bottom surface of the field limiting ring facing the substrate layer; or, the bottom surface of any m-th subjunction terminal extension region facing the substrate layer is located between the bottom surface of the field limiting ring facing the substrate layer and the substrate layer.

[0008] Optionally, any mth junction terminal extension region includes an mth subjunction terminal extension region and an M+mth subjunction terminal extension region, and the M+mth subjunction terminal extension region is located on the side of the mth subjunction terminal extension region away from the substrate layer and in contact with the mth subjunction terminal extension region; wherein any M+mth subjunction terminal extension region surrounds the side walls of a plurality of the field limiting rings; and any mth subjunction terminal extension region is located between the field limiting ring and the substrate layer.

[0009] Optionally, any M+j-th sub-node terminal extension area is connected to the M+j+1-th sub-node terminal extension area; any j-th sub-node terminal extension area is spaced from the j+1-th sub-node terminal extension area; j is an integer greater than or equal to 1 and less than or equal to M-1.

[0010] Optionally, the bottom surface of any M+m-th sub-junction terminal extension region facing the substrate layer is located between the bottom surface of the field limiting ring facing the substrate layer and the substrate layer; or, the bottom surface of any M+m-th sub-junction terminal extension region facing the substrate layer is flush with the bottom surface of the field limiting ring facing the substrate layer.

[0011] Optionally, the doping concentrations from the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region are consistent.

[0012] Optionally, the doping concentrations of the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region are all less than the doping concentration of the Mth subjunction terminal extension region.

[0013] Optionally, M is equal to 3, and the junction terminal extension zone includes a first junction terminal extension zone, a second junction terminal extension zone and a third junction terminal extension zone; wherein the first junction terminal extension zone, the second junction terminal extension zone and the third junction terminal extension zone are arranged in sequence along the direction from the active zone to the terminal zone and are all surrounded by side walls of multiple field limiting rings; the first junction terminal extension zone includes a first sub-junction terminal extension zone, the second junction terminal extension zone includes a second sub-junction terminal extension zone, and the third junction terminal extension zone includes a third sub-junction terminal extension zone, and the concentrations of the first sub-junction terminal extension zone, the second sub-junction terminal extension zone and the third sub-junction terminal extension zone decrease along the direction from the active zone to the terminal zone.

[0014] Optionally, it also includes: a main junction located in the terminal area and spaced apart from the field limiting ring, the main junction being surrounded by the field limiting ring and the junction terminal extension area; the conductivity type of the main junction is the same as the conductivity type of the field limiting ring.

[0015] The present application also provides a method for preparing a terminal structure of a semiconductor power device, comprising: forming an epitaxial layer on a substrate layer, the epitaxial layer comprising an active area and a terminal area surrounding the active area; forming a plurality of field limiting rings arranged at intervals in the terminal area of ​​the epitaxial layer, the plurality of field limiting rings being arranged in sequence along the direction from the active area to the terminal area; forming a junction terminal extension area in the terminal area, the formation of the junction terminal extension area comprising forming a first junction terminal extension area to an Mth junction terminal extension area, M being an integer greater than or equal to 3, the first junction terminal extension area to the Mth junction terminal extension area being arranged in sequence along the direction from the active area to the terminal area and all surrounding the side walls of the plurality of field limiting rings; any mth junction terminal extension area comprises an mth subjunction terminal extension area, the concentrations of the first subjunction terminal extension area to the Mth subjunction terminal extension area decrease along the direction from the active area to the terminal area, m being an integer greater than or equal to 1 and less than or equal to M.

[0016] Optionally, forming an arbitrary m-th junction terminal extension region only includes forming an m-th sub-junction terminal extension region, and the arbitrary m-th sub-junction terminal extension region surrounds side walls of a plurality of field limiting rings.

[0017] Optionally, forming an arbitrary mth junction terminal extension region includes forming an mth subjunction terminal extension region and forming an M+m subjunction terminal extension region, and the M+m subjunction terminal extension region is located on the side of the mth subjunction terminal extension region away from the substrate layer and in contact with the mth subjunction terminal extension region; wherein, any M+m subjunction terminal extension region surrounds the side walls of a plurality of the field limiting rings; and any mth subjunction terminal extension region is located between the field limiting ring and the substrate layer.

[0018] The technical solution of the present invention has the following technical effects:

[0019] The terminal structure of the semiconductor power device provided by the technical solution of the present invention has a more uniform distribution of the total electric field along the direction from the active area to the terminal area because the concentration from the first sub-junction terminal extension area to the Mth sub-junction terminal extension area decreases along the direction from the active area to the terminal area. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of a terminal structure of a semiconductor power device in an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of a terminal structure of a semiconductor power device in another embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a terminal structure of a semiconductor power device in another embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a terminal structure of a semiconductor power device in another embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a terminal structure of a semiconductor power device in another embodiment of the present application;

[0026] Figure 6 It is a schematic diagram of a terminal structure of a semiconductor power device in yet another embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0031] An embodiment of the present invention provides a terminal structure of a semiconductor power device, referring to Figures 1 to 6 ,include:

[0032] Substrate layer 101;

[0033] An epitaxial layer 102 located on the substrate layer 101, wherein the epitaxial layer 102 includes an active region and a terminal region surrounding the active region;

[0034] A plurality of spaced field limiting rings 170 located in the terminal region of the epitaxial layer 102, wherein the plurality of field limiting rings 170 are sequentially arranged along a direction from the active region to the terminal region;

[0035] A junction terminal extension zone located in the terminal zone, the junction terminal extension zone includes a first junction terminal extension zone to an Mth junction terminal extension zone, M is an integer greater than or equal to 3, the first junction terminal extension zone to the Mth junction terminal extension zone are arranged in sequence along the direction from the active zone to the terminal zone and all surround the side walls of multiple field limiting rings 170; any mth junction terminal extension zone includes an mth sub-junction terminal extension zone, the concentrations of the first sub-junction terminal extension zone to the Mth sub-junction terminal extension zone decrease along the direction from the active zone to the terminal zone, m is an integer greater than or equal to 1 and less than or equal to M.

[0036] In this embodiment, since the concentration from the first subjunction terminal extension region to the Mth subjunction terminal extension region decreases along the direction from the active region to the terminal region, the distribution of the total electric field along the direction from the active region to the terminal region is more uniform.

[0037] In one embodiment, taking M equal to 3 as an example, the junction terminal extension region includes a first junction terminal extension region, a second junction terminal extension region and a third junction terminal extension region; wherein the first junction terminal extension region, the second junction terminal extension region and the third junction terminal extension region are arranged in sequence along the direction from the active region to the terminal region and all surround the sidewalls of multiple field limiting rings; the first junction terminal extension region includes a first sub-junction terminal extension region 160a, the second junction terminal extension region includes a second sub-junction terminal extension region 160b, and the third junction terminal extension region includes a third sub-junction terminal extension region 160c, and the concentrations of the first sub-junction terminal extension region 160a, the second sub-junction terminal extension region 160b and the third sub-junction terminal extension region 160c decrease along the direction from the active region to the terminal region. The doping concentration of the second sub-junction terminal extension region 160b is less than the doping concentration of the first sub-junction terminal extension region 160a, and the doping concentration of the third sub-junction terminal extension region 160c is less than the doping concentration of the second sub-junction terminal extension region 160b.

[0038] In one embodiment, the doping concentration of the first subjunction terminal extension region 160a is 8E16atom / cm 3 ~1E17atom / cm 3 The doping concentration of the second subjunction terminal extension region 160b is 5E16atom / cm 3 ~7E16atom / cm 3 The doping concentration of the third subjunction terminal extension region 160c is 1E16atom / cm 3 ~3E16atom / cm 3 .

[0039] It should be noted that, in other embodiments, M may be an integer greater than 3.

[0040] In one embodiment, reference Figures 1 to 4 , any m-th junction terminal extension region only includes the m-th sub-junction terminal extension region, and any m-th sub-junction terminal extension region surrounds the sidewalls of multiple field limiting rings 170. The first junction terminal extension region only includes the first sub-junction terminal extension region 160a, the second junction terminal extension region only includes the second sub-junction terminal extension region 160b, and the third junction terminal extension region only includes the third sub-junction terminal extension region 160c.

[0041] In one embodiment, reference Figure 1 to Figure 2, any j-th sub-junction terminal extension region contacts the j+1-th sub-junction terminal extension region, j is an integer greater than or equal to 1 and less than or equal to M-1. When M is equal to 3, the first sub-junction terminal extension region 160a contacts the second sub-junction terminal extension region 160b, and the second sub-junction terminal extension region 160b contacts the third sub-junction terminal extension region 160c.

[0042] In one embodiment, reference Figure 3 to Figure 4 , any j-th subjunction terminal extension region and the j+1-th subjunction terminal extension region are spaced; any j-th subjunction terminal extension region and the j+1-th subjunction terminal extension region have one or more field limiting rings between them; j is an integer greater than or equal to 1 and less than or equal to M-1. The epitaxial layer between the adjacent m-th subjunction terminal extension region and the field limiting ring constitutes the m-th current cut-off region, and the conductivity type of the m-th current cut-off region is opposite to the conductivity type of the field limiting ring and the m-th subjunction terminal extension region. When M is equal to 3, the first subjunction terminal extension region 160a and the second subjunction terminal extension region 160b are spaced, and the second subjunction terminal extension region 160b and the third subjunction terminal extension region 160c are spaced. There are one or more field limiting rings 170 between the first subjunction terminal extension region 160a and the second subjunction terminal extension region 160b. There are one or more field limiting rings 170 between the second subjunction terminal extension region 160b and the third subjunction terminal extension region 160c. The epitaxial layer between the adjacent first subjunction terminal extension region 160a and the field limiting ring 170 constitutes a first current cutoff region, and the conductivity type of the first current cutoff region is opposite to the conductivity type of the field limiting ring and the first subjunction terminal extension region. The epitaxial layer between the adjacent second subjunction terminal extension region 160b and the field limiting ring 170 constitutes a second current cutoff region, and the conductivity type of the second current cutoff region is opposite to the conductivity type of the field limiting ring and the second subjunction terminal extension region. The epitaxial layer between the adjacent third subjunction terminal extension region 160c and the field limiting ring 170 constitutes a third current cutoff region, and the conductivity type of the third current cutoff region is opposite to the conductivity type of the field limiting ring and the third subjunction terminal extension region.

[0043] Since the first current cut-off region to the Mth current cut-off region are provided, the conductivity type of any mth current cut-off region is opposite to the conductivity type of the field limiting ring 170 and the junction terminal extension region, the mth current cut-off region and the mth sub-junction terminal extension region on one side of the mth current cut-off region form a PN junction, and the mth current cut-off region and the field limiting ring 170 on the other side of the mth current cut-off region form a PN junction, which can block the lateral movement of charges and impurity ions. On the one hand, the electric field peak is prevented from drifting, and the stability of the terminal region of the terminal structure of the semiconductor power device can be improved. On the other hand, the voltage difference between the surface of the terminal region close to the active region and the surface of the side away from the active region can be prevented from being too high, the terminal structure of the semiconductor power device is prevented from leaking, and the reliability of the terminal structure of the semiconductor power device is improved. Therefore, the reliability and stability of the terminal structure of the semiconductor power device are high.

[0044] In one embodiment, reference Figure 1 and Figure 3 , any m-th subjunction terminal extension area is flush with the bottom surface of the field limiting ring 170 facing the substrate layer 101. When M is equal to 3, the bottom surface of the first subjunction terminal extension area 160a facing the substrate layer 101 is flush with the bottom surface of the field limiting ring 170 facing the substrate layer 101, the bottom surface of the second subjunction terminal extension area 160b facing the substrate layer 101 is flush with the bottom surface of the field limiting ring 170 facing the substrate layer 101, and the bottom surface of the third subjunction terminal extension area 160c facing the substrate layer 101 is flush with the bottom surface of the field limiting ring 170 facing the substrate layer 101. The advantage is that any m-th subjunction terminal extension area and the field limiting ring 170 are depleted simultaneously with the epitaxial layer 102, reducing the electric field strength of the terminal area while increasing the process preparation window of the junction terminal extension area.

[0045] In one embodiment, reference Figure 2 and Figure 4, the bottom surface of any m-th subjunction terminal extension region facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101. When M is equal to 3, the bottom surface of the first subjunction terminal extension region 160a facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101, the bottom surface of the second subjunction terminal extension region 160b facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101, and the bottom surface of the third subjunction terminal extension region 160c facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101. The advantages are: the field limiting ring 170 and the mth subjunction terminal extension region surrounding the field limiting ring 170 are depleted, the mth subjunction terminal extension region and the epitaxial layer at the bottom of the mth subjunction terminal extension region are depleted, and the electric field is further transferred into the body of the epitaxial layer, thereby reducing the electric field, limiting the movement of ions on the surface of the epitaxial layer, and improving the reliability of the terminal structure of the semiconductor power device.

[0046] In one embodiment, the bottom surface of any m-th subjunction terminal extension region is 0.3 microns to 2 microns deeper than the bottom surface of the field limiting ring 170, for example, 0.3 microns, 0.5 microns, 0.8 microns, 1 micron, 1.5 microns or 2 microns. The electric field peak is transferred to the body of the epitaxial layer, reducing the surface electric field of the epitaxial layer. The bottom surface of the m-th subjunction terminal extension region is the surface of the m-th subjunction terminal extension region facing the substrate layer, and the bottom surface of the field limiting ring 170 is the surface of the field limiting ring 170 facing the substrate layer.

[0047] In one embodiment, reference Figure 5 and Figure 6 , any m-th junction terminal extension region includes an m-th sub-junction terminal extension region and an M+m-th sub-junction terminal extension region, the M+m-th sub-junction terminal extension region is located on the side of the m-th sub-junction terminal extension region away from the substrate layer 101 and is in contact with the m-th sub-junction terminal extension region; wherein any M+m-th sub-junction terminal extension region surrounds the side walls of a plurality of the field limiting rings 170; and any m-th sub-junction terminal extension region is located between the field limiting ring 170 and the substrate layer 101.

[0048] refer to Figure 5 and Figure 6When M is equal to 3, the first junction terminal extension region includes a first sub-junction terminal extension region 160a and a fourth sub-junction terminal extension region 160d, the fourth sub-junction terminal extension region 160d is located on the side of the first sub-junction terminal extension region 160a away from the substrate layer 101 and is in contact with the first sub-junction terminal extension region 160a, the fourth sub-junction terminal extension region 160d surrounds the side walls of the plurality of field limiting rings 170, and the first sub-junction terminal extension region 160a is located between the field limiting ring 170 and the substrate layer 101. The second junction terminal extension region includes a second sub-junction terminal extension region 160b and a fifth sub-junction terminal extension region 160e. The fifth sub-junction terminal extension region 160e is located on a side of the second sub-junction terminal extension region 160b away from the substrate layer 101 and in contact with the second sub-junction terminal extension region 160b. The fifth sub-junction terminal extension region 160e surrounds the side walls of the plurality of field limiting rings 170. The second sub-junction terminal extension region 160b is located between the field limiting rings 170 and the substrate layer 101. The third junction terminal extension region includes a third sub-junction terminal extension region 160c and a sixth sub-junction terminal extension region 160f. The sixth sub-junction terminal extension region 160f is located on a side of the third sub-junction terminal extension region 160c away from the substrate layer 101 and in contact with the third sub-junction terminal extension region 160c. The sixth sub-junction terminal extension region 160f surrounds the side walls of the plurality of field limiting rings 170. The third sub-junction terminal extension region 160c is located between the field limiting rings 170 and the substrate layer 101.

[0049] refer to Figure 5 and Figure 6 , any M+j-th sub-node terminal extension area is connected to the M+j+1-th sub-node terminal extension area; any j-th sub-node terminal extension area is spaced from the j+1-th sub-node terminal extension area; j is an integer greater than or equal to 1 and less than or equal to M-1. When M is equal to 3, the fourth sub-node terminal extension area 160d is connected to the fifth sub-node terminal extension area 160e, and the fifth sub-node terminal extension area 160e is connected to the sixth sub-node terminal extension area 160f. The first sub-node terminal extension area 160a is spaced from the second sub-node terminal extension area 160b, and the second sub-node terminal extension area 160b is spaced from the third sub-node terminal extension area 160c.

[0050] It should be noted that, in other embodiments, any M+j-th sub-junction terminal extension region and the M+j+1-th sub-junction terminal extension region are spaced.

[0051] It should be noted that, in other embodiments, any j-th sub-junction terminal extension region is connected to the j+1-th sub-junction terminal extension region.

[0052] refer to Figure 5, any M+mth subjunction terminal extension region is flush with the bottom surface of the substrate layer 101 and the bottom surface of the field limiting ring 170 facing the substrate layer 101. When M is equal to 3, the fourth subjunction terminal extension region 160d is flush with the bottom surface of the substrate layer 101 and the bottom surface of the field limiting ring 170 facing the substrate layer 101, the fifth subjunction terminal extension region 160e is flush with the bottom surface of the substrate layer 101 and the bottom surface of the field limiting ring 170 facing the substrate layer 101, and the sixth subjunction terminal extension region 160f is flush with the bottom surface of the substrate layer 101 and the bottom surface of the field limiting ring 170 facing the substrate layer 101.

[0053] refer to Figure 6 , the bottom surface of any M+m-th subjunction terminal extension region facing the substrate layer is located between the bottom surface of the field limiting ring facing the substrate layer and the substrate layer. When M is equal to 3, the bottom surface of the fourth subjunction terminal extension region 160d facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101, the bottom surface of the fifth subjunction terminal extension region 160e facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101, and the bottom surface of the sixth subjunction terminal extension region 160f facing the substrate layer 101 is located between the bottom surface of the field limiting ring 170 facing the substrate layer 101 and the substrate layer 101.

[0054] refer to Figure 5 and Figure 6 , the doping concentration from the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region is consistent.

[0055] It should be noted that, in other embodiments, the doping concentrations from the M+1th sub-junction terminal extension region to the 2Mth sub-junction terminal extension region may be at least partially inconsistent.

[0056] In one embodiment, the doping concentrations from the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region are all less than the doping concentration of the Mth subjunction terminal extension region. The doping concentrations from the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region are relatively small, thereby reducing the surface electric field of the epitaxial layer.

[0057] In one embodiment, a plurality of spaced field limiting rings 170 are arranged at equal intervals along the direction from the active region to the terminal region. In another embodiment, the intervals between different adjacent field limiting rings 170 along the direction from the active region to the terminal region are at least partially different, for example, the intervals between adjacent field limiting rings 170 along the direction from the active region to the terminal region decrease or increase.

[0058] In one embodiment, the terminal structure of the semiconductor power device further includes: a main junction 103 located in the terminal region and spaced apart from the field limiting ring, the main junction 103 being surrounded by the field limiting ring 170 and the junction terminal extension region; the conductivity type of the main junction 103 is the same as the conductivity type of the field limiting ring 170.

[0059] In one embodiment, the terminal structure of the semiconductor power device also includes: a drain electrode layer 100, located on the side of the substrate layer 101 away from the epitaxial layer 102; a source electrode layer 104, located on the side of the main junction 103 away from the epitaxial layer 102; a field oxide layer 105, wherein the field oxide layer 105 is located on the surface of the epitaxial layer 102 away from the substrate layer 101 and covers the field limiting ring 170 and the junction terminal extension area.

[0060] Another embodiment of the present application also provides a method for preparing a terminal structure of a semiconductor power device, comprising: forming an epitaxial layer on a substrate layer, the epitaxial layer comprising an active area and a terminal area surrounding the active area; forming a plurality of spaced field limiting rings in the terminal area of ​​the epitaxial layer, the plurality of field limiting rings being arranged in sequence along the direction from the active area to the terminal area; forming a junction terminal extension area in the terminal area, the formation of the junction terminal extension area comprising forming a first junction terminal extension area to an Mth junction terminal extension area, M being an integer greater than or equal to 3, the first junction terminal extension area to the Mth junction terminal extension area being arranged in sequence along the direction from the active area to the terminal area and all surrounding the side walls of the plurality of field limiting rings; any mth junction terminal extension area comprises an mth subjunction terminal extension area, the concentrations of the first subjunction terminal extension area to the Mth subjunction terminal extension area decrease along the direction from the active area to the terminal area, m being an integer greater than or equal to 1 and less than or equal to M.

[0061] In one embodiment, a plurality of spaced field limiting rings 170 are arranged at equal intervals along the direction from the active region to the terminal region. In another embodiment, the intervals between different adjacent field limiting rings 170 along the direction from the active region to the terminal region are at least partially different, for example, the intervals between adjacent field limiting rings 170 along the direction from the active region to the terminal region decrease or increase.

[0062] In one embodiment, forming any m-th junction terminal extension region only includes forming an m-th sub-junction terminal extension region, and any m-th sub-junction terminal extension region surrounds the sidewalls of multiple field limiting rings. The description of the first sub-junction terminal extension region to the M-th sub-junction terminal extension region refers to the description of the above embodiment and will not be described in detail.

[0063] In one embodiment, forming any m-th junction terminal extension region includes forming an m-th sub-junction terminal extension region and forming an M+m-th sub-junction terminal extension region, wherein the M+m-th sub-junction terminal extension region is located on the side of the m-th sub-junction terminal extension region away from the substrate layer and in contact with the m-th sub-junction terminal extension region; wherein any M+m-th sub-junction terminal extension region surrounds the side walls of a plurality of field limiting rings; and any m-th sub-junction terminal extension region is located between the field limiting rings and the substrate layer. The description of the first sub-junction terminal extension region to the M-th sub-junction terminal extension region and the M+1-th sub-junction terminal extension region to the 2M-th sub-junction terminal extension region refers to the description of the aforementioned embodiment and will not be described in detail.

[0064] In one embodiment, the field limiting ring is formed after the junction termination extension region is formed. In another embodiment, the field limiting ring is formed after the junction termination extension region is formed.

[0065] The process of forming the field limiting ring includes an ion implantation process. The process of forming the junction terminal extension region includes an ion implantation process.

[0066] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A terminal structure of a semiconductor power device, characterized in that: include: substrate layer; An epitaxial layer located on the substrate layer, the epitaxial layer comprising an active region and a terminal region surrounding the active region; A plurality of spaced field limiting rings located in a terminal region of the epitaxial layer, wherein the plurality of field limiting rings are sequentially arranged along a direction from the active region to the terminal region; A junction terminal extension zone located in the terminal zone, the junction terminal extension zone includes a first junction terminal extension zone to an Mth junction terminal extension zone, M is an integer greater than or equal to 3, the first junction terminal extension zone to the Mth junction terminal extension zone are arranged in sequence along the direction from the active zone to the terminal zone and are surrounded by side walls of multiple field limiting rings; any mth junction terminal extension zone includes an mth sub-junction terminal extension zone, the concentrations of the first sub-junction terminal extension zone to the Mth sub-junction terminal extension zone decrease along the direction from the active zone to the terminal zone, m is an integer greater than or equal to 1 and less than or equal to M.

2. The terminal structure of the semiconductor power device according to claim 1, characterized in that: Any m-th junction termination extension region only includes an m-th sub-junction termination extension region, and any m-th sub-junction termination extension region surrounds side walls of a plurality of field limiting rings.

3. The terminal structure of the semiconductor power device according to claim 2, characterized in that: Any j-th sub-junction terminal extension region is in contact with the j+1-th sub-junction terminal extension region, where j is an integer greater than or equal to 1 and less than or equal to M-1.

4. The terminal structure of the semiconductor power device according to claim 2, characterized in that: Any j-th sub-junction terminal extension region and any j+1-th sub-junction terminal extension region have a contact interval; any j-th sub-junction terminal extension region and any j+1-th sub-junction terminal extension region have one or more field limiting rings between them; j is an integer greater than or equal to 1 and less than or equal to M-1; The epitaxial layer between the adjacent mth subjunction terminal extension region and the field limiting ring constitutes an mth current cutoff region, and the conductivity type of the mth current cutoff region is opposite to the conductivity type of the field limiting ring and the mth subjunction terminal extension region.

5. The terminal structure of the semiconductor power device according to claim 2, characterized in that: The bottom surface of any m-th subjunction terminal extension region facing the substrate layer is flush with the bottom surface of the field limiting ring facing the substrate layer; Alternatively, the bottom surface of any m-th subjunction terminal extension region facing the substrate layer is located between the bottom surface of the field limiting ring facing the substrate layer and the substrate layer.

6. The terminal structure of the semiconductor power device according to claim 1, characterized in that: Any m-th junction terminal extension region includes an m-th sub-junction terminal extension region and an M+m-th sub-junction terminal extension region, wherein the M+m-th sub-junction terminal extension region is located at a side of the m-th sub-junction terminal extension region away from the substrate layer and in contact with the m-th sub-junction terminal extension region; Wherein, any M+mth sub-junction terminal extension region surrounds the side walls of a plurality of the field limiting rings; and any mth sub-junction terminal extension region is located between the field limiting ring and the substrate layer.

7. The terminal structure of the semiconductor power device according to claim 6, characterized in that: Any M+j-th sub-node terminal extension area is connected to the M+j+1-th sub-node terminal extension area; any j-th sub-node terminal extension area is spaced from the j+1-th sub-node terminal extension area; j is an integer greater than or equal to 1 and less than or equal to M-1.

8. The terminal structure of the semiconductor power device according to claim 6, characterized in that: The bottom surface of any M+mth subjunction terminal extension region facing the substrate layer is located between the bottom surface of the field limiting ring facing the substrate layer and the substrate layer; or, the bottom surface of any M+mth subjunction terminal extension region facing the substrate layer is flush with the bottom surface of the field limiting ring facing the substrate layer.

9. The terminal structure of the semiconductor power device according to claim 6, characterized in that: The doping concentrations from the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region are consistent.

10. The terminal structure of the semiconductor power device according to claim 1, characterized in that: The doping concentrations from the M+1th subjunction terminal extension region to the 2Mth subjunction terminal extension region are all less than the doping concentration of the Mth subjunction terminal extension region.

11. The terminal structure of a semiconductor power device according to claim 1, characterized in that: M is equal to 3, and the junction terminal extension region includes a first junction terminal extension region, a second junction terminal extension region and a third junction terminal extension region; wherein the first junction terminal extension region, the second junction terminal extension region and the third junction terminal extension region are arranged in sequence along the direction from the active region to the terminal region and all surround the side walls of multiple field limiting rings; the first junction terminal extension region includes a first sub-junction terminal extension region, the second junction terminal extension region includes a second sub-junction terminal extension region, and the third junction terminal extension region includes a third sub-junction terminal extension region, and the concentrations of the first sub-junction terminal extension region, the second sub-junction terminal extension region and the third sub-junction terminal extension region decrease along the direction from the active region to the terminal region.

12. The terminal structure of the semiconductor power device according to claim 1, characterized in that: It also includes: a main junction located in the terminal area and spaced apart from the field limiting ring, the main junction being surrounded by the field limiting ring and the junction terminal extension area; and the conductivity type of the main junction is the same as that of the field limiting ring.

13. A method for preparing a terminal structure of a semiconductor power device, characterized in that: include: forming an epitaxial layer on the substrate layer, wherein the epitaxial layer comprises an active region and a terminal region surrounding the active region; forming a plurality of spaced field limiting rings in a terminal region of the epitaxial layer, wherein the plurality of field limiting rings are sequentially arranged along a direction from the active region to the terminal region; A junction terminal extension zone is formed in the terminal zone, and the formation of the junction terminal extension zone includes forming a first junction terminal extension zone to an Mth junction terminal extension zone, where M is an integer greater than or equal to 3, and the first junction terminal extension zone to the Mth junction terminal extension zone are arranged in sequence along the direction from the active zone to the terminal zone and are all surrounded by side walls of multiple field limiting rings; any mth junction terminal extension zone includes an mth sub-junction terminal extension zone, and the concentrations of the first sub-junction terminal extension zone to the Mth sub-junction terminal extension zone decrease along the direction from the active zone to the terminal zone, and m is an integer greater than or equal to 1 and less than or equal to M.

14. The method for preparing a terminal structure of a semiconductor power device according to claim 13, characterized in that: Forming an arbitrary m-th junction termination extension region only includes forming an m-th sub-junction termination extension region, and the arbitrary m-th sub-junction termination extension region surrounds the side walls of the plurality of field limiting rings.

15. The method for preparing a terminal structure of a semiconductor power device according to claim 13, characterized in that: Forming any m-th junction terminal extension region includes forming an m-th sub-junction terminal extension region and forming an M+m-th sub-junction terminal extension region, wherein the M+m-th sub-junction terminal extension region is located on a side of the m-th sub-junction terminal extension region away from the substrate layer and in contact with the m-th sub-junction terminal extension region; Wherein, any M+mth sub-junction terminal extension region surrounds the side walls of a plurality of the field limiting rings; and any mth sub-junction terminal extension region is located between the field limiting ring and the substrate layer.

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