Monolithic integrated half-bridge GaN HEMT (High Electron Mobility Transistor) device with substrate coupling crosstalk suppression effect

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a monolithic integrated half-bridge GaN HEMT (High Electron Mobility Transistor) device with a substrate coupling crosstalk suppression effect. According to the structure, the Sub transistor which is connected with the half-bridge lower tube in parallel and has the same on-off state as the lower tube is added, charge accumulated in the substrate is released in the opening process of the Sub transistor, the potential of the substrate is adjusted through on-off of the Sub transistor, charge accumulation of the substrate in the long-time working state is avoided, and the service life of the substrate is prolonged. Dynamic self-adaptive adjustment of a substrate bias state is realized, the problem of substrate coupling crosstalk caused by monolithic integration is reduced, the stability of a half-bridge structure in a power supply conversion system is improved, the energy conversion efficiency of a power supply system is improved, in addition, additional mask plates and process steps do not need to be added in a device manufacturing process, and the manufacturing cost is reduced. The structure is compatible with a conventional process, and integration of devices is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular refers to a monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression function. Background Art

[0002] GaN has a high critical breakdown electric field and high electron saturation drift velocity, and the two-dimensional electron gas (2DEG) generated by the polarization effect between the AlGaN / GaN heterostructure has high mobility and electron density, which makes GaN high electron mobility transistors (HEMT) unique in high-frequency, high-efficiency, and high-power density applications. With the development of electric vehicles and smart grids, the demand for high-efficiency and high-density power conversion equipment is increasing, and the GaN half-bridge structure has been widely used in power conversion, DC motor drive and other fields. Monolithic integration of the two transistors of the half-bridge structure can reduce the area of ​​the overall circuit and obtain higher power density, thereby realizing the miniaturization and integration of the power system.

[0003] However, the monolithic integration of the half-bridge structure introduces the related problems of substrate coupling crosstalk: ① When the substrate is connected to the source of the upper tube, when the upper tube is turned on, the substrate potential will reach a value close to the bus voltage. At this time, it is equivalent to applying a forward bias voltage close to the bus voltage to the substrate, which makes the lower tube have a significant substrate bias effect. The acceptor traps in the channel of the lower tube will be captured by the buffer layer. When the upper tube is turned off, the substrate potential decreases, which is equivalent to removing the forward bias voltage of the substrate. At this time, the captured acceptor traps cannot be released in time, thereby reducing the conduction ability of the lower tube; ② When the substrate is connected to the source of the lower tube, the substrate The bottom potential is always kept near 0V. When the upper tube is turned on, the relatively high voltage maintained by the upper tube as a whole is equivalent to applying a reverse bias voltage to the substrate, which causes the upper tube to have a liner bias effect, and forms a current generated by the vertical electric field between the upper tube and the substrate, thereby reducing the current capacity of the upper tube; ③ When the substrate is in a floating state, the substrate will have different potential differences with the source and drain of the upper and lower tubes at the same time. These potential differences will induce a certain amount of negative charge in the substrate. These negative charges cannot be released and will gradually accumulate in the substrate, thereby causing the dynamic on-resistance of the upper and lower tubes to increase. Therefore, it is of great significance to improve the device structure to reduce the substrate coupling crosstalk problem caused by the monolithic integration of GaN half-bridges, thereby improving the energy conversion efficiency of the power supply system. Summary of the invention

[0004] In view of the above problems, the present invention belongs to the field of power semiconductor technology and relates to a monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression. The structure realizes dynamic adaptive adjustment of the substrate bias state by adding a Sub transistor in parallel with the lower tube of the half-bridge and having the same switching state as the lower tube, reduces the substrate coupling crosstalk problem caused by monolithic integration, improves the stability of the half-bridge structure in the power conversion system, and improves the energy conversion efficiency of the power system.

[0005] The technical solution of the present invention is:

[0006] A monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression function comprises a substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4 and a barrier layer 5 which are sequentially stacked from bottom to top along the vertical direction of the device;

[0007] It is characterized in that the two ends of the upper layer of the barrier layer 5 are respectively provided with a first conductive material 14 and a fourth conductive material 9, wherein the first conductive material 14 is arranged at one end of the upper layer of the barrier layer 5 along the longitudinal direction of the device, and the other end of the upper layer of the barrier layer 5 along the longitudinal direction of the device is provided with a second conductive material 11, and there is a gap between the first conductive material 14 and the second conductive material 11; the middle part of the first conductive material 14 is convex downward and the convex part extends to the upper layer of the substrate layer 1 in the vertical direction; a first isolation region 15 is provided in the barrier layer 5 between the first conductive material 14 and the second conductive material 11, and the first isolation region 15 extends to the upper layer of the GaN buffer layer 3 in the vertical direction;

[0008] A passivation layer 6 is provided on the upper surface of the barrier layer 5 between the first conductive material 14, the second conductive material 11 and the fourth conductive material 9;

[0009] A third conductive material 10 is provided in the middle of the barrier layer 5 between the first conductive material 14, the second conductive material 11 and the fourth conductive material 9, and both ends of the third conductive material 10 extend downward through the passivation layer 6 and then are embedded in the upper layer of the barrier layer 5, and a second isolation region 16 is provided between the portions extending downward at both ends of the third conductive material 10, the upper end of the second isolation region 16 contacts the passivation layer 6, and the lower end of the second isolation region 16 extends downward along the vertical direction of the device to the upper layer of the GaN buffer layer 3;

[0010] A first gate structure is provided on the upper surface of the passivation layer 6 between the first conductive material 14, the second conductive material 11 and the third conductive material 10. The first gate structure is close to the first conductive material 14 and the second conductive material 11 and has a gap between the first conductive material 14 and the second conductive material 11. The first gate structure includes a first P-type GaN layer 7 and a fifth conductive material 13. The bottom of the first P-type GaN layer 7 contacts the upper surface of the barrier layer 5. The bottom of the fifth conductive material 13 contacts the upper surface of the first P-type GaN layer 7. The passivation layer 6 wraps the side surface of the first P-type GaN layer 7 and the surface not covered by the fifth conductive material 13.

[0011] A second gate structure is provided on the upper surface of the passivation layer 6 between the third conductive material 10 and the fourth conductive material 9, the second gate structure is close to the third conductive material 10 and has a gap with the third conductive material 10; the second gate structure includes a second P-type GaN layer 8 and a sixth conductive material 12, the bottom of the second P-type GaN layer 8 contacts the upper surface of the barrier layer 5, the bottom of the sixth conductive material 12 contacts the upper surface of the second P-type GaN layer 8, and the passivation layer 6 wraps the side surface of the second P-type GaN layer 8 and the surface not covered by the sixth conductive material 12;

[0012] The contact between the first conductive material 14 and the barrier layer 5 is an ohmic contact, and the lead-out end is the substrate electrode; the contact between the third conductive material 10 and the barrier layer 5 is an ohmic contact, and the lead-out end is the switch electrode; the contact between the fourth conductive material 9 and the barrier layer 5 is an ohmic contact, and the lead-out end is the drain electrode; the contact between the second conductive material 11 and the barrier layer 5 is an ohmic contact, and the lead-out end is the source electrode; the lead-out ends of the fifth conductive material 13 and the sixth conductive material 12 are gate electrodes.

[0013] The longitudinal direction refers to a third dimension direction that is perpendicular to both the vertical direction and the lateral direction of the device.

[0014] Furthermore, a seventh conductive material 20, an eighth conductive material 17 and a ninth conductive material 21 are sequentially distributed on a side of the first gate structure away from the second gate structure in the lateral direction, and the contacts with the barrier layer 5 are all ohmic contacts, and the lead ends are the source electrode, the drain electrode of the Sub transistor and the substrate electrode in sequence, wherein the eighth conductive material 17 is electrically connected to the third conductive material 10; a third isolation region 22 is provided between the seventh conductive material 20 and the eighth conductive material 17, the upper end of the third isolation region 22 is in contact with the passivation layer 6, and the lower end of the third isolation region 22 extends to the GaN buffer layer 3 along the vertical direction of the device; the structure of the ninth conductive material (21) is the same as that of the first conductive material (14), except that the ninth conductive material (21) runs through the device along the longitudinal direction of the device;

[0015] There is also a third gate structure between the eighth conductive material 17 and the ninth conductive material 21. The third gate structure is close to the ninth conductive material 21 and has a spacing. The third gate structure is the same as the first gate structure, including a third P-type GaN layer 19 and a tenth conductive material 18. The bottom of the third P-type GaN layer 19 contacts the upper surface of the barrier layer 5, and the bottom of the tenth conductive material 18 contacts the upper surface of the third P-type GaN layer 19. The passivation layer 6 wraps the side surfaces of the third P-type GaN layer 19 and the surface not covered by the tenth conductive material 18. The tenth conductive material 18 is electrically connected to the fifth conductive material 13.

[0016] Furthermore, the first isolation region 15 , the second isolation region 16 and the third isolation region 22 are one of ion implantation isolation, trench isolation and P-type GaN isolation.

[0017] Furthermore, the barrier layer 5 is made of one or a combination of AlN, AlGaN, InGaN, and InAlN; the GaN channel layer 4 and the barrier layer 5 form a heterojunction, and 2DEG is generated at the heterojunction interface.

[0018] The beneficial effects of the present invention are:

[0019] The Sub transistor shares the same gate with the lower tube of the half-bridge structure and has the same switching state as the lower tube. During the process of turning on the Sub transistor, the charge accumulated in the substrate is released, and the substrate potential is regulated by switching the Sub transistor, thereby avoiding the accumulation of substrate charge under long-term working conditions, reducing the substrate coupling crosstalk problem caused by monolithic integration, improving the stability of the half-bridge structure in the power conversion system, and improving the energy conversion efficiency of the power system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic structural diagram of Example 1;

[0021] Figure 2 is a top view of Example 1;

[0022] Figure 3 is a cross-sectional view of Example 1 along AA';

[0023] Figure 4 is a cross-sectional view of Example 1 along BB';

[0024] Figure 5 is a cross-sectional view of Example 1 along CC';

[0025] Figure 6 is a schematic structural diagram of Example 2;

[0026] Figure 7It is a structural schematic diagram of Example 3. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0028] Example 1

[0029] like Figure 1 As shown, a monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression effect includes a substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4 and a barrier layer 5 which are stacked in sequence from bottom to top along the vertical direction of the device;

[0030] The barrier layer 5 is made of AlGaN, and the GaN channel layer 4 and the barrier layer 5 form a heterojunction, and a 2DEG is generated at the heterojunction interface;

[0031] The barrier layer 5 is characterized in that three windows are respectively provided at the left end along the lateral direction, the longitudinal direction surface part and the middle along the longitudinal direction, wherein the left end along the lateral direction window exposes the GaN buffer layer 3 and is provided with an isolation region 15, and the middle along the longitudinal direction window exposes the GaN buffer layer 3 and is provided with an isolation region 16; the left end along the longitudinal direction surface part window exposes the substrate layer 1 and is provided with a substrate region filled with a first conductive material 14;

[0032] The isolation region is isolated by trenches, and the isolation region 15 and the isolation region 16 are filled with a passivation layer 6;

[0033] A passivation layer 6 is provided above the AlGaN barrier layer 5, and a total of 4 windows are provided at both ends and in the middle of the passivation layer 6; in the left end window, the window is divided by the isolation region 15 in the longitudinal direction, wherein a first conductive material 14 is provided along the surface direction, extending downwardly in the vertical direction into the barrier layer 5 outside the substrate region, and the contact with the barrier layer 5 is an ohmic contact, and its lead end is the substrate electrode; a second conductive material 11 is provided along the depth direction, extending downwardly in the vertical direction into the barrier layer 5, and the contact with the barrier layer 5 is an ohmic contact, and its lead end is the source electrode; the middle two windows are on both sides of the isolation region 16, and the third conductive material 10 connects the two windows, and the third conductive material 10 extends downwardly in the vertical direction into the barrier layer 5, and the contact with the barrier layer 5 is an ohmic contact, and its lead end is the switch electrode; the right end window has a fourth conductive material 9, extending downwardly in the vertical direction into the barrier layer 5, and the contact with the barrier layer 5 is an ohmic contact, and its lead end is the drain electrode;

[0034] The gate structure 1 is located at the passivation layer window on the source electrode side, close to the switch electrode side and connected to the isolation region 15, and is spaced apart from the first conductive material 14 and the second conductive material 11; the gate structure 2 is located at the middle passivation layer window, close to the drain electrode side, and is spaced apart from the third conductive material 10; the gate structure is composed of P-type GaN layers 7, 8 stacked on the upper surface of the barrier layer 5, a fifth conductive material 13, a sixth conductive material 12 and a nearby passivation layer 6, the lead end of the fifth conductive material 13 is the gate electrode 1, and the lead end of the sixth conductive material 12 is the gate electrode 2.

[0035] The right end refers to an end of the drain electrode in the lateral direction, and the corresponding left end refers to an end away from the drain electrode.

[0036] The longitudinal direction refers to a third dimension direction that is perpendicular to both the vertical direction and the lateral direction of the device.

[0037] Working principle of the present invention:

[0038] When the upper tube of the half-bridge structure is turned on, the Sub transistor is in the off state. At this time, the substrate is floating, and negative charges begin to accumulate in the substrate due to the potential difference, and the substrate potential gradually increases; when the half-bridge working state is switched, the upper tube is turned off and the lower tube is turned on. At this time, the Sub transistor is in the on state. At this time, the substrate is connected to the circuit, and the negative charges accumulated in the Sub off state are released through the Sub transistor, avoiding the charge accumulation of the substrate under long-term working conditions, realizing dynamic adaptive adjustment of the substrate bias state, reducing the substrate coupling crosstalk problem caused by monolithic integration, improving the stability of the half-bridge structure in the power conversion system, and improving the energy conversion efficiency of the power system.

[0039] Example 2

[0040] The difference between this example and Example 1 is that the isolation region 22 of the monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression described in this example is located on the side of the seventh conductive material 20 away from the gate structure 1 in the lateral direction, the isolation region 22 has an eighth conductive material 17 on the side away from the seventh conductive material 20, extends downward into the barrier layer 5 in the vertical direction outside the substrate region, and the contact with the barrier layer 5 is an ohmic contact, the lead end is the drain electrode of the Sub transistor, and is electrically connected to the Switch electrode, the isolation region 22 is spaced from both the seventh conductive material 20 and the eighth conductive material 17, the ninth conductive material 21 is located at the left end of the device, the gate structure 3 is located on the side of the ninth conductive material 21 close to the drain electrode of the Sub transistor, and is spaced from the ninth conductive material 21, and the gate structure is composed of a P-type GaN layer 19, a tenth conductive material 18, and a nearby passivation layer 6 stacked on the upper surface of the barrier layer 5, and the lead end of the tenth conductive material 18 is a gate electrode 3, which is electrically connected to the gate electrode 1. Compared with Example 1, the advantage of this example is that the Sub transistor has the same chip area as the lower tube and has a higher charge control capability.

[0041] Example 3

[0042] The difference between this example and Example 1 is that the isolation method of the isolation region 15 and the isolation region 16 of the monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression described in this example is P-type GaN. Compared with Example 1, the advantage of this example is that no additional isolation step is required, the process flow is simplified, and the process efficiency is improved.

Claims

1. A monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression function, comprising a substrate layer (1), an AlN nucleation layer (2), a GaN buffer layer (3), a GaN channel layer (4) and a barrier layer (5) stacked in sequence from bottom to top along the vertical direction of the device; It is characterized in that The barrier layer (5) has a first conductive material (14) and a fourth conductive material (9) at both ends of the upper layer, wherein the first conductive material (14) is arranged at one end of the upper layer of the barrier layer (5) along the longitudinal direction of the device, and the second conductive material (11) is provided at the other end of the upper layer of the barrier layer (5) along the longitudinal direction of the device, and there is a spacing between the first conductive material (14) and the second conductive material (11); the middle part of the first conductive material (14) protrudes downward and the protruding part extends to the upper layer of the substrate layer (1) in the vertical direction; and a first isolation region (15) is provided in the barrier layer (5) between the first conductive material (14) and the second conductive material (11), and the first isolation region (15) extends to the upper layer of the GaN buffer layer (3) in the vertical direction; A passivation layer (6) is provided on the upper surface of the barrier layer (5) between the first conductive material (14), the second conductive material (11) and the fourth conductive material (9); A third conductive material (10) is provided in the middle of the barrier layer (5) between the first conductive material (14), the second conductive material (11) and the fourth conductive material (9); both ends of the third conductive material (10) extend downward, penetrate the passivation layer (6) and are then embedded in the upper layer of the barrier layer (5); and a second isolation region (16) is provided between the portions extending downward from both ends of the third conductive material (10); the upper end of the second isolation region (16) is in contact with the passivation layer (6), and the lower end of the second isolation region (16) extends downward along the vertical direction of the device to the upper layer of the GaN buffer layer (3); A first gate structure is provided on the upper surface of the passivation layer (6) between the first conductive material (14), the second conductive material (11) and the third conductive material (10); the first gate structure is close to the first conductive material (14) and the second conductive material (11) and has a spacing between the first conductive material (14) and the second conductive material (11); the first gate structure comprises a first P-type GaN layer (7) and a fifth conductive material (13); the bottom of the first P-type GaN layer (7) contacts the upper surface of the barrier layer (5); the bottom of the fifth conductive material (13) contacts the upper surface of the first P-type GaN layer (7); and the passivation layer (6) wraps the side surface of the first P-type GaN layer (7) and the surface not covered by the fifth conductive material (13); A second gate structure is provided on the upper surface of the passivation layer (6) between the third conductive material (10) and the fourth conductive material (9), the second gate structure being close to the third conductive material (10) and having a spacing therebetween; the second gate structure comprises a second P-type GaN layer (8) and a sixth conductive material (12), the bottom of the second P-type GaN layer (8) being in contact with the upper surface of the barrier layer (5), the bottom of the sixth conductive material (12) being in contact with the upper surface of the second P-type GaN layer (8), and the passivation layer (6) wrapping the side surfaces of the second P-type GaN layer (8) and the surface not covered by the sixth conductive material (12); The contact between the first conductive material (14) and the barrier layer (5) is an ohmic contact, and the lead-out end is a substrate electrode; the contact between the third conductive material (10) and the barrier layer (5) is an ohmic contact, and the lead-out end is a switch electrode; the contact between the fourth conductive material (9) and the barrier layer (5) is an ohmic contact, and the lead-out end is a drain electrode; the contact between the second conductive material (11) and the barrier layer (5) is an ohmic contact, and the lead-out end is a source electrode; and the lead-out ends of the fifth conductive material (13) and the sixth conductive material (12) are gate electrodes.

2. The monolithic integrated half-bridge GaN HEMT device with substrate-coupled crosstalk suppression according to claim 1, characterized in that: A seventh conductive material (20), an eighth conductive material (17) and a ninth conductive material (21) are sequentially distributed on a side of the first gate structure away from the second gate structure in the lateral direction, and the contacts with the barrier layer (5) are all ohmic contacts, and the lead ends are sequentially a source electrode, a drain electrode of the Sub transistor and a substrate electrode, wherein the eighth conductive material (17) is electrically connected to the third conductive material (10); a third isolation region (22) is provided between the seventh conductive material (20) and the eighth conductive material (17), the upper end of the third isolation region (22) is in contact with the passivation layer (6), and the lower end of the third isolation region (22) extends into the GaN buffer layer (3) along the vertical direction of the device; the structure of the ninth conductive material (21) is the same as that of the first conductive material (14), except that the ninth conductive material (21) runs through the device along the longitudinal direction of the device; A third gate structure is provided between the eighth conductive material (17) and the ninth conductive material (21). The third gate structure is close to the ninth conductive material (21) and has a spacing therebetween. The third gate structure is the same as the first gate structure and comprises a third P-type GaN layer (19) and a tenth conductive material (18). The bottom of the third P-type GaN layer (19) contacts the upper surface of the barrier layer (5), the bottom of the tenth conductive material (18) contacts the upper surface of the third P-type GaN layer (19), the passivation layer (6) wraps the side surface of the third P-type GaN layer (19) and the surface not covered by the tenth conductive material (18), and the tenth conductive material (18) is electrically connected to the fifth conductive material (13).

3. The monolithic integrated half-bridge GaN HEMT device with substrate-coupled crosstalk suppression according to claim 1 and claim 2, characterized in that: The first isolation region (15), the second isolation region (16) and the third isolation region (22) are one of ion implantation isolation, trench isolation and P-type GaN isolation.

4. The monolithic integrated half-bridge GaN HEMT device with substrate-coupled crosstalk suppression according to claim 1, characterized in that: The barrier layer (5) is made of a material selected from the group consisting of AlN, AlGaN, InGaN, and InAlN, or a combination of several of them; the GaN channel layer (4) and the barrier layer (5) form a heterojunction, and a 2DEG is generated at the heterojunction interface.

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