Display panel and display device including same

Abstract

A display panel and a display device including the same are provided. A display panel according to an embodiment includes: a substrate; an insulating layer disposed over the substrate; a bank pattern disposed on the insulating layer; a first electrode disposed on the bank pattern; a contact electrode disposed on the insulating layer and spaced apart from the bank pattern; a light emitting element disposed over the first electrode; a first optical layer surrounding the light emitting element and made of an organic insulating material including metal particles; a second optical layer formed over the contact electrode; and a third optical layer formed on the first optical layer.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a display device including the display panel. Background Art

[0002] As the flat panel display device, a liquid crystal display device and an organic light emitting display device, etc. are used. Compared with the liquid crystal display device, the organic light emitting display device has advantages such as improved light emitting efficiency, fast response speed, wide viewing angle, etc. However, since the organic light emitting display device has low light emitting efficiency and is easily affected by moisture due to organic materials contained therein, its reliability and lifespan may be reduced.

[0003] Recently, a micro light emitting diode display device has been proposed as an inorganic light emitting display device. The micro light emitting diode display device generates an image by providing an inorganic light emitting diode having a size of, for example, 100 μm or less in each pixel.

[0004] The descriptions provided in the background section should not be considered as prior art merely because they are mentioned in or related to the background section.The background section may include information describing one or more aspects of the subject technology. Summary of the invention

[0005] The present disclosure provides a display panel capable of reducing or preventing diffusion of fine metal particles and a display device including the same.

[0006] Problems or limitations to be solved or addressed by the present disclosure are not limited to the above-mentioned contents, and other problems or limitations not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] According to an embodiment of the present specification, a display panel may include: a substrate; an insulating layer disposed above the substrate; a dam pattern disposed on the insulating layer; a first electrode disposed on the dam pattern; a contact electrode disposed on the insulating layer and spaced apart from the dam pattern; a light-emitting element disposed above the first electrode; a first optical layer surrounding the light-emitting element and made of an organic insulating material including metal particles; a second optical layer formed above the contact electrode; and a third optical layer formed on the first optical layer.

[0008] According to an embodiment of the present specification, a display device may include a display panel including a plurality of pixels and a pixel driving circuit for driving the plurality of pixels, and the display panel may include: a substrate; an insulating layer disposed above the substrate; a dam pattern disposed on the insulating layer; a first electrode disposed on the dam pattern; a contact electrode disposed on the insulating layer and spaced apart from the dam pattern; a light-emitting element disposed above the first electrode; a first optical layer surrounding the light-emitting element and made of an organic insulating material including metal particles; a second optical layer formed above the contact electrode; and a third optical layer formed on the first optical layer.

[0009] According to the present disclosure, a first optical layer including fine metal particles is formed to surround a micro light emitting diode, and a third optical layer not including fine metal particles is formed on the first optical layer, thereby reducing or preventing diffusion of fine metal particles of the first optical layer.

[0010] According to the present disclosure, since the third optical layer reduces or prevents diffusion of metal particles of the first optical layer, the flatness of the third optical layer formed with the cathode increases, so that damage to the cathode can be reduced or prevented.

[0011] According to the present disclosure, since the flatness of the second optical layer is increased, the cathode can be prevented from being damaged, and since the increase in the resistance of the cathode is suppressed, the lighting rate of the micro light emitting diode can be improved.

[0012] According to the present disclosure, since an increase in the resistance of the cathode is suppressed and thus the lighting rate of the micro light emitting diode is improved, power consumption can be reduced, making low-power driving possible.

[0013] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principle of the present disclosure.

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1is a diagram showing a display device according to an exemplary embodiment of the present specification;

[0018] Figure 2 yes Figure 1 An enlarged view of area A;

[0019] Figure 3 is a diagram showing a local area of ​​a pixel;

[0020] Figure 4 is along Figure 3 A cross-sectional view taken along line II' in FIG.

[0021] Figure 5 is along Figure 3 A cross-sectional view taken along line II-II';

[0022] Figure 6 is along Figure 3 A cross-sectional view taken along line III-III';

[0023] Figure 7 is a cross-sectional view showing an example in which a main light emitting element and a sub-light emitting element are electrically connected to a pixel driving circuit;

[0024] Figure 8 is a diagram illustrating a display device according to another exemplary embodiment of the present specification;

[0025] Fig. 9 is along Figure 8 A cross-sectional view taken along line IV-IV';

[0026] Fig.10 is a view showing an image of a light emitting element covered by a first optical layer;

[0027] Fig.11 is a view showing an image in which a third optical layer is overlaid on a first optical layer;

[0028] Fig.12 is a view showing an image in which no third optical layer exists on the first optical layer;

[0029] Fig.13 is a view showing a method of manufacturing a display device according to a first exemplary embodiment of the present disclosure;

[0030] FIG. 14A to FIG. 14G It is used to illustrate Fig.13 A view showing a method of manufacturing a display device;

[0031] Fig.15 is a view for explaining a method of manufacturing a display device according to a second exemplary embodiment of the present disclosure;

[0032] 16A to 16H It is used to illustrate Fig.15 A view showing a method of manufacturing a display device;

[0033] Fig.17 is a view for explaining a method of manufacturing a display device according to a third exemplary embodiment of the present disclosure;

[0034] FIG. 18A to FIG. 18G It is used to illustrate Fig.17 A view showing a method of manufacturing a display device; and

[0035] Fig.19 is a diagram showing simulation results of light output efficiency of Examples and Comparative Examples.

[0036] Throughout the drawings and detailed description, unless otherwise specified, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and descriptions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The described progression of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as known in the art, except for steps and / or operations that must occur in a particular order. The names of various elements used in the following description may have been selected solely for ease of writing the specification and, therefore, may differ from the names used in an actual product.

[0038] From the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and their implementation methods will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the attached claims.

[0039] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, a detailed description of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0040] Terms such as “include,” “comprising,” “having,” and “containing” used herein are generally intended to allow the addition of other components unless these terms are used with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0041] Even if not explicitly stated, the components are interpreted as including the normal error range.Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0042] When terms such as "on top of," "above," "below," "beside," "connected or coupled," "crossing," "intersecting," etc. are used to describe the position or interconnection relationship between two components, one or more other components may be inserted between the two components unless "immediately" or "directly" is used.

[0043] Terms such as "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between items as shown in the drawings. It should be understood that these terms are spatially relative and based on the orientation shown in the drawings.

[0044] When words such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a temporal sequence, they may not be continuous based on time unless “immediately” or “directly” is used.

[0045] Terms such as “first,” “second,” “A,” “B,” “(a),” “(b),” etc. may be used to distinguish elements from one another, but the function or structure of a component is not limited by sequence numbers preceding the component or the component name.

[0046] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first element, a second element, and a third element" covers the combination of all three listed elements, the combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by a person of ordinary skill in the art to which the example embodiments belong. It should also be understood that terms (e.g., terms defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. For example, as will be understood by a person of ordinary skill in the art, the term "component" or "unit" may be applied to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function.

[0048] The following embodiments can be combined or combined with each other in part or in whole, and can be linked and operated in various ways in terms of technology. These embodiments can be implemented independently of each other or in association with each other.

[0049] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] In the present specification, a first optical layer including fine metal particles is formed to surround a light emitting element, and a third optical layer not including fine metal particles is formed on the first optical layer, thereby reducing or preventing diffusion of fine metal particles of the first optical layer by double-layer coating of the first optical layer and the third optical layer.

[0051] Figure 1 is a diagram showing a display device according to an exemplary embodiment of the present specification; Figure 2 According to an exemplary embodiment of this specification Figure 1 An enlarged view of area A; Figure 3 is a diagram illustrating a partial area of ​​a pixel according to an exemplary embodiment of the present specification.

[0052] Reference Figure 1 and Figure 2 , a display device according to an exemplary embodiment of the present specification includes a display panel 100 that visually reproduces an input image. The display panel 100 may include a display area AA in which an image is displayed and a non-display area NA in which an image is not displayed. In the non-display area NA, various wires and driving circuits may be installed and / or a pad portion PAD to which an integrated circuit, a printed circuit, etc. are connected may be provided.

[0053] The plurality of light emitting elements 10 disposed in the display area AA to form the pixel PXL may be inorganic light emitting elements (eg, micro inorganic light emitting elements). The inorganic light emitting elements may be grown on a silicon wafer and then attached to the display panel through a transfer process, but are not limited thereto.

[0054] The transfer process of the light emitting element 10 may be performed for each pre-divided region. Figure 1 , the display area AA is divided into nine transfer areas ST, but the size or number of the division of the transfer area is not limited thereto. As an example, the display area AA can be divided into two or more transfer areas ST. As an example, the display area AA can be divided into more than nine transfer areas ST. The transfer process can be performed sequentially or simultaneously on at least some of the first transfer area to the ninth transfer area ST. In the transfer area ST, the blue, green and red light-emitting elements 10 can be transferred in sequence, respectively, but are not limited thereto. As an example, the arrangement of the blue, green and red light-emitting elements 10 can be variously changed in various ways. As an example, light-emitting elements of other colors are also feasible.

[0055] In the non-display area NA, as an example, a data drive circuit or a gate drive circuit may be provided, and a conductor for providing a control signal to control these drive circuits may be provided, but is not limited thereto. Here, the control signal may include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, and may be received through the pad portion PAD. As an example, the data drive circuit or the gate drive circuit may not be provided in the non-display area NA. As an example, the data drive circuit or the gate drive circuit may be provided separately in a separate panel, and connected to the display panel 100 (e.g., the pad portion PAD) by, for example, a tape automated bonding (TAB) method, a chip on glass (COG) method, a chip on panel (COP) method, or a chip on film (COF) method, but is not limited thereto.

[0056] The pixel PXL can be driven by a pixel driving circuit. The pixel driving circuit can receive a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and output an anode voltage and a cathode voltage of the light-emitting element 10 to drive a plurality of pixels. The driving voltage can be a high potential voltage (EVDD). The cathode voltage can be a low potential voltage (EVSS) applied to the pixel (for example, in common). The anode voltage can be a voltage corresponding to the pixel data value of the image signal. The pixel driving circuit can be arranged in the non-display area NA or in the lower part of the display area AA.

[0057] Each of the pixels PXL may include a plurality of sub-pixels each having a different color. For example, each of the plurality of pixels may include a red sub-pixel in which a light-emitting element 10 emitting light in a red wavelength is provided, a green sub-pixel in which a light-emitting element 10 emitting light in a green wavelength is provided, and a blue sub-pixel in which a light-emitting element 10 emitting light in a blue wavelength is provided. The plurality of pixels may also include a white pixel. Embodiments are not limited thereto. As an example, sub-pixels emitting light of other colors such as magenta, cyan, or yellow may be included alternatively or additionally.

[0058] Reference Figure 2 and Figure 3, a plurality of pixels PXL may be sequentially arranged along a first direction (X-axis direction) and a second direction (Y-axis direction), but is not limited thereto. As an example, a plurality of pixels PXL may be sequentially arranged along any direction between the first direction and the second direction. As an example, in each of the pixels of the display area AA, a plurality of sub-pixels of the same color may be arranged. For example, each of the plurality of pixels may include a first red sub-pixel in which a 1-1 light-emitting element 11a emitting light in a red wavelength is disposed, a second red sub-pixel in which a 1-2 light-emitting element 11b emitting light in a red wavelength is disposed, a first green sub-pixel in which a 2-1 light-emitting element 12a emitting light in a green wavelength is disposed, a second green sub-pixel in which a 2-2 light-emitting element 12b emitting light in a green wavelength is disposed, a first blue sub-pixel in which a 3-1 light-emitting element 13a emitting light in a blue wavelength is disposed, and / or a second blue sub-pixel in which a 3-2 light-emitting element 13b emitting light in a blue wavelength is disposed. As an example, the 1-1st light emitting element 11a, the 2-1st light emitting element 12a, and the 3-1st light emitting element 13a may be interpreted as a main light emitting element. As an example, the 1-2nd light emitting element 11b, the 2-2nd light emitting element 12b, and the 3-2nd light emitting element 13b may be interpreted as a sub-light emitting element. Embodiments are not limited thereto. As an example, each of the plurality of pixels may include one or more red sub-pixels, one or more green sub-pixels, and one or more blue sub-pixels. As an example, in each of the plurality of pixels, the number of red sub-pixels, the number of green sub-pixels, and the number of blue sub-pixels may be the same or different from each other.

[0059] As an example, one pixel includes one or more sub-pixels of the same color, or one sub-pixel includes one or more light-emitting elements, and if one sub-pixel or one light-emitting element becomes defective, the brightness of another sub-pixel or another light-emitting element of the same color may be increased to adjust the brightness of the pixel or the sub-pixel. However, it is not necessarily limited thereto, and one pixel may include one sub-pixel having the same color and / or one sub-pixel may include only one light-emitting element.

[0060] Each of the plurality of first electrodes 161 may be disposed at a lower portion of the light emitting element 10, and may be selectively connected to a corresponding one of the plurality of signal wirings TL1 to TL6 through a connection portion 161a. A high potential voltage may be applied to the pixel driving circuit through the signal wirings TL1 to TL6. The first electrode 161 and a corresponding one of the signal wirings TL1 to TL6 may be formed as an integrated electrode pattern in an electrode patterning process.

[0061] As an example, the first signal wiring TL1 may be connected to the anode of the first red sub-pixel, and the second signal wiring TL2 may be connected to the anode of the second red sub-pixel. The third signal wiring TL3 may be connected to the anode of the first green sub-pixel, and the fourth signal wiring TL4 may be connected to the anode of the second green sub-pixel. The fifth signal wiring TL5 may be connected to the anode of the first blue sub-pixel, and the sixth signal wiring TL6 may be connected to the anode of the second blue sub-pixel. If one pixel includes only one sub-pixel of the same color, or one sub-pixel includes only one light-emitting element, the number of signal wirings TL may be halved.

[0062] The second electrode 170 may be a cathode arranged in each row to apply a cathode voltage to the light emitting elements 10 arranged continuously in the first direction (X-axis direction). A plurality of second electrodes 170 may be arranged to be spaced apart from each other in the second direction (Y-axis direction). A plurality of second electrodes 170 may receive a cathode voltage through a contact electrode 163. Each of the plurality of second electrodes 170 may be electrically connected to the contact electrode 163. However, it is not necessarily limited thereto, and the second electrode 170 may include an electrode layer instead of being divided into a plurality of electrodes to serve as a common electrode. As another example, the second electrode 170 may be divided into a plurality of electrodes arranged in each column and spaced apart from each other in the first direction, or may be divided in other directions.

[0063] Figure 4 is along Figure 3 A cross-sectional view taken along line II' in FIG. Figure 5 is along Figure 3 A cross-sectional view taken along line II-II'. Figure 6 is along Figure 3 A cross-sectional view taken along line III-III'. Figure 7 is a cross-sectional view showing an example in which two light emitting elements are connected to a pixel driving circuit.

[0064] Reference Figures 3 to 5 According to an exemplary embodiment, the display device includes a plurality of first electrodes 161 and a contact electrode 163 disposed on a substrate 110, a plurality of light emitting elements 10 disposed on the plurality of first electrodes 161, a first optical layer 141 disposed between the plurality of light emitting elements 10, and a second electrode 170 disposed on the plurality of light emitting elements 10.

[0065] The substrate 110 may be made of a flexible plastic. For example, the substrate 110 may be made of a single-layer or multi-layer substrate of a material selected from polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, polyarylate, polysulfone, and cycloolefin copolymer, but is not limited thereto. For example, the substrate 110 may be a ceramic substrate or a glass substrate. The embodiment is not limited thereto. As an example, the substrate 110 may be a rigid substrate made of a rigid material.

[0066] The pixel driving circuit 20 may be disposed in the display area AA on the substrate 110. The pixel driving circuit 20 may include a plurality of thin film transistors using an amorphous silicon semiconductor, a polysilicon semiconductor, an oxide semiconductor, an organic semiconductor, a compound semiconductor, or any other semiconductor.

[0067] The pixel driving circuit 20 may include at least one driving thin film transistor, at least one switching thin film transistor, and at least one storage capacitor. When the pixel driving circuit 20 includes a plurality of thin film transistors, it may be formed on the substrate 110 by a thin film transistor (TFT) manufacturing process. In an embodiment, the pixel driving circuit 20 may be a collective term for a plurality of thin film transistors electrically connected to the light emitting element 10.

[0068] The pixel driving circuit 20 may be a driving driver manufactured using a metal oxide silicon field effect transistor (MOSFET) manufacturing process on a single crystal semiconductor substrate 110, but is not limited thereto. The driving driver may include a plurality of pixel driving circuits for driving a plurality of sub-pixels. When the pixel driving circuit 20 is implemented as a driving driver, after the adhesive layer is disposed on the substrate 110, the driving driver may be mounted on the adhesive layer by a transfer process, but is not limited thereto.

[0069] A buffer layer 121 covering the pixel driving circuit 20 may be disposed on the substrate 110. The buffer layer 121 may be made of an organic insulating material (eg, photosensitive photoacryl or photosensitive polyimide), but is not limited thereto.

[0070] The buffer layer 121 may be formed by stacking an inorganic insulating material (eg, silicon nitride (SiNx) or silicon oxide (SiO2)) in multiple layers, may be formed by stacking an organic insulating material in multiple layers, or may be formed by stacking an organic insulating material and an inorganic insulating material in multiple layers.

[0071] The insulating layer 122 may be disposed on the buffer layer 121. The insulating layer 122 may be made of an organic insulating material (e.g., photosensitive photopropylene or photosensitive polyimide), but is not limited thereto. The connection wirings RT1 and RT2 may be disposed on the buffer layer 121. The connection wirings RT1 and / or RT2 may be connected through corresponding signal wirings TL1 to TL6, or may be connected to the signal wirings TL1 to TL6. The connection wirings RT1 and RT2 may include a plurality of wiring patterns disposed on different layers and having one or more insulating layers interposed therebetween. The wiring patterns disposed on different layers may be electrically connected through contact holes passing through the insulating layers.

[0072] A plurality of bank patterns 130 may be disposed on the insulating layer 122. At least one light emitting element 10 may be disposed on each bank pattern 130. For example, a first light emitting element 11 may be disposed on the first bank pattern 130, a second light emitting element 12 may be disposed on the second bank pattern 130, and a third light emitting element 13 may be disposed on the third bank pattern 130.

[0073] The bank pattern 130 may be made of an organic insulating material (eg, photosensitive acryl or photosensitive polyimide) or an inorganic insulating material, but is not limited thereto. The bank pattern 130 may guide the position to which the light emitting element 10 is to be attached during the transfer process of the light emitting element 10. The bank pattern 130 may be omitted.

[0074] The solder pattern 162 may be disposed on the first electrode 161. The solder pattern 162 may be made of indium (In), tin (Sn), or an alloy thereof, but is not limited thereto.

[0075] A plurality of light emitting elements 10 may be mounted on the solder pattern 162, respectively. One pixel may include three colors of light emitting elements 10. The first light emitting element 11 may be a red light emitting element, the second light emitting element 12 may be a green light emitting element, and the third light emitting element 13 may be a blue light emitting element. As an example, two light emitting elements may be mounted in each sub-pixel.

[0076] The first optical layer 141 may cover the plurality of light emitting elements 10 and the dyke pattern 130. Thus, the first optical layer 141 may cover between the plurality of light emitting elements 10 and between the plurality of dyke patterns 130. The first optical layer 141 may extend along the first direction (X) and be spaced apart along the second direction (Y) to be separated between pixel rows. As an example, the first optical layer 141 may cover the edge of the first electrode 161, but is not limited thereto.

[0077] As an example, the first optical layer 141 may include an organic insulating material in which fine metal particles such as titanium dioxide particles are dispersed, but is not limited thereto. Light emitted from the plurality of light emitting elements 10 may be scattered by fine metal particles dispersed in the first optical layer 141 to be emitted outward. The embodiment is not limited thereto. As an example, the first optical layer 141 may include an organic insulating material in which particles of other materials are dispersed. As an example, the first optical layer 141 may include an organic insulating material in which particles or fine particles having a certain reflectivity are dispersed. As an example, the first optical layer 141 may include an organic insulating material in which fine metal oxide particles are dispersed. As an example, the first optical layer 141 may include an organic insulating material in which particles containing metal elements are dispersed.

[0078] The second electrode 170 may be disposed on a plurality of light emitting elements 10. The second electrode 170 may be commonly connected to a plurality of pixels PXL. The second electrode 170 may be an electrode that transmits light. The second electrode 170 may be a transparent electrode material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)), but is not necessarily limited thereto. As an example, the second electrode 170 may be a semi-transmissive metal material (e.g., magnesium Mg, silver Ag, or an alloy thereof).

[0079] The second electrode 170 may extend in the first direction (X-axis direction) and be spaced apart in the second direction (Y-axis direction). The second electrode 170 may include a first region 171 disposed on the top surface of the light emitting element 10 and the top surface of the first optical layer 141, a second region 172 contacting the contact electrode 163 and electrically connected to the contact electrode 163, and a third region 173 disposed on the side of the first optical layer 141 and connecting the first region 171 and the second region 172.

[0080] On a plane, each of the plurality of second electrodes 170 may overlap the first optical layer 141, and the second region 172 may cover a plane outside the first optical layer 141. As an example, the second region 172 may cover a plane outside the first optical layer 141 along the second direction.

[0081] The second optical layer 142 may be an organic insulating material surrounding the first optical layer 141. The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (e.g., siloxane). For example, the first optical layer 141 may be siloxane containing titanium oxide (TiOx), and the second optical layer 142 may be siloxane not containing titanium oxide (TiOx). However, it is not necessarily limited thereto, and the first optical layer 141 and the second optical layer 142 may be formed of the same material or may be formed of different materials.

[0082] According to the exemplary embodiment, since the second region 172 of the second electrode 170 is connected to the contact electrode 163 in a generally flat state, excessive stress is not concentrated at the point of connection with the contact electrode 163. Therefore, cracks in the second electrode 170 may be effectively reduced or prevented.

[0083] The second optical layer 142 may cover the second region 172 and the third region 173 of the second electrode 170. The top surface of the second optical layer 142 and the top surface of the first region 171 of the second electrode 170 may be coplanar. In other words, the first optical layer 141 and the second optical layer 142 may be used as a planarization layer. As a result, since there is no step on the surface on which the black matrix 190 is formed, the pattern of the black matrix 190 may be easily formed on the first optical layer 141 and the second optical layer 142. However, it is not necessarily limited thereto, and the second optical layer 142 and the top surface of the second electrode 170 may have different heights. As an example, the pattern of the black matrix 190 may be omitted according to the design.

[0084] As an example, the third optical layer 143 may be an organic insulating material covered on the first optical layer 141. The third optical layer 143 may block the diffusion of metal particles of the first optical layer 141. The third optical layer 143 may be formed so that the top surface is on the same line as the top surface of the light emitting element 10 or is lower than the top surface of the light emitting element 10. The third optical layer 143 may also be formed on the first optical layer 141 to have a constant thickness. However, the embodiment is not necessarily limited thereto, and the thickness of the third optical layer 143 may be uniformly formed or may be irregularly formed. As an example, the third optical layer 143 may be omitted according to the design.

[0085] For example, the thickness d of the third optical layer 143 may be set within a range of, for example, 1 μm to 2 μm, but is not limited thereto.

[0086] In this case, the second optical layer 142 and the third optical layer 143 may be made of the same organic insulating material. For example, the second optical layer 142 and the third optical layer 143 may be made of siloxane that does not contain titanium oxide (TiOx). However, the embodiment is not necessarily limited thereto. As an example, in addition to the fine particles of the first optical layer 141, the first optical layer 141, the second optical layer 142, and the third optical layer 143 may be made of the same organic insulating material. As an example, at least one of the first optical layer 141, the second optical layer 142, and the third optical layer 143 may be made of a different material.

[0087] The black matrix 190 may include an opaque material. As an example, the black matrix 190 may include an organic insulating material to which a black pigment is added, but is not limited thereto. Under the black matrix 190, the second electrode 170 may be in contact with the contact electrode 163. A transmission hole 191 may be formed between the patterns of the black matrix 190, and light emitted from the light emitting element 10 is emitted outward through the transmission hole 191. Through the black matrix 190, the problem that light emitted from adjacent light emitting elements 10 is mixed by the first optical layer 141 can be improved.

[0088] The cover layer 180 may be an organic insulating material for covering the black matrix 190 and the second electrode 170. Figure 3 In the figure, the structures of the black matrix 190 and the cover layer 180 are omitted.

[0089] The contact electrode 163 is electrically connected to the first connection wiring RT1 disposed at the lower portion thereof, and the first connection wiring RT1 may be connected to the pixel driving circuit 20. Therefore, a cathode voltage may be applied to the second electrode 170 through the contact electrode 163. The first electrode 161 may be electrically connected to the second connection wiring RT2. This will be described later.

[0090] Reference Figure 5 The contact electrode 163 and the signal wirings TL1 to TL6 may be disposed on the same plane. The pixel driving circuit 20 may be disposed below the contact electrode 163 and the signal wirings TL1 to TL6. When the pixel driving circuit 20 is a driving driver, a plurality of driving drivers may be disposed in the display panel.

[0091] The passivation layer 133 may expose the contact electrode 163 so that the contact electrode 163 is electrically connected to the second electrode 170. In addition, the passivation layer 133 may insulate the signal wirings TL2 to TL5 from the second electrode 170.

[0092] Reference Figure 6 , the connection portion 161a of the first electrode 161 extends to one side surface 131 of the bank pattern 130 and is electrically connected to the connection wiring RT2 provided on the insulating layer 122. As an example, the connection portion 161a branches from the first electrode 161 in a direction crossing or perpendicular to a direction in which the light emitting elements 10 are arranged on the bank pattern 130, but is not limited thereto.

[0093] The first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wiring RT1 and RT2 may include a single layer or multiple layers of metal selected from titanium (Ti), molybdenum (Mo) and aluminum (Al), but are not limited thereto. The first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wiring RT1 and RT2 may be formed as a multilayer structure including a first layer ML1, a second layer ML2, a third layer ML3 and a fourth layer ML4, but are not limited thereto. As an example, the first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wiring RT1 and RT2 may collectively include at least one of the first layer ML1, the second layer ML2, the third layer ML3 and the fourth layer ML4. As an example, the first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wiring RT1 and RT2 may include different numbers of layers or different materials.

[0094] The first layer ML1 and the third layer ML3 may include titanium (Ti) or molybdenum (Mo). The second layer ML2 may include aluminum (Al). The fourth layer ML4 may include a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) having good adhesion to the solder pattern 162, corrosion resistance, and acid resistance.

[0095] The first layer ML1 , the second layer ML2 , the third layer ML3 , and the fourth layer ML4 may be sequentially deposited and then patterned by performing a photolithography process and an etching process, but are not limited thereto.

[0096] The passivation layer 133 may be disposed on the first electrode 161 and the signal wiring TL, and may include an opening 133 a exposing the first electrode 161 .

[0097] The light emitting element 10 may include a first conductive type semiconductor layer 10-1, an active layer 10-2 disposed on the first conductive type semiconductor layer 10-1, and a second conductive type semiconductor layer 10-3 disposed on the active layer 10-2. The first driving electrode 15 may be disposed at a lower portion of the first conductive type semiconductor layer 10-1, and the second driving electrode 14 may be disposed at an upper portion of the second conductive type semiconductor layer 10-3.

[0098] The light emitting element 10 can be formed on a silicon wafer using methods such as metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, etc.

[0099] The first conductive type semiconductor layer 10-1 may be implemented as a compound semiconductor such as a III-V group, a II-VI group, etc., and may be doped with a first dopant, but is not limited thereto. The first conductive type semiconductor layer 10-1 may be composed of a composition formula of Al x1 In y1 Ga (1-x1-y1) The first conductive type semiconductor layer 10-1 may be formed of any one or more of semiconductor materials of N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), InAlGaN, AlGaAs, GaP, GaAs, and AlGaInP, but is not limited thereto. When the first dopant is an n-type dopant such as Si, Ge, Sn, Se, Te, etc., the first conductive type semiconductor layer 10-1 may be an n-type semiconductor layer. However, when the first dopant is a p-type dopant, the first conductive type semiconductor layer 10-1 may be a p-type semiconductor layer.

[0100] The active layer 10-2 is a layer where electrons (or holes) injected through the first conductive type semiconductor layer 10-1 meet holes (or electrons) injected through the second conductive type semiconductor layer 10-3. As the electrons and holes recombine, the active layer 10-2 may transition to a lower energy level and generate light having a corresponding wavelength.

[0101] The active layer 10-2 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the structure of the active layer 10-2 is not limited thereto. The active layer 10-2 may generate light in a visible light band or even in an invisible light band. As an example, the active layer 10-2 may output light in any one of a blue band, a green band, and a red band, but is not limited thereto.

[0102] The second conductive type semiconductor layer 10-3 may be disposed on the active layer 10-2. The second conductive type semiconductor layer 10-3 may be implemented as a compound semiconductor such as a III-V group, a II-VI group, etc., and the second conductive type semiconductor layer 10-3 may be doped with a second dopant, but is not limited thereto. The second conductive type semiconductor layer 10-3 may be composed of a composition formula of In x2 Al y2 Ga 1-x2+y2The second conductive type semiconductor layer 10-3 may be formed of a semiconductor material selected from the group consisting of AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc., the second conductive type semiconductor layer 10-3 doped with the second dopant may be a p-type semiconductor layer. When the second dopant is an n-type dopant, the second conductive type semiconductor layer 10-3 may be an n-type semiconductor layer.

[0103] As an example, the reflective layer 16 may be disposed on the side surface and the lower portion of the light emitting element 10. The reflective layer 16 may have a structure in which a reflective material is dispersed in a resin layer, but is not necessarily limited thereto. As an example, the reflective layer 16 may be manufactured into a reflector of various structures. The light emitted from the active layer 10-2 may be reflected upward by the reflective layer 16 to increase the light extraction efficiency. The embodiment is not limited thereto. As an example, the reflective layer 16 may be disposed only on the side surface of the light emitting element 10 in the first direction or the second direction. As an example, the reflective layer 16 may be disposed only on a portion of the side surface of the light emitting element 10, or may be omitted according to the design.

[0104] Although the embodiment is described as a vertical structure in which the driving electrodes 14 and 15 are disposed on the upper and lower portions of the light emitting structure, the light emitting device may have a lateral structure or a flip chip structure different from the vertical structure.

[0105] Reference Figure 7 , the main light emitting element 12a and the sub light emitting element 12b of the sub-pixel may be disposed on the bank pattern 130. The second light emitting element 12 will be exemplarily described. The 1-1 electrode 161-1 connected to the main light emitting element 12a may extend to one side surface of the bank pattern 130 to be electrically connected to the 2-1 connection wiring RT21 disposed at a lower portion thereof. The 1-2 electrode 161-2 connected to the sub light emitting element 12b may extend to the other side surface of the bank pattern 130 to be electrically connected to the 2-2 connection wiring RT22 disposed at a lower portion thereof.

[0106] The pixel driving circuit 20 can apply an anode voltage to the main light emitting element 12a through the 2-1st connection wiring RT21, and can apply an anode voltage to the sub light emitting element 12b through the 2-2nd connection wiring RT22. The pixel driving circuit 20 can apply a cathode voltage to the main light emitting element 12a and the sub light emitting element 12b through the first connection wiring RT1 and the second electrode 170.

[0107] The pixel driving circuit 20 can adjust the brightness by driving only one of the main light-emitting element 12a and the sub-light-emitting element 12b, or can adjust the brightness by driving the main light-emitting element 12a and the sub-light-emitting element 12b at the same time. If the main light-emitting element 12a becomes dark, the brightness can be adjusted by driving only the sub-light-emitting element 12b. As an example, the main light-emitting element 12a and the sub-light-emitting element 12b can be driven independently. As an example, the main light-emitting element 12a and the sub-light-emitting element 12b can be connected to different transistors in the pixel driving circuit 20. As an example, in normal operation, the pixel driving circuit 20 can drive the main light-emitting element 12a, or can drive both the main light-emitting element 12a and the sub-light-emitting element 12b.

[0108] Figure 8 is a diagram illustrating a display device according to another exemplary embodiment of the present specification. Fig. 9 is along Figure 8 A cross-sectional view taken along line IV-IV'.

[0109] Reference Figure 8 and Fig. 9 , the second electrode 170 may be electrically connected to the contact electrode 163 via a contact hole TH1 formed in the second optical layer 142. The second optical layer 142 may include a contact hole TH1 exposing the contact electrode 163. The second electrode 170 may be inserted into the contact hole TH1 of the second optical layer 142 and may contact an upper surface of the contact electrode 163. The contact hole TH1 may be formed in an outer region of the pixel.

[0110] The reason why the third optical layer is formed on the first optical layer in this embodiment is as follows.

[0111] Fig.10 is a view showing an image of a light emitting element covered by a first optical layer. Fig.11 is a view showing an image in which a third optical layer is overlaid on a first optical layer. Fig.12 is a view showing an image in which the third optical layer does not exist on the first optical layer.

[0112] like Fig.10 As shown in a scanning electron microscope (SEM) image of , the light emitting element is covered by the first optical layer 141 , but the top surface of the light emitting element is not covered by the first optical layer 141 .

[0113] As shown in the comparative example Fig.12 As shown, when the third optical layer is not formed on the first optical layer 141, it can be seen that the fine metal particles of the first optical layer 141 are diffused, and the top surface is not flat and irregularly formed.

[0114] When the second electrode is formed on the first optical layer 141 having the rough top surface, damage of the second electrode may occur due to diffusion of fine metal particles of the first optical layer 141 .

[0115] On the other hand, when the exemplary embodiment is shown Fig.11 As shown in FIG. 1 , when the third optical layer 143 is formed on the first optical layer 141, it can be seen that the top surface of the third optical layer 143 is not formed to be rough but is formed to be flat. The reason is that even if the fine metal particles of the first optical layer 141 are diffused, the fine metal particles are blocked by the third optical layer 143, so the top surface of the third optical layer 143 is formed to be flat.

[0116] Since the second electrode is formed on the third optical layer 143 instead of being formed on the first optical layer 141 having the rough top surface, damage of the second electrode may be reduced or prevented by the third optical layer 143 .

[0117] Therefore, in exemplary embodiments, the third optical layer 143 is formed on the first optical layer 141 .

[0118] Fig.13 is a view illustrating a method of manufacturing a display device according to a first exemplary embodiment of the present disclosure. FIG. 14A to FIG. 14G It is used to illustrate Fig.13 For convenience, a structure in which two micro light emitting diodes are formed is described as an example, but the embodiment is not necessarily limited thereto and can be applied to various types of structures.

[0119] Reference Fig.13 , Fig.14A and Fig. 14B , the pixel driving circuit 20 may be formed on the substrate 110, and the buffer layer 121 may be formed on the pixel driving circuit 20. The pixel driving circuit 20 may receive a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and output an anode voltage and a cathode voltage of the light emitting element 10 to drive a plurality of pixels. The pixel driving circuit 20 may be placed in the non-display area NA or below the display area AA.

[0120] Subsequently, the connection wirings RT1 and RT2 may be formed on the buffer layer 121, and then the insulating layer 122 may be formed. The connection wirings RT1 and RT2 may be electrically connected to the pixel driving circuit 20 by passing through the buffer layer 121. In order to drive each pixel, the number of the connection wirings RT1 and RT2 and the stacking number of the connection wirings RT1 and RT2 may vary. Therefore, the stacking number of the connection wirings RT1 and RT2 and the insulating layer 122 may be one or more layers.

[0121] The bank pattern 130 may be formed on the insulating layer 122 to select a position to transfer the light emitting element 10. The bank pattern 130 may be made of an organic insulating material (e.g., photosensitive acryl or photosensitive polyimide), but is not limited thereto. In the transfer process of the light emitting element 10, the bank pattern 130 may guide a position to which the light emitting element 10 is to be attached. However, the bank pattern 130 may be omitted.

[0122] An electrode material may be applied on the insulating layer 122 and the bank pattern 130, and then patterned to form a plurality of first electrodes 161 and a contact electrode 163. The first electrode 161 serves as a region where the light emitting element 10 is disposed, and the contact electrode 163 serves as a region electrically connected to the second electrode 170. Subsequently, a passivation layer 133 may be formed on the plurality of first electrodes 161 and the contact electrode 163 and the bank pattern 130 to expose at least a portion of the contact electrode 163 and the plurality of first electrodes 161.

[0123] The solder pattern 162 may be formed on the exposed first electrode 161. The solder pattern 162 may be made of indium (In), tin (Sn), or an alloy thereof, but is not limited thereto. As an example, the solder pattern 162 may be omitted according to design.

[0124] Subsequently, a plurality of light emitting elements 10 may be transferred to the solder pattern 162, respectively (S110). One pixel may include light emitting elements 10 of three colors. The first light emitting element may be a red light emitting element, the second light emitting element may be a green light emitting element, and the third light emitting element may be a blue light emitting element. As an example, one or more (e.g., two) light emitting elements may be installed in each sub-pixel.

[0125] The transfer method is not particularly limited. That is, the light emitting element 10 grown on the semiconductor growth substrate may be primarily transferred to a transfer substrate and then secondarily transferred to a panel substrate, or the light emitting element 10 grown on the semiconductor growth substrate may be directly transferred to a panel substrate.

[0126] Reference Fig.13 and FIG. 14C to FIG. 14E , the first optical layer 141 may be integrally formed on the substrate 110 (S120), and the third optical layer 143 may be formed on the first optical layer 141 (S130), and then patterned to expose the contact electrode 163 and the top surface of the light emitting element 10 (S140). As an example, the upper surface of the first optical layer 141 may be lower than the upper surface of the light emitting element 10, and the lower surface of the third optical layer 143 may be lower than the upper surface of the light emitting element 10, but is not limited thereto.

[0127] For example, the first optical layer 141 may be formed on the substrate 110, and the third optical layer 143 may be formed on the first optical layer 141 (S130), and then the first optical layer 141 and the third optical layer 143 may be cured at a predetermined temperature within a predetermined time. For example, the predetermined time may be set to 60 minutes, and the predetermined temperature may be set to 170° C., but is not necessarily limited thereto.

[0128] Subsequently, some areas of the first optical layer 141 and the third optical layer 143 may be removed by exposure through a mask, but it is not necessary to be limited thereto. As an example, some areas of the first optical layer 141 and the third optical layer 143 may be removed to expose at least a portion of the contact electrode 163, but it is not necessary to be limited thereto. The rest of the first optical layer 141 may be partially removed to have a thickness sufficient to cover the light emitting element 10 and the dike pattern 130. As an example, the rest of the first optical layer 141 may be partially removed to expose the upper surface of the light emitting element 10, but it is not necessary to be limited thereto. Therefore, the first optical layer 141 may cover between a plurality of light emitting elements 10 and a plurality of dike patterns 130. In this case, the top surface of the light emitting element 10 may be exposed to the top of the third optical layer 143.

[0129] The first optical layer 141 may include an organic insulating material in which fine metal oxide particles such as titanium dioxide particles are dispersed. The third optical layer 143 may include an organic insulating material. As an example, the third optical layer 143 may include an organic insulating material that does not contain fine metal oxide particles.

[0130] Reference Fig.13 and Fig.14F , the second electrode 170 may be formed on a plurality of light emitting elements 10 (S150). As an example, the second electrode 170 may be commonly connected to all pixels. As an example, the second electrode 170 may be commonly connected to at least some of the pixels. As an example, the second electrode 170 may be a thin metal electrode that transmits light. As an example, the second electrode 170 may be a transparent electrode material (e.g., indium tin oxide (ITO)), but is not necessarily limited thereto.

[0131] The second electrode 170 may be divided to be disposed in each row by patterning, and the plurality of divided second electrodes 170 may be electrically connected to the contact electrodes 163, respectively.

[0132] Reference Fig.13 and Figure 14G , the second optical layer 142 may be formed to surround the first optical layer 141 ( S160 ). In this process, the second optical layer 142 may cover a portion of the second electrode 170 connected to the contact electrode 163 .

[0133] The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (e.g., siloxane), but are not necessarily limited thereto. For example, the first optical layer 141 may be siloxane including titanium oxide (TiOx), and the second optical layer 142 may be siloxane not including titanium oxide (TiOx).

[0134] Subsequently, a black matrix 190 may be formed on the second electrode 170 and the second optical layer 142 , and a capping layer 180 may be formed on the black matrix 190 .

[0135] Fig.15 2 is a view for explaining a method of manufacturing a display device according to a second exemplary embodiment of the present disclosure. FIG. 16A to FIG. 16G It is used to illustrate Fig.15 A view showing a method of manufacturing a display device.

[0136] Reference Fig.15 , Fig.16A and Fig. 16B , the pixel driving circuit 20 may be formed on the substrate 110, and the buffer layer 121 may be formed on the pixel driving circuit 20. Subsequently, the connection wirings RT1 and RT2 may be formed on the buffer layer 121, and then the insulating layer 122 may be formed. The bank pattern 130 may be formed on the insulating layer 122 to selectively transfer the position of the light emitting element 10. An electrode material may be applied on the insulating layer 122 and the bank pattern 130, and then patterned to form a plurality of first electrodes 161 and contact electrodes 163. The solder pattern 162 may be formed on the first electrode 161.

[0137] Subsequently, a plurality of light emitting elements 10 may be transferred to the solder pattern 162, respectively (S210). One pixel may include light emitting elements 10 of three colors. The first light emitting element may be a red light emitting element, the second light emitting element may be a green light emitting element, and the third light emitting element may be a blue light emitting element. As an example, two or more light emitting elements may be installed in each sub-pixel.

[0138] Reference Fig.15 and FIG. 16C to FIG. 16E , the first optical layer 141 may be integrally formed on the substrate 110 (S220), and the third optical layer 143 may be formed on the first optical layer 141 (S230), and then may be patterned to expose the contact electrode 163 and the top surface of the light emitting element 10 (S240).

[0139] Reference Fig.15 , Fig.16F and Figure 16G, the second optical layer 142 may be formed in the region where the first optical layer 141 and the third optical layer 143 are removed (S250), and may then be patterned to expose at least a portion of the contact electrode 163 (S260).

[0140] Reference Fig.15 and Fig.16H , the second electrode 170 may be formed on the plurality of light emitting elements 10 (S270). The second electrode 170 may be commonly connected to all pixels or at least some of the pixels. As an example, the second electrode 170 may be a thin metal electrode that transmits light. As an example, the second electrode 170 may be a transparent electrode material (e.g., indium tin oxide (ITO)), but is not necessarily limited thereto.

[0141] Subsequently, a black matrix 190 may be formed on the second electrode 170 , and a capping layer 180 may be formed on the black matrix 190 .

[0142] Fig.17 is a view for explaining a method of manufacturing a display device according to a third exemplary embodiment of the present disclosure. FIG. 18A to FIG. 18F It is used to illustrate Fig.17 A view showing a method of manufacturing a display device.

[0143] Reference Fig.17 , Fig.18A and Fig.18B , the pixel driving circuit 20 may be formed on the substrate 110, and the buffer layer 121 may be formed on the pixel driving circuit 20. Subsequently, the connection wirings RT1 and RT2 may be formed on the buffer layer 121, and then the insulating layer 122 may be formed. The bank pattern 130 may be formed on the insulating layer 122 to selectively transfer the position of the light emitting element 10. An electrode material may be applied on the insulating layer 122 and the bank pattern 130, and then patterned to form a plurality of first electrodes 161 and contact electrodes 163. The solder pattern 162 may be formed on the first electrode 161.

[0144] Subsequently, a plurality of light emitting elements 10 may be transferred to the solder pattern 162, respectively (S310). One pixel may include light emitting elements 10 of three colors. The first light emitting element may be a red light emitting element, the second light emitting element may be a green light emitting element, and the third light emitting element may be a blue light emitting element. As an example, two or more light emitting elements may be installed in each sub-pixel.

[0145] Reference Fig.17 and FIG. 18C to FIG. 18F, the first optical layer 141 may be integrally formed on the substrate 110 (S320), and then may be patterned (S330). For example, the first optical layer 141 may be patterned to expose at least a portion of the contact electrode 163 and at least a portion of the passivation layer 133, but is not limited thereto. Then, the organic insulating material 140 may be formed on the patterned first optical layer 141 (S340) and then may be patterned to expose the contact electrode 163 and the top surface of the light emitting element 10, so that as a result of the patterning, the second optical layer 142 and the third optical layer 143 may be separately formed (S350).

[0146] For example, the third optical layer 143 may be formed by removing some areas of the coating in the first area by exposure using a halftone mask, and the second optical layer 142 having the contact hole TH1 may be formed by removing some areas of the coating in the second area by exposure using a fulltone mask, but is not limited thereto.

[0147] Subsequently, the second optical layer 142 and the third optical layer 143 may be cured at a predetermined temperature within a predetermined time. For example, the predetermined time may be set to 60 minutes, and the predetermined temperature may be set to 170° C., but are not necessarily limited thereto.

[0148] Subsequently, a descum process may be performed to remove the residue.

[0149] Reference Fig.17 and Figure 18G , the second electrode 170 may be formed on the plurality of light emitting elements 10 (S360). The second electrode 170 may be commonly connected to all pixels or at least some of the pixels. The third optical layer 143 reduces or prevents diffusion of fine metal particles of the first optical layer 141, thereby making it possible to easily form the second electrode 170.

[0150] Subsequently, a black matrix 190 may be formed on the second electrode 170 , and a capping layer 180 may be formed on the black matrix 190 .

[0151] In an exemplary embodiment, since the second coating layer and the third coating layer are made of the same material, the second coating layer and the third coating layer can be formed in one process and then formed by exposure through different masks. Using this method has the advantage of reducing the manufacturing process and cost of the display device.

[0152] Fig.19 is a diagram showing simulation results of light output efficiency of Examples and Comparative Examples.

[0153] Fig.19The simulation results of the light output efficiency of the exemplary embodiment in which the third coating layer is formed on the first coating layer and the comparative example in which only the first coating layer is formed are shown, and it can be seen that there is almost no difference therebetween.

[0154] In the structure of the exemplary embodiment, when the fine metal particles diffused 0%, the light output efficiency decreased by about 3.7% compared to the comparative example, and when the fine metal particles diffused 50%, the light output efficiency decreased by about 0.4% compared to the comparative example.

[0155] Therefore, there is little difference between the structure of the exemplary embodiment and the structure of the comparative example in terms of light output efficiency, but in the structure of the exemplary embodiment, upward diffusion of fine metal particles is reduced or prevented, thereby making it possible to easily form a common electrode.

[0156] According to the embodiments of the present specification, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notepads, electronic books, portable multimedia players (PMP), personal digital assistants (PDA), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, in-car navigation, vehicle display devices, vehicle devices, cinema devices, cinema display devices, televisions, wallpaper devices, sign devices, gaming devices, laptops, monitors, cameras, video cameras, and home appliances, etc. In addition, the display device according to one or more embodiments of the present disclosure can be applied to organic light emitting lighting devices or inorganic light emitting lighting devices.

[0157] According to one or more embodiments of the present specification, a display device may be described as follows.

[0158] According to an embodiment of the present specification, a display panel may include: a substrate; an insulating layer disposed above the substrate; a dam pattern disposed on the insulating layer; a first electrode disposed on the dam pattern; a contact electrode disposed on the insulating layer and spaced apart from the dam pattern; a light-emitting element disposed above the first electrode; a first optical layer surrounding the light-emitting element and made of an organic insulating material including metal particles; a second optical layer formed above the contact electrode; and a third optical layer formed on the first optical layer.

[0159] The third optical layer may be formed to have a thickness in the range of 1.0 μm to 1.5 μm.

[0160] The third optical layer may be formed such that a top surface is located on the same line as a top surface of the light emitting element or is located below the top surface of the light emitting element.

[0161] The display panel may further include a solder pattern between the first electrode and the light emitting element.

[0162] The second optical layer may include a contact hole for exposing the contact electrode.

[0163] The display panel may further include a second electrode formed on the second optical layer and the third optical layer.

[0164] The second optical layer and the third optical layer may be made of the same organic insulating material excluding metal particles.

[0165] The display panel may further include a buffer layer disposed between the substrate and the insulating layer.

[0166] The optical layer may be formed in the first region where the first optical layer is formed and in the second region where the contact electrode is formed, and the third optical layer may be formed by exposing the optical layer formed in the first region using a half-tone mask.

[0167] The second optical layer may be formed by exposing the optical layer formed in the second region to light using a full-tone mask.

[0168] The display panel may further include a pixel driving circuit disposed on the substrate.

[0169] According to an embodiment of the present specification, a display device may include: a display panel including a plurality of pixels and a pixel driving circuit for driving the plurality of pixels, the display panel may include: a substrate; an insulating layer disposed above the substrate; a dam pattern disposed on the insulating layer; a first electrode disposed on the dam pattern; a contact electrode disposed on the insulating layer and spaced apart from the dam pattern; a light-emitting element disposed above the first electrode; a first optical layer surrounding the light-emitting element and made of an organic insulating material including metal particles; a second optical layer formed above the contact electrode; and a third optical layer formed on the first optical layer.

[0170] The third optical layer may be formed such that a top surface is located on the same line as a top surface of the light emitting element or is located below the top surface of the light emitting element.

[0171] The second optical layer may include a contact hole for exposing the contact electrode.

[0172] The display device may further include a second electrode formed on the second optical layer and the third optical layer.

[0173] The second optical layer and the third optical layer may be made of the same organic insulating material.

[0174] The optical layer may be formed in the first region where the first optical layer is formed and the second region where the contact electrode is formed, and the third optical layer may be formed by exposing the optical layer formed in the first region by using a half-tone mask.

[0175] The second optical layer may be formed by exposing the optical layer formed in the second region by using a full-tone mask.

[0176] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0177] CROSS-REFERENCE TO RELATED APPLICATIONS

[0178] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0093225, filed on Jul. 18, 2023, the disclosure of which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display panel, comprising: substrate; an insulating layer, the insulating layer being disposed above the substrate; a first electrode, the first electrode being disposed above the insulating layer; a light emitting element, wherein the light emitting element is disposed on the first electrode; a first optical layer surrounding the light emitting element and made of an organic insulating material including particles; as well as A third optical layer is formed on the first optical layer and surrounds the light emitting element.

2. The display panel according to claim 1, wherein: The third optical layer is formed to have a thickness in the range of 1.0 μm to 1.5 μm.

3. The display panel according to claim 1, wherein: The third optical layer is formed such that a top surface is located on the same line as a top surface of the light emitting element or is located below a top surface of the light emitting element.

4. The display panel according to claim 1, further comprising: A solder pattern is located between the first electrode and the light emitting element.

5. The display panel according to claim 1, wherein: The third optical layer is made of a material that does not include the particles.

6. The display panel according to claim 1, wherein: The particles in the first optical layer are not diffused to a top surface of the third optical layer.

7. The display panel according to claim 1, wherein: The particles are particles containing a metal element.

8. The display panel according to claim 1, further comprising: A second electrode is located on the light emitting element and the third optical layer.

9. The display panel according to claim 8, further comprising: A second optical layer is disposed on the insulating layer and adjacent to the first optical layer.

10. The display panel according to claim 9, wherein: The second electrode extends from a top surface of the third optical layer to below the second optical layer between the third optical layer and the second optical layer and between the first optical layer and the second optical layer.

11. The display panel according to claim 10, further comprising: a contact electrode disposed on the insulating layer and spaced apart from the first electrode, and wherein the second optical layer covers at least a portion of the contact electrode, and Wherein, the second electrode extends to be connected to the contact electrode below the second optical layer.

12. The display panel according to claim 9, further comprising: a contact electrode disposed on the insulating layer and spaced apart from the first electrode, and The second optical layer covers at least a portion of the contact electrode and includes a contact hole for exposing the contact electrode.

13. The display panel according to claim 12, wherein: The second electrode is also formed on the second optical layer and is connected to the contact electrode through the contact hole.

14. The display panel according to claim 9, wherein: The second optical layer and the third optical layer are made of the same organic insulating material excluding particles.

15. The display panel according to claim 9, wherein: A top surface of the second optical layer is coplanar with a top surface of the second electrode on the third optical layer, or a top surface of the second optical layer is coplanar with a top surface of the third optical layer.

16. The display panel according to claim 11 or 12, further comprising: a pixel driving circuit, wherein the pixel driving circuit is arranged on the substrate below the insulating layer, The second electrode is connected to the pixel driving circuit via the contact electrode, and the first electrode extends below the first optical layer to be connected to the pixel driving circuit by penetrating the insulating layer.

17. The display panel according to claim 9, wherein: The second optical layer is formed by using a full-tone mask while the third optical layer is formed by using a half-tone mask.

18. The display panel according to claim 1, further comprising a dam pattern disposed on the insulating layer and surrounded by the first optical layer, in, The first electrode is disposed on the bank pattern.

19. A display device, comprising: A display panel according to any one of claims 1 to 18.

Images