Compact cross temperature control method based on network-on-chip

Abstract

The invention discloses a compact cross temperature control method based on a network-on-chip, relates to the technical field of multiprocessor embedded development, and designs a staggered phase control strategy to increase the node correction frequency of a minimum network unit in a control period and avoid a thermal problem caused by synchronous temperature control. Designing a negative feedback temperature control strategy to control an interaction behavior between a node and an adjacent node so as to further stabilize the temperature of the node, comparing distribution of node types in the network-on-chip into a graph coloring problem based on a control phase distribution algorithm, setting pruning constraints and selection constraints to optimize a backtracking method, and rapidly generating an optimal type distribution scheme; the optimal cross temperature control of the network-on-chip is realized by combining a staggered phase control strategy and a negative feedback temperature control strategy, a performance evaluation scheme is designed, and the evaluation indexes of the method provided by the invention are superior to those of a comparison scheme through inspection, so that the thermal problem of the network-on-chip is effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-processor embedded development, and in particular to a compact cross temperature control method based on network on chip. Background Art

[0002] As a communication infrastructure, on-chip networks are widely used in multi-processor systems, providing a scalable, high-bandwidth solution for communication between multiple processing units. However, with the increase in application complexity and the improvement of semiconductor process technology, the number of processing units integrated in multi-processor systems continues to increase. The increased power density and traffic load have brought thermal problems such as hot spots, thermal gradients, and thermal cycles to the on-chip network. Thermal problems can increase system transmission delays and leakage power consumption, affect system performance, and reduce system reliability. Therefore, solving thermal problems is crucial for on-chip networks.

[0003] There are a large number of thermal management technologies currently available, among which the distributed dynamic thermal management method is the most widely used. The distributed dynamic thermal management method embeds a controller in each node of the on-chip network to control the temperature of the node, and starts a specific temperature control method based on demand. For example, the existing Chinese patent application with publication number CN115729276A proposes a temperature control method, device, equipment and storage medium for a system on chip, obtains the attribute information of the system on chip to generate a temperature control sequence, determines the target temperature range based on the current temperature of each node in the system on chip to obtain a reference time and a corresponding reference temperature, determines the temperature change trend of the system on chip, selects the target sequence element corresponding to the change trend in the temperature control sequence, and uniformly controls the temperature of each node of the system on chip according to the target sequence element, thereby realizing efficient and accurate temperature control of the system on chip without affecting the performance of the system on chip.

[0004] The node management strategies involved in existing distributed dynamic thermal management methods are activated synchronously. The synchronous control of nodes will also increase the network burden and cause reliability risks related to system oscillation and thermal cycling. In addition, overly complex temperature prediction methods and control strategies will add additional thermal overhead to systems that already face thermal problems. Summary of the invention

[0005] The purpose of the present invention is to provide a compact cross-temperature control method based on on-chip network, which realizes negative feedback temperature control of nodes by staggering the control phases of adjacent nodes, alleviates the thermal problems caused by synchronous temperature control, and designs an optimal control phase allocation algorithm to improve the performance and scalability of on-chip network.

[0006] The technical solution to achieve the purpose of the present invention is:

[0007] A compact cross temperature control method based on an on-chip network includes the following specific steps:

[0008] Design an interleaved phase control strategy to increase the number of node corrections of the smallest network unit within the control period Δt;

[0009] Design a negative feedback temperature control strategy to control the interaction between nodes and neighboring nodes;

[0010] Obtaining the optimal type allocation scheme of the on-chip network based on the control phase allocation algorithm to achieve the best cross-temperature control of the on-chip network;

[0011] A performance evaluation scheme is designed to verify the performance of the compact cross-connect temperature control method based on on-chip network.

[0012] Furthermore, designing the staggered phase control strategy includes the following specific steps:

[0013] Get the control period Δt of the on-chip network and define the type Type to represent the control phase Phase of a single node;

[0014] Determine the number of types N that satisfy the dual constraints;

[0015] A phase-type relationship function f(·) is established to characterize the single-value mapping relationship between the control phase Phase and the type Type. The phase-type relationship function f(·) is as follows:

[0016]

[0017] Among them, Type n Indicates the nth type, Type n =n-1, Phase n Indicates the control phase corresponding to the nth type, n = 1, ..., N;

[0018] All nodes in the smallest network unit are randomly assigned different types.

[0019] Specifically, the number of types is limited by dual constraints, which are generally set to the total number of nodes in the minimum network unit. The dual constraints include:

[0020] The number of types N should be greater than or equal to the total number of nodes in the minimum network unit, so that all nodes in the minimum network unit can be assigned different types. For a mesh-type on-chip network, the minimum network unit contains 5 nodes, N ≥ 5;

[0021] The number of types N should be minimized to avoid affecting the normal operation of the complete on-chip network.

[0022] Furthermore, the negative feedback temperature control strategy determines the tendency of adjacent nodes based on the state of a single node, thereby forming a negative feedback loop to regulate the temperature of a single node. When the state of a single node is not current-limited, the adjacent nodes tend to start the current-limiting state to avoid a sharp rise in the temperature of the single node. When the state of a single node is current-limited, the adjacent nodes tend to turn off the current-limiting state to avoid a sharp drop in the temperature of the single node. A single node is also an adjacent node of other nodes. The negative feedback temperature control strategy can be regarded as a continuous interaction between two adjacent nodes.

[0023] Furthermore, the control phase allocation algorithm includes the following specific steps:

[0024] Analogous to the graph coloring problem, an undirected graph G is constructed based on whether there is an adjacency relationship between each node;

[0025] Define a color set S whose number of colors is equal to the number of types N, and establish a mapping c:V→S between colors and nodes;

[0026] Set pruning constraints to require that the colors of two adjacent nodes cannot be the same;

[0027] The backtracking structure is selected as a tree structure, and the backtracking method is used to assign types to the on-chip network nodes to generate the optimal type assignment scheme.

[0028] Specifically, the graph coloring problem stipulates that any two adjacent vertices in a graph must have different colors. By abstracting the nodes and types of the on-chip network into vertices and colors, maximizing the type diversity of each node and adjacent nodes in the on-chip network can be analogized to the graph coloring problem.

[0029] Furthermore, constructing an undirected graph includes the following specific steps:

[0030] Get the total number of nodes M, and regard the M nodes as nodes of the undirected graph G to form a node set V;

[0031] Define the edge to represent the adjacency relationship between nodes. If two nodes are adjacent, there is an edge belonging to the edge set E between the two nodes, and there is no edge between the nodes themselves.

[0032] Construct an adjacency matrix A to actually represent the undirected graph G. If the i-th node v i and the jth node v j There is an edge e ij , then the i-th row and j-th column A(i,j) and the j-th row and i-th column A(j,i) of the adjacency matrix A are set to 1, otherwise they are set to 0, and the diagonal elements of the adjacency matrix A are 0.

[0033] Furthermore, the generation of the optimal type allocation scheme using the backtracking method includes the following steps;

[0034] Set the solution space to the color set S, set a hierarchical solution space tree, and select the root node;

[0035] Execute the assignment of feasible solutions, select a feasible solution for the root node in sequence from the solution space, and perform the selection of extended nodes, and select an adjacent node that is adjacent to the root node and has not been selected in sequence based on the adjacency matrix A as the extended node;

[0036] Going deep into the next layer of the hierarchical solution space tree, perform adjacency solution screening, and based on the adjacency matrix A, screen out all adjacent nodes that are adjacent to the extended node and have existing solutions as the pruning basis nodes of the extended node;

[0037] Sub-solution space generation is performed based on pruning constraints, all solutions assigned to pruning nodes are excluded from the solution space, and the sub-solution space of the expanded node is generated;

[0038] Execute the no-solution judgment to determine whether the expanded node is a feasible node. If it is not a feasible node, go back to the node of the previous layer and continue to execute the no-solution judgment;

[0039] Until backtracking to a feasible node, perform feasible solution assignment, and reselect feasible solutions for the feasible node in sequence from the solution space or sub-solution space of the feasible node;

[0040] If it is a feasible node, perform the feasible solution assignment and select a feasible solution from the sub-solution space of the feasible node in sequence;

[0041] The extended node selection, adjacent solution screening, sub-solution space generation, no-solution judgment and feasible solution assignment are repeated to continuously go deeper into the next layer until all nodes of the on-chip network are assigned solutions, the backtracking method stops, and the optimal type allocation solution is generated.

[0042] Furthermore, the optimal type allocation scheme generated by backtracking can be further optimized by setting selection constraints, which include:

[0043] Root node selection constraints: the root node is generally selected as the node located at the upper left corner of the on-chip network and at the edge;

[0044] The selection constraint of the extended node means that there is a directional priority in the selection of the extended node. The directional priority follows the rule that if there is a right node, choose the right node; if there is no right node, choose the left node; if there is no right node, choose the left node directly;

[0045] The solution selection constraint means that the root node should be assigned the first type, and the solution selection in the horizontal direction should be cyclically extended in the pattern of {0, 1, 2, 3, 4}, and in the vertical direction in the pattern of {0, 2, 4, 1, 3}.

[0046] Furthermore, the design performance evaluation scheme includes the following specific steps:

[0047] Building an 8×8 on-chip network in the Accesss Noxim simulation platform;

[0048] Get the traffic trace file from the Gem5 simulator and convert it into a format compatible with the Accesss Noxim simulation platform;

[0049] Set the current limiting critical temperature and define the evaluation indicators, including throughput, maximum temperature, time variance, and space variance;

[0050] A comparative scheme is selected, and a random traffic pattern and an increasing packet injection rate are designed to test the compact cross-type temperature control method based on on-chip network proposed in the present invention and the comparative scheme.

[0051] Furthermore, the test results show that the throughput of the compact cross-temperature control method based on on-chip network proposed in the present invention is higher than that of the comparative scheme, and it can more effectively reduce the maximum temperature than the comparative scheme, while achieving a stable and smooth control effect in time and space.

[0052] Compared with the prior art, the present invention has the following significant advantages:

[0053] 1. Design an interleaved phase control strategy to determine the control phase by assigning different types to all nodes in the smallest network unit, avoiding thermal problems caused by synchronous control and increasing the number of corrections within the control cycle;

[0054] 2. Design a negative feedback temperature control strategy based on the continuous interaction between two adjacent nodes to generate a negative feedback loop to stabilize the temperature of the two adjacent nodes, further assisting in solving the thermal problem;

[0055] 3. Design a control phase allocation algorithm by establishing an undirected graph to analogize the graph coloring problem, obtain the optimal type allocation solution based on the backtracking method, and set pruning constraints and selection constraints to reduce the complexity of the backtracking method. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 The flowchart is a compact cross temperature control method based on on-chip network;

[0057] Figure 2 It is a schematic diagram of the on-chip network control strategy;

[0058] Figure 3 This is a schematic diagram of the negative feedback temperature control strategy of the present invention;

[0059] Figure 4 It is a flow chart of the backtracking method of the present invention;

[0060] Figure 5 The present invention controls the phase allocation algorithm to generate an optimal type allocation scheme schematic diagram for a specific on-chip network. DETAILED DESCRIPTION

[0061] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0062] like Figure 1 As shown, the embodiment provided by the present invention: a compact cross temperature control method based on an on-chip network includes the following specific steps:

[0063] Design an interleaved phase control strategy to increase the number of node corrections of the smallest network unit within the control period Δt;

[0064] Design a negative feedback temperature control strategy to control the interaction between nodes and neighboring nodes;

[0065] A control phase allocation algorithm is designed, and the node type allocation of the on-chip network is analogized to a graph coloring problem. The optimal type allocation scheme of all nodes in the on-chip network is obtained based on the backtracking method, and the interleaved control strategy and negative feedback temperature control strategy are applied to achieve the optimal cross-temperature control of the on-chip network.

[0066] A performance evaluation scheme is designed to verify the performance of the compact cross-connect temperature control method based on on-chip network.

[0067] Furthermore, designing the staggered phase control strategy includes the following specific steps:

[0068] Get the control period Δt of the on-chip network, define the type Type to represent the control phase Phase of a single node, and nodes with the same control phase belong to the same type;

[0069] Determine the number of types N that satisfy the dual constraints;

[0070] A phase-type relationship function f(·) is established to characterize the single-value mapping relationship between the control phase Phase and the type Type. The phase-type relationship function f(·) is as follows:

[0071]

[0072] Among them, Type n Indicates the nth type, Type n =n-1, Phase n Indicates the control phase corresponding to the nth type, n = 1, ..., N;

[0073] Different types are randomly assigned to all nodes of the minimum network unit, where the minimum network unit is a single node with the largest number of adjacent nodes in the on-chip network and a sub-on-chip network consisting of all adjacent nodes. Since the on-chip network is a grid type, a single node has at most adjacent nodes in four directions: up, down, left, and right. The minimum network unit is a sub-on-chip network consisting of a single node and four adjacent nodes.

[0074] Specifically, the number of types N is subject to dual constraints, and is generally set to the total number of nodes of the minimum network unit, that is, N=5. The dual constraints include:

[0075] The number of types N should be greater than or equal to the total number of nodes in the smallest network unit. Since the traditional distributed dynamic thermal management synchronously refreshes the control strategy of all nodes, each node will be affected by the control decision of the adjacent nodes. The node and all adjacent nodes should be assigned different types to avoid the thermal impact caused by synchronous temperature control. Therefore, the number of types must at least exceed the total number of nodes in the smallest network unit, that is, N≥5;

[0076] The number of types N should be reduced as much as possible, because when the staggered phase control strategy of the minimum network unit is subsequently extended to the entire on-chip network, too many types N will make the correction within the control cycle Δt too frequent, affecting the normal operation of the on-chip network.

[0077] like Figure 2 As shown, Figure 2 (a) is a schematic diagram of the traditional synchronization control strategy. The traditional synchronization control strategy will correct all nodes of the minimum network unit once within the node control cycle Δt. Figure 2 (b) is a schematic diagram of the staggered phase control strategy of the present invention, which allocates different types to the node and the four adjacent nodes in the minimum network unit, so as to perform a total of 5 corrections in different control phases within the control period Δt.

[0078] like Figure 3 As shown, further, the negative feedback temperature control strategy determines the tendency of adjacent nodes based on the state of a single node, and forms a negative feedback loop between a single node and adjacent nodes to regulate the temperature of the node. Specifically, when a single node is in an unrestricted state, under a high traffic load, the single node will self-generate heat and send a large number of data packets to adjacent nodes, while transferring heat to adjacent nodes. At this time, the adjacent nodes tend to start the current limiting state to reduce the self-generated heat and the data packets flowing to the single node, forming a negative feedback loop to ensure that the temperature of the single node does not rise sharply. Similarly, when the state of a single node is current limiting, the adjacent nodes tend to turn off the current limiting state to ensure that the temperature of the single node does not drop sharply.

[0079] Furthermore, the definition of adjacent nodes is relative. Each node in the on-chip network is also an adjacent node of other nodes. Therefore, the negative feedback loop formed by the negative feedback temperature control strategy can be regarded as a continuous interaction between two adjacent nodes.

[0080] Furthermore, the control phase allocation algorithm includes the following specific steps:

[0081] Analogously to the graph coloring problem, each node of the on-chip network is constructed into an undirected graph G = (V, E) based on whether there is an adjacency relationship, where V represents the node set and E represents the edge set;

[0082] Define the color set S = {s 1 ,s 2 ,…,s N}, the number of colors in the color set is equal to the number of types N, and a mapping c:V→S is established between colors and nodes, where the nth color s n With the nth type Type n correspond;

[0083] Set pruning constraints, specifically when the i-th node v i and the jth node v j There is an edge e ij ∈E, it is necessary to satisfy c(v i )≠c(v j ), that is, when the i-th node v i and the jth node v j When adjacent, node v i and node v j The colors cannot be the same;

[0084] The backtracking structure is selected as a tree structure, and the backtracking method is used to assign types to all nodes of the on-chip network to generate the optimal type assignment scheme. The interleaved control strategy and negative feedback temperature control strategy are applied to achieve the optimal cross temperature control of the on-chip network.

[0085] Specifically, the graph coloring problem stipulates that any two adjacent vertices in a graph must have different colors. Under the premise that the number of types N is determined, the on-chip network needs to maximize the type diversity of each node and adjacent nodes, so that each node will be corrected based on the negative feedback temperature control strategy a sufficient number of times within the control period Δt. The nodes of the on-chip network are abstracted as vertices, and the types are abstracted as colors, which can be compared to the graph coloring problem.

[0086] Furthermore, constructing an undirected graph G = (V, E) includes the following specific steps:

[0087] Obtain a total number of nodes M of the on-chip network, and regard the M nodes of the on-chip network as nodes of an undirected graph G to form a node set V of the undirected graph G;

[0088] Define the edge to represent the adjacency relationship between nodes. Specifically, if the i-th node v i and the jth node v j In the on-chip network, the i-th node v i and the jth node v j There is an edge e ij∈E, where E is the edge set;

[0089] Construct an adjacency matrix A to actually represent the undirected graph G. Specifically, the adjacency matrix A is a symmetric matrix of dimension M×M. If the i-th node v in the undirected graph G i and the jth node v j There is an edge e ij , then the i-th row and j-th column A(i,j) and the j-th row and i-th column A(j,i) of the adjacency matrix A are set to 1, otherwise they are set to 0. It is worth noting that due to the potential rule in the definition of the edge, that is, there is no edge between a node and itself, the diagonal elements of the adjacency matrix A must be 0.

[0090] like Figure 4 As shown, further, using the backtracking method to generate the optimal type allocation scheme includes the following steps:

[0091] Set the solution space to the color set S = {s 1 ,s 2 ,…,s N}, set a hierarchical solution space tree, select any node in the on-chip network as the root node of the hierarchical solution space tree, and define the root node to be located at the first level of the hierarchical solution space tree;

[0092] Execute the assignment of feasible solutions, select a feasible solution for the root node from the solution space in sequence. A feasible solution refers to a solution that has not been selected in the solution space or sub-solution space. The solution is the color assigned to the color set S. Execute the selection of extended nodes, and select an adjacent node that is adjacent to the root node and has not been selected in sequence based on the adjacency matrix A as the extended node;

[0093] Going deep into the next layer of the hierarchical solution space tree, perform adjacency solution screening, and based on the adjacency matrix A, screen out all adjacent nodes that are adjacent to the extended node and have existing solutions as the pruning basis nodes of the extended node;

[0094] Sub-solution space generation is performed based on pruning constraints, all solutions assigned to pruning nodes are excluded from the solution space, and the sub-solution space of the expanded node is generated;

[0095] Execute the no-solution judgment to determine whether the extended node is a feasible node. A feasible node refers to a root node or an extended node whose solution space or sub-solution space is not empty and has a feasible solution. If it is not a feasible node, go back to the node of the previous layer and continue to execute the no-solution judgment;

[0096] Until backtracking to a feasible node, the feasible node may be a root node or an extended node, and the feasible solution assignment is performed, and a feasible solution is re-selected for the feasible node in sequence from the solution space or sub-solution space of the feasible node;

[0097] If it is a feasible node, perform the feasible solution assignment and select a feasible solution from the sub-solution space of the feasible node in sequence;

[0098] The extended node selection, adjacent solution screening, sub-solution space generation, no-solution judgment and feasible solution assignment are repeatedly performed to continuously go deeper into the next layer until all M nodes of the on-chip network are assigned solutions, the backtracking method stops, and the optimal type allocation solution is generated.

[0099] Furthermore, the optimal type allocation scheme generated by the backtracking method can be further optimized to reduce the complexity. Since the number of types N is generally equal to the total number of a single node and all adjacent nodes, selection constraints can be set for the specific network structure of the on-chip network to reduce the complexity of the backtracking method to allocate types to nodes. The selection constraints include:

[0100] The root node selection constraint specifically refers to that the root node is generally selected as the node located at the upper left corner and the most edge of the on-chip network, that is, the node located at the upper left corner vertex of the grid-type on-chip network;

[0101] Extension node selection constraint, specifically refers to the directional priority of the extension node selection. For the mesh-type on-chip network, the directional priority follows the rule that if there is an unselected adjacent node on the right side of the node in the previous layer, the current extension node will prioritize the right side. If there is no unselected adjacent node on the right side, the left side will be prioritized. If there is no unselected adjacent node on both the left and right sides, the adjacent node below will be further selected.

[0102] Solution selection constraint, specifically in the mesh-type on-chip network, the number of types N = 5, the root node should be assigned the first type Type 1 =0, the solution selection in the horizontal axis direction should be cyclically extended in the mode {0, 1, 2, 3, 4}, and the solution selection in the vertical axis direction should be cyclically extended in the mode {0, 2, 4, 1, 3}.

[0103] like Figure 5 As shown, Figure 5 (a) is a specific schematic diagram of a 4×4 on-chip network. Figure 5 (b) is an undirected graph G constructed based on the node adjacency relationship in the 4×4 on-chip network. Figure 5 (c) is the optimal type allocation scheme. The optimal type allocation scheme meets the selection constraints. Based on the existence of the solution selection constraints, when the on-chip network expands in scale, the newly added nodes can be easily assigned the best type.

[0104] Furthermore, the design performance evaluation scheme includes the following specific steps:

[0105] Building an 8×8 on-chip network in the Accesss Noxim simulation platform;

[0106] Get the traffic trace file from the Gem5 simulator and convert it into a format compatible with the Accesss Noxim simulation platform;

[0107] Set the current limiting critical temperature to 93°C and define the evaluation indicators, including throughput, maximum temperature, time variance and spatial variance. The time variance is the mean of the variance of temperature changes at different nodes in the on-chip network, and the spatial variance is the mean of the temperature differences between nodes in the on-chip network at different times.

[0108] The most advanced active thermal management method based on artificial neural network predictor and reactive dynamic thermal management method are used as comparison schemes;

[0109] A random traffic pattern and an increasing packet injection rate are designed to test the compact cross-type temperature control method based on on-chip network proposed in the present invention and the comparative scheme.

[0110] Furthermore, the test results show that the throughput of the compact cross-temperature control method based on on-chip network proposed in the present invention is respectively improved by an average of 35.85% and 42.46% over the two comparative schemes. For the three indicators of maximum temperature, time variance and spatial variance, the compact cross-temperature control method based on on-chip network proposed in the present invention performs best and can effectively reduce the maximum temperature while achieving stable and smooth control effects in time and space.

[0111] The present invention discloses a compact cross-temperature control method based on an on-chip network, designs an interlaced phase control strategy to increase the number of node corrections of the minimum network unit within a control cycle, avoids thermal problems caused by synchronous temperature control, designs a negative feedback temperature control strategy to control the interaction between nodes and adjacent nodes, further stabilizes the temperature of the nodes, quickly generates an optimal type allocation scheme based on a control phase allocation algorithm, realizes optimal cross-temperature control of the on-chip network, and designs an effective performance evaluation scheme to test the performance to prove the effectiveness of the compact cross-temperature control method based on the on-chip network.

[0112] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A compact cross-temperature control method based on on-chip network, characterized in that: The specific steps include: Design an interleaved phase control strategy to increase the number of node corrections of the smallest network unit within the control cycle; Design a negative feedback temperature control strategy to control the interaction between nodes and neighboring nodes; Obtain the optimal type allocation scheme of the on-chip network based on the control phase allocation algorithm to achieve optimal cross-temperature control; Design a performance evaluation scheme to verify performance.

2. A compact cross-connect temperature control method based on an on-chip network as claimed in claim 1, characterized in that: The design of the staggered phase control strategy includes the following specific steps: Get the control period and define the type to represent the control phase of a single node; Determine the number of types that satisfy the dual constraints; A phase-type relationship function is established to characterize a single-value mapping relationship between control phase and type; Randomly assign different types to nodes in the smallest network unit.

3. A compact cross-connect temperature control method based on an on-chip network as claimed in claim 2, characterized in that: The dual constraints include: The number of types should be greater than or equal to the total number of nodes in the smallest network unit, so that all nodes in the smallest network unit can be assigned different types; The number of types should be minimized to avoid affecting the normal operation of the on-chip network.

4. A compact cross-connect temperature control method based on an on-chip network as claimed in claim 1, characterized in that: The control phase allocation algorithm comprises the following specific steps: Analogous to the graph coloring problem, an undirected graph is constructed based on whether there is an adjacency relationship between each node; Define a color set whose number of colors is equal to the number of types, and establish a mapping between colors and nodes; Set pruning constraints to require that the colors of two adjacent nodes cannot be the same; The node type is assigned by using the backtracking method with a tree structure to generate the optimal type assignment scheme.

5. A compact cross temperature control method based on on-chip network as claimed in claim 4, characterized in that: The construction of the undirected graph comprises the following specific steps: Get the total number of nodes, treat all nodes as nodes of an undirected graph, and form a node set; The definition of edge represents the adjacency relationship between nodes. If two nodes are adjacent, there is an edge between the two nodes, and there is no edge between a node and itself; An adjacency matrix is ​​constructed to actually represent the undirected graph. If there is an edge between two nodes, the corresponding position of the adjacency matrix is ​​set to 1, otherwise it is set to 0, and the diagonal elements of the adjacency matrix are 0.

6. A compact cross temperature control method based on on-chip network as claimed in claim 4, characterized in that: The method of using the backtracking method to generate the optimal type allocation scheme comprises the following steps: Set the solution space to a color set, set a hierarchical solution space tree, and select the root node; Execute the assignment of feasible solutions, select a feasible solution for the root node in order from the solution space, execute the selection of extended nodes, and select an adjacent node that is adjacent to the root node and has not been selected as the extended node; Going down to the next layer, perform adjacent solution screening, and filter out all adjacent nodes that are adjacent to the expanded node and have existing solutions as pruning basis nodes; Execute sub-solution space generation, exclude all solutions assigned to the pruning nodes from the solution space, and generate the sub-solution space of the expanded node; Execute the no-solution judgment to determine whether the expanded node is a feasible node. If it is not a feasible node, go back to the node of the previous layer and continue to execute the no-solution judgment; Until backtracking to a feasible node, perform feasible solution assignment, and re-select feasible solutions in order from the solution space or sub-solution space of the feasible node; If it is a feasible node, perform the feasible solution assignment and select a feasible solution from the sub-solution space of the feasible node in sequence; The expansion node selection, adjacent solution screening, sub-solution space generation, no-solution determination and feasible solution assignment are repeated to continuously go deeper into the next layer until all nodes are assigned solutions and the backtracking method stops.

7. A compact cross temperature control method based on on-chip network as claimed in claim 6, characterized in that: The backtracking method to generate the optimal type allocation solution can be further optimized by setting selection constraints, and the selection constraints include: Root node selection constraints: the root node is generally selected as the node located at the upper left corner of the on-chip network and at the edge; Extension node selection constraint means that the selection of extension nodes has a certain direction priority; The solution selection constraint means that the root node should be assigned the first type, and the solution selection in the horizontal and vertical directions follows different patterns for cyclic extension.

8. A compact cross-connect temperature control method based on an on-chip network as described in any one of claims 4 to 7, characterized in that: The graph coloring problem stipulates that any two adjacent vertices in a graph must have different colors. By abstracting the nodes and types of the on-chip network into vertices and colors, maximizing the type diversity of each node and adjacent nodes in the on-chip network can be analogized to the graph coloring problem.

9. A compact cross-connect temperature control method based on an on-chip network as claimed in claim 1, characterized in that: The negative feedback temperature control strategy determines the tendency of adjacent nodes based on the state of a single node, thereby forming a negative feedback loop to adjust the temperature of a single node. The negative feedback temperature control strategy can be regarded as a continuous interaction between two adjacent nodes.

10. A compact cross temperature control method based on on-chip network as claimed in claim 1, characterized in that: The design performance evaluation scheme includes the following specific steps: Building an on-chip network in the Accesss Noxim simulation platform; Get the traffic trace file from the Gem5 simulator and convert it into a format compatible with the Accesss Noxim simulation platform; Set the current limiting critical temperature, define the evaluation index and select the comparison scheme; A random traffic pattern and an increasing packet injection rate are designed to test the compact cross-type temperature control method based on on-chip network proposed in the present invention and the comparative scheme.

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