Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. While the influence of voltage noise is suppressed, the adjustment range of the power supply voltage generated based on the reference voltage is expanded. The semiconductor device includes a reference voltage generation circuit, a regulator, a buffer, and a voltage control circuit. The reference voltage generation circuit is configured to be able to adjust the reference voltage. The regulator is configured to be capable of changing an output ratio of the supply voltage to the reference voltage based on the control signal. The semiconductor device also includes a voltage control circuit to output a voltage control signal to the regulator to switch the output ratio.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-120811 filed on July 25, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2004-319034

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2007-193933

[0007] A power supply circuit mounted on a microcontroller unit (MCU) generates a power supply voltage VDD based on a reference voltage after a power-on reset is released. Patent Documents 1 and 2 disclose a technique for fine-tuning a power supply voltage by fine-tuning a reference voltage. Summary of the invention

[0008] It is desirable to expand the adjustment range of a power supply voltage generated based on a reference voltage while suppressing the influence of voltage noise.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] A semiconductor device according to an embodiment includes a reference voltage generating circuit that generates a reference voltage, a regulator that generates a power supply voltage based on the reference voltage, and a buffer that sends the reference voltage from the reference voltage generating circuit to the regulator. The reference voltage generating circuit is configured to be able to adjust the reference voltage. The regulator is configured to be able to change the output ratio of the power supply voltage to the reference voltage. The semiconductor device also includes a voltage control circuit that outputs a voltage control signal to the regulator to switch the output ratio.

[0011] According to one embodiment, the adjustment range of a power supply voltage generated based on a reference voltage can be expanded while suppressing the influence of voltage noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram explaining the configuration of a semiconductor device related to a comparative example.

[0013] Figure 2 is a diagram explaining the relationship between the power supply voltage and the voltage guarantee signal in the comparative example.

[0014] Figure 3 is a diagram explaining the fluctuation range of the power supply voltage and the voltage detection value in the comparative example.

[0015] Figure 4 : are diagrams for explaining the operation of a semiconductor device related to a comparative example.

[0016] Figure 5 is a diagram for explaining a problem of a semiconductor device related to a comparative example.

[0017] Figure 6 is a diagram for explaining a problem of a semiconductor device related to a comparative example.

[0018] Figure 7 is a diagram explaining the configuration of a semiconductor device related to a study example.

[0019] Figure 8 is a diagram explaining a problem of a semiconductor device related to a research example.

[0020] Fig. 9 is a diagram for explaining the configuration of a semiconductor device related to the first embodiment.

[0021] Fig.10 1 is a diagram showing voltage noise in the semiconductor device according to the first embodiment.

[0022] Fig.11 1 is a diagram for explaining the operation of the regulator related to the first embodiment.

[0023] Fig.12 : is a diagram explaining the fluctuation range of the power supply voltage and the voltage detection value in the first embodiment.

[0024] Fig.13 are diagrams for explaining the operation of the semiconductor device associated with the first embodiment.

[0025] Fig.14 1 is a diagram for explaining the configuration of a semiconductor device related to Embodiment 1 of the first embodiment.

[0026] Fig.15 2 is a diagram for explaining the configuration of a semiconductor device related to Embodiment 2 of the first embodiment. DETAILED DESCRIPTION

[0027] For the purpose of explanation, the following description and drawings are appropriately omitted and simplified. Each element described in the drawings as a functional block that performs various processing can be configured in hardware by a CPU, a memory, and other circuits, and can be implemented in software by a program loaded into the memory, etc. Therefore, it can be understood by those skilled in the art that these functional blocks can be implemented in various forms by hardware, software operating on hardware, or a combination thereof, and are not limited to any one. In the drawings, the same elements are represented by the same reference numerals, and their repeated descriptions are omitted when necessary.

[0028] The program described above includes a set of instructions (or software code), which, when loaded into a computer, is used to make the computer perform one or more functions described in the embodiment. The program can be stored in a non-temporary computer-readable medium or a tangible storage medium. Non-limiting examples of computer-readable media or tangible storage media include random access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other storage technology, CD-ROM, digital versatile disk (DVD), Blu-ray (registered trademark) disk or other optical disk storage, cassette, tape, disk storage or other magnetic storage device. The program can be transmitted on a temporary computer-readable medium or communication medium. Non-limiting examples of temporary computer-readable media or communication media include electrical, optical, acoustic or other forms of propagation signals.

[0029] (Considerations leading to embodiments)

[0030] Figure 1 1 is a diagram showing a configuration of a semiconductor device 100 according to a comparative example. The semiconductor device 100 includes a reset generation circuit 110, a reference voltage generation circuit 120, a buffer 130, a regulator 140, a voltage detection circuit 150, an oscillator 160, and a trimming circuit 170. The reset generation circuit 110 outputs a power-on reset to the trimming circuit 170 and the like.

[0031] The reference voltage generating circuit is a circuit that generates a reference voltage VREF, and is configured to be able to adjust the reference voltage VREF. The reference voltage generating circuit 120 includes a BGR (bandgap reference) 121, an operational amplifier 122, a p-type FET (field effect transistor) 123, a series ladder resistor 124, and a selector 125. The BGR 121 generates a BGR voltage VBGR. The BGR voltage VBGR is input to the negative input terminal of the operational amplifier 122. The output terminal of the operational amplifier 122 is connected to the gate terminal of the FET 123. The source terminal of the FET 123 is connected to a power line that supplies a power supply voltage VCC, and the drain terminal of the FET 123 is connected to the ground via the ladder resistor 124. The power supply voltage VCC is also called a main power supply. The power supply voltage VDD to be described later is also called a secondary power supply. The selector 125 selects a node from a plurality of nodes on the ladder resistor 124 based on a fine-tuning code to be described later, and inputs the voltage of the selected one connection node (referred to as a feedback loop voltage VFB1) to the positive input terminal of the operational amplifier 122. A voltage of a predetermined node included in a plurality of nodes on the ladder resistor 124 (referred to as a voltage detection value HDET) is supplied to the voltage detection circuit 150. The reference voltage generation circuit 120 outputs a voltage of a node between the FET 123 and the ladder resistor 124 as a reference voltage VREF.

[0032] The buffer 130 transmits the reference voltage VREF generated by the reference voltage generating circuit 120 to the regulator 140. The characteristics of the elements included in the buffer 130 are fine-tuned based on the fine-tuning code. The buffer 130 may be, for example, a voltage follower circuit including an operational amplifier.

[0033] The regulator 140 includes an operational amplifier 141, a p-type FET 142, a resistor R0, and a resistor R1. The negative input terminal of the operational amplifier 141 is connected to the output terminal of the buffer 130. The output terminal of the operational amplifier 141 is connected to the gate terminal of the FET 142. The source terminal of the FET 142 is connected to a power line supplying a power supply voltage VCC. The drain terminal of the FET 142 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R0. The other end of the resistor R0 is connected to the ground. The voltage at the node between the resistors R0 and R1 is input to the positive input terminal of the operational amplifier 141. The regulator 140 outputs the voltage at the node between the FET 142 and the resistor R1 as the power supply voltage VDD. The power supply voltage VDD is also referred to as a secondary power supply. The power supply voltage VDD is supplied to the non-volatile memory block 172 to be described later, and the power supply voltage VCC is supplied to other circuits.

[0034] The voltage detection circuit 150 includes a circuit for detecting when the power supply voltage VDD exceeds the voltage detection value HDET, and a circuit for detecting when the power supply voltage VDD exceeds the voltage detection value LDET. Like the voltage detection value HDET, the voltage detection value LDET can be supplied from the reference voltage generation circuit 120. The voltage detection value LDET is lower than the voltage detection value HDET. When the power supply voltage VDD exceeds the voltage detection value HDET, the voltage detection circuit 150 outputs a voltage guarantee signal to the fine-tuning circuit 170.

[0035] Figure 2 1 is a diagram explaining the relationship between the power supply voltage VDD and the voltage guarantee signal. In the top curve graph, the power supply voltage VDD is shown by a solid line, the voltage detection value HDET is shown by a dotted line, and the voltage detection value LDET is shown by a dotted line. The voltage detection value HDET is also referred to as a first threshold, and the voltage detection value LDET is also referred to as a second threshold. At power-on, when the power supply voltage VDD exceeds the voltage detection value HDET, the voltage guarantee signal (L level) is output. During normal operation, the output of the voltage guarantee signal continues as long as the power supply voltage VDD exceeds the voltage detection value LDET. When the voltage detection circuit 150 detects that the power supply voltage VDD has fallen below the voltage detection value LDET, it terminates the output of the voltage guarantee signal. The output operation of the voltage guarantee signal has a hysteresis phenomenon, which provides a margin to prevent the power supply voltage VDD from dropping.

[0036] refer to Figure 1 , the oscillator 160 generates a clock signal based on the reference voltage VREF. The fine-tuning circuit 170 includes a fine-tuning control circuit 171, a non-volatile memory block 172, and a fine-tuning code supply circuit 173. When the fine-tuning control circuit 171 receives a power-on reset, it performs a reset operation. When the fine-tuning control circuit 171 receives a voltage guarantee signal, it outputs a fine-tuning start request to the non-volatile memory block 172. Then, the fine-tuning control circuit 171 outputs a signal (referred to as a fine-tuning data supply control) to control the fine-tuning code supply circuit 173 to supply the fine-tuning code to the fine-tuning code supply circuit 173. The non-volatile memory block 172 stores information (referred to as a fine-tuning code) for fine-tuning the reference voltage VREF. The fine-tuning code may include information for fine-tuning the characteristics of the elements included in the buffer 130. When the non-volatile memory block 172 receives the fine-tuning start request, it outputs reset transmission information including the fine-tuning code to the fine-tuning code supply circuit 173. The trimming code supply circuit 173 outputs the trimming code read from the nonvolatile memory block 172 to the selector 125 and the buffer 130 according to the trimming data supply control.

[0037] Figure 3: is a diagram explaining the fluctuation range of the power supply voltage VDD and the voltage detection value HDET relative to the change ΔVBGR of the BGR voltage VBGR. The left diagram shows the fluctuation range of the power supply voltage VDD and the voltage detection value HDET before fine adjustment. The right diagram shows the fluctuation range of the power supply voltage VDD and the voltage detection value HDET after fine adjustment. The horizontal axis represents ΔVBGR, and the vertical axis represents voltage.

[0038] The reference voltage generating circuit 120 generates a reference voltage VREF based on the BGR voltage VBGR. The power supply voltage VDD and the voltage detection value HDET are generated based on the reference voltage VREF. Therefore, in a stable state, the power supply voltage VDD is proportional to the BGR voltage VBGR, and the voltage detection value HDET is proportional to the BGR voltage VBGR. Therefore, a linear change relative to ΔVBGR is propagated to the power supply voltage VDD and the voltage detection value HDET.

[0039] The solid line on the upper side of each figure represents the power supply voltage VDD, and the solid line on the lower side represents the voltage detection value HDET. The double arrow on the upper side represents the change of the power supply voltage VDD when ΔVBGR is fixed. The change of the upper and lower limits of the change of the power supply voltage VDD is shown by the dotted line. The double arrow on the lower side represents the change of HDET when ΔVBGR is fixed. The change of the upper and lower limits of the change of the voltage detection value HDET is shown by the dotted line. Due to the change ΔVBGR of the BGR voltage VBGR, the fluctuation range of the power supply voltage VDD becomes a range greater than or equal to VDD (minimum) and less than or equal to VDD (maximum). Similarly, due to the change ΔVBGR of the BGR voltage VBGR, the fluctuation range of the voltage detection value HDET becomes a range of HDET (minimum) or greater than HDET and HDET (maximum) or less than HDET. Referring to the right figure, the fluctuation range of the power supply voltage VDD after fine-tuning is narrower than the fluctuation range of the power supply voltage VDD before fine-tuning. Similarly, the fluctuation range of the voltage detection value HDET after fine-tuning is narrower than the fluctuation range of the voltage detection value HDET before fine-tuning.

[0040] The main reason for the fluctuation of the power supply voltage VDD is the differential mismatch of the operational amplifier 141 included in the regulator 140. The main reason for the fluctuation of the voltage detection value HDET is the differential mismatch of the operational amplifier (not shown) included in the voltage detection circuit 150. Since the manufacturing differences of the regulator 140 and the voltage detection circuit 150 are independent of each other, the power supply voltage VDD and the voltage detection value HDET fluctuate independently.

[0041] Figure 41 is a diagram for explaining the operation of the semiconductor device 100. When the power supply voltage VCC exceeds the threshold value, the power-on reset is released. Then, when the power supply voltage VDD exceeds the voltage detection value HDET, the voltage guarantee signal (L level) is output. Then, the trimming control circuit 171 outputs a trimming start request (H level), and the nonvolatile memory block 172 outputs reset transfer information. Then, the trimming code supply circuit 173 changes the trimming code from the initial value to the correction value.

[0042] Next, I will explain the problem newly found by the inventors of the present invention regarding the semiconductor device 100. In the semiconductor device 100, since the power supply voltage VDD and the voltage detection value HDET fluctuate independently, when the MCU is low voltage, the power supply voltage VDD before trimming may be lower than the voltage detection value HDET. Figure 5 2 is a diagram for explaining the fluctuation range of the power supply voltage VDD and the voltage detection value HDET when the power supply voltage VDD is low. Figure 3 , the left figure shows the fluctuation range before fine-tuning, and the right figure shows the fluctuation range after fine-tuning. Referring to the left figure, the minimum value VDD(min) of the power supply voltage VDD is lower than the maximum value HDET(max) of the voltage detection value HDET. Therefore, there is a possibility that the power supply voltage VDD may be lower than the voltage detection value HDET.

[0043] When the power supply voltage VDD before trimming is lower than the voltage detection value HDET, the voltage detection circuit 150 does not output a voltage guarantee signal to the trimming control circuit 171. Then, the trimming control circuit 171 does not output a trimming request to the nonvolatile memory block 172. Therefore, the semiconductor device 100 cannot adjust the reference voltage VREF. Figure 6 is a diagram explaining the operation of the semiconductor device 100 when the power supply voltage VDD is lower than the voltage detection value HDET. Since the power supply voltage VDD does not exceed the voltage detection value HDET, the voltage guarantee signal (L level) is not output. The trimming code maintains the initial value, and the reference voltage VREF is not trimmed.

[0044] The inventors of the present invention have considered increasing the initial power supply voltage VDD higher than the power supply voltage VDD during normal operation to solve the above-mentioned problem so that the power supply voltage VDD having fluctuated downward becomes higher than the voltage detection value HDET. Figure 7 1 is a diagram for explaining the configuration of a semiconductor device 200 according to a research example. Illustration of the reset generation circuit 110, the oscillator 160, and the trimming circuit 170 is omitted. Figure 1 and Figure 7, the reference voltage generating circuit 120 has been replaced by a reference voltage generating circuit 120a. The reference voltage generating circuit 120a also includes a selector 126. The selector 126 has a function of switching the height of the reference voltage VREF output to the buffer 130 based on a voltage control signal supplied from the outside of the reference voltage generating circuit 120a. Compared with the selector 125, the selector 126 can be said to roughly adjust the reference voltage VREF. Even when the power supply voltage VDD is lower than the voltage detection value HDET, the semiconductor device 200 can fine-tune the reference voltage VREF by increasing the reference voltage VREF at power-on.

[0045] Next, the problem of the semiconductor device 200 will be explained. When the selector 126 switches the height of the reference voltage VREF, charge movement from the selected node occurs. Therefore, transient switching noise propagates to the feedback loop voltage VFB1 and the voltage detection value HDET. The dotted arrow indicates a path through which the switching noise propagates. The voltage noise generated in the feedback loop voltage VFB1 propagates to the BGR 121 through the capacitive coupling included in the differential amplification circuit of the operational amplifier 122. The voltage noise propagated to the BGR 121 deteriorates the accuracy of the BGR voltage VBGR, and the voltage noise propagated to the voltage detection circuit 150 deteriorates the accuracy of the voltage detection value HDET. Figure 8 The time variation of the reference voltage VREF, the feedback loop voltage VFB1, the voltage detection value HDET and the BGR voltage VBGR when the height of the reference voltage VREF is switched using the voltage control signal is shown. If the accuracy of the power supply voltage VDD is reduced, the frequency accuracy of the oscillator may also be reduced by the power supply voltage VDD.

[0046] Based on the above considerations, the inventors of the present invention conceived the following embodiments.

[0047] First embodiment

[0048] Fig. 9 1 is a circuit diagram showing the configuration of a semiconductor device 300 according to the first embodiment. Figure 1 and Fig. 9 , the regulator 140 has been replaced by the regulator 140 a . And the semiconductor device 300 further includes a voltage control circuit 180 .

[0049] The regulator 140a is configured to be able to change the output ratio of the power supply voltage VDD to the reference voltage VREF. For example, the resistor R1 can be configured as a variable resistor Rct. The output voltage VOUT of the operational amplifier 141 is expressed as VOUT=(1+Rct / R0)VREF. Alternatively, a series ladder resistor (not shown) can be arranged between the power supply line of the output power supply voltage VDD and the ground, and a selector (not shown) for selecting one node from a plurality of nodes can be provided. The voltage of the selected node is input to the negative input terminal of the operational amplifier 141. The voltage input to the negative input terminal of the operational amplifier 141 is called the feedback loop voltage VFB2.

[0050] The voltage control circuit 180 outputs a voltage control signal for switching the output ratio of the power supply voltage VDD to the reference voltage VREF to the regulator 140a. Specifically, the voltage control circuit 180 outputs a pre-fine adjustment setting value (VDD setting value 1) or a post-fine adjustment setting value (VDD setting value 2) as a voltage control signal based on an external notification (referred to as a fine adjustment read completion notification). If the voltage control fine adjustment read completion notification is not input, the voltage control circuit 180 outputs a setting value (e.g., "0") for outputting a high power supply voltage VDD to the regulator 140a. If the fine adjustment completion notification is input, the voltage control circuit 180 outputs a setting value (e.g., "1") for outputting a low power supply voltage VDD to the regulator 140a. "0" represents an L level, and "1" represents an H level. The fine adjustment read completion notification may be sent from the non-volatile memory block 172, or may be sent from a counter (not shown). The voltage control circuit 180 may, for example, change the power supply voltage VDD by approximately 0.1V.

[0051] Similar to the studied example, voltage noise is generated due to the fluctuation of the power supply voltage VDD, but the voltage noise propagating to the BGR 121 and the voltage detection circuit 150 is small. This is because the voltage noise propagates through the buffer 130. Therefore, the semiconductor device 300 can suppress the influence of the voltage noise on the BGR voltage VBGR and the voltage detection value HDET. Fig.10 is a graph showing time changes of the voltage detection value HDET and the BGR voltage VBGR. The power supply voltage VDD and the feedback loop voltage VFB2 fluctuate according to the switching of the voltage control signal, but the voltage noise propagating to the voltage detection value HDET and the BGR voltage VBGR is small.

[0052] Fig.111 is a diagram for explaining the operation of the regulator 140a. The upper diagram shows the operation of the regulator 140a before the reference voltage VREF is fine-tuned. The lower diagram shows the operation of the regulator 140a after the reference voltage VREF is fine-tuned. The regulator 140a includes a ladder resistor 143 and a selector 144. The series ladder resistor 143 is arranged between the power line supplying the power supply voltage VDD and the ground. The selector 144 selects a node from two nodes on the ladder resistor 143 based on the voltage control signal. The selector 144 can be composed of one or more switches. The voltage of a selected node is input to the operational amplifier 141 as the feedback loop voltage VFB2. Before fine-tuning, the selector 144 inputs the low feedback loop voltage VFB2 to the operational amplifier 141, and after fine-tuning, it inputs the high feedback loop voltage VFB2 to the operational amplifier 141.

[0053] Fig.12 1 is a diagram explaining the fluctuation range of the power supply voltage VDD and the voltage detection value HDET in the semiconductor device 100. Referring to the left diagram, the power supply voltage VDD is set high so that the minimum value VDD(min) of the power supply voltage VDD is higher than the maximum value HDET(max) of the power supply voltage HDET. Referring to the right diagram, the power supply voltage VDD after fine-tuning is set to a low value.

[0054] In the semiconductor device 100, after the power supply voltage VDD exceeds the voltage detection value HDET (first threshold), the output ratio of the power supply voltage VDD to the reference voltage VREF is switched from the first output ratio to the second output ratio which is smaller than the first output ratio. This allows the semiconductor device 100 to reliably fine-tune the reference voltage VREF.

[0055] Fig.13 3 is a diagram for explaining the operation of the semiconductor device 300. When the power supply voltage VDD exceeds the voltage detection value HDET, a voltage assurance signal (L level) is output. Then, a trimming start request (H level) is output, and the transmission of reset transfer information is started. Then, the trimming code is changed from the initial value to the correction value, and the reference voltage VREF is trimmed. This results in the trimming of the power supply voltage VDD. After the reference voltage VREF is trimmed, a trimming read completion notification (L level) is output, and the power supply voltage VDD becomes a low value.

[0056] The semiconductor device 300 according to the first embodiment can expand the adjustment range of the power supply voltage VDD while suppressing the influence of voltage noise generation. The semiconductor device 300 can prevent the voltage noise from propagating to the BGR 121, the voltage detection circuit 150, etc., and prevent the accuracy of the power supply voltage VDD and the voltage detection value HDET from being reduced. In addition, the semiconductor device 300 can prevent the fine adjustment of the reference voltage from not being performed by expanding the fine adjustment range of the power supply voltage VDD.

[0057] Example 1

[0058] Next, a semiconductor device 300 a according to Embodiment 1 as a specific example of the first embodiment will be described. Fig.14 FIG. 2 is a diagram for explaining the configuration of a semiconductor device 300 a according to Embodiment 1. Fig. 9 and Fig.14 , the regulator 140a is configured as a DCDC converter. The clock signal CLK generated by the oscillator 160 is supplied to the fine-tuning control circuit 171 and the non-volatile memory block 172. The non-volatile memory block may be, for example, an MRAM (magnetoresistive random access memory), or it may be a flash memory. In addition to the fine-tuning start request, the fine-tuning control circuit 171 also outputs a memory reset to the non-volatile memory block 172.

[0059] The regulator 140a also includes a pulse generator 145, a p-type MOSFET 146, an n-type MOSFET 147, a diode 148, an inductor L, and a capacitor C. The source terminal of the MOSFET 146 is connected to a power line supplying a power supply voltage VCC. The drain terminals of the MOSFET 146 and the MOSFET 147 are connected to each other. The source terminal of the MOSFET 147 is connected to the ground GND. The pulse generator 145 switches the conduction and cutoff of the MOSFET 146 and the MOSFET 147 based on the output voltage of the operational amplifier 141 and the clock signal CLK. The voltage at the node between the MOSFET 146 and the MOSFET 147 is output as the power supply voltage VDD through the inductor L. The anode terminal of the diode 148 is connected to the ground GND. The cathode terminal of the diode 148 is connected to the node between the MOSFET 147 and the inductor L. The capacitor C is placed between the power line outputting the power supply voltage VDD and the ground GND.

[0060] The dotted lines around the buffer 130 and the regulator 140a indicate that these circuits are powered by the power supply voltage VCC. The dotted lines around the trimming control circuit 171, the trimming code supply circuit 173, and the voltage control circuit 180 indicate that these circuits are supplied with the power supply voltage VCC. In addition, the power supply voltage VCC is supplied to the reset generation circuit 110, the reference voltage generation circuit 120, the voltage detection circuit 150, and the oscillator 160. The nonvolatile memory block 172 is supplied with the power supply voltage VDD generated by the regulator 140.

[0061] The operation of the semiconductor device 300a according to Embodiment 1 will be described. After power-on, when the power supply voltage VCC becomes equal to or higher than the threshold value, the reset generation circuit 110 releases the power-on reset, and the oscillator 160 starts oscillating. In parallel with the release of the power-on reset and the start of oscillation, the regulator 140a generates the power supply voltage VDD based on the power supply voltage VCC based on the voltage control signal generated by the voltage control circuit 180. Then, the voltage detection circuit 150 detects that the power supply voltage VDD is within the voltage guarantee range, that is, the power supply voltage VDD has exceeded the voltage detection value HDET, and outputs a voltage guarantee signal to the trimming control circuit 171. Then, the trimming control circuit 171 outputs a memory reset and a trimming start request to the nonvolatile memory block 172. It should be noted that the power-on reset of the trimming control circuit 171 is released, and the clock is supplied from the oscillator 160 to the trimming control circuit 171. Then, the reset transmission information including the trimming code is read from the nonvolatile memory block 172, and the trimming code is stored in the trimming code supply circuit 173. Then, the reference voltage VREF generated by the reference voltage generating circuit 120 is fine-tuned. Then, the nonvolatile memory block 172 outputs a fine-tuning read completion notification to the voltage control circuit 180. Upon receiving the fine-tuning code completion notification, the voltage control circuit 180 changes the power supply voltage VDD by outputting a voltage control signal to the regulator 140a. The power supply voltage VDD changes from a high voltage (e.g., 0.9V) to a low voltage (e.g., 0.8V).

[0062] It should be noted that in Fig.13 In FIG. 1 , the regulator 140 a constitutes a step-down DCDC converter, but the regulator 140 a may constitute a step-up DCDC converter or a linear regulator.

[0063] In the semiconductor device 300 a according to Embodiment 1, the nonvolatile memory block 172 storing the trimming code can notify the voltage control circuit 180 of the appropriate timing for switching the power supply voltage VDD.

[0064] Example 2

[0065] Next, a semiconductor device 300 b according to Embodiment 2 as a specific example of the first embodiment will be described. Fig.15 FIG. 2 is a diagram for explaining the configuration of a semiconductor device 300 b according to Embodiment 2. Fig.14 and Fig.15, the semiconductor device 300b further includes a counter 190. The power supply voltage VCC is supplied to the counter 190. The fine-tuning control circuit 171 outputs a memory reset to the nonvolatile memory block 172 and the counter 190. The counter 190 starts counting when the memory reset is received. When the count reaches a predetermined number corresponding to the period until the reference voltage VREF is fine-tuned, the counter 190 sends a fine-tuning read completion notification to the voltage control circuit 180. This ensures that there is a sufficient period (referred to as a fine-tuning read period) from the output of the memory reset to the output of the fine-tuning read completion notification. The fine-tuning read completion notification can also be said to be a notification of the timing of the output voltage control signal.

[0066] The operation of the semiconductor device 300b will be described. After power-on, when the power supply voltage VCC exceeds the threshold, the reset generation circuit 110 releases the power-on reset, and the oscillator 160 starts to oscillate. When the fine-tuning control circuit 171 outputs a memory reset and a fine-tuning start request to the non-volatile memory block 172, the counter 190 starts counting the number of pulses of the clock signal generated by the oscillator 160. The counter 190 can ensure the length of the fine-tuning read cycle. Then, the fine-tuning code is read from the non-volatile memory block 172 and stored in the fine-tuning code supply circuit 173. Then, when the counted number of pulses reaches a predetermined number, the counter 190 outputs a fine-tuning read completion notification to the voltage control circuit 180, and the voltage control circuit 180 changes the power supply voltage VDD. As in Embodiment 1, the regulator 140a can be configured as a step-up DCDC converter or a linear regulator.

[0067] In the semiconductor device 300 b according to Embodiment 2, the counter 190 can notify the voltage control circuit 180 of appropriate timing for switching the power supply voltage VDD.

[0068] Finally, the effects of the semiconductor device 300 according to the first embodiment will be described. The semiconductor device 300 can expand the adjustment range of the power supply voltage VDD while maintaining the accuracy of both the voltage detection value HDET and the power supply voltage VDD without significantly changing the circuit area.

[0069] With the semiconductor device 300, the operating voltage during normal operation of the MCU can be determined based on the relationship between the variation range of the power supply voltage VDD after fine-tuning and the electrical characteristics in the process, regardless of the variation range of the power supply voltage VDD before fine-tuning. Therefore, the semiconductor device 300 can help reduce the operating voltage of the MCU.

[0070] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments described above, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device comprising: A reference voltage generating circuit is configured to generate a reference voltage, a regulator circuit configured to generate a power supply voltage based on the reference voltage, and a buffer circuit configured to send the reference voltage from the reference voltage generating circuit to the regulator circuit, wherein the reference voltage generating circuit is configured to adjust the reference voltage, wherein the regulator circuit is configured to change an output ratio of the power supply voltage to the reference voltage, and The semiconductor device further includes a voltage control circuit configured to output a voltage control signal to the regulator circuit to change the output ratio.

2. The semiconductor device according to claim 1, further comprising: a nonvolatile memory circuit configured to store a trimming code for adjusting the reference voltage, and A trimming code supply circuit is configured to supply the trimming code read from the nonvolatile memory circuit to the reference voltage generation circuit.

3. The semiconductor device according to claim 1, When the power supply voltage exceeds a first threshold, the voltage control circuit changes the output ratio from a first output ratio to a second output ratio, wherein the second output ratio is smaller than the first output ratio.

4. The semiconductor device according to claim 2, The memory circuit is further configured to notify the voltage control circuit of timing information for supplying the voltage control signal.

5. The semiconductor device according to claim 1, further comprising: an oscillator configured to generate a clock signal; as well as a counter configured to count the number of pulses of the clock signal, The counter is further configured to notify the voltage control circuit of timing information of supplying the voltage control signal based on the pulse number. 6 . The semiconductor device according to claim 3 , further comprising a voltage detection circuit configured to detect that the power supply voltage exceeds the first threshold voltage.

7. The semiconductor device according to claim 6, The reference voltage generating circuit comprises: A bandgap reference circuit generates a bandgap reference voltage; Operational amplifier; a ladder resistor connected between the output terminal of the operational amplifier and a ground terminal; as well as a selector circuit configured to select one node from a plurality of nodes on the ladder resistor and output a voltage of the one node to an input terminal of the operational amplifier, wherein the bandgap voltage is output to the operational amplifier, and The reference voltage is adjusted by the selector circuit.

8. The semiconductor device according to claim 7, wherein the first threshold is a voltage of a specific node among the plurality of nodes, and The voltage of the specific node is supplied to the voltage detection circuit.

9. The semiconductor device according to claim 6, wherein the voltage detection circuit outputs a voltage guarantee signal when the power supply voltage exceeds a first threshold, and When the power supply voltage drops below a second threshold signal, the voltage detection circuit stops outputting the voltage guarantee signal, and the second threshold signal is lower than the first threshold voltage. 10 . The semiconductor device according to claim 2 , wherein the power supply voltage is supplied to the nonvolatile memory circuit.

Images