Power consumption attack resistant protection circuit for high-reliability modeling-resistant double-layer APUF

Abstract

The invention relates to the technical field of digital integrated circuit design and security anti-counterfeiting, and discloses a power-attack-resistant protection circuit for a high-reliability modeling-resistant double-layer APUF, which comprises a high-reliability modeling-resistant double-layer APUF module and a power-attack-resistant module, and is characterized in that the high-reliability modeling-resistant double-layer APUF module is in electric signal connection with the power-attack-resistant module; the high-reliability modeling-resistant double-layer APUF module is used for resisting external modeling attacks, the power consumption attack-resistant module is used for resisting power consumption analysis of a circuit structure by the outside and preventing the outside from speculating a circuit structure in the high-reliability modeling-resistant double-layer APUF module, and the high-reliability modeling-resistant double-layer APUF module is composed of a first arbiter, a second arbiter and three basic units; and the protection circuit is provided with a path control unit, a path selection unit and an output recovery unit, so that the power consumption attack resistance of the circuit is higher, the cracking difficulty is increased, and the cracking time is increased by geometric multiples.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit design and security anti-counterfeiting technology, and in particular to a protection circuit for resisting power consumption attacks on a high-reliability anti-modeling double-layer APUF. Background Art

[0002] The Physical Unclonable Function mainly uses the inevitable random differences in the chip manufacturing process to generate a unique "chip fingerprint", which has natural anti-tampering and anti-cloning capabilities. Therefore, PUF can provide a low-cost and high-security authentication and key generation method for the Internet of Things, which can effectively solve the security issues of digital technology products.

[0003] Traditional physical unclonable circuits, feedforward circuit anti-modeling double-layer APUF is a new type of PUF structure, which can output extremely high response while resisting modeling attacks, so it has higher stability and security, but it also has some potential weaknesses. The correlation between its output and power consumption is obvious. When there is data dependency between the data processed by the device and its side channel leakage (running time, energy curve, electromagnetic radiation, power consumption, etc.), attackers can use this leakage information to gradually predict its response under specific conditions. Therefore, a protection circuit against power consumption attacks for high-reliability anti-modeling double-layer APUF is proposed to solve the above problems. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a protection circuit for high-reliability anti-modeling double-layer APUF against power consumption attacks, which has the advantages of strong resistance to power consumption attacks and high difficulty in cracking, and solves the problems mentioned in the above background technology.

[0005] In order to achieve the above-mentioned purpose of strong anti-power consumption attack capability and high cracking difficulty, the present invention provides the following technical solutions: a protection circuit for anti-power consumption attack of a high-reliability anti-modeling double-layer APUF, characterized in that it includes a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module, the high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module are connected by electrical signals, the high-reliability anti-modeling double-layer APUF module is used to resist external modeling attacks, and the anti-power consumption attack module is used to resist the power consumption analysis of the circuit structure by the outside world, so as to prevent the outside world from inferring the circuit structure inside the high-reliability anti-modeling double-layer APUF module; The high-reliability anti-modeling double-layer APUF module consists of a first arbitrator, a second arbitrator and three basic units, and the first arbitrator and the second arbitrator are respectively arranged between any two basic units; The anti-power consumption attack module includes a path selection unit, an arbitration unit, a decision unit and an output recovery unit, and the path selection unit, the arbitration unit, the decision unit and the output recovery unit are all connected with circuit signals; The path selection unit is composed of six multiplexers, and the six two-to-two multiplexers are connected by electrical signals. The path selection unit is used to disturb the delay entering the arbitration unit through the control signal S to cover up the power consumption generated by the real delay output; The arbitration unit is composed of six arbiters. The six arbiters are all based on D flip-flops. The arbitration unit is used to obtain the mutual delay characteristic values ​​between delay paths. The decision unit is composed of a custom algorithm, and is used to find the two paths with the largest delay difference; The output recovery unit is composed of a NOT gate and a two-to-one multiplexer, and is used to restore the correct output.

[0006] Preferably, the output ends of the high-reliability anti-modeling double-layer APUF module are four delay links A, B, C, and D from top to bottom. Pairing the four delay links A, B, C, and D in pairs will produce six results, namely, six combination results of AB, AC, AD, BC, BD, and CD, which are used as inputs of the path selection unit: The low level and high level of the control signal S are both 0 and 1, and are positive integers. When the control signal S=0, that is, the low level, each combination result is transmitted in parallel, and the delay path remains unchanged when output to the arbitration unit. When the control signal S=1, that is, the high level, each combination result is cross-transmitted, and the delay path changes when output to the arbitration unit.

[0007] Preferably, the six combination results correspond to the six D flip-flops in the arbitration unit, the output value of the D flip-flop represents the delay characteristic value of the delay size relationship between the two paths with input, each D flip-flop is used to compare the delay size relationship between the two inputs, each D flip-flop has two lines, one close to the upper input and one close to the lower input, if the delay of the upper input of the D flip-flop is large, it outputs 1, otherwise it outputs 0; The decision unit performs delay sorting on the four-way delays according to the arbitration result of the delay difference output by the arbitration unit; The input end of the NOT gate is electrically connected to the output end of the decision unit, the output end of the NOT gate is electrically connected to the input end of the two-to-one multiplexer, the input end of the two-to-one multiplexer is electrically connected to the output end of the high-reliability anti-modeling double-layer APUF module, the NOT gate is used to provide another path delay result, and the two-to-one multiplexer is used to select a suitable path as the final output response.

[0008] Preferably, the control signal S is the result of an exclusive OR operation between the first arbitrator and the second arbitrator.

[0009] Preferably, when the results output by the decision unit are the same, the two-to-one multiplexer selects the path that passes through the NOT gate for output, and when the results output by the decision unit are opposite, the two-to-one multiplexer selects the path that does not pass through the NOT gate for output.

[0010] Compared with the prior art, the present invention provides a protection circuit for high-reliability anti-modeling double-layer APUF against power consumption attacks, which has the following beneficial effects: 1. The protection circuit against power consumption attacks for the high-reliability anti-modeling double-layer APUF increases the circuit's ability to resist power consumption attacks by adding a path control unit, a path selection unit, and an output recovery unit, thereby increasing the difficulty of cracking and increasing the cracking time exponentially.

[0011] 2. The protection circuit against power consumption attacks for the high-reliability anti-modeling double-layer APUF uses a two-to-two multiplexer to change the input of the D flip-flop, confuse the delay comparison result, and restores the originally changed delay through the output recovery unit. While ensuring the accuracy of the response result, it significantly improves the APUF's anti-power consumption attack performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a protection circuit structure for resisting power consumption attacks on a high-reliability anti-modeling double-layer APUF proposed by the present invention; Figure 2 A schematic diagram of the internal structure of a protection circuit anti-power consumption attack module for a high-reliability anti-modeling double-layer APUF proposed by the present invention; Figure 3 A schematic diagram of a protection circuit path selection unit for resisting power consumption attacks for a high-reliability anti-modeling double-layer APUF proposed by the present invention; Figure 4 A schematic diagram of an arbitration unit for a protection circuit structure against power consumption attacks proposed by the present invention for a high-reliability anti-modeling double-layer APUF; Figure 5 A schematic diagram of a protection circuit structure judgment unit for resisting power consumption attacks of a high-reliability anti-modeling double-layer APUF proposed by the present invention; Figure 6 A schematic diagram of a protection circuit structure path recovery unit for a high-reliability anti-modeling double-layer APUF against power consumption attacks proposed by the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] See also Figure 1-6, a protection circuit for high-reliability anti-modeling double-layer APUF against power consumption attacks, including a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module, the high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module are connected by electrical signals, the high-reliability anti-modeling double-layer APUF module is used to resist external modeling attacks, while increasing the diversity of signal transmission paths, making the circuit more reliable and the generated response more stable, the anti-power consumption attack module is used to resist the power consumption analysis of the circuit structure by the outside world, and prevent the outside world from speculating the circuit structure inside the high-reliability anti-modeling double-layer APUF module; reduce the correlation between device power consumption and stimulus response, and enhance the anti-power consumption attack capability of the double-layer APUF; The high-reliability anti-modeling double-layer APUF module consists of a first arbitrator, a second arbitrator and three basic units, and the first arbitrator and the second arbitrator are respectively arranged between any two basic units; The high-reliability and anti-modeling dual-layer APUF module is the same as the dual-layer APUF circuit structure in the existing patent application number 202410079033.3, named high-reliability and anti-modeling dual-layer APUF circuit structure based on feedforward circuit.

[0015] The anti-power consumption attack module includes a path selection unit, an arbitration unit, a decision unit and an output recovery unit, and the path selection unit, the arbitration unit, the decision unit and the output recovery unit are all connected with circuit signals; The path selection unit is composed of six multiplexers, and the six two-to-two multiplexers are connected by electrical signals. The path selection unit is used to disturb the delay entering the arbitration unit through the control signal S to cover up the power consumption generated by the real delay output; The arbitration unit is composed of six arbiters. The six arbiters are all based on D flip-flops. The arbitration unit is used to obtain the mutual delay characteristic values ​​between delay paths. The decision unit is composed of a custom algorithm, and is used to find the two paths with the largest delay difference; Specifically, when the control signal S is 0, if the output of the six D flip-flops is '111111', the relationship between the four-way delay is A>B>C>D. Since the path delay relationship remains unchanged, '111111' is still the comparison result of A and B, A and C, A and D, B and C, B and D, and C and D. Therefore, the delay comparison output result of the D flip-flop remains unchanged, and the output recovery module does not work at this time; when S is 1, the two-to-two multiplexer internal cross transmission changes the delay transmission path. At this time, the output of the D flip-flop is B and A, C and A, D and A. The comparison results of C and B, D and B, and D and C are opposite to the comparison results when S is 0, so the four-way delay size relationship represented by the output signal '000000' is still A>B>C>D, but in the judgment module, the delay relationship represented by '000000' is D>C>B>A, not A>B>C>D, which will cause the judgment module to produce incorrect output. The premise of anti-power attack is to ensure the correctness of the response. If the response is unstable and incorrect due to anti-power attack, then the anti-power attack will lose its meaning. Therefore, we need to restore the result. The output recovery module reverses the response to restore the change in the response result caused by the previous change in the path. The final delay relationship is still A>B>C>D, and the response remains unchanged. In another case, when the output signal is '001011', the delay relationship of the four signals is C>B>A>D. When the control signal S is 0, the delay relationship does not change, the recovery module does not work, and the output delay relationship is still C>B>A>D; when the control signal S is 1, the output delay relationship becomes D>A>B>C, so the output restoration module is also needed to reverse the response to get the correct result.

[0016] The output recovery unit is composed of a NOT gate and a two-to-one multiplexer, and is used to restore the correct output.

[0017] The output of the high-reliability anti-modeling double-layer APUF module is four delay links A, B, C, and D from top to bottom. Pairing the four delay links A, B, C, and D will produce six results, namely AB, AC, AD, BC, BD, and CD, which are used as the input of the path selection unit: The low level and high level of the control signal S are both 0 and 1, and are positive integers. When the control signal S=0, that is, the low level, each combination result is transmitted in parallel, and the delay path remains unchanged when output to the arbitration unit. When the control signal S=1, that is, the high level, each combination result is cross-transmitted, and the delay path changes when output to the arbitration unit.

[0018] The six combination results correspond to the six D flip-flops in the arbitration unit. The output value of the D flip-flop represents the delay characteristic value of the delay size relationship between the two paths with inputs. Each D flip-flop is used to compare the delay size relationship between the two inputs. Each D flip-flop has two lines, one for the upper input and one for the lower input. Each D flip-flop has two input lines, one line input is the data end, that is, the D port, and the other line is the clock end, that is, the CLK port. If the signal at the data end of the D flip-flop arrives first, the output is 1, otherwise the output is 0; Take D flip-flop 1 as an example, A is connected to the CLK input terminal, B is connected to the D input terminal, when the output value AB=1, it means that the rising edge of the A signal is slower than the rising edge of the B signal, that is, the delay of A is greater than the delay of B, then it can be judged that A>B; if the output value AB=0, it means that the rising edge of the A signal is faster than the rising edge of the B signal, that is, the delay of A is less than the delay of B, then it can be judged that A>B <B。

[0019] The decision unit performs delay sorting on the four-way delays according to the arbitration result of the delay difference output by the arbitration unit; The decision unit sorts the delays of the four-way delays according to the arbitration result of the delay difference output by the arbitration unit. For example, when the six output signals are '111111', it can be judged that A>B>C>D. At this time, the delay difference between A and D is the largest, so it is more reliable to select the output of trigger 3 as the response output. However, at this time, the power consumption of the six D flip-flops is also the maximum. This feature can be easily captured by attackers and becomes the key to cracking PUF. Therefore, we connect six two-to-two multiplexers before the trigger to control whether the four delay paths of A, B, C and D are cross-transmitted, and connect a two-to-one multiplexer with a NAND gate after the decision module to return the response change caused by our change of the transmission path. The control signal is S, and S is the result of the XOR of the two arbitrators, which can be regarded as a pseudo-random number.

[0020] The input end of the NOT gate is electrically connected to the output end of the decision unit, the output end of the NOT gate is electrically connected to the input end of the two-to-one multiplexer, the input end of the two-to-one multiplexer is electrically connected to the output end of the high-reliability anti-modeling double-layer APUF module, the NOT gate is used to provide another path delay result, and the two-to-one multiplexer is used to select a suitable path as the final output response.

[0021] The control signal S is the result of the exclusive OR operation between the first arbitrator and the second arbitrator.

[0022] Regarding the problem of power consumption detection, attackers always detect the power consumption of the D flip-flop. The power consumption difference between the result of the D flip-flop jumping from 0 to 1 and from 1 to 0 is too large. We use the method of confusing the delay path to confuse the prominent feature of the power consumption difference. Since the control signal S is the result of the XOR of the two arbiters, it can be regarded as a pseudo-random number. Therefore, the power consumption generated when the output of the D flip-flop jumps will no longer have special power consumption characteristics. In other words, the detected power consumption has no obvious relationship with the output jump. The dependence of the jump of the D flip-flop output result and the power consumption has been weakened, so that the attacker cannot use power consumption as a breakthrough to crack the APUF, thereby achieving the purpose of resisting power consumption attacks.

[0023] When the results of the decision unit outputs are the same, the two-to-one multiplexer selects the path that passes through the NOT gate for output. When the results of the decision unit outputs are opposite, the two-to-one multiplexer selects the path that does not pass through the NOT gate for output.

[0024] In summary, the protection circuit against power consumption attacks for the high-reliability anti-modeling double-layer APUF, by adding a path control unit, a path selection unit and an output recovery unit, makes the circuit more resistant to power consumption attacks, increases the difficulty of cracking, and increases the cracking time exponentially.

[0025] In addition, by using a two-to-two multiplexer to change the input of the D flip-flop, the delay comparison result is confused, and the originally changed delay is restored through the output recovery unit. While ensuring the accuracy of the response result, the APUF's anti-power consumption attack performance is significantly improved.

[0026] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0027] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A protection circuit for high-reliability anti-modeling double-layer APUF against power consumption attacks, characterized in that: It includes a high-reliability anti-modeling double-layer APUF module and an anti-power consumption attack module. The high-reliability anti-modeling double-layer APUF module and the anti-power consumption attack module are connected by electrical signals. The high-reliability anti-modeling double-layer APUF module is used to resist external modeling attacks. The anti-power consumption attack module is used to resist external power consumption analysis of the circuit structure, so as to prevent the outside world from speculating the internal circuit structure of the high-reliability anti-modeling double-layer APUF module. The high-reliability anti-modeling double-layer APUF module consists of a first arbitrator, a second arbitrator and three basic units, and the first arbitrator and the second arbitrator are respectively arranged between any two basic units; The anti-power consumption attack module includes a path selection unit, an arbitration unit, a decision unit and an output recovery unit, and the path selection unit, the arbitration unit, the decision unit and the output recovery unit are all connected with circuit signals; The path selection unit is composed of six multiplexers, and the six two-to-two multiplexers are connected by electrical signals. The path selection unit is used to disturb the delay entering the arbitration unit through the control signal S to cover up the power consumption generated by the real delay output; The arbitration unit is composed of six arbiters. The six arbiters are all based on D flip-flops. The arbitration unit is used to obtain the mutual delay characteristic values ​​between delay paths. The decision unit is used to find the two paths with the largest delay difference; The output recovery unit is composed of a NOT gate and a two-to-one multiplexer, and is used to restore the correct output.

2. A protection circuit for anti-power consumption attack of a high-reliability anti-modeling double-layer APUF according to claim 1, characterized in that: The output ends of the high-reliability anti-modeling double-layer APUF module are four delay links A, B, C, and D from top to bottom. Pairing the four delay links A, B, C, and D will produce six results, namely AB, AC, AD, BC, BD, and CD, which are used as inputs of the path selection unit: The low level and high level of the control signal S are both 0 and 1, and are positive integers. When the control signal S=0, that is, the low level, each combination result is transmitted in parallel, and the delay path remains unchanged when output to the arbitration unit. When the control signal S=1, that is, the high level, each combination result is cross-transmitted, and the delay path changes when output to the arbitration unit.

3. According to claim 1, a protection circuit for anti-power consumption attack for a high-reliability anti-modeling double-layer APUF, characterized in that: The six combination results correspond to the six D flip-flops in the arbitration unit. The output value of the D flip-flop represents the delay characteristic value of the delay size relationship between the two paths with inputs. Each D flip-flop is used to compare the delay size relationship between the two inputs. Each D flip-flop has two lines, one for the upper input and one for the lower input. If the delay of the upper input of the D flip-flop is larger, the output is 1, otherwise the output is 0. The decision unit performs delay sorting on the four-way delays according to the arbitration result of the delay difference output by the arbitration unit; The input end of the NOT gate is electrically connected to the output end of the decision unit, the output end of the NOT gate is electrically connected to the input end of the two-to-one multiplexer, the input end of the two-to-one multiplexer is electrically connected to the output end of the high-reliability anti-modeling double-layer APUF module, the NOT gate is used to provide another path delay result, and the two-to-one multiplexer is used to select a suitable path as the final output response.

4. The protection circuit against power consumption attack for a high-reliability anti-modeling double-layer APUF according to claim 1, characterized in that: The control signal S is the result of the exclusive OR operation between the first arbitrator and the second arbitrator.

5. The protection circuit for anti-power consumption attack of high-reliability anti-modeling double-layer APUF according to claim 3 is characterized in that: When the results of the decision unit outputs are the same, the two-to-one multiplexer selects the path that passes through the NOT gate for output. When the results of the decision unit outputs are opposite, the two-to-one multiplexer selects the path that does not pass through the NOT gate for output.

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