Neuromorphic processor capable of learning online based on approximate calculation

Abstract

The invention relates to a neural morphological processor capable of learning online based on approximate calculation. The neural morphological processor comprises a communication subsystem, a training subsystem and a reasoning subsystem, the communication subsystem is used for constructing a multi-pulse core neuromorphic processor with a hierarchical routing architecture; the training subsystem is used for optimizing weight and threshold parameters of the multi-pulse core neuromorphic processor by adopting an online learning method; and the reasoning subsystem is used for reasoning the encoded input image data by the multi-pulse core neuromorphic processor after online training or offline weight deployment, and generating classified output of the multi-pulse core neuromorphic processor. The invention provides a neural morphological processor architecture based on online learning and approximate calculation so as to realize high trade-off among the precision, the energy efficiency ratio and the response speed of a processor and efficiently process dynamic and complex task data in real time.

Description

Technical Field

[0001] The present invention relates to the technical field of neuromorphic processor design, and in particular to an online learning neuromorphic processor based on approximate computing. Background Art

[0002] Neuromorphic processors based on spiking neural networks (SNNs) are designed to simulate the functions of brain neural networks through bionic principles and hardware design, to achieve efficient computing and task processing, especially with online learning and event-driven features. Neuromorphic processors are an important research direction in the field of neuromorphic computing, and are widely used in fields such as medical image processing, autonomous driving, intelligent monitoring systems, and smart transportation. Unlike traditional circuits based on artificial neural networks (ANNs), for example, convolutional neural networks (CNNs) use continuous signal processing and fixed training models, which are less efficient when processing dynamic and sparse data. At the same time, since hardware circuits designed based on CNNs cannot fully simulate the biological characteristics and dynamic learning capabilities of the brain, CNN-based circuits rely on offline training, and their adaptability and energy efficiency are poor for real-time applications and resource-limited environments.

[0003] Current digital pulse neuromorphic processors have key problems such as high hardware resource overhead, low neuron computing efficiency, limitations of online learning methods, and low inter-chip communication flexibility, which hinder their application in practical scenarios. Among them, pulse neurons are the computing core of neuromorphic chips, but the current pulse neurons have large resource overhead and low computing efficiency. Pulse neurons are the computing core of neuromorphic chips. For example, the current-based digital leaky integrate-and-fire (LIF) model makes neuron behavior configurable, but its complex membrane potential conversion brings additional overhead. ODIN uses both LIF neurons and the Izhikevich (Izh) neuron model with higher biological accuracy. The LIF neuron model has not been optimized in hardware, resulting in low computing efficiency. Although the Izh neuron model realizes up to dozens of neuron behavior simulations, it brings very complex control logic and additional resource consumption. Due to the complex neuron calculations in neural networks, many research works have applied approximate computing techniques such as weight quantization and pruning to neuron circuits, but there are problems such as affecting the accuracy of neural network models (substantially reduced). Secondly, the SNN processors in the prior art usually do not have online learning capabilities or are insufficiently optimized. Based on computational complexity and cost considerations, many existing SNN processors, such as the existing TrueNorth, Tsinghua Tianjic and SpiNNaker processors, do not have on-chip learning capabilities, and can only deploy weights offline, which makes them unable to adapt to changing real-world scenarios. Other neuromorphic chips with online learning capabilities, such as the online learning method for Spiking-Timing-Dependent Plasticity (STDP), can design different learning rules in the format of microcode, but this learning rule is relatively complex and occupies a large amount of hardware resources when implemented in hardware. ODIN uses a spike-driven synaptic plasticity (SDSP) learning rule simplified from STDP, but overly simple learning rules can easily cause the neural network to overfit, resulting in reduced recognition accuracy. In addition, the hardware implementation solution proposed in the prior art lacks flexible on-chip routing control. Neuromorphic chips mainly update neuron states and synaptic weights in real time based on pulse information. In order to adapt to different time windows and multi-scale input images, certain routing scheduling is required to control the correctness and flexibility of the operation of the spiking neural network. Existing technologies usually require customized neuron storage space and row and column storage access to neuron states, but the fixed storage space limits the applicability of the processor to large neural networks.Another common solution is to input the same time window fixedly, because if the time window size of each layer is different, the processing time of each layer will be different, because the core completes the operation of this layer, but before the previous layer completes the calculation, it must wait, which leads to a waste of computing resources. However, under the increasingly complex computing requirements, designing on-chip routing to solve the calculation of large networks and support the processing of different time windows is an inevitable trend. Summary of the invention

[0004] The purpose of the present invention is to solve the technical problems of large hardware resource overhead, low computing efficiency, limited online learning ability, insufficient routing scheduling, etc. in existing neuromorphic processors, so as to achieve more efficient neuromorphic computing effects. Aiming at the goal of applying neuromorphic processor technology to real-time intelligent computing, a neuromorphic processor architecture based on approximate computing and capable of online learning is proposed to achieve a high degree of trade-off between the processor's recognition accuracy, response speed and hardware resource consumption, and accurately, in real time and efficiently realize the processing of dynamic and complex image target recognition tasks.

[0005] The present invention combines biologically inspired computing models and hardware designs to propose a processor design system that can dynamically update and efficiently process complex tasks, a low-power, high-precision, online-learning processor based on pulse neural networks, and can efficiently simulate the complex computing functions of biological neural systems. This design system can not only significantly improve computing speed and energy efficiency, but also reduce the hardware resource consumption of processor design. The system is suitable for various industries that require neural network computing, such as medical image processing, autonomous driving, intelligent monitoring systems, and smart transportation. To solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A neuromorphic processor capable of online learning based on approximate computing, comprising: an inference subsystem, a training subsystem and a communication subsystem;

[0008] The reasoning subsystem includes an input layer, a hidden layer and an output layer, wherein the hidden layer includes a plurality of pulse processing cores for parallel processing, and the output layer includes at least one pulse processing core; each pulse processing core includes a plurality of physical neurons established by a preset neuron model;

[0009] The reasoning subsystem is used to perform approximate calculations on the multi-scale input image connected to the input layer after encoding based on the pre-stored synaptic weights and activation thresholds through the pulse processing cores in the hidden layer and the output layer, and to count the calculation results of multiple time steps in a time window to generate a recognition result of the multi-scale input image;

[0010] The training subsystem is used to access multiple images to the hidden layer and the output layer using the input layer, and update the synaptic weight and the activation threshold using a random online learning method based on historical weights;

[0011] The reasoning subsystem is further used to update the recognition result of the multi-scale input image by performing approximate calculations through the pulse processing cores in the hidden layer and the output layer based on the synaptic weights and activation thresholds updated after training;

[0012] The communication subsystem is used to perform multi-level routing control on the data transmission between the reasoning subsystem and the training subsystem through a hierarchical routing architecture.

[0013] Optionally, the input layer includes a plurality of virtual neurons, the number of which matches the scale of the input image, and is used to access a pulse sequence of a binary image after rate encoding the input image;

[0014] The pulse processing cores in the hidden layer and the output layer are both equipped with synaptic cores and neuron computing cores; the synaptic cores pre-store synaptic weights obtained through pre-training; the neuron computing cores pre-store activation thresholds obtained through pre-training; the neuron computing cores are equipped with multiple physical neurons; the multiple physical neurons form a pipeline structure to sequentially transmit the pulse sequence of the connected binary image.

[0015] Optionally, each of the physical neurons comprises: a PE array consisting of a plurality of approximate computing units, an approximate addition tree and a pulse emission decision unit; the approximate computing unit is built with an accumulation control logic circuit and at least one approximate adder; the approximate addition tree is composed of a plurality of approximate adders added hierarchically in pairs;

[0016] The PE array is used to access the local pulse sequence of the binary image in batches, and issue each pulse of the local pulse sequence to the corresponding approximate calculation unit for independent parallel summation; and perform the accumulation calculation of multiple local pulse sequences of the binary image in batches by time-division multiplexing of the multiple approximate calculation units to obtain the membrane potential increment accumulated by each approximate calculation unit;

[0017] Each of the approximate calculation units is further used to update the local membrane potential of the physical neuron distributed in the current approximate calculation unit at the current moment according to the preset neuron model using the membrane potential increment accumulated at each batch moment;

[0018] The approximate addition tree is used to sum the local membrane potential output by each approximate calculation unit to obtain the membrane potential of the physical neuron corresponding to the connected binary image;

[0019] The pulse emission decision unit is used to compare the membrane potential summarized by the approximate addition tree with the activation threshold to determine whether to activate the current physical neuron; if the current physical neuron is not activated, the membrane potential of the current physical neuron is attenuated according to a preset neuron model; if the current physical neuron is activated, a new pulse is emitted to the next layer of neurons, and after the physical neuron is activated and emits a pulse, the membrane potential of the current neuron is reset according to the preset neuron model.

[0020] Optionally, the neuron model includes a neuron charging model, and the mathematical model of the neuron charging model is:

[0021] V(t)=V(t-1)+X(t),

[0022] or

[0023]

[0024] or

[0025]

[0026] Among them, V(t) is the membrane potential of the neuron at the current moment, V(t-1) is the membrane potential of the neuron at the previous moment, and X(t) is the membrane potential increment formed by the input pulse at the current moment. is the preset membrane potential attenuation factor; V rst Reset baseline potential for the neuron.

[0027] Optionally, the neuron model includes a neuron reset model:

[0028] V(t + )=V rst ,

[0029] or

[0030]

[0031] Among them, the V(t + ) is the reset membrane potential of the neuron at the current moment, V(t - ) is the pre-reset membrane potential of the neuron at the current moment; V rst is a preset reset reference potential; is the preset membrane potential attenuation factor; V th is the activation threshold of the current neuron.

[0032] Optionally, the training subsystem includes: a controller, a neuron comparator, an update arbitrator, a random number generator and a parameter updater;

[0033] The controller is used to control the duration of the input pulse sequence received by the neuron, and to control the correct timing and functional operation of the training subsystem;

[0034] The neuron comparator is used to compare and obtain the activation states of different physical neurons, and select the most active physical neuron based on the pulse emission rate;

[0035] The update arbitrator is used to receive the output result of the neuron comparator and transmit the most active physical neuron to the parameter updater;

[0036] The random number generator is used to generate pseudo-random numbers by using a shift operation based on a linear feedback shift register;

[0037] The parameter updater is used for a random online learning strategy based on historical weights, and updates the synaptic weight and activation threshold of the most active physical neuron using the pseudo-random number and the synaptic weight currently stored in the neuron.

[0038] Optionally, the random online learning strategy based on historical weights specifically includes:

[0039] If the difference between the current membrane potential of the physical neuron and the current activation threshold is greater than the pseudo-random number, the synaptic weight and activation threshold of the current physical neuron are updated according to the following mathematical model:

[0040]

[0041] Where W(t) represents the updated synaptic weight, W(t-1) represents the synaptic weight before the update, and V th (t) represents the updated activation threshold, V th (t-1) represents the activation threshold before updating, Δt represents the time difference between the release of the pulse by the front neuron and the rear neuron, a and b represent two different weight update amplitudes; c represents the update amplitude of the activation threshold;

[0042] Otherwise, the synaptic weights and activation thresholds of the physical neurons at the current moment remain unchanged.

[0043] Optionally, the neuron comparator selects the most active physical neuron based on the pulse firing rate, specifically:

[0044] Perform weighted summation on each pulse signal in the input pulse train and the synaptic weight corresponding to the current physical neuron to obtain the cumulative membrane potential of the input pulse train;

[0045] Subtracting the accumulated membrane potential from the activation threshold of the current physical neuron to obtain an accumulated difference;

[0046] Assigning trigger timings to each pulse signal in the input pulse sequence in sequence; and performing weighted summation on each pulse signal with the trigger timing and the synaptic weight corresponding to the current physical neuron to obtain a timing-weighted membrane potential of the input pulse sequence;

[0047] The ratio of the time-series weighted membrane potential to the accumulated difference is used as the normalized pulse emission duration of the current physical neuron;

[0048] Compare the normalized pulse emission durations of all physical neurons in the hidden layer one by one, and select the neuron corresponding to the minimum value as the most active physical neuron in the hidden layer;

[0049] The normalized pulse emission durations of all physical neurons in the output layer are compared one by one, and the neuron corresponding to the minimum value is the most active physical neuron in the output layer.

[0050] Optionally, the approximate adder is a speculative carry adder with an error correction mechanism.

[0051] Optionally, the communication subsystem is a three-level routing system, including: a zero-level router, a first-level router, and a second-level router;

[0052] The zero-level router is arranged inside each pulse processing core, and is used to transmit the encapsulated signal of the first-level router to the corresponding pulse processing core, and re-encapsulate the calculation result of the pulse processing core into a data packet and then send it to the first-level router;

[0053] The first-level router is used to collect and encapsulate the data of the zero-level router according to a preset communication protocol to realize the communication and transmission of data between various pulse processing cores;

[0054] The secondary router is used to collect the output data of the primary router according to a preset communication protocol to realize data communication between multiple neuromorphic processors composed of pulse processing core clusters, or data communication between a neuromorphic processor and an external circuit.

[0055] The beneficial effects of the present invention are:

[0056] The present invention proposes a neuromorphic processor with optimized structure and capable of online learning. By designing a hardware-friendly neuron structure, a high-precision approximate computing circuit, an improved online learning method and a flexible three-level on-chip communication routing, combined with the computing characteristics of a spiking neural network, a neuromorphic processor with low power consumption, high computing efficiency and high recognition accuracy is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0058] Figure 1 A schematic diagram of a specific structure of an online learning neuromorphic processor based on approximate computing according to an embodiment of the present invention;

[0059] Figure 2 A schematic diagram of a principle structure of a hidden layer pulse processing core of an embodiment of the present invention;

[0060] Figure 3 A schematic diagram of the principle structure of an output layer pulse processing core of an embodiment of the present invention;

[0061] Figure 4 is a structural block diagram of a multi-pulse core neuromorphic processor according to an embodiment of the present invention;

[0062] Figure 5 A circuit structure diagram of a pulse processing core according to an embodiment of the present invention;

[0063] Figure 6 A flow chart of a method for selecting the most active neuron based on a competitive learning strategy according to an embodiment of the present invention;

[0064] Figure 7 A flow chart of an update algorithm for selecting the most active neuron in a hidden layer or output layer of a network based on normalized pulse emission duration according to an embodiment of the present invention;

[0065] Figure 8 A schematic diagram of an encapsulation format of a data packet distributed in various levels of routing according to an embodiment of the present invention;

[0066] Fig. 9 A schematic diagram of an achievable structure of a second-level router in a three-level router on a chip according to an embodiment of the present invention;

[0067] Fig.10 A partial structural diagram of a neuromorphic processor constructed by using a three-level on-chip routing architecture combined with a multi-pulse processing core according to an embodiment of the present invention. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] This embodiment proposes a neuromorphic processor capable of online learning based on approximate computing, including: an inference subsystem, a training subsystem, and a communication subsystem. Figure 1 , which is a schematic diagram of the principle of a specific structure of an online learning neuromorphic processor based on approximate computing provided by an embodiment of the present invention.

[0071] The inference subsystem includes an input layer, a hidden layer and an output layer, wherein the hidden layer includes a plurality of pulse processing cores for parallel processing, and the output layer includes at least one pulse processing core; each pulse processing core includes a plurality of physical neurons established by a preset neuron model. Figure 1 The hidden layer of the neuromorphic processor shown in FIG. 1 includes four pulse processing cores, and the output layer includes one pulse processing core. The structure of each hidden layer pulse processing core 1-4 is the same, as shown in FIG. Figure 2 As shown; the structure of the output layer pulse processing kernel is as follows Figure 3 As shown. The structure setting principle of the hidden layer pulse processing core and the output layer pulse processing core is the same, but the number and function of neurons in the current network layer will be different depending on the input signal of the current network layer and the position of the current network layer. In a preferred implementation, the pulse processing core of the hidden layer is constructed based on the IF neuron model, and the pulse processing core of the output layer is constructed based on the LIF neuron model, which can obtain higher recognition accuracy.

[0072] The inference subsystem is used to perform approximate calculations on the multi-scale input image connected to the input layer after encoding based on the pre-stored synaptic weights and activation thresholds through the pulse processing cores in the hidden layer and the output layer, and to count the calculation results of multiple time steps in a time window to generate a recognition result of the multi-scale input image.

[0073] The training subsystem is used to access multiple images to the hidden layer and the output layer using the input layer, and to update the synaptic weights and the activation threshold using a random online learning method based on historical weights.

[0074] The reasoning subsystem is further used to update the recognition result of the multi-scale input image by performing approximate calculations through the pulse processing cores in the hidden layer and the output layer based on the synaptic weights and activation thresholds updated after training.

[0075] The communication subsystem is used to perform multi-level routing control on the data transmission between the reasoning subsystem and the training subsystem through a hierarchical routing architecture.

[0076] Preferably, if Figure 4 As shown, in an embodiment of the present invention, the input layer includes a plurality of virtual neurons, the number of which matches the scale of the input image, and is used to access a pulse sequence of a binary image after rate encoding the input image;

[0077] like Figure 5 As shown, the pulse processing cores in the hidden layer and the output layer are both built with a synaptic core 300 and a neuron computing core 400; the synaptic core 300 pre-stores the synaptic weight W obtained through pre-training; the neuron computing core 400 pre-stores the activation threshold V obtained through pre-training th ; The neuron computing core 400 has a plurality of physical neurons (NE) built in; the plurality of physical neurons (NE) form a pipeline structure, and sequentially transmit the pulse sequence of the connected binary image. In specific implementation, the number of physical neurons (NE) built in the neuron computing core 400 of the pulse processing core in the hidden layer and the output layer may be different. In a preferred embodiment, the number of physical neurons NE in the hidden layer is 20, and the number of physical neurons NE in the output layer matches the total number of categories of object targets to be identified. For example, for the MNIST data set of handwritten digits 0 to 9, the number of physical neurons NE in the output layer should be 10.

[0078] Different from traditional ANN which can directly receive the pixel values ​​of the image, SNN is driven based on a pulse sequence. Therefore, before the two-dimensional image is input into SNN, the image needs to undergo a series of preprocessing.

[0079] Preferably, the online-learning neuromorphic processor based on approximate computing also includes a pulse encoder, which is used to rate encode the input digital image according to a preset time step to generate multiple frames of binary images; the pulse encoder is also used to transmit the pulse sequence of each frame of the binary image in batches by whole rows or whole columns to the corresponding physical neurons in the hidden layer to perform parallel membrane potential calculations; or, to transmit the pulse sequence of each frame of the binary image at one time by whole frames to the corresponding pulse processing core of the hidden layer to perform parallel membrane potential calculations.

[0080] In an achievable manner, the embodiment of the present invention downsamples an input image of any size to obtain an image of width (M) × height (N) pixels, and then encodes the input image into a pulse sequence whose number of emission times conforms to the Poisson process by rate coding, such as Poisson coding:

[0081]

[0082] Among them, M and N represent the number of image pixels with variable scale, P represents the probability that the random variable X takes the value k, which should be normalized to [0,1], k represents the number of times the event occurs, and λ represents the average number of times the event occurs, also known as the parameter or average rate of the Poisson distribution. It represents the expected number of times an event occurs within a given time period or region.

[0083] Therefore, the pulse input process of the present invention to realize multi-scale image through Poisson coding is as follows: first, the time step is set to T. In each time step, the probability of each pixel generating a pulse is proportional to the size of the pixel value. Then, several time steps are executed to obtain the pulse sequence generated by each pixel. Finally, the pulse sequence generated by each pixel is input into the corresponding SNN input layer neuron through the external interface.

[0084] Preferably, the online learning neuromorphic processor based on approximate computing further includes a neuron timing generator 100 (e.g. Figure 5 As shown). The neuron timing generator 100 is used to generate a time step for controlling the pulse sequence input to the physical neuron. The time step can control the pulse coding length of each pixel of the input image after rate coding, thereby affecting the representation accuracy of each pixel value and the recognition accuracy obtained after the pulse processing core calculation. Therefore, for a whole frame of input image, after rate coding, a number of multiple frames of binary images corresponding to the time step can be obtained according to the time step, and the pixel values ​​of each frame of the binary image form a pulse sequence, which is distributed to the input layer of the pulse processing core in a whole row, a whole column or a whole frame through the controller 200, so as to start the calculation of each physical neuron in the hidden layer and the output layer in turn according to the preset neuron model.

[0085] Since the spiking neural network (SNN) allows multiple forms of synaptic connections, including various types of neurons, to simulate the diversity of neurons in organisms, this enables the SNN network to better simulate the information processing method in the biological nervous system and achieve a higher level of neural computing. In the embodiment of the present invention, in order to flexibly adapt to the neuron model in the spiking neural network, two neuron models are adopted, namely, Integrate and Fire (IF) neurons and Leaky Integrate and Fire (LIF) neurons.

[0086] The IF neuron model is an ideal integrator model, which is characterized by the fact that the membrane potential of the neuron remains constant when there is no input. The basic equation (charging equation) of the IF neuron model is:

[0087]

[0088] where I(t) is the input current, V(t) is the membrane potential, and C is the membrane capacitance.

[0089] In specific implementation, since the pulse input signal of the spiking neural network (SNN) is discrete, it is difficult to obtain the input current I(t) by performing differential operations in a continuous signal calculation mode when it is implemented on digital circuit hardware. In order to adapt the spiking neural network model to the implementation on digital circuit hardware, the present invention improves the above two models respectively to obtain a hardware-friendly neuromorphic processor based on the spiking neural network.

[0090] For the original IF neuron model, the present invention approximates the continuous time differential equation to a discrete time recursive equation, and the differential term can be approximately equivalent to:

[0091]

[0092] Then the charging equation (also called neuron dynamic equation) of the IF neuron model can be equivalent to:

[0093]

[0094] This equation is the neural dynamics equation of the current physical neuron before it reaches the activation threshold, and describes the change of the membrane potential of the current physical neuron before it reaches the threshold potential required for firing a pulse (pulse value is 1).

[0095] For the LIF neuron model, the effect of leakage conductance on the membrane potential change of the physical neuron needs to be considered. When there is no input current (the pulse value is 0), the membrane potential will gradually return to the resting potential, which simulates the natural diffusion process of ions through the membrane. The basic equation of the LIF model (charging equation) is:

[0096]

[0097] Among them, g is the leak conductance, E is the resting potential of the neuron, and the equation describes the relationship between input current, membrane potential, and decay. Similarly, the differential equation of the LIF neuron charging model (neuron dynamic equation) can be approximated as a recursive equation for discrete-time signals.

[0098] In the embodiment of the present invention, the pulse sequence is serially input according to the overall clock pace of the digital circuit system. At the same time, the multi-bit pulses (0 or 1) can be merged into a multi-bit digital signal and then input in parallel to the neuron for parallel calculation. Within the accumulated discrete time step Δt, for SNN, the pulse sequence input current I(t) mainly affects the increment X(t) of the neuron membrane potential. Therefore, the membrane potential increment X(t) can be obtained by multiplying the input current I(t) and the time step Δt, that is, X(t) = I(t) · Δt.

[0099] The embodiment of the present invention inputs the pulse sequence of the binary image obtained after rate encoding the input image into the physical neuron, calculates the real-time membrane potential of the physical neuron according to the preset neuron charging model, and decides whether to send pulses to the next layer of physical neurons. The neuron model provided by the embodiment of the present invention includes a neuron charging model.

[0100] In a preferred embodiment, after improving the above IF neuron model, the mathematical model of the neuron charging model is:

[0101] V(t)=V(t-1)+X(t),

[0102] Alternatively, after improving the LIF neuron model, we can obtain:

[0103] Model of neuron charging without attenuation of input pulses:

[0104]

[0105] Or, a neuron charging model that decays its input spikes:

[0106]

[0107] Among them, V(t) is the membrane potential of the neuron at the current moment, V(t-1) is the membrane potential of the neuron at the previous moment, and X(t) is the membrane potential increment formed by the input pulse at the current moment. is the preset membrane potential attenuation factor; V rst Reset baseline potential for the neuron.

[0108] In practice, when the LIF neuron charging model is used without attenuation of the input pulse, the membrane potential increment X(t) directly affects the membrane potential of the neuron, which then changes according to the attenuation factor Adjust the membrane potential at the previous moment and reset the reference potential V rst The difference between the membrane potential and the reference potential V rst Attenuation. When the LIF neuron charging model that attenuates the input pulse is adopted, the increment of the membrane potential X(t) also participates in the attenuation, and the change in the overall membrane potential of the neuron takes into account both the impact of the input membrane potential increment and the natural attenuation of the membrane potential relative to the reset potential. In the neurodynamic equations of the above two optimized LIF neuron charging models, τ is a time constant, which can be determined according to the requirements of the neuron model, biological rationality, etc. Preferably, if the physical neuron needs to respond quickly to the rapidly changing input pulse signal, a smaller τ (larger attenuation factor) is selected so that the membrane potential can decay faster; and vice versa. This value selection method mainly imitates the response mechanism of actual biological neurons. For example, fast-paced neurons in the cerebral cortex usually have smaller time constants (larger attenuation factors), while neurons related to memory and learning usually have larger time constants (smaller attenuation factors). In biological neuroscience, a τ value consistent with the behavior of actual biological neurons is selected. As for resetting the reference potential V rst The setting is preferably V rst It is set lower than the resting membrane potential E in order to put the neurons in the refractory period after excitation, simulate the real neuronal behavior of organisms, and prevent over-activation. This mechanism is very common in biological nervous systems.

[0109] In the optimized IF neuron model of this embodiment, the membrane potential remains constant in the absence of pulse input. This model is suitable for computing units that need to maintain high sensitivity, because any small input current can quickly affect the membrane potential, allowing neurons to respond quickly to input signals.

[0110] The optimized LIF neuron model in this embodiment takes into account the natural decay of the membrane potential. When there is no input, the membrane potential gradually returns to the resting potential. This model is closer to the behavior of biological neurons, suitable for simulating the real biological signal processing process, and has a certain noise resistance.

[0111] In this embodiment, the neuron models of the physical neurons of the hidden layer and the output layer can select different types of neuron models (including IF neuron models and LIF neuron models) according to the characteristics of the input image. Specifically, for images with varied and complex details, the LIF neuron model is preferred, because the LIF neuron simulates the dynamic characteristics of biological neurons, namely the leakage and refractory period of the neuron membrane potential, which helps to extract time-related features in the input image, enhance the feature representation of the subtle difference part, and adapt to more varied and complex input images. For input images with simpler textures, the IF neuron model is preferred, because the membrane potential of the IF neuron will not leak, and it will not reset until it reaches the activated state, and it is more sensitive to the change of the pulse, which is suitable for processing simple input images with more obvious features, and realizes fast and accurate classification and recognition of targets. For example, combining the characteristics of the two neurons, using LIF neurons in the hidden layer can enhance the feature representation of the input image, extract subtle features in the image, and after the extraction of the hidden layer, the IF neurons in the output layer can quickly and accurately complete the classification according to the pulse sequence of these significant features, and better reasoning performance (recognition accuracy) can be obtained.

[0112] At each time step, if no neuron activation event occurs, the leaked neuron membrane potential will be stored for use by the neuron event at the next time step; as time accumulates, the neuron membrane potential can change in real time with the number and frequency of input pulses. If the neuron makes a corresponding neuron pulse emission event for the membrane potential increment X(t) formed by multiple input pulses of the neuron membrane potential according to the above neuron charging model, that is, the neuron is activated to emit a pulse (signal "1"), then the neuron model will simulate the actual biological neuron behavior and reset the neuron's potential state.

[0113] Specifically, the neuron model includes a neuron reset model. The neuron reset model includes a hard mode:

[0114] V(t + )=V rst ,

[0115] Or, in Soft mode:

[0116]

[0117] Among them, the V(t + ) is the reset membrane potential of the neuron at the current moment, V(t - ) is the pre-reset membrane potential of the neuron at the current moment; V rst is a preset reset reference potential; is the preset membrane potential attenuation factor; V this the activation threshold of the current neuron.

[0118] Therefore, for the hard mode, the reset of the neuron membrane potential is directly set to the pre-set reset reference potential; while for the soft mode, the membrane potential does not need to be reset, but the membrane potential is reset based on the attenuation factor and the activation threshold of the current membrane potential.

[0119] During the inference process, the neuromorphic processor provided by the embodiment of the present invention can be used to identify the target of the input image. Specifically, the input image is encoded and converted into a pulse sequence of a binary image corresponding to the time step, and the pulse sequence code stream is input into the input layer of the neuromorphic processor. According to the design principle of the above-mentioned neuron model, after layer-by-layer calculation between the physical neurons of the hidden layer and the physical neurons of the output layer, the category label of the input image can be quickly and intelligently identified through the emission and propagation of pulses.

[0120] The embodiment of the present invention further implements the physical neurons of each pulse processing core in the hidden layer and the output layer based on digital circuits to obtain low-power neuron activation and reset with high-speed processing. In a preferred implementation, the circuit structure of each physical neuron in the hidden layer and the output layer is the same, but the synaptic weights connected thereto may differ according to the training update of the input pulses, so the membrane potential and activation state of each physical neuron are not consistent during real-time calculation.

[0121] In a preferred embodiment, Figure 5 As shown, each of the physical neurons (NE) includes: a PE (Processing Element) array consisting of multiple approximate computing units (Approximate Computational Unit, abbreviated as ACU), an approximate addition tree and a pulse emission decision unit; the approximate computing unit has a built-in accumulation control logic circuit and at least one approximate adder; the approximate addition tree is composed of multiple approximate adders added in pairs in a hierarchical manner.

[0122] The PE array is used to access the local pulse sequence of the binary image in batches, and issue each pulse of the local pulse sequence to the corresponding approximate calculation unit for independent parallel summation; and perform the accumulation calculation of multiple local pulse sequences of the binary image in batches by time-division multiplexing of the multiple approximate calculation units to obtain the membrane potential increment accumulated by each approximate calculation unit;

[0123] Each of the approximate computing units (ACU) is further used to update the local membrane potential of the physical neuron distributed in the current approximate computing unit at the current moment according to the preset neuron model using the membrane potential increment accumulated at each batch moment;

[0124] The approximate addition tree is used to sum the local membrane potential output by each approximate calculation unit to obtain the membrane potential of the physical neuron corresponding to the connected binary image;

[0125] The pulse emission decision unit is used to compare the membrane potential summarized by the approximate addition tree with the activation threshold to determine whether to activate the current physical neuron; if the current physical neuron is not activated, the membrane potential of the current physical neuron is attenuated according to a preset neuron model; if the current physical neuron is activated, a new pulse is emitted to the next layer of neurons, and after the physical neuron is activated and emits a pulse, the membrane potential of the current neuron is reset according to the preset neuron model.

[0126] During the reasoning process, the controller 200 in the pulse processing core is used to control the operation of the entire reasoning subsystem, is responsible for managing and coordinating the operation of each internal device, receives the time step information sent by the neuron timing generator 100 and the feedback information of other modules, and performs correct timing and function control on the entire reasoning process. The synaptic core 300 is used to store the synaptic weights of the synapses connected to each physical neuron through the built-in memory 301, and receives the pulse signal sent from the input end or the previous layer (for the three-layer SNN, it is the hidden layer) of the neuron. In the reasoning stage, the synaptic core 300 will transmit the synaptic weights corresponding to each physical neuron to the neuron computing core 400 through the first arbitrator 302 to participate in the reasoning calculation. The neuron computing core 400 is built-in with a pipeline neuron sequence 401 composed of multiple physical neurons (NE), and the neuron computing core 400 stores the parameters such as the membrane potential, activation threshold and activation state of each physical neuron. These parameters can be obtained in advance through offline training before online training, and are pre-stored in the neuron storage 403 space inside it. Each physical neuron (NE) in the neuron computing core 400 includes an approximate computing array (i.e., PE array), an approximate addition tree, and a neuron pulse emission unit to simulate the membrane potential changes of biological neuron cells. In one neuron time, the membrane potential of the neuron is calculated using the approximate computing array and the approximate addition tree, and the membrane potential is sent to the neuron pulse emission unit at each time step. The second arbitrator 402 compares the preset neuron model (e.g., the optimized IF or LIF model) with the activation threshold, and then determines whether the current physical neuron emits a pulse in conjunction with the pulse emission decision unit, and stores the neuron membrane potential after reset or leakage.

[0127] In the embodiment of the present invention, the multiple physical neurons (NE) built into the neuron computing core 400 form a pipeline structure, which sequentially transmits the pulse sequence of the connected binary image; and each physical neuron uses a time division multiplexing method, through the built-in multiple approximate computing units (ACU), each clock cycle will distribute the corresponding input multiple pulses to each of the above ACUs for parallel computing, and realize the accumulation of the local membrane potential of the current physical neuron according to the neuron model. Figure 5 The multiple approximate computing units (ACUs) shown in the figure form a one-dimensional PE array with less resource usage, which can significantly reduce the area and power consumption of the circuit. Then, through time division multiplexing, the pulse sequence of the input image is input into the physical neuron in batches according to the clock cycle for parallel superposition, thereby achieving a better computing efficiency. Specifically, the pulse sequence corresponding to a row or column (the number is M) of pixels can be input each time, so the PE array of the physical neuron is composed of M ACUs in parallel. By multiplexing N times, all pulse signals of the input image of M×N scale can be transmitted to the physical neuron for membrane potential calculation. Therefore, through certain instruction control, input images of various scales can be processed under limited hardware resources.

[0128] In the pulse processing core, the adder is the core component of the approximate computing unit and the approximate addition tree of the PE array. In order to obtain a hardware-friendly low-power, fast neuron circuit, simulate the operating mechanism of biological neurons, and calculate the membrane potential of physical neurons, an approximate computing unit ACU is designed. The core circuit of the ACU and the various adders that constitute the approximate addition tree are all approximate adders.

[0129] In a preferred embodiment, the approximate adder is a speculative carry adder with an error correction mechanism. The existing mainstream adder is a ripple carry adder (RCA), but a feature of the ripple carry adder is that the adder at the subsequent stage depends on the carry signal of the previous stage. When the carry signals of this critical path are all 1, the delay of the critical path becomes very large. The longer the critical path, the longer the calculation time of the entire processor, that is, the lower the calculation efficiency. The calculation principle of RCA is expressed as follows by a mathematical formula:

[0130] s i =a i ⊕b i ⊕c i

[0131] c i+1 =a i b i +c i (a i +b i )

[0132] p i =a i +b i

[0133] g i =a i b i

[0134] Among them, a i and b i is the ith input operand, s i The output sum of the input i-th bit, c i is the carry signal of the i-th bit, p i is the carry propagate signal, g i It is the carry generation signal.

[0135] Therefore, the embodiment of the present invention proposes an approximate adder that can reduce the length of the carry propagation chain, and adopts a carry speculation strategy to truncate the length of the carry chain, which can effectively reduce the delay of the critical path while ensuring that the accuracy loss of the adder is small. Specifically, for two input signals a and b to be added with a bit width of n, the signal a and the signal b can be divided into m segments, each sub-signal of which is k bits, that is, n=m*k.

[0136] Assuming that the symbol i is used to represent the serial number of each sub-addition block, this embodiment allocates the m-segment k-bit sub-signals to i propagation carry generators, i.e., k is the sub-signal bit width of the local membrane potential; and for any 1≤i≤m-1, the inferred carry signal of the propagation carry generator in the i-th sub-addition block is is set to the generated signal of the most significant bit of the i-1 block, that is, Among them, the carry signal of carry generator 0 remains And this embodiment assumes that for any 1≤i≤m-1, Indicates the presumed carry signal, which can be obtained by using Replace the real carry signal c at each level i ,get:

[0137]

[0138] Where i represents the current sub-addition block number, j represents the bit number within the sub-addition block, and k represents the bit width of each sub-addition block. represents the generated signal of the k-1th bit in sub-addition block i, represents the propagation signal of the jth bit in sub-addition block i, Represents the approximate carry signal of the i-th sub-addition block.

[0139] From the above definitions, this embodiment draws two conclusions:

[0140] Conclusion 1: If the carry signal generated by the i-th propagation carry generator generates a speculated carry signal of 1, then the real carry signal generated by the i-th carry generator must be 1. The reason is: According to the definition of the signal and the generation principle of the carry signal of the RCA adder, the real carry signal Expanding this formula yields:

[0141]

[0142] in, Equal to the presumed carry signal If it is equal to 1, then Must be 1.

[0143] Conclusion 2: Assumption If P pi =0, that is, the result of the logical "AND" operation of the propagation signal generated by each bit in the sub-addition block is 0, then the inferred carry output must be equal to the real carry output. The reason is: P pi =0, indicating that there is no carry propagation chain from the carry input of the i-th carry generator to its carry output, so the carry output does not depend on the carry input, so the carry output only depends on the locally generated carry. Therefore, the inferred carry output must be 0, and the real carry output must also be 0.

[0144] However, due to the actual situation, there may be P pi =1, this will happen that when the carry signal is estimated to be 0 in this embodiment, the actual carry signal is 1. In this case, an error of level 2i will be generated, which will cause irreparable errors in the entire neural network reasoning or training process. Therefore, in order to reduce this error, the present invention proposes an error correction mechanism: only a "two-choice" multiplexer is inserted between the sub-addition blocks of 1≤i≤m-1. The two input signals of the multiplexer are the generated signal of the previous addition block and the speculative carry signal generated by the previous addition block Select signal as transfer signal P pi . Due to P pi The carry generator of each addition block has been generated, so there is no need to design additional circuits. The circuit function of this embodiment is defined as follows: pi =1, the output of the multiplexer is selected as Otherwise select The output signal is used as the carry input signal of the sub-adder of the current adder block. It can be seen that this modification does not increase the area of ​​the original adder by a lot, but can effectively prevent excessive errors caused by carry errors.

[0145] Furthermore, in the addition of signed numbers, if the sign is wrong, it will lead to a very large calculation error. In the approximate adder, some loss of precision is allowed, but the loss of the sign bit is an unacceptable error. In the present invention, by transmitting the signal P pi and The result of the AND operation is used as the symbol error correction signal S pi , if there is any level of S pi If the signal is 1, the sign error correction circuit is triggered to determine whether to select the approximate carry signal. As the final carry signal, the final sign is corrected to prevent irreversible major errors.

[0146] Next, the relative error of the approximate adder is listed to prove that it is reliable. The relative error between the approximate sum and the correct sum (E re )The formula is as follows:

[0147]

[0148] Among them, S is the result of the exact adder, S apx is the result of the approximate adder, SG i is the result of each stage of precise adder, SG apx,i is the result of each level of approximate adder.

[0149] For the maximum value of the error, according to the above carry generation signal principle, the maximum error is caused by the failure of the m-1th carry signal speculation, so:

[0150]

[0151] Combining the above two formulas, we can see that the maximum relative error is In the present invention, k is greater than or equal to 3. Due to the robustness of the neural network, the error will hardly affect the pulse emission of the neuron.

[0152] The approximate adder with error correction mechanism designed in the present invention can reduce the delay of the critical path, thereby improving the maximum operating frequency of the processor; at the same time, the introduction of the idea of ​​approximate calculation can reduce the complexity of calculation and reduce the operating power consumption of the entire processor; finally, the introduction of the error correction mechanism improves the accuracy of the accumulated result, prevents the system crash caused by approximate calculation, and ensures the robustness of the pulse neural network based on approximate calculation. Experimental results show that the use of the approximate adder has almost no effect on the recognition accuracy of the reasoning and training process of the entire pulse neural network.

[0153] In an embodiment of the present invention, when the neuromorphic processor uses the inference subsystem to perform real-time target recognition on the input image, each physical neuron needs to use the model parameters such as synaptic weights and activation thresholds stored inside it to operate normally. Before online learning or online training, these model parameters such as synaptic weights and activation thresholds need to be obtained in advance through an offline training process. Usually, during offline training, synaptic weights and activation thresholds are obtained by training on an external computing platform through a large number of labeled data sets, and the synaptic weights are iteratively adjusted using optimization algorithms such as gradient descent and back propagation. After the training is completed, the optimized synaptic weights need to be quantized and fixed-point processed before they can be deployed in a neuromorphic processor based on digital circuits for use in the inference stage.

[0154] In an embodiment of the present invention, the neuromorphic processor further includes a training subsystem. The subsystem can access the encoded image pulse sequence and use the training subsystem to update the synaptic weight and activation threshold stored in each physical neuron in real time, so that the neuromorphic processor can be applied to different scenarios in the actual environment, and enhance the adaptability and accuracy of the model in practical applications.

[0155] Specifically, Figure 5 As shown, the training subsystem includes: a controller 200, a neuron comparator 500, an update arbitrator 400, a random number generator 700 and a parameter updater 600. Figure 2 and Figure 3 As shown, in the pulse processing core, the controller 200 combines the neuron comparator, the update arbitrator, the random number generator and the parameter updater to realize the online learning function.

[0156] The controller 200 is used to control the duration of the input pulse sequence received by the neuron, and to control the correct timing and functional operation of the training subsystem.

[0157] The neuron comparator 500 is used to compare and obtain activation states of different physical neurons, and select the most active physical neuron based on the pulse emission rate.

[0158] Preferably, if Figure 6 As shown, the neuron comparator 500 adopts a competitive learning strategy to select the most active neuron. Specifically, the neuron comparator 500 selects the most active physical neuron based on the pulse emission rate, specifically:

[0159] Step S101: performing weighted summation on each pulse signal in the input pulse sequence and the synaptic weight corresponding to the current physical neuron to obtain the cumulative membrane potential of the input pulse sequence;

[0160] Step S102: subtracting the accumulated membrane potential from the activation threshold of the current physical neuron to obtain an accumulated difference;

[0161] Step S103: Assign trigger timings to each pulse signal in the input pulse sequence in order; and perform weighted summation on each pulse signal with a trigger timing and the synaptic weight corresponding to the current physical neuron to obtain the timing-weighted membrane potential of the input pulse sequence. In particular, neurons that need to perform cumulative calculations can be further screened before weighted summation. For example, whether each pulse signal with a trigger timing is greater than or equal to 1, if it is greater than or equal to 1, it is selected as a candidate neuron, and the membrane potential of each candidate neuron is weightedly summed with the synaptic weight to obtain the timing-weighted membrane potential.

[0162] Step S104: taking the ratio of the time-series weighted membrane potential to the accumulated difference as the normalized pulse emission duration of the current physical neuron;

[0163] Step S105: comparing the normalized pulse emission durations of all physical neurons in the hidden layer one by one, and selecting the neuron corresponding to the minimum value as the most active physical neuron in the hidden layer;

[0164] Step S106: Compare the normalized pulse emission durations of all physical neurons in the output layer one by one, and obtain the neuron corresponding to the minimum value as the most active physical neuron in the output layer.

[0165] Combining the above steps S101-S106, the update algorithm flow of the most active neuron in the hidden layer or output layer of the selected network can be shown as follows: Figure 7 As shown, it provides an implementation process of how to determine the shortest pulse time and the update mechanism of selecting the most active neurons.

[0166] First, the parameter updater 600 is initialized (step S201), and the pulse signal Z is input. sorted [i] (Step S202), the pulse signal is an input pulse sequence with a trigger timing (e.g., timing 1, 2, 3, ...), and the accumulated sum of the synaptic weights ∑W of N neurons connected to the current neuron is taken out from the storage 301 of the synaptic core 300 sorted [j], the first arbiter 302 determines each pulse signal Z with a trigger timing sorted [i] is greater than or equal to 1; if so, the synaptic weight index of the candidate neuron is set to 1, the synaptic weight of the neuron is marked as the object to be processed, and the neuron corresponding to the serial number is listed as a candidate update neuron (step S203). In addition, the cumulative sum of the synaptic weights of the i-th candidate neuron ∑W is calculated. sorted [j] and its activation threshold V thCumulative difference of [i] (step S204):

[0167]

[0168] Calculate the output pulse Z with trigger timing of the i-th candidate neuron sorted [i] multiplied by the sum of the synaptic weights of the neuron W sorted [i], get the time-weighted membrane potential C of the input pulse train usum (Step S204), that is

[0169]

[0170] Traverse all input pulses to determine whether the input pulse sequence has been calculated (step S205); if not, continue to perform the above calculation; if so, enter the parameter determination step S206.

[0171] In step S206, if C usum [i] and W cs [i] are all greater than 0, C usum [i] and W cs The ratio of [i] is taken as the normalized pulse duration Z of the neuron. out [i] (Step S207), then select the neurons with the minimum normalized pulse emission duration Z from the neurons in this layer. out The neuron [i] is regarded as the most active neuron to be updated (judged in step S208 and confirmed in step S209). usum [i] and W cs [i] If all are not greater than 0, then filter out W cs [i] The largest neuron (step S210) is taken as the most active neuron that needs to be updated (step S209).

[0172] In resource-constrained hardware implementations, the competitive learning strategy described above is used to update only the most active neurons, which can significantly reduce the consumption of computing resources. The embodiment of the present invention reduces unnecessary computing overhead and improves learning efficiency by focusing on important inputs to update weights and membrane potentials. At the same time, the sparse activation feature reduces energy consumption and helps improve the stability and accuracy of the model.

[0173] The training subsystem further includes an update arbitrator 400 . The update arbitrator 400 is used to receive the output result of the neuron comparator 500 and transmit the most active physical neuron to the parameter updater 600 .

[0174] The update arbitrator 400 is responsible for receiving the results of the neuron comparator 500, determining the state of each neuron, and ultimately determining which neuron needs to be updated. This decision-making process not only takes into account factors such as the membrane potential and synaptic weight of the current neuron, but also evaluates its contribution to the overall performance of the network. Once the neuron that needs to be updated is determined, the arbitrator sends an update signal to the parameter updater 600 to trigger the adjustment of specific weights and activation thresholds. It can be seen that the more active the neuron, the more likely it is that the synaptic weight will be updated, which is in line with the basic characteristics of biological learning.

[0175] At the same time, Figure 5 As shown, the training subsystem introduces a random number generator 700. The function of this module is to increase the flexibility and versatility of the network by introducing a certain degree of randomness. The random number generator 700 generates a pseudo-random number P based on a linear feedback shift register (LFSR). The LFSR is composed of a group of registers. At each clock, the value in the register is shifted, and a new input bit is generated based on the feedback signal of some registers. The shift register and the feedback logic work together to generate a cyclic pseudo-random sequence. The cumulative difference W of the neuron mentioned above is cs Compared with the size of the pseudo-random number P, if W cs If it is greater than P, the next step of parameter update is performed, otherwise the update logic is terminated.

[0176] The parameter updater 600 is used for updating the synaptic weight and activation threshold of the most active physical neuron by using the pseudo-random number and the synaptic weight currently stored in the neuron based on the random online learning strategy of the historical weight.

[0177] In the online training process of this embodiment, the neuron timing generator is also used to generate the time step of the neuron, that is, the time length of the input pulse sequence, which can adjust the representation accuracy of the pulse data after the input image is encoded, that is, it determines how many frames of binary images the input image is encoded into, and the pulse sequence of each frame of the binary image needs to be input into the neuromorphic processor in a certain order for training, so it also determines the number of training rounds in the training subsystem, and each time step will execute a training process. During the training process, the controller is used to control the operation of the entire training subsystem, responsible for managing and coordinating the operation of each submodule, receiving the time step information sent by the neuron time generation module and the feedback information of other modules, and performing correct timing and function control on the entire training process. In the weight update stage, the synaptic core 300 will send the synaptic weight to the parameter updater 600 to participate in the update operation, and receive the updated synaptic weight and store it. During the training process, similarly, the neuron computing core 400 stores parameters such as the membrane potential, activation threshold and activation state of the neuron. Each NE in its built-in pipeline neuron sequence 401 includes an approximate calculation PE array, a neuron pulse emission unit, and an approximate calculation unit ACU and an approximate addition tree according to the optimized LIF / IF neuron model to simulate the membrane potential changes of biological neuron cells. In a neuron time step, the approximate adder in the PE array is used to calculate the partial membrane potential (local membrane potential), and the membrane potential accumulated by the approximate adder will determine the occurrence of the neuron event at the current moment. When the accumulated membrane potential of the neuron exceeds the neuron threshold, a pulse emission event will be triggered, and the membrane potential will be reset to the set reference potential, otherwise the current membrane potential will be attenuated and stored to the next time step. It can be seen that in this embodiment, the training process of the neuromorphic processor of the multi-pulse processing core includes all modules and calculation steps of the reasoning process. That is, during the training process, the training subsystem calls and controls the components of the reasoning subsystem to update the data such as the membrane potential, synaptic weight, activation threshold, etc. of the neuron, and optimize the performance of the pulse neural network.

[0178] Experiments have found that the synaptic weight of a neuron is affected by the pulses of the pre-neuron and post-neuron of the synaptic connection. Specifically, if the pre-neuron pulses first and the post-neuron pulses later, the synaptic weight will increase; if the pre-neuron pulses later and the post-neuron pulses first, the synaptic weight will decrease. Therefore, a synaptic plasticity mechanism can be proposed: Spike Timing Dependent Plasticity (STDP), which is used to implement an online training subsystem. The STDP training subsystem can be fitted with the following equation:

[0179] t in =α(1-input) β

[0180]

[0181] Among them, t in Used to calculate the pulse time of each input neuron; input is the normalized input pixel value, ranging from [0,1], that is, the pulse value (0 or 1) of the binary image obtained after encoding; α and β are used to adjust the constants of time encoding. The larger the pixel input value of the original image, the larger the input pulse time t in The smaller it is, the earlier the input neuron fires its pulse. is the membrane potential of the output neuron, and set C contains the pulse time that is earlier than the output time t of the current neuron. out The input neuron W i represents the synaptic weight, is the time-dependent term of the input pulse, V th is the activation threshold of the neuron. out It is the logarithm of the output neuron membrane potential, representing the time when the output neuron emits a pulse. ΔW represents the change in synaptic weight, which depends on the time difference Δt between the output pulse time and the input pulse time. If the output pulse time is later than the input pulse time (Δt>0), the weight increases; if the output pulse time is earlier than the input pulse time (Δt≤0), the weight decreases. A P and A n is the amplitude parameter of weight change, T p and T n is a time constant. These equations together describe the weight update process of the STDP learning method. However, since the above-mentioned training subsystem adjusts the synaptic weight of the neuron according to the time difference between the previous and next pulses of the synapse, in order to obtain the changing weight ΔW in this STDP learning method, the time difference Δt needs to be accurately obtained, which requires logarithmic and exponential operations to update the synaptic weight. However, these complex mathematical calculations are difficult to accurately implement in digital circuits, and also require a large amount of storage space to save the pulse release of each neuron under the time step, which is obviously not conducive to the rational allocation of hardware resources.

[0182] Therefore, in order to reduce the computational complexity of the weight update stage and reasonably allocate the consumption of hardware resources, the embodiment of the present invention proposes a simplified linear calculation online learning method. Specifically, the training subsystem can adopt a random online learning strategy based on historical weights to implement the update of the synaptic weights and activation thresholds of each physical neuron, reduce the computational complexity, and at the same time, improve the training accuracy and reasoning accuracy of the neuromorphic processor based on hardware implementation.

[0183] In an achievable preferred manner, the random online learning strategy based on historical weights specifically includes:

[0184] If the difference between the current membrane potential of the physical neuron and the current activation threshold (|W cs |) is greater than the pseudo-random number (P), the synaptic weight and activation threshold of the current physical neuron are updated according to the following mathematical model:

[0185]

[0186] Where W(t) represents the updated synaptic weight, W(t-1) represents the synaptic weight before the update, and V th (t) represents the updated activation threshold, V th (t-1) represents the activation threshold before updating, Δt represents the time difference between the release of the pulse by the front neuron and the rear neuron, a and b represent two different weight update amplitudes; c represents the update amplitude of the activation threshold;

[0187] Otherwise (i.e. |W cs |≤P), the synaptic weight and activation threshold of the physical neuron at the current moment remain unchanged.

[0188] Among them, Δt only represents the time difference between the front / rear neurons releasing pulses, that is, if the rear neuron releases a pulse before the front neuron, then Δt is greater than 0, otherwise it is considered to be less than 0. Compared with the traditional STDP algorithm, the embodiment of the present invention no longer needs to store a large amount of historical parameter information, reducing the excessive demand for storage space. a and b are the update amplitude parameters of the synaptic weight, and the setting of this parameter is empirically obtained through a large number of experiments. In a preferred embodiment, it is assumed that a>b, and the synaptic weights with historical records are introduced to participate in the update process of the current synaptic weight, and the historical weight W(t-1) at the previous moment is preferably used. Specifically, when Δt>0, W(t-1)≤0, the weight is increased by a larger value a; when Δt>0, W(t-1)>0, the weight is increased by a smaller value b. If Δt≤0, W(t-1)<0, the weight is reduced by a smaller value b, otherwise it is reduced by a larger value a. The present invention considers how to optimize the expression method of time difference and the weight itself to determine the plasticity of synaptic weight, and uses two parameters a and b to reflect the weight adjustment in different situations. In particular, a can be set to 2 and b can be set to 1. Similarly, the setting of the activation threshold can also be empirically obtained through a large number of experiments. In the embodiment of the present invention, it is preferred to set the activation threshold V thThe update amplitude c of (t) is set to the same value as the update amplitude a of the synaptic weight. Generally, the activation threshold and the update amplitude of the synaptic weight need to be set to the same change amplitude to ensure the normal operation of the physical neuron model. For example, when the value of a is set to 2, the value of c is also set to 2.

[0189] In biological neural systems, the update of synaptic weights is not a deterministic process, but is affected by many factors (such as neuronal activity, voltage changes, neurotransmitter release, etc.), showing a high degree of randomness and probability. By introducing probability to determine whether synaptic weights are updated, this characteristic of biological learning can be better simulated. At the same time, in this way, the system can effectively avoid the problem of network overfitting caused by frequent updates. Overfitting usually causes the network to perform well on training data, but lacks generalization ability in practical applications. In a neural network, the update of each neuron and synapse is independent. By setting the update probability, the network can form a variety of synaptic connections, which helps to cover the input space more widely and improve the prediction ability of unknown data.

[0190] Furthermore, the neuromorphic processor in the embodiment of the present invention also includes a communication subsystem. Figure 1 and Figure 4 As shown, in a preferred embodiment, the communication subsystem is a three-level routing system, including: a zero-level router (L0 routing), a first-level router (L1 routing), and a second-level router (L2 routing).

[0191] The zero-level router (L0 router) is set inside each pulse processing core, and is used to transmit the encapsulated signal of the first-level router to the corresponding pulse processing core, and re-encapsulate the calculation result of the pulse processing core into a data packet and send it to the first-level router. Figure 5 As shown, the L0 router includes a scheduler L01, a packet encoding module L02, a packet decoding module L03, a data buffer (FIFO1) L04 required for encoding, and a data buffer (FIFO2) L05 required for decoding.

[0192] The first-level router (L1 router) is used to collect and encapsulate the data of the zero-level router according to a preset communication protocol to realize the communication transmission of data between various pulse processing cores;

[0193] The secondary router (L2 router) is used to collect the output data of the primary router according to a preset communication protocol to realize data communication between multiple neuromorphic processors composed of pulse processing core clusters, or data communication between a neuromorphic processor and an external circuit.

[0194] in, Figure 4The communication routing characteristics of a neuromorphic processor with multiple pulse processing cores are demonstrated.

[0195] In specific implementation, the secondary router can perform data exchange between the processor and the outside through interface modules in several directions. Specifically, the secondary router (L2 routing) transmits data with the outside through the local interface (LOCAL) and the external interface (EXT.I / F) to ensure the high efficiency and real-time data transmission of a single neuromorphic processor; it can also realize the array combination of multi-core neuromorphic processors through four directional interfaces, East (EAST), South (SOUTH), West (WEST), and North (NORTH), so as to build a neuromorphic processor with a larger computing scale.

[0196] The three-level on-chip routing transmission pulse data packet is used to obtain a pulse sequence after preprocessing the input image data, and is transmitted to the pulse processing core through the three-level routing structure for data preparation in the inference stage. Figure 8 Provides a package format for data packets distributed in various levels of routing. Figure 8 As shown in the figure, the contents of the pulse data packet (Package) include flow control units (Flits) for different transmission information: routing path, chip selection (signal), (input) pulse sequence, neuron type, image dimension, number of neurons and synaptic weight. The purpose of decomposing the package into multiple Flits is to better control the transmission of smaller Flits between routes and prevent route blocking. Each Flits records the above different transmission information respectively.

[0197] Level 2 Router (L2): L2 routing is responsible for the highest level of on-chip connections, with five different parallel links leading to the east, west, south, north, and local directions. For L2 routing, pulse data is sent to the local or other four directions of L2 routing based on the routing path of the pulse data packet (Package). L2 routing is controlled by a polling arbitrator, which cycles the communication in each link direction in turn. When a path in one direction is allowed, its next permission time is at most the time to traverse the other four paths, ensuring the maximum delay required to process the data packet.

[0198] Level 1 router (L1): L1 router preferably adopts on-chip routing with a star structure, which can determine the number of pulse processing cores to be used, and can reach one to four hidden layers of pulse processing cores to process input pulses in parallel. The pulse processing core of the output layer will only send data to the processing core for calculation and output after the pulse processing cores of the above four hidden layers have completed calculations. In L1 routing, for the pulse data packet (Package) from L2 routing, the pulse data packet is re-encapsulated as follows Figure 8 The flow control unit (Flits) shown contains different transmission information, through the input cache, waits for the on-chip routing path calculation module to obtain the transmission path according to the chip selection signal, and then determines the pulse processing core to which each Flits should flow according to the input chip selection signal through the polling arbitration module. For example, the input chip selection signal, through the L1 routing calculation path, determines that the pulse data packet is sent to one of the hidden layer pulse processing cores 1, 2, 3, and 4. The four cores receive the pulse sequences of different time steps of the same image after Poisson encoding, and process all pulse sequences in parallel. After the four cores have finished processing, the hidden layer pulses are sent to the output layer pulse processing core for calculation of the output layer neurons.

[0199] Zero-level router (L0 router): L0 router is the lowest level router in the pulse processing core. For the encapsulated signal from L1 router, Flits are sent to the computing core for processing according to the control of the scheduler. For the local calculation results, an encoder is used to package each Flits into a pulse data packet, and then FIFO is used to temporarily store and wait for the control signal to be sent to the upper level L1 router.

[0200] After three levels of routing, the data involved in the reasoning process or training process is routed through L0, and according to the control of the scheduler, the Flits are sent to the physical neurons for reasoning calculation or training learning. Figure 1 In the figure, white neurons represent virtual neurons, which are only used to receive input pulse sequences and do not actually perform calculations. They are only used to receive input pulses. Black neurons represent neurons in the hidden layer or output layer. There is a physical circuit to implement the neuron model to determine the generation of pulses.

[0201] In an achievable preferred embodiment, the entire reasoning process of the neuromorphic processor provided by the present invention for object recognition of an input image based on the above three-level on-chip routing is as follows:

[0202] (1) Multi-size image processing and network construction: According to the image dimension signal in the Flits of the pulse data packet, the ratio M*N of the input image can be determined (for example, if M is 14 and N is less than or equal to 28, an input image of 14*14 pixels or 14*28 pixels is obtained). At the same time, this signal also determines the number of virtual neurons, that is, the number of virtual neurons in the input layer used to receive the input pulse sequence. For input images of different sizes, it can be ensured that the image is not distorted. Specifically, M virtual neurons can be used to simultaneously receive the pulses corresponding to a row of pixels, and access the entire frame of the image in batches (N times); N virtual neurons can also be used to simultaneously receive the pulses corresponding to a row of pixels, and access the entire frame of the image in batches (M times); and when the input image size is not large, M×N virtual neurons can be used to simultaneously access all pixels of the entire frame of the image. The neuron number signal in the encapsulated pulse data packet will determine the number of physical neurons in the hidden layer to meet the construction requirements of neural networks of different sizes, such as lightweight or large.

[0203] (2) Data preparation of the synaptic core 300 and the neuron computing core 400: According to the synaptic weights and input pulse sequences in the Flits of the pulse data packet, the synaptic core 300 and the neuron computing core 400 respectively receive and store the corresponding synaptic weights and neuron initial states for further inference calculations.

[0204] (3) Inference calculation in the hidden layer physical neuron approximate calculation array: After determining the input image size and the number of neurons, according to the data structure required by the approximate calculation array, the neuron calculation core 400 has received the input pulse sequence from the L0 reason, and fetched the corresponding synaptic weight from the synaptic core 300, and calculated the membrane potential of the neuron in the PE array in the NE. When a neuron time step is completed, the accumulated membrane potential at the current moment is sent to the neuron pulse emission decision unit.

[0205] (4) The neuron pulse emission decision unit determines the neuron pulse event: When the neuron pulse emission decision unit obtains the neuron membrane potential output by the approximate calculation array, it will determine the event state of the neuron at the current moment based on the aforementioned neuron model.

[0206] (5) The on-chip three-level routing aggregates the pulses of the hidden layer neurons and transmits them: After the neuron time ends, the reasoning stage of all neuron time steps is carried out. At the last neuron step, the on-chip three-level routing will aggregate the pulse sequences of all output neurons in the neuron time. This result has two transmission directions: ① The pulse processing core (pulse processing core 0) where the output layer neurons are located: If the pulse aggregation of all hidden layer neurons has been completed, the output pulses of the hidden layer are transmitted to the next output layer through the L1 routing to continue the reasoning stage. The reasoning process is the same as the above process. ② The pulse processing core (pulse processing core 1, 2, 3, 4) where the next hidden layer neurons are located: If there are still neurons in the next hidden layer (multiple hidden layers) that have not been calculated, the output pulses of the hidden layer are transmitted to the next hidden layer through the L1 routing to continue the reasoning stage. The reasoning process is the same as the above process. When all hidden layer neurons are calculated, they will be sent to the pulse processing core where the physical neurons of the output layer are located to calculate the output layer pulses.

[0207] (6) Identification and reasoning results: If all hidden layer neurons are calculated, without on-chip training, the encapsulated pulse data packets will pass through the three-level on-chip routing after calculation by the physical neurons of the output layer, and the final recognition results will be output by the L2 routing, completing the entire reasoning process of the input image.

[0208] Fig. 9 A realizable structural diagram of the second-level router in the on-chip three-level router is provided. The structure and implementation principle of the first-level router and the zero-level router are similar to those of the second-level router.

[0209] like Fig. 9 As shown, the L2 router is divided into three pipeline stages, corresponding to stage 1 (path calculation), stage 2 (switching), and stage 3 (transmission). Different tasks are assigned to each stage through the scheduler.

[0210] Stage 1: Path Calculation

[0211] In this stage, the router receives the encapsulated data packet from the input buffer. The encapsulation format of the data packet is as follows: Figure 8 As shown in the figure, it contains key information such as path information and input data. The data packet is decomposed into multiple Flits, each of which contains key information such as path information and input data. The routing calculation module determines the next transmission direction of the data packet by parsing this information. The calculation result (i.e., the transmission direction) is stored in the RC register for use in subsequent stages.

[0212] Stage 2: Switching

[0213] In the second stage, the path information in the RC register is transmitted to the switching module, which is responsible for matching the output channel of the data packet with the path information and generating the corresponding path permission signal. This signal is then stored in the SW register to prepare for the next step of data transmission.

[0214] Stage 3: Transmission

[0215] In the final stage, according to the arbitration result of the path permission signal, the data packet is transmitted to the specified output port (south, north, east, west or local) through the crossbar. Finally, the data packet is sent to the next router node through the output buffer to complete the data packet forwarding task.

[0216] This three-stage pipeline structure significantly improves the throughput of the router and the efficiency of packet forwarding, ensuring that data packets can be transmitted quickly and efficiently in the network.

[0217] The L2 routing connects the routing nodes of the neuromorphic processor. It can be seen that the data can flow in certain paths after certain arbitration, namely east, south, west, north and local directions, to achieve an array combination of multiple neuromorphic processors. The L1 routing connects the five pulse processing cores to achieve data flow between the internal pulse processing core and the external top-level processor.

[0218] Fig.10 The multi-core processing system using the three-level on-chip routing architecture of the embodiment of the present invention is shown in FIG. Fig.10 As shown. The top layer adopts a Mesh structure composed of L2 routing to connect various L2 routing nodes. Through appropriate arbitration mechanisms, data packets can flow along the east-west, south-north, and local directions. The local direction is connected to the L1 routing, and the remaining directions are the L2 routing of other nodes. In the L1 routing layer, the L0 routing of the five pulse processing cores is connected, which replaces the routing nodes in the east-west, south-north, and local directions respectively. The transmission directions are pulse processing core 0 (output layer pulse processing core), 1 (hidden layer pulse processing core), 2 (hidden layer pulse processing core), 3 (hidden layer pulse processing core), and 4 (hidden layer pulse processing core). The five pulse processing cores transmit pulse data packets through the communication between L1 routing and L0 routing, forming an on-chip routing system with a star topology. In the bottom L0 routing, the pulse data packet is decoded into the corresponding input signal and sent to the pulse processing core for processing. After the processing is completed, the output signal is re-encoded into a pulse data packet, and the data communication between different processing cores is carried out through L1 routing.

[0219] In summary, the embodiment of the present invention achieves higher computing speed and accuracy on the basis of ensuring efficient network transmission. Among them, three aspects of improvement are mainly made: optimization of neuron approximate computing kernel, optimization of online learning method, and optimization of on-chip routing design. First, in the SNN processor, the adder is a key component for performing neuron membrane potential accumulation and weight update. In order to solve the impact of the large area and high delay of the carry-lookahead adder on the performance of the SNN system, a new approximate computing method is proposed-a high-precision approximate computing adder design with an error correction module. By adopting this new adder design, not only can the area of ​​the adder be reduced and the operating frequency be increased, but also the overall performance of the processor can be improved. At the same time, in order to further reduce energy consumption, the system sets a shutdown mechanism for idle neurons to optimize energy use while ensuring processing efficiency. Second, the traditional online learning method of time synaptic plasticity STDP is improved, and an improved random STDP learning method based on historical weights (Weighted-STDP, referred to as W-STDP) is proposed, which improves the training accuracy, reduces the use of storage space, and reduces the area of ​​the logic circuit related to weight update. Third, a hierarchical routing strategy and a multi-directional data transmission strategy are adopted, and combined with a flexible SNN core connection design, on-chip routing is optimized to achieve efficient data processing and transmission.

[0220] Furthermore, in order to demonstrate the performance improvement of the neuromorphic processor provided by the present invention in terms of recognition accuracy and computing efficiency, this embodiment has developed a neuromorphic processor with the parameters shown in Table 1 based on a 40 nanometer (nm) CMOS process, and has conducted a detailed evaluation of its frequency, power consumption and area; and further verified the training accuracy and inference accuracy of the neuromorphic processor provided by the present invention on the MNIST handwritten digit dataset (the dataset includes ten categories of handwritten digit images of the digits 0-9, including 70,000 handwritten digit images, 60,000 training images and 10,000 test images. This embodiment uses these two types of images as training sets and test sets, respectively.)

[0221] Table 1: Parameters of the neuromorphic processor proposed in this invention

[0222]

[0223]

[0224] As shown in Table 1, the neuromorphic processor proposed in this embodiment is implemented based on 40nm digital technology, integrates 330 neurons and 128640 synapses, supports online learning, uses random and simplified STDP algorithms, and has a weight of 4 bits. The processor occupies an area of ​​1.01mm 2, the operating voltage is 0.8V, the maximum frequency is 333MHz, and the dynamic power consumption is 75.6μW / MHz.

[0225] As shown in the experimental results in Table 2, the maximum operating frequency of the neuromorphic processor is 333MHz and the area is 1.01mm under the 40nm CMOS process. 2 , the total power consumption is 29.9mW, and the dynamic power consumption is 25.2mW. On the MNIST dataset, after on-chip training, the inference accuracy can reach 95%, which is higher than the 89% accuracy of offline training on the dataset in the same network structure. Compared with other processors with similar functions, the neuromorphic processor in the present invention has advantages in area, power consumption and recognition accuracy.

[0226] Table 2: Comparison with other previous neuromorphic processors with online functions

[0227]

[0228] Table 2 shows the comparison between this embodiment and other online learning neuromorphic processors. In comparison, the processor of this embodiment has a larger number of neurons (330) at the same technology node, and the classification accuracy on the MNIST dataset reaches 95%, which is higher than most other comparison processors. In addition, the processor has a 1.01mm 2 It achieves high learning ability and power efficiency within the normalized area, showing superior performance. Although the processor of this embodiment uses a synaptic bit width of 4 bits, while other processors use synaptic bit widths ranging from 1 bit to 9 bits, the processor of this embodiment still achieves a good balance between power consumption and accuracy. For example, compared with the 65nm processor in TBCAS2019, the processor of this embodiment has higher accuracy on the MNIST data set, and its dynamic power consumption is 75.6μW / MHz, which is much lower than some processors with larger bit widths (such as TCAS2022, which uses 311.3μW / MHz of a processor with 9-bit synapses).

[0229] The neuromorphic processor of this embodiment has shown significant advantages in terms of the number of neurons, processing accuracy, power efficiency and area utilization through reasonable design and optimization. This makes it not only superior to existing similar processors in performance, but also achieves a good balance between power consumption and integration, providing strong support for future neuromorphic computing applications.

[0230] This embodiment combines biologically inspired computing models and hardware designs to propose a processor design system that can dynamically update and efficiently handle complex tasks. It is a low-power, high-precision, online-learning processor based on pulse neural networks that can efficiently simulate the complex computing functions of biological neural systems. This design system can not only significantly improve computing speed and energy efficiency, but also reduce the hardware resource consumption of processor design. The system is suitable for various industries that require neural network computing, such as medical image processing, autonomous driving, intelligent monitoring systems, and smart transportation. To solve the problems existing in the above-mentioned prior art.

[0231] Currently, neuromorphic processors are widely used in the field of intelligent computing. This embodiment provides a neuromorphic processor microarchitecture based on online learning and approximate computing, which improves the energy efficiency and response speed of the processor while ensuring the calculation accuracy of the processor. This embodiment mainly focuses on two technical issues: one is how to effectively reduce the hardware resource overhead and energy consumption of the neuromorphic processor, thereby improving the overall computing efficiency of the processor and meeting real-time processing requirements; the second is how to make full use of the online learning mechanism while reducing resource overhead to improve the processor's adaptability and processing accuracy to dynamic tasks. Ultimately, by combining bio-inspired computing models and hardware design, an efficient and flexible neuromorphic processor architecture is provided that can dynamically update and efficiently process complex tasks in practical applications.

[0232] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A neuromorphic processor capable of online learning based on approximate computing, characterized in that: include: Reasoning subsystem, training subsystem, and communication subsystem; The reasoning subsystem includes an input layer, a hidden layer and an output layer, wherein the hidden layer includes a plurality of pulse processing cores for parallel processing, and the output layer includes at least one pulse processing core; each pulse processing core includes a plurality of physical neurons established by a preset neuron model; The reasoning subsystem is used to perform approximate calculations on the multi-scale input image connected to the input layer after encoding based on the pre-stored synaptic weights and activation thresholds through the pulse processing cores in the hidden layer and the output layer, and to count the calculation results of multiple time steps in a time window to generate a recognition result of the multi-scale input image; The training subsystem is used to access multiple images to the hidden layer and the output layer using the input layer, and update the synaptic weight and the activation threshold using a random online learning method based on historical weights; The reasoning subsystem is further used to update the recognition result of the multi-scale input image by performing approximate calculations through the pulse processing cores in the hidden layer and the output layer based on the synaptic weights and activation thresholds updated after training; The communication subsystem is used to perform multi-level routing control on the data transmission between the reasoning subsystem and the training subsystem through a hierarchical routing architecture.

2. The online learning neuromorphic processor based on approximate computing according to claim 1, characterized in that: The input layer includes a plurality of virtual neurons, the number of which matches the scale of the input image, and is used to access a pulse sequence of a binary image after rate encoding the input image; The pulse processing cores in the hidden layer and the output layer are both equipped with synaptic cores and neuron computing cores; the synaptic cores pre-store synaptic weights obtained through pre-training; the neuron computing cores pre-store activation thresholds obtained through pre-training; the neuron computing cores are equipped with multiple physical neurons; the multiple physical neurons form a pipeline structure to sequentially transmit the pulse sequence of the connected binary image.

3. The online learning neuromorphic processor based on approximate computing according to claim 1, characterized in that: Each of the physical neurons comprises: a PE array consisting of a plurality of approximate computing units, an approximate addition tree and a pulse emission decision unit; the approximate computing unit is built with an accumulation control logic circuit and at least one approximate adder; the approximate addition tree is composed of a plurality of approximate adders added in pairs in a hierarchical manner; The PE array is used to access the local pulse sequence of the binary image in batches, and issue each pulse of the local pulse sequence to the corresponding approximate calculation unit for independent parallel summation; and perform the accumulation calculation of multiple local pulse sequences of the binary image in batches by time-division multiplexing of the multiple approximate calculation units to obtain the membrane potential increment accumulated by each approximate calculation unit; Each of the approximate calculation units is further used to update the local membrane potential of the physical neuron distributed in the current approximate calculation unit at the current moment according to the preset neuron model using the membrane potential increment accumulated at each batch moment; The approximate addition tree is used to sum the local membrane potential output by each approximate calculation unit to obtain the membrane potential of the physical neuron corresponding to the connected binary image; The pulse emission decision unit is used to compare the membrane potential summarized by the approximate addition tree with the activation threshold to determine whether to activate the current physical neuron; if the current physical neuron is not activated, the membrane potential of the current physical neuron is attenuated according to a preset neuron model; if the current physical neuron is activated, a new pulse is emitted to the next layer of neurons, and after the physical neuron is activated and emits a pulse, the membrane potential of the current neuron is reset according to the preset neuron model.

4. The online learning neuromorphic processor based on approximate computing according to claim 1, characterized in that: The neuron model includes a neuron charging model, and the mathematical model of the neuron charging model is: V(t)=V(t-1)+X(t), or or Among them, V(t) is the membrane potential of the neuron at the current moment, V(t-1) is the membrane potential of the neuron at the previous moment, and X(t) is the membrane potential increment formed by the input pulse at the current moment. is the preset membrane potential attenuation factor; V rst Reset baseline potential for the neuron.

5. The online learning neuromorphic processor based on approximate computing according to claim 1, characterized in that: The neuron model includes a neuron reset model: V(t + )=V rst , or Among them, the V(t + ) is the reset membrane potential of the neuron at the current moment, V(t - ) is the pre-reset membrane potential of the neuron at the current moment; V rst is a preset reset reference potential; is the preset membrane potential attenuation factor; V th is the activation threshold of the current neuron.

6. The online learning neuromorphic processor based on approximate computing according to claim 1, characterized in that: The training subsystem includes: a controller, a neuron comparator, an update arbitrator, a random number generator and a parameter updater; The controller is used to control the duration of the input pulse sequence received by the neuron, and to control the correct timing and functional operation of the training subsystem; The neuron comparator is used to compare and obtain the activation states of different physical neurons, and select the most active physical neuron based on the pulse emission rate; The update arbitrator is used to receive the output result of the neuron comparator and transmit the most active physical neuron to the parameter updater; The random number generator is used to generate pseudo-random numbers by using a shift operation based on a linear feedback shift register; The parameter updater is used for a random online learning strategy based on historical weights, and updates the synaptic weight and activation threshold of the most active physical neuron using the pseudo-random number and the synaptic weight currently stored in the neuron.

7. The online learning neuromorphic processor based on approximate computing according to claim 6, characterized in that: The random online learning strategy based on historical weights specifically includes: If the difference between the current membrane potential of the physical neuron and the current activation threshold is greater than the pseudo-random number, the synaptic weight and activation threshold of the current physical neuron are updated according to the following mathematical model: Where W(t) represents the updated synaptic weight, W(t-1) represents the synaptic weight before the update, and V th (t) represents the updated activation threshold, V th (t-1) represents the activation threshold before updating, Δt represents the time difference between the release of the pulse by the front neuron and the rear neuron, a and b represent two different weight update amplitudes; c represents the update amplitude of the activation threshold; Otherwise, the synaptic weights and activation thresholds of the physical neurons at the current moment remain unchanged.

8. The online learnable neuromorphic processor based on approximate computing according to claim 6, characterized in that: The neuron comparator selects the most active physical neuron based on the pulse firing rate, specifically: Perform weighted summation on each pulse signal in the input pulse train and the synaptic weight corresponding to the current physical neuron to obtain the cumulative membrane potential of the input pulse train; Subtracting the accumulated membrane potential from the activation threshold of the current physical neuron to obtain an accumulated difference; Allocating trigger timings to the respective pulse signals in the input pulse sequence in sequence; and performing weighted summation on each pulse signal with a trigger timing and the synaptic weight corresponding to the current physical neuron to obtain a timing-weighted membrane potential of the input pulse sequence; The ratio of the time-series weighted membrane potential to the accumulated difference is used as the normalized pulse emission duration of the current physical neuron; Compare the normalized pulse emission durations of all physical neurons in the hidden layer one by one, and select the neuron corresponding to the minimum value as the most active physical neuron in the hidden layer; The normalized pulse emission durations of all physical neurons in the output layer are compared one by one, and the neuron corresponding to the minimum value is the most active physical neuron in the output layer.

9. The online learnable neuromorphic processor based on approximate computing according to claim 3, characterized in that: The approximate adder is a speculative carry adder with an error correction mechanism.

10. The online learning neuromorphic processor based on approximate computing according to claim 1, characterized in that: The communication subsystem is a three-level routing system, including: a zero-level router, a first-level router, and a second-level router; The zero-level router is arranged inside each pulse processing core, and is used to transmit the encapsulated signal of the first-level router to the corresponding pulse processing core, and re-encapsulate the calculation result of the pulse processing core into a data packet and then send it to the first-level router; The first-level router is used to collect and encapsulate the data of the zero-level router according to a preset communication protocol to realize the communication and transmission of data between various pulse processing cores; The secondary router is used to collect the output data of the primary router according to a preset communication protocol to realize data communication between multiple neuromorphic processors composed of pulse processing core clusters, or data communication between a neuromorphic processor and an external circuit.

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