Semiconductor device and semiconductor system including the same

Abstract

The invention discloses a semiconductor device and a semiconductor system including the same. The semiconductor device includes: a plurality of pads; a data pattern analysis circuit configured to generate an analysis signal by analyzing a data pattern of each of the data mapped to each of the plurality of pads; a data remapping circuit configured to redetermine a relationship between the data and the plurality of pads based on the analysis signal, and remap the data with the plurality of pads based on the redetermined relationship; and an output circuit configured to output the remapped data through the plurality of pads.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0098157, filed on Jul. 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor design technology, and more particularly, to a semiconductor device including an interface and a semiconductor system including the semiconductor device. Background Art

[0004] The semiconductor system may include semiconductor devices, and each of the semiconductor devices may include an interface for transmitting / receiving signals between the semiconductor devices.

[0005] As semiconductor systems operate at high speeds and with high levels of integration, the frequency of errors in the transmission of signals through interfaces has increased. Errors can occur for a variety of reasons. One of the reasons is crosstalk between transmission lines that transmit signals. In other words, crosstalk refers to the unintended distortion of signals transmitted through physically adjacent transmission lines due to the connection between the transmission lines. Summary of the invention

[0006] Various embodiments of the present disclosure relate to a semiconductor device that remaps (or reorders) a signal and a transmission line when the signal is transmitted through the transmission line, and a semiconductor system including the semiconductor device.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a plurality of pads; a data pattern analysis circuit configured to generate an analysis signal by analyzing a data pattern of each of the data mapped to each of the plurality of pads; a data remapping circuit configured to redetermine a relationship between the data and the plurality of pads based on the analysis signal, and remap the data to the plurality of pads based on the redetermined relationship; and an output circuit configured to output the remapped data through the plurality of pads.

[0008] According to an embodiment of the present disclosure, an electronic device may include: a plurality of pads; and a processor, configured to update a correspondence between the plurality of data and the plurality of pads based on a data pattern of each of the plurality of data input into the processor, and output a plurality of remapped data through respective corresponding pads among the plurality of pads based on the updated correspondence.

[0009] According to an embodiment of the present disclosure, a semiconductor system may include: a first semiconductor device, configured to calculate a crosstalk score of a plurality of first data based on a predetermined remapping strategy, redetermine a correspondence between the plurality of first data and a plurality of first pads based on the crosstalk score, and generate a plurality of remapped data corresponding to the plurality of first data according to the redetermined correspondence; and a second semiconductor device, configured to receive the plurality of remapped data and generate a plurality of second data corresponding to the plurality of first data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor system according to an embodiment of the present disclosure.

[0011] Figure 2 yes Figure 1 The block diagram of the transmitter is shown.

[0012] Figure 3 yes Figure 2 A block diagram of a first processor is shown.

[0013] Figure 4 yes Figure 1 A block diagram of the receiver is shown.

[0014] Figure 5 yes Figure 4 A block diagram of a second processor is shown.

[0015] Figure 6 and Figure 7 is a diagram illustrating the operation of an image sensor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure are described below with reference to the accompanying drawings in order to describe the present disclosure in detail so that a person skilled in the art to which the present disclosure belongs can easily implement the technical spirit of the present disclosure.

[0017] It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or directly coupled to another element, or electrically connected to or electrically coupled to another element with one or more elements interposed therebetween. In addition, it should also be understood that when used in this specification, unless otherwise stated, the terms "include", "have" and "include" do not exclude the presence of one or more other elements, but may further include or have one or more other elements. In the description throughout the specification, some components are described in singular form, but the present disclosure is not limited thereto, and it will be understood that these components may be formed in plural form.

[0018] Figure 1 is a block diagram illustrating a semiconductor system 10 according to an embodiment of the present disclosure.

[0019] Reference Figure 1 , the semiconductor system 10 may include a first semiconductor device 100 and a second semiconductor device 200. Each of the first semiconductor device 100 and the second semiconductor device 200 may be an electronic device. In an embodiment, the electronic device may refer to a device including a semiconductor device or a device included in a semiconductor device.

[0020] The first semiconductor device 100 may calculate a crosstalk score of the data DOUT<0:N> based on a predetermined remapping strategy, where "N" is a natural number. The crosstalk score is a numerical value of a factor that affects the crosstalk that occurs between the data DOUT<0:N>. The first semiconductor device 100 may redetermine or update the relationship (e.g., a corresponding relationship) between the data DOUT<0:N> and the first pad based on the crosstalk score, and generate transmission data S<0:N> corresponding to the data DOUT<0:N>, respectively, according to the redetermined or updated corresponding relationship. The output data DOUT<0:N> may include a plurality of data, i.e., N+1 bits.

[0021] The first semiconductor device 100 may include a transmitter TX. The transmitter TX may generate transmission data S<0:N> based on the data DOUT<0:N>.

[0022] The second semiconductor device 200 may receive the transmission data S<0:N> and generate data DIN<0:N> respectively corresponding to the data DOUT<0:N>.

[0023] The second semiconductor device 200 may include a receiver RX. The receiver RX may generate data DIN<0:N> based on the transmission data S<0:N>.

[0024] Figure 2 It is shown Figure 1 FIG. 1 is a block diagram of a transmitter TX included in the first semiconductor device 100. For example, Figure 2 The first to eighth pads T0 to T7 are shown, ie, N=7.

[0025] Reference Figure 2 , the transmitter TX may include a first processor 102 and first to eighth pads T0 to T7.

[0026] The first processor 102 can redetermine or update the correspondence between the first to eighth data DOUT<0:7> and the first to eighth pads T0 to T7 based on the respective data patterns of the first to eighth data DOUT<0:7>, and output the first to eighth data DOUT<0:7> through the respective corresponding pads among the first to eighth pads T0 to T7 based on the redetermined or updated correspondence.

[0027] The first pad T0 may be used to rearrange the first transmission data S of the first to eighth data DOUT<0:7>. <0> Sent to the second semiconductor device 200 .

[0028] The second pad T1 may be used to rearrange the second transmission data S of the first to eighth data DOUT<0:7>. <1> Sent to the second semiconductor device 200 .

[0029] The third pad T2 may be used to rearrange the third transmission data S of the first to eighth data DOUT<0:7>. <2> Sent to the second semiconductor device 200 .

[0030] The fourth pad T3 may be used to rearrange the first to eighth data DOUT<0:7> into the fourth transmission data S <3> Sent to the second semiconductor device 200 .

[0031] The fifth pad T4 may be used to rearrange the first to eighth data DOUT<0:7> into the fifth transmission data S <4> Sent to the second semiconductor device 200 .

[0032] The sixth pad T5 may be used to rearrange the first to eighth data DOUT<0:7> into the sixth transmission data S <5> Sent to the second semiconductor device 200 .

[0033] The seventh pad T6 may be used to rearrange the first to eighth data DOUT<0:7> into the seventh transmission data S <6> Sent to the second semiconductor device 200 .

[0034] The eighth pad T7 may be used to rearrange the first to eighth data DOUT<0:7> into the eighth transmission data S <7> Sent to the second semiconductor device 200 .

[0035] Figure 3 yes Figure 2 A block diagram of the first processor 102 is shown.

[0036] Reference Figure 3 , the first processor 102 may include a data pattern analysis circuit 110 , a data remapping circuit 120 , and an output circuit 130 .

[0037] The data pattern analysis circuit 110 may analyze the data pattern of each of the first to eighth data DOUT<0:7> based on the clock signal CLK and the first to eighth data DOUT<0:7> mapped to each of the first to eighth pads T0 to T7 at each cycle of the clock signal CLK, and generate first to eighth analysis signals AN<0:7> corresponding to the analysis results. The first to eighth analysis signals AN<0:7> and the first to eighth data DOUT<0:7> may correspond one to one. The first to eighth analysis signals AN<0:7> may include mapping information related to the number of transitions of each of the first to eighth data DOUT<0:7>.

[0038] The mapping information may include: the number of valid data #1 having a high logic level in each of the first to eighth data DOUT<0:7>, the number of valid data #0 having a low logic level in each of the first to eighth data DOUT<0:7>, the number of times #post_odd that each of the first to eighth data DOUT<0:7> transitions from a low logic level to a high logic level in an odd cycle of the clock signal CLK, the number of times #post_even that each of the first to eighth data DOUT<0:7> transitions from a low logic level to a high logic level in an even cycle of the clock signal CLK, the number of times #negt_odd that each of the first to eighth data DOUT<0:7> transitions from a high logic level to a low logic level in an odd cycle of the clock signal CLK, the number of times #negt_even that each of the first to eighth data DOUT<0:7> transitions from a high logic level to a low logic level in an even cycle of the clock signal CLK, and the total number of times tot_tran that each of the first to eighth data DOUT<0:7> transitions (see Figure 4 ).

[0039] The data remapping circuit 120 may re-determine the correspondence relationship based on the first to eighth analysis signals AN<0:7> and the first to eighth data DOUT<0:7>, and generate the first to eighth remapped data DM<0:7> corresponding to the first to eighth data DOUT<0:7>, respectively, according to the re-determined correspondence relationship. The first to eighth remapped data DM<0:7> and the first to eighth data DOUT<0:7> may correspond one to one. That is, the data remapping circuit 120 may remap the first to eighth data DOUT<0:7> to the first pad T0 to the eighth pad T7 according to the first to eighth analysis signals AN<0:7>.

[0040] The output circuit 130 may output the first to eighth transmission data S<0:7> through the first to eighth pads T0 to T7 based on the first to eighth remapped data DM<0:7>. The first to eighth transmission data S<0:7> correspond to the first to eighth remapped data DM<0:7>.

[0041] Figure 4 It is shown Figure 1 FIG. 2 is a block diagram of a receiver RX included in the second semiconductor device 200. For example, Figure 4 The first to eighth pads R0 to R7 are shown, ie, N=7.

[0042] Reference Figure 4 , the receiver RX may include first to eighth pads R0 to R7 and a second processor 202 .

[0043] The first pad R0 may receive the rearranged first transmission data S from the first semiconductor device 100. <0> .

[0044] The second pad R1 may receive the rearranged second transmission data S from the first semiconductor device 100. <1> .

[0045] The third pad R2 may receive the rearranged third transmission data S from the first semiconductor device 100. <2> .

[0046] The fourth pad R3 may receive the rearranged fourth transmission data S from the first semiconductor device 100. <3> .

[0047] The fifth pad R4 may receive the rearranged fifth transmission data S from the first semiconductor device 100. <4> .

[0048] The sixth pad R5 may receive the rearranged sixth transmission data S from the first semiconductor device 100. <5> .

[0049] The seventh pad R6 may receive the rearranged seventh transmission data S from the first semiconductor device 100. <6> .

[0050] The eighth pad R7 may receive the rearranged eighth transmission data S from the first semiconductor device 100. <7> .

[0051] The second processor 202 may generate first to eighth data DIN<0:7> whose arrangement order is restored based on the rearranged first to eighth transmission data S<0:7> respectively input through the first to eighth pads R0 to R7 .

[0052] Figure 5 yes Figure 4 A block diagram of the second processor 202 is shown.

[0053] Reference Figure 5 , the second processor 202 may include an input circuit 210 and a data recovery circuit 220 .

[0054] The input circuit 210 may generate first to eighth input data DR<0:7> based on first to eighth transmission data S<0:N> respectively input through the first to eighth pads R0 to R7 .

[0055] The data recovery circuit 220 may receive the first to eighth input data DR<0:7>. The data recovery circuit 220 may restore the arrangement order of the first to eighth input data DR<0:7> based on the mapping information included in each of the first to eighth input data DR<0:7>, thereby generating the first to eighth data DIN<0:7>. The arrangement order of the first to eighth data DIN<0:7> may be the same as the arrangement order of the first to eighth data DOUT<0:7> of the first semiconductor device 100.

[0056] The mapping information may include whether each of the first to eighth data DOUT<0:7> is inverted and a previous (ie, original) arrangement order of each of the first to eighth data DOUT<0:7>. The mapping information may be recorded in a header of each of the first to eighth data DOUT<0:7>.

[0057] In the following, refer to Figure 6 and Figure 7 The operation of the semiconductor system 10 having the above-described configuration according to the embodiment of the present disclosure is described.

[0058] The first semiconductor device 100 may output transmission data S<0:N> corresponding to the data DOUT<0:N> to the second semiconductor device 200. In this case, the first semiconductor device 100 may rearrange the transmission path of the data DOUT<0:N> to minimize the crosstalk occurring between the transmission data S<0:N>. For example, the transmitter TX included in the first semiconductor device 100 may calculate the crosstalk score of the data DOUT<0:N> based on a predetermined remapping strategy, re-determine the correspondence between the data DOUT<0:N> and the pads T0 to T7 based on the crosstalk score, and generate the transmission data S<0:N> corresponding to the data DOUT<0:N> according to the re-determined correspondence.

[0059] The remapping strategy may be referenced by the data remapping circuit 120 and follows the following description.

[0060] (1) The data DOUT<0:N> may be rearranged so that data having a differential relationship or a pseudo differential relationship among the data DOUT<0:N> are sent adjacent to each other (i.e., adjacent to each other). The pseudo differential relationship may indicate that the relationship between two data is substantially the same as or similar to the differential relationship. For example, the data DOUT<0:N> may be rearranged so that data having a relatively large number of transitions from a low logic level to a high logic level #post_odd or #post_even and data having a relatively large number of transitions from a high logic level to a low logic level #negt_odd or #negt_even are sent adjacent to each other.

[0061] (2) Among the data DOUT<0:N>, the data DOUT<0:N> may be rearranged so that the data with the largest number of data transitions and the data with the smallest number of data transitions are transmitted adjacent to each other. For example, the data with the smallest number of data transitions may be static data that has never been transitioned.

[0062] (3) The data DOUT<0:N> may be rearranged so that data having the same pattern or similar data patterns among the data DOUT<0:N> are not transmitted adjacent to each other.

[0063] (4) At least one of the data DOUT<0:N> may be inverted. This may be in the same situation as the above "(1)". Since at least one of two or more pieces of data having similar data patterns is inverted, the two or more pieces of data may have a differential relationship or a pseudo-differential relationship.

[0064] Figure 6 is a graph used to describe the crosstalk score. For example, Figure 6 The first to eighth data patterns DP0 to DP7 are shown, and each of the first to eighth data patterns DP0 to DP7 may have eight burst lengths, ie, 8 bits.

[0065] Reference Figure 6 , when the first data pattern DP0 is "01010101", the number of valid data #1 with a low logic level is "4", the number of valid data #0 with a high logic level is "4", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "0", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "4", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "3", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "7".

[0066] When the second data pattern DP1 is "10101010", the number of valid data #1 with a low logic level is "4", the number of valid data #0 with a high logic level is "4", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "3", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "0", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "4", and the total number of data transitions tot_tran is "7".

[0067] When the third data pattern DP2 is "00110011", the number of valid data #1 with a low logic level is "4", the number of valid data #0 with a high logic level is "4", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "2", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "1", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "3".

[0068] When the fourth data pattern DP3 is "11001100", the number of valid data #1 with a low logic level is "4", the number of valid data #0 with a high logic level is "4", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "1", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "2", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "3".

[0069] When the fifth data pattern DP4 is "00001111", the number of valid data #1 with a low logic level is "4", the number of valid data #0 with a high logic level is "4", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "1", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "0", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "1".

[0070] When the sixth data pattern DP5 is "11110000", the number of valid data #1 with a low logic level is "4", the number of valid data #0 with a high logic level is "4", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "0", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "1", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "1".

[0071] When the seventh data pattern DP6 is "00000000", the number of valid data #1 with a low logic level is "0", the number of valid data #0 with a high logic level is "8", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "0", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "0", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "0".

[0072] When the eighth data pattern DP7 is "11111111", the number of valid data #1 with a low logic level is "8", the number of valid data #0 with a high logic level is "0", the number of times the data transitions in a rising edge manner in the odd cycle of the clock signal CLK #post_odd is "0", the number of times the data transitions in a rising edge manner in the even cycle of the clock signal CLK #post_even is "0", the number of times the data transitions in a falling edge manner in the odd cycle of the clock signal CLK #negt_odd is "0", the number of times the data transitions in a falling edge manner in the even cycle of the clock signal CLK #negt_even is "0", and the total number of data transitions tot_tran is "0".

[0073] Figure 7 1 is a diagram for describing in more detail the operation of the transmitter TX included in the first semiconductor device 100. For example, Figure 7 Only the first to fourth data DOUT<0:3> and data DM<0:3> and S<0:3> related thereto are shown.

[0074] like Figure 7 As shown, the first data DOUT <0> The data pattern is "10101010", the second data DOUT <1> The data pattern is "11111111", the third data DOUT <2> The data pattern is "11001100", the fourth data DOUT <3> The data pattern is "10101010".

[0075] Since the first data DOUT <0> and the fourth data DOUT <3> have the same data pattern, so the first data DOUT <0> and the fourth data DOUT <3> can be set to be non-adjacent to each other, or the first data DOUT <0> and the fourth data DOUT <3> Since there is no inversion between the second and third data DOUT<1:2> and the first data DOUT <0> The data having a differential relationship or a pseudo-differential relationship, therefore, preferably, the first data DOUT <0> and the fourth data DOUT <3> In the embodiment, the fourth data DOUT is described. <3> Therefore, the data remapping circuit 120 can generate the first data DOUT <0> The corresponding first re-mapped data DM <0> , and generates the fourth data DOUT <3> The second re-mapped data DM corresponding to the inverted data <1> (“(1), (3) and (4)” in the remapping strategy are applied). In this case, the first remapping data DM <0> The first data DOUT may be included as mapping information <0> information and non-inverted information, and the second remapped data DM <1> The fourth data DOUT may be included as mapping information <3> information and inverse information Inv.

[0076] Since the second data DOUT <1> is a static signal, so the second data DOUT <1> can be set adjacent to data having a large number of transition times. <3> There is no third data DOUT <2> The third data DOUT has a differential relationship or a pseudo differential relationship. <2> can be set adjacent to the static data. Therefore, the data remapping circuit 120 can generate <1> The corresponding third re-mapping data DM <2> , and generates the third data DOUT <2> The corresponding fourth re-mapped data DM <3> (“(2) and (3)” in the remapping strategy are applied). In this case, the third remapping data DM <2> The second data DOUT may be included as mapping information <1> information and non-inverted information, and the fourth remapped data DM <3> The third re-mapping data DM may be included as mapping information <2> information and reverse information.

[0077] The output circuit 130 may output the first to fourth transmission data S<0:3> corresponding to the first to fourth remapped data DM<0:3> to the second semiconductor device 200 through the first to fourth pads T0 to T3. As described above, the first to fourth transmission data S<0:3> are transmitted through the transmission path coupled to the first to fourth pads T0 to T3 while being rearranged based on the remapping strategy, and thus crosstalk occurring between the first to fourth transmission data S<0:3> may be minimized.

[0078] According to an embodiment of the present disclosure, data having a data pattern resistant to crosstalk may be rearranged to be transmitted adjacent to each other, which enables improvement in transmission efficiency of data.

[0079] According to the embodiments of the present disclosure, when data is transmitted through a transmission line, data distortion caused by crosstalk can be suppressed, which makes it possible to improve the quality of data.

[0080] Although the present disclosure has been shown and described with respect to specific embodiments, the disclosed embodiments are provided for description and are not intended to be limiting. Further, it should be noted that, as will be appreciated by those skilled in the art in light of the present disclosure, the present disclosure may be implemented in various ways by substitution, change and modification within the scope of the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: Multiple pads; a data pattern analysis circuit that generates an analysis signal by analyzing a data pattern of each of the data mapped to each of the plurality of pads; a data remapping circuit that redetermines the relationship between the data and the plurality of pads based on the analysis signal, and remaps the data to the plurality of pads based on the redetermined relationship; as well as The output circuit outputs the remapped data through the plurality of pads.

2. The semiconductor device according to claim 1, wherein Each of the analysis signals includes mapping information related to the number of transitions of each of the data.

3. The semiconductor device according to claim 2, wherein: The mapping information includes: the number of valid data with a low logic level in each of the data, the number of valid data with a high logic level in each of the data, the number of times each of the data transitions from the low logic level to the high logic level in odd cycles of the clock signal, the number of times each of the data transitions from the low logic level to the high logic level in even cycles of the clock signal, the number of times each of the data transitions from the high logic level to the low logic level in odd cycles of the clock signal, the number of times each of the data transitions from the high logic level to the low logic level in even cycles of the clock signal, and the total number of transitions for each of the data.

4. The semiconductor device according to claim 1, wherein The data remapping circuit remaps the data based on the analysis signal so that data having a differential relationship or a pseudo differential relationship among the data are transmitted adjacent to each other.

5. The semiconductor device according to claim 4, wherein: The data remapping circuit remaps the data so that data having a relatively large number of transitions from the low logic level to the high logic level and data having a relatively large number of transitions from the high logic level to the low logic level are transmitted adjacent to each other.

6. The semiconductor device according to claim 1, wherein The data remapping circuit remaps the data based on the analysis signal so that data having a largest number of data transitions and data having a smallest number of data transitions among the data are transmitted adjacent to each other.

7. The semiconductor device according to claim 1, wherein The data remapping circuit inverts at least one of the data based on the analysis signal.

8. The semiconductor device according to claim 1, wherein Each of the remapped data includes mapping information including whether each of the data is reversed and a previous arrangement order of each of the data.

9. The semiconductor device according to claim 1, wherein: The data pattern analysis circuit analyzes a data pattern of each of the data at each cycle of a clock signal and generates an analysis signal corresponding to the analysis result.

10. The semiconductor device according to claim 1, wherein The data remapping circuit generates remapped data corresponding to the data according to the redefined relationship.

11. An electronic device comprising: Multiple pads; as well as A processor updates a correspondence between the plurality of data and the plurality of pads based on a data pattern of each of the plurality of data input to the processor, and outputs a plurality of remapped data through respective corresponding pads among the plurality of pads based on the updated correspondence.

12. The electronic device according to claim 11, wherein: The processor comprises: a data pattern analysis circuit that generates an analysis signal by analyzing a data pattern of each of a plurality of data mapped to each of the plurality of pads; a data remapping circuit that updates the correspondence between the plurality of data and the plurality of pads based on the analysis signal, and remaps the plurality of data to the plurality of pads based on the updated correspondence; and The output circuit outputs a plurality of remapped data through the plurality of pads.

13. The electronic device according to claim 12, wherein: Each of the analysis signals includes mapping information related to the number of times each of the plurality of data is transitioned.

14. The electronic device according to claim 13, wherein: The mapping information includes: the number of valid data with a low logic level in each of the multiple data, the number of valid data with a high logic level in each of the multiple data, the number of times each of the multiple data transitions from the low logic level to the high logic level in odd cycles of the clock signal, the number of times each of the multiple data transitions from the low logic level to the high logic level in even cycles of the clock signal, the number of times each of the multiple data transitions from the high logic level to the low logic level in odd cycles of the clock signal, the number of times each of the multiple data transitions from the high logic level to the low logic level in even cycles of the clock signal, and the total number of transitions for each of the multiple data.

15. The electronic device according to claim 12, wherein: The data remapping circuit remaps the plurality of data based on the analysis signal so that data having a differential relationship or a pseudo-differential relationship among the plurality of data are transmitted adjacent to each other, and The data remapping circuit remaps the plurality of data so that data having a relatively large number of transitions from a low logic level to a high logic level and data having a relatively large number of transitions from the high logic level to the low logic level among the plurality of data are transmitted adjacent to each other.

16. The electronic device according to claim 12, wherein: The data remapping circuit performs at least one of the following operations: 1) remapping the plurality of data based on the analysis signal so that data with the largest number of data transitions and data with the smallest number of data transitions among the plurality of data are sent adjacent to each other; and 2) inverting at least one of the plurality of data based on the analysis signal.

17. The electronic device according to claim 12, wherein: Each of the plurality of re-mapped data includes mapping information including whether each of the plurality of data is reversed and a previous arrangement order of each of the plurality of data.

18. The electronic device according to claim 12, wherein: The data pattern analysis circuit analyzes the data pattern of each of the plurality of data based on the clock signal at each cycle of the clock signal and generates an analysis signal corresponding to the analysis result, and The data remapping circuit generates a plurality of remapped data corresponding to the plurality of data according to the corresponding relationship.

19. A semiconductor system comprising: a first semiconductor device that calculates crosstalk scores of a plurality of first data based on a predetermined remapping strategy, redetermines a correspondence relationship between the plurality of first data and a plurality of first pads based on the crosstalk scores, and generates a plurality of remapped data corresponding to the plurality of first data according to the redetermined correspondence relationship; as well as The second semiconductor device receives the plurality of re-mapped data and generates a plurality of second data corresponding to the plurality of first data.

20. The semiconductor system according to claim 19, wherein: The second semiconductor device comprises: an input circuit that generates a plurality of input data based on the plurality of re-mapped data input through the second pad; and The data recovery circuit receives the plurality of input data and recovers the arrangement order of the plurality of input data based on the mapping information included in the plurality of input data to generate the plurality of second data.

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