Column address generation circuit and semiconductor device including same

Abstract

Various embodiments of the present disclosure describe a column address generation circuit and a semiconductor device including the same. The column address generation circuit includes a command set conversion section configured to generate column address information based on sector information included in a first command set synchronized with a first clock signal, and output a second command set according to the first command set by replacing information on a column address period of the first clock signal with column address information in response to the conversion signal; and a column address output section configured to output a column address based on the second command set.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0096683, filed on Jul. 25, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a semiconductor device, and more particularly, to a semiconductor device including a column address generation circuit. Background Art

[0004] Electronic devices may include many electronic components, and among these electronic devices, computer systems may include many electronic components made of semiconductors. Among semiconductor devices constituting computer systems, memory devices may store data under the control of external devices.

[0005] In order to improve the interface performance between the semiconductor device and the external device, a technology for quickly transmitting a control signal between the external device and the semiconductor device during fewer clock cycles may be required. Summary of the invention

[0006] According to an embodiment of the present disclosure, a column address generation circuit may include: a command set conversion unit, configured to generate column address information based on sector information included in a first command set synchronized with a first clock signal, and output a second command set according to the first command set by replacing information about a column address period of the first clock signal with the column address information in response to a conversion signal; and a column address output unit, configured to output a column address based on the second command set.

[0007] According to an embodiment of the present disclosure, a column address generation circuit may include: a command set conversion unit, configured to determine a selection value based on sector information, and continuously output the selection value and a fixed value independent of the sector information as column address information in response to a conversion signal; and a column address output unit, configured to output a fixed value as a lower part of the column address and output the selection value as an upper part of the column address in response to the column address information.

[0008] According to an embodiment of the present disclosure, a column address generation circuit may include: a control signal output unit, configured to output a conversion signal in an enabled state when a command set includes a random data output command, and output sector information included in the command set during a selection period; and a command set conversion unit, configured to output a lower part of the column address during a period before the selection period in response to the conversion signal in an enabled state and the sector information, and output an upper part of the column address corresponding to the sector information during the selection period. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 Block diagram of the cell area and buffer area.

[0011] Figure 3 It is used to illustrate the embodiment according to the present disclosure. Figure 1 Schematic diagram of a read operation and a random data output operation of a semiconductor device in FIG.

[0012] Figure 4 is a diagram for explaining an external command set for normal operation according to an embodiment of the present disclosure.

[0013] Figure 5 is a diagram for explaining an external command set for a random data output operation according to an embodiment of the present disclosure.

[0014] Figure 6 The present invention is a diagram showing an embodiment of the present invention. Figure 1 Block diagram of the column address generation unit in .

[0015] Figure 7 It is used to illustrate the embodiment according to the present disclosure. Figure 1 A timing diagram of signals for random data output operation of a semiconductor device.

[0016] Figure 8 It is used to illustrate the embodiment according to the present disclosure. Figure 1 A timing diagram of signals for random data output operation of a semiconductor device. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0018] Figure 1 is a block diagram illustrating a semiconductor device 100 according to an embodiment of the present disclosure.

[0019] Reference Figure 1, the semiconductor device 100 can operate under the control of the external device 10. The semiconductor device 100 can exchange signals CS with the external device 10. The signal CS may include, for example, a command latch enable signal, an address latch enable signal, an external clock signal, an external command set, and data DATA. The semiconductor device 100 can perform various internal operations, such as a programming operation, a read operation, a full data output operation, and a random data output operation in response to the signal CS transmitted from the external device 10. Regarding the random data output operation, in an embodiment, the semiconductor device 100 can support an external command set transmitted from the external device 10 in a shorter time than before. Therefore, in an embodiment, the semiconductor device 100 can perform a random data output operation very efficiently.

[0020] In an embodiment, the semiconductor device 100 may be a semiconductor memory device. The semiconductor memory device may include various types of memory, such as NAND flash memory, three-dimensional NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0021] The semiconductor device 100 may include a cell region 110 and a peripheral region 120 .

[0022] The cell region 110 may include a plurality of memory cells storing data DATA. Figure 2 A specific configuration of the unit region 110 is described.

[0023] The peripheral region 120 may perform an internal operation on the cell region 110 in response to a signal CS transmitted from the external device 10. The peripheral region 120 may store and read data DATA in and from the cell region 110 in response to the signal CS.

[0024] Specifically, the peripheral area 120 may include a control unit 121, a column address generation unit 122, a buffer area 123, and a column selection unit 124. Each of the control unit 121, the column address generation unit 122, the buffer area 123, and the column selection unit 124 may be configured by hardware, software, firmware, or a combination thereof. In an embodiment, the control unit 121, the column address generation unit 122, the buffer area 123, and the column selection unit 124 may each be configured by a circuit. In an embodiment, the column address generation unit 122 may be implemented by a circuit and is referred to as a column address generation circuit. In an embodiment, reference is made to Figure 6 , the column address information output unit 222 may be implemented by a multiplexer. Figure 6, the second command set output unit 223 can be implemented by a multiplexer.

[0025] The control unit 121 may control the overall operation of the semiconductor device 100 based on the signal CS received from the external device 10. For example, the control unit 121 may generate a cell region control signal CCTL in response to the signal CS, and control the cell region 110 through the cell region control signal CCTL. The cell region control signal CCTL may include, for example, various levels of operating voltages (e.g., program voltage, read voltage, erase voltage, verification voltage, etc.) required in a program operation, a read operation, and an erase operation.

[0026] The control unit 121 may also transfer data DATA received from the external device 10 to the buffer area 123, and output data DATA received from the buffer area 123 to the external device 10. The control unit 121 may generate a buffer area control signal BCTL in response to the signal CS, and control the buffer area 123 through the buffer area control signal BCTL.

[0027] Based on the external command set synchronized with the external clock signal included in the signal CS, the control unit 121 may output the first command set CS1 synchronized with the first clock signal CL1 to the column address generation unit 122. The first clock signal CL1 may be the same as the external clock signal, or may be a clock signal delayed from the external clock signal. The control unit 121 may receive the external command set in response to the external clock signal, and output the received external command set as the first command set CS1.

[0028] Although not shown, the control unit 121 may include an interface configured to communicate with the external device 10 and a voltage generating circuit configured to generate operating voltages of various levels.

[0029] The column address generation unit 122 may output the column address CA to the column selection unit 124 in response to the first command set CS1 synchronized with the first clock signal CL1. When the first command set CS1 includes a random data output command, the column address generation unit 122 may output the column address CA by performing a column address conversion operation. The column address conversion operation may be an operation for generating the column address CA, and even if the column address CA is not received from the external device 10, the random data output operation may be performed based on the sector information received from the external device 10.

[0030] Specifically, the column address CA for performing the random data output operation may include a fixed value that is independent of the sector information received from the external device 10. The column address generation unit 122 may determine the selection value based on the sector information included in the first command set CS1. The selection value may not be a fixed value that is independent of the sector information, but may be a variable value that depends on the sector information received from the external device 10. Therefore, the column address generation unit 122 may generate column address information including a fixed value and a selection value, and output the column address CA based on the column address information.

[0031] When the first command set CS1 includes a predetermined command other than a random data output command, the column address generation unit 122 may output the column address CA included in the first command set CS1 without performing a column address conversion operation. The term "predetermined" as used herein with respect to a parameter (e.g., a predetermined command, a predetermined column address cycle, a predetermined value, or a predetermined operation) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0032] The buffer area 123 may exchange data DATA between the cell area 110 and the control unit 121. The buffer area 123 may store data DATA to be stored in the cell area 110 before the data DATA is stored in the cell area 110. The buffer area 123 may store data DATA read from the cell area 110 before the data DATA is output to the control unit 121.

[0033] The column selection unit 124 may control the data DATA to be input to the location corresponding to the column address CA in the buffer area 123, or control the data DATA to be output from the location corresponding to the column address CA. The column selection unit 124 may generate a column control signal ICTL based on the column address CA, and control the buffer area 123 through the column control signal ICTL.

[0034] According to an embodiment of the present disclosure, the sector information received from the external device 10 may include much fewer bits than the column address for performing the random data output operation, and the transmission of the sector information may require only fewer clock cycles than the column address. Therefore, in an embodiment, the time for transmitting the external command set for the random data output operation from the external device 10 to the semiconductor device 100 can be effectively shortened. In an embodiment, since only the sector information is decoded when a fixed value is used, the column address conversion operation can be effectively simplified.

[0035] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1Block diagram of the cell region 110 and the buffer region 123. Figure 2 The numbers of the individual components in are examples.

[0036] Reference Figure 2 , the unit area 110 may include logic units LU1 to LU4. According to an embodiment, each logic unit may be a semiconductor memory chip or a semiconductor memory die. Each of the logic units LU1 to LU4 may be identified by a corresponding logic unit address.

[0037] The logic units LU1 to LU4 may be configured similarly. As an example, when describing the logic unit LU1, the logic unit LU1 may include planes P11 to P14. A plane may be a group of memory blocks commonly connected to a single buffer. The planes P11 to P14 may be connected to buffers B11 to B14, respectively. Take planes P11 to P14 as an example. When describing the plane P11, the plane P11 may include memory blocks MB1 to MBi commonly connected to the buffer B11. A memory block may be a memory unit that performs an erase operation.

[0038] The buffer region 123 may include buffers B11 to B44 respectively connected to the planes P11 to P44 included in the cell region 110. The buffers B11 to B44 may be configured and operated similarly. When the buffer B11 is described as an example, the data DATA to be programmed to the plane P11 by the programming operation may be stored in the buffer B11 before being written. The data DATA read from the plane P11 by the reading operation may be stored in the buffer B11 before being output to the external device 10.

[0039] Figure 3 It is used to illustrate the embodiment according to the present disclosure. Figure 1 1 is a diagram of a read operation and a random data output operation of the semiconductor device 100 in FIG.

[0040] Reference Figure 3 , a page PG is a memory unit included in the cell region 110, and may be a unit used by the semiconductor device 100 to perform a program operation or a read operation. The page PG may be a unit in which the semiconductor device 100 moves data between the cell region 110 and the buffer BF (i.e., one of the buffers B11 to B44). The semiconductor device 100 may perform a read operation to read data DATA_PG from the page PG to the buffer BF connected to the page PG. The semiconductor device 100 may perform a read operation in response to a read command received from the external device 10.

[0041] The page PG may include the first to fourth sectors ST1 to ST4. For example, when the capacity of a single page PG is 18KB and the first to fourth sectors ST1 to ST4 have the same capacity, the capacity of each of the first to fourth sectors ST1 to ST4 may be 4.5KB. When data is processed in units of 4KB outside the semiconductor device 100, each sector may store 4KB data and 0.5KB or less additional data for the 4KB data (e.g., error correction data for the 4KB data).

[0042] After performing the read operation, the semiconductor device 100 may output all or part of the data DATA_PG stored in the buffer BF to the external device 10 under the control of the external device 10. The full data output operation may be an operation of outputting the total data DATA_PG of 18KB from the buffer BF to the external device 10 under the control of the external device 10. The semiconductor device 100 may perform the full data output operation in response to a full data output command received from the external device 10. The random data output operation may be an operation of outputting only the data of the selected sector from the first sector ST1 to the fourth sector ST4 from the buffer BF to the external device 10 under the control of the external device 10. That is, the sector may be a memory unit in which the semiconductor device 100 performs the random data output operation. The semiconductor device 100 may perform the random data output operation in response to the random data output command received from the external device 10. For example, the semiconductor device 100 may output only the data DATA_ST2 of the second sector ST2 from the buffer BF to the external device 10 in response to the random data output command.

[0043] On the other hand, each bit in the 18KB stored in the page PG may correspond to a column address CA increasing from 0 to 1. In this case, the column address CA may be represented as a 4-bit hexadecimal number (15 bits in binary), so that each bit in the 18KB may be specified. The first bit (in other words, the starting bit) of the data stored in each of the first sector ST1 to the fourth sector ST4 (indicated by the shading) may correspond to column addresses (CA) 0000h, 1200h, 2400h, and 3600h, respectively. The mark h after the number indicates hexadecimal. Column addresses (CA) 0000h, 1200h, 2400h, and 3600h may be referred to as the starting column addresses of the first sector ST1 to the fourth sector ST4. According to an embodiment, the starting column address CA corresponding to each sector may be determined differently from the above case according to the capacity of the page PG, the number of sectors constituting the page PG, and the capacity of each sector.

[0044] The external device may put sector information indicating the sector for performing the random data output operation from the buffer BF into the external command set for the random data output operation. The semiconductor device 100 may generate a column address CA for performing the random data output operation based on the sector information, and perform the random data output operation on the sector corresponding to the generated column address CA. The column address CA for performing the random data output operation may refer to the starting column address CA of the sector for performing the random data output operation. The column address CA for performing the random data output operation may be generated as any one of the starting column addresses of the first sector ST1 to the fourth sector ST4. For example, when the column address CA for performing the random data output operation is determined to be 1200h, the semiconductor device 100 may output only the data DATA_ST2 of the second sector ST2 from the buffer BF to the external device 10.

[0045] Figure 4 is a diagram for explaining an external command set for normal operation according to an embodiment of the present disclosure.

[0046] Reference Figure 4 , the normal operation may not be a random data output operation, but may be a predetermined operation that does not require a column address conversion operation for the semiconductor device 100 according to an embodiment of the present disclosure. The external command set ECS for the normal operation may include a column address CA for performing the normal operation. For example, the normal operation may be a read operation, a program operation, a full data output operation, etc.

[0047] Specifically, the external command set ECS for normal operation may include a command CMD for normal operation, a first column address CA1, a second column address CA2, etc. The external command set ECS may be transmitted from the external device 10 to the semiconductor device 100 by synchronizing with the external clock signal ECL. Each cycle of the external clock signal ECL may be defined under the control of the external device 10. For example, although not shown, the semiconductor device 100 may further receive a command latch enable signal defining a command cycle and an address latch enable signal defining an address cycle from the external device 10.

[0048] For example, the first cycle C1 of the external clock signal ECL may be a command cycle, the second cycle C2 may be a first address cycle, and the third cycle C3 may be a second address cycle. The semiconductor device 100 may recognize the information received in the first cycle C1 of the external clock signal ECL as a command CMD, and determine the details of a normal operation to be performed through the command CMD. When the command CMD is a command for normal operation, the semiconductor device 100 may recognize the information received in the second cycle C2 and the third cycle C3 of the external clock signal ECL as a column address CA.

[0049] The semiconductor device 100 may generate an internal command set synchronized with an internal clock signal based on an external command set ECS synchronized with an external clock signal ECL. When the column address CA included in the external command set ECS is synchronized with the second cycle C2 and the third cycle C3 of the external clock signal ECL, the column address included in the internal command set may also be synchronized with the second cycle and the third cycle of the internal clock signal. Therefore, the second cycle and the third cycle of the external clock signal ECL and the internal clock signal may be defined as a column address cycle hereinafter. According to an embodiment, the column address cycle may vary according to the cycle of the external clock signal ECL synchronized with the column address CA included in the external command set ECS.

[0050] As described above, when the capacity of the page PG is 18KB, the column address CA can be represented by 15 bits. Therefore, as shown in Table T1, the first column address CA1 may include the lower portion of the column address CA (i.e., CA<7:0>) for performing internal operations of the semiconductor device 100. The lower portion of the column address CA may refer to the lower 8 bits close to the LSB among the 15 bits constituting the column address CA. The second column address CA2 may include the upper portion of the column address CA (i.e., CA<14:8>). The upper portion of the column address CA may refer to the upper 7 bits close to the MSB among the 15 bits constituting the column address CA.

[0051] During the additional cycles of the external clock signal ECL, the semiconductor device 100 may further receive a logic unit address, a plane address, a block address, a page address, etc. for performing an internal operation from the external device 10. In an embodiment, when describing an example determined by the specification of the semiconductor device 100, the semiconductor device 100 may receive all addresses including the column address CA during a total of 5 cycles.

[0052] Figure 5 is a diagram for explaining an external command set ECS for a random data output operation according to an embodiment of the present disclosure.

[0053] Reference Figure 5 , the external command set ECS for the random data output operation transmitted from the external device 10 may include a random data output command RDO, a first address AD1, a second address AD2, and a confirmation command CF. The semiconductor device 100 may receive the external command set ECS for the random data output operation during 4 cycles of the external clock signal ECL. The semiconductor device 100 may recognize the random data output command RDO in response to the command cycle of the external clock signal ECL, i.e., the first cycle C1, and recognize the confirmation command CF in response to the confirmation command cycle of the external clock signal ECL, i.e., the fourth cycle C4, thereby determining to perform the random data output operation.

[0054] Referring to Table T2, 2 bits (e.g., bit 0 and bit 1) included in the first address AD1 may include a logic unit address LUN corresponding to a logic unit for performing a random data output operation, and the other 2 bits (e.g., bit 4 and bit 5) may include a plane address PA corresponding to a plane for performing a random data output operation. The term "RESERVED" may indicate that the corresponding bit is set aside for potential use. The semiconductor device 100 may identify the first address AD1 in response to a second cycle C2 of the external clock signal ECL, and determine a logic unit and a plane for performing a random data output operation.

[0055] In addition, the 2 bits (e.g., bit 0 and bit 1) included in the second address AD2 may include sector information SI indicating a sector for performing a random data output operation. For example, when a single page PG includes a first sector ST1 to a fourth sector ST4, the first sector ST1 to the fourth sector ST4 may correspond to sector indexes from 00b to 11b, respectively, and the sector information SI may include a sector index corresponding to the sector for performing a random data output operation. The mark b after the number represents a binary number. For example, when the external device 10 wants to receive data of only the third sector ST3 from the semiconductor device 100 through a random data output operation, the external device 10 may transmit an external command set ECS for a random data output operation to the semiconductor device 100, and the external command set ECS includes a sector index 10b corresponding to the third sector ST3. The semiconductor device 100 may identify the sector information SI of the second address AD2 in response to the third cycle C3 of the external clock signal ECL, and determine the sector for performing a random data output operation based on the sector information SI.

[0056] According to an embodiment, in addition to Figure 5 In addition, the first address AD1 may include sector information SI, and the second address AD2 may include a logical unit address LUN and a plane address PA.

[0057] Thus, in an embodiment, since the external command set ECS includes the first address AD1 and the second address AD2 transmitted only during 2 cycles, the external command set ECS for the random data output operation can be transmitted very quickly. In an embodiment, although the semiconductor device 100 does not receive a total of 15-bit column address CA for performing the random data output operation from the external device 10 during the column address cycles C2 and C3, but only receives the sector information SI including a smaller number of bits than the column address, the semiconductor device 100 can still effectively determine the 15-bit column address CA based on the sector information SI. Specifically, the starting column address of the sector constituting the page PG may include a lower portion having the same value, so the semiconductor device 100 can determine the lower portion of the column address CA for performing the random data output operation as a fixed value regardless of the value of the sector information SI. For example, since the starting column addresses 0000h, 1200h, 2400h, and 3600h of the first to fourth sectors ST1 to ST4 include lower portions having the same value (i.e., 00h), the semiconductor device 100 may generate the lower portion of the column address CA for performing the random data output operation as 00h regardless of the value of the sector information SI. By decoding the sector information SI, the semiconductor device 100 may determine the upper portion of the column address CA for performing the random data output operation as any one of 00h, 12h, 24h, and 36h. In an embodiment, since only the sector information SI is decoded when the fixed value 00h is used, the column address conversion operation may be effectively simplified.

[0058] Figure 6 The present invention is a diagram showing an embodiment of the present invention. Figure 1 1. Block diagram of the column address generation unit 122 in FIG.

[0059] Reference Figure 6 When the first command set CS1 includes a random data output command, the column address generation unit 122 may output the column address CA by performing a column address conversion operation based on the sector information SI. When the first command set CS1 includes a predetermined command other than the random data output command, the column address generation unit 122 may output the column address CA included in the first command set CS1.

[0060] The column address generation unit 122 may include a control signal output section 210, a command set conversion section 220, and a column address output section 230. In an embodiment, the control signal output section 210, the command set conversion section 220, and the column address output section 230 may all be formed by circuits.

[0061] The control signal output section 210 may receive a first command set CS1 synchronized with the first clock signal CL1, and output a conversion signal TRS, a selection signal SEL, and a second clock signal CL2. The control signal output section 210 may identify the type of command included in the first command set CS1 in response to a command cycle of the first clock signal CL1. When the first command set CS1 includes a random data output command RDO, the control signal output section 210 may control the command set conversion section 220 to perform a column address conversion operation through the conversion signal TRS and the selection signal SEL.

[0062] Specifically, when the first command set CS1 includes the random data output command RDO, the control signal output section 210 may output the conversion signal TRS in an enabled state during the column address period of the first clock signal CL1. As described above, the column address period of the first clock signal CL1 in which the conversion signal TRS is output in the enabled state may be the second period and the third period of the first clock signal CL1. In an embodiment, this may be to simplify the hardware structure by generating the column address in the same period even in the random data output operation, because when the first command set CS1 includes the column address in normal operation, the column address is generated in response to the second period and the third period of the first clock signal CL1.

[0063] The conversion signal TRS may also be changed from a disabled state to an enabled state before the start of a selection period to be described below. After the start of the selection period, the conversion signal TRS may be changed from an enabled state to a disabled state. The disabled state may be a first state of the conversion signal TRS, and the enabled state may be a second state of the conversion signal TRS. For example, the conversion signal TRS may be output at a logic high level in a disabled state and may be output at a logic low level in an enabled state.

[0064] More specifically, in response to the command cycle of the first clock signal CL1, that is, the first cycle, the control signal output section 210 may output the conversion signal TRS that changes from the disabled state to the enabled state. For example, the control signal output section 210 may output the conversion signal TRS that changes from the disabled state to the enabled state in response to the first rising edge or the first falling edge of the first clock signal CL1.

[0065] After outputting the conversion signal TRS in the enabled state, the control signal output section 210 may output the conversion signal TRS changed from the enabled state to the disabled state in response to the confirmation command cycle of the first clock signal CL1, that is, the fourth cycle. For example, the control signal output section 210 may output the conversion signal TRS changed from the enabled state to the disabled state in response to the fourth rising edge or the fourth falling edge of the first clock signal CL1.

[0066] When the first command set CS1 includes a predetermined command other than the random data output command RDO, the control signal output section 210 may maintain the conversion signal TRS in a disabled state. That is, when the first command set CS1 includes a predetermined command that does not require the command set conversion section 220 to perform a column address conversion operation, the control signal output section 210 may maintain the conversion signal TRS in a disabled state.

[0067] When the first command set CS1 includes the random data output command RDO, the control signal output section 210 may output the sector information SI included in the first command set CS1, that is, the selection signal SEL including the sector index. For example, the control signal output section 210 may output the sector index as the selection signal SEL as it is. The control signal output section 210 may identify (that is, sample) the sector information SI included in the first command set CS1 in response to a predetermined column address cycle of the first clock signal CL1. Figure 5 In the described example, the control signal output unit 210 may identify the sector information SI included in the first command set CS1 in response to the third cycle of the first clock signal CL1, and output the 2-bit sector information SI as the selection signal SEL. According to an embodiment, the number of bits constituting the selection signal SEL may vary according to the number of sectors constituting the page PG, the number of bits constituting the sector information SI, and the number of values ​​input to the column address information output unit 222.

[0068] The control signal output section 210 may output the sector information SI as the selection signal SEL during the selection period. The selection period may start after the control signal output section 210 receives the sector information SI. For example, the selection period may start after the control signal output section 210 recognizes the sector information SI included in the first command set CS1 in response to the third cycle of the first clock signal CL1. According to an embodiment, the selection period may start from the third cycle after the control signal output section 210 recognizes the sector information SI included in the first command set CS1 in response to the second cycle of the first clock signal CL1. The selection period may end after the conversion signal TRS changes from an enabled state to a disabled state.

[0069] The control signal output section 210 may output a predetermined value as the selection signal SEL during a period other than the selection period. For example, the predetermined value may be a reset value consisting of 0.

[0070] When the first command set CS1 includes a predetermined command other than the random data output command RDO, the control signal output section 210 may maintain the selection signal SEL at a predetermined value. That is, when the first command set CS1 includes a predetermined command that does not require the command set conversion section 220 to perform a column address conversion operation, the control signal output section 210 may maintain the selection signal SEL at a predetermined value.

[0071] The control signal output section 210 may control the column address output section 230 to output the column address CA through the second clock signal CL2. The control signal output section 210 may output the second clock signal CL2 based on the first clock signal CL1. The second clock signal CL2 may be the same as the first clock signal CL1, or may be a clock signal delayed from the first clock signal CL1.

[0072] The command set conversion section 220 may perform a column address conversion operation in response to a selection signal SEL and a conversion signal TRS. Specifically, the command set conversion section 220 may generate column address information CAI based on the selection signal SEL and the sector information SI included in the first command set CS1. Subsequently, the command set conversion section 220 may output a second command set CS2 according to the first command set CS1 by replacing information about a column address cycle of the first clock signal CL1 with the column address information CAI based on the conversion signal TRS. As described above, the column address information CAI may include a fixed value FV used as a lower portion of a column address CA for performing a random data output operation. The fixed value FV may be a value of the same lower portion of a start column address of a sector constituting a page PG.

[0073] Specifically, the command set conversion unit 220 may include a decoder 221, a column address information output unit 222, and a second command set output unit 223. In an embodiment, the decoder 221, the column address information output unit 222, and the second command set output unit 223 may all be configured by circuits. In an embodiment, the column address information output unit 222 may be implemented by a multiplexer. In an embodiment, the second command set output unit 223 may be implemented by a multiplexer.

[0074] The decoder 221 may receive the sector information SI included in the first command set CS1, and output any one of the decoded values ​​DV1 to DV3 based on the sector information SI. The decoded values ​​DV1 to DV3 may be the remaining values ​​excluding the same value as the fixed value FV among the upper portion of the start column address of the sector constituting the page PG. That is, the same value as the fixed value FV among the upper portion of the start column address of the sector constituting the page PG may not be output from the decoder 221, because the fixed value FV may be used as it is.

[0075] Specifically, when the start column address of the sector corresponding to the sector information SI has the same upper portion as the fixed value FV, the decoder 221 may not output a decoded value. In other words, the decoder 221 may ignore the sector information SI of a specific value. In response to the sector information SI other than the ignored specific value, the decoder 221 may output a decoded value corresponding to the upper portion of the start column address of the corresponding sector. Figure 3 and Figure 5In the described example, the decoded values ​​DV1 to DV3 may be the upper 12h, 24h and 36h of the start column addresses of the second sector ST2 to the fourth sector ST4, respectively. When the sector information SI is 00b, the decoder 221 may not output anything, when the sector information SI is 01b, the decoder 221 may output 12h, when the sector information SI is 10b, the decoder 221 may output 24h, and when the sector information SI is 11b, the decoder 221 may output 36h.

[0076] The column address information output unit 222 may output any one of the fixed value FV and the decoded values ​​DV1 to DV3 as the column address information CAI in response to the selection signal SEL. Specifically, the column address information output unit 222 may output the fixed value FV in response to the selection signal SEL having a predetermined value during a period other than the selection period. Subsequently, the column address information output unit 222 may output the selection value in response to the selection signal SEL including the sector information SI during the selection period. The selection value is a value selected by the sector information SI and may be one of the decoded values ​​DV1 to DV3 and the fixed value FV. Therefore, the column address information output unit 222 may continuously output the lower part (i.e., the fixed value FV) and the upper part (i.e., the selection value) of the column address CA for performing the random data output operation as the column address information CAI based on the selection signal SEL.

[0077] The second command set output unit 223 can output the second command set CS2 by replacing the information of the column address period included in the first command set CS1 with the column address information CAI based on the conversion signal TRS. Specifically, the second command set output unit 223 can output the information included in the first command set CS1 as is to be included in the second command set CS2 in response to the conversion signal TRS in the disabled state. Subsequently, the second command set output unit 223 can output the column address information CAI to be included in the second command set CS2 in response to the conversion signal TRS in the enabled state. As described above, the conversion signal TRS is output in the enabled state in the column address period of the first clock signal CL1, and therefore, the second command set CS2 can continuously include the fixed value FV and the selection value in the column address period of the first clock signal CL1.

[0078] On the other hand, when the first command set CS1 includes a predetermined command other than the random data output command RDO and the conversion signal TRS is maintained in the disabled state, the second command set output part 223 may output the first command set CS1 as the second command set CS2 as it is. Therefore, the column address CA included in the first command set CS1 may be included in the second command set CS2 as it is.

[0079] The column address output unit 230 can output the column address CA based on the second command set CS2 in the column address cycle of the second clock signal CL2. For example, the column address output unit 230 can output the value sampled in the second command set CS2 as the lower part of the column address CA in response to the first column address cycle of the second clock signal CL2, that is, the second cycle. Subsequently, the column address output unit 230 can output the value sampled in the second command set CS2 as the upper part of the column address CA in response to the second column address cycle of the second clock signal CL2, that is, the third cycle. The column address output unit 230 can output the lower part of the column address CA and the upper part of the column address CA in parallel. In short, regardless of whether the second command set CS2 is related to the random data output operation, the column address output unit 230 can output the column address CA.

[0080] Figure 7 It is used to illustrate the embodiment according to the present disclosure. Figure 1 A timing diagram of signals of a random data output operation of the semiconductor device 100 in FIG. Figure 7 The embodiments can be followed by referring to Figure 3 , Figure 5 and Figure 6 An example of description.

[0081] Reference Figure 7 , the control unit 121 may receive a command latch enable signal CLE, an address latch enable signal ALE, an external clock signal ECL, and an external command set ECS from the external device 10. The external command set ECS may successively include a random data output command RDO synchronized with the external clock signal ECL, a first address AD1, a second address AD2, and a confirmation command CF. The second address AD2 may include sector information SI.

[0082] The control unit 121 may identify a random data output command RDO and a confirmation command CF included in the external command set ECS in response to the command latch enable signal CLE and the external clock signal ECL. The control unit 121 may determine to perform a random data output operation based on the random data output command RDO.

[0083] The control unit 121 may identify the first address AD1 and the second address AD2 included in the external command set ECS in response to the address latch enable signal ALE and the external clock signal ECL. The control unit 121 may determine the logic unit and the plane for performing the random data output operation based on the first address AD1. In other words, the control unit 121 may determine to perform the random data output operation on the buffer BF connected to the specific plane according to the first address AD1. The control unit 121 may also identify the sector information SI based on the second address AD2.

[0084] The control unit 121 may generate a first clock signal CL1 based on the external clock signal ECL and output a first command set CS1 in synchronization with the first clock signal CL1. The first command set CS1 may sequentially include a random data output command RDO, a first address AD1, a second address AD2, and a confirmation command CF as in the external command set ECS.

[0085] The control signal output section 210 may receive the first command set CS1 and the first clock signal CL1. The control signal output section 210 may determine to perform a random data output operation in response to a random data output command RDO included in the first command set CS1, and output a conversion signal TRS and a selection signal SEL.

[0086] Specifically, the control signal output unit 210 may output the conversion signal TRS changed from the disabled state (i.e., logic high level) to the enabled state (i.e., logic low level) in response to the first rising edge of the first clock signal CL1. Subsequently, the control signal output unit 210 may output the conversion signal TRS changed from the enabled state to the disabled state in response to the fourth rising edge of the first clock signal CL1. The conversion signal TRS may change from the disabled state to the enabled state before the selection period SELP starts, and may change from the enabled state to the disabled state after the selection period SELP starts.

[0087] The control signal output section 210 may output the selection signal SEL based on the sector information SI included in the first command set CS1. Specifically, the control signal output section 210 may output the reset value 00b as the selection signal SEL in the period before the selection period SELP. The control signal output section 210 may output the sector information SI as the selection signal SEL in the selection period SELP after the sector information SI is identified. The value of the selection signal SEL in the selection period SELP may be any one of 00b to 11b, which is the same as the sector information SI. The selection period SELP may end after the conversion signal TRS changes from an enabled state to a disabled state. The control signal output section 210 may output the reset value 00b as the selection signal SEL in the period after the selection period SELP.

[0088] The column address information output section 222 may output a fixed value (FV) 00h to be used as the lower portion of the column address CA as the column address information CAI in response to the selection signal SEL of the reset value 00b in the period before the selection period SELP. In response to the selection signal SEL including the sector information SI during the selection period SELP, the column address information output section 222 may output a selection value to be used as the upper portion of the column address CA (i.e., any one of 00h, 12h, 24h, 36h) as the column address information CAI. In response to the selection signal SEL of the reset value 00b in the period after the selection period SELP, the column address information output section 222 may output a fixed value (FV) 00h as the column address information CAI.

[0089] The second command set output section 223 may output information included in the first command set CS1 to be included in the second command set CS2 when the conversion signal TRS is in a disabled state, and output column address information CAI to be included in the second command set CS2 when the conversion signal TRS is in an enabled state. Since the conversion signal TRS is in an enabled state at least during the column address period (i.e., the second period C2 and the third period C3) of the first clock signal CL1, information about the column address periods C2 and C3 of the first clock signal CL1 in the first command set CS1 may be replaced with the column address information CAI. Since the selection signal SEL is changed from the reset value 00b to the sector information SI when the conversion signal TRS is in an enabled state, the column address information CAI of the second command set CS2 may continuously include the fixed value FV and the selection value.

[0090] The column address output unit 230 may output the fixed value (FV) 00h in the second command set CS2 as the lower portion of the column address CA in response to the second cycle C2 of the second clock signal CL2. The mark xx in the illustrated xx00h indicates that the upper 7 bits of the column address CA have not yet been determined. Subsequently, the column address output unit 230 may output the selected value of the second command set CS2 to the upper portion of the column address CA in response to the third cycle C3 of the second clock signal CL2. For example, when the selected value is 12h, the total column address CA may be output as 1200h.

[0091] Figure 8 is a timing diagram of signals processed in the semiconductor device 100 according to an embodiment of the present disclosure.

[0092] Reference Figure 8 ,and Figure 5 Differently, according to an embodiment, the first address AD1 of the external command set ECS may include 2-bit sector information SI, and the second address AD2 may include a logical unit address LUN and a plane address PA.

[0093] The control signal output section 210 may identify the sector information SI included in the first command set CS1 in the second cycle C2 of the first clock signal CL1 according to a prearrangement with the external device 10. Subsequently, the control signal output section 210 may output the selection signal SEL including the sector information SI in response to the third cycle C3 of the first clock signal CL1. Figure 7 In summary, even if the sector information SI is received in any clock address cycle of the first clock signal CL1, the column address generation unit 122 can still generate the column address CA.

[0094] According to an embodiment, regardless of the operation other than the random data output operation, the column address generation unit 122 of the present disclosure can generate the column address CA similarly to the above, as long as the operation is an operation of accessing only the selected sector of the page PG. Specifically, for a specific operation of accessing only the selected sector of the page PG, the external device 10 can provide the semiconductor device 100 with the sector information SI similarly to the above. Subsequently, similarly to the above, the semiconductor device 100 can generate the column address CA based on the sector information SI and access the selected sector.

[0095] The column address generation circuit according to an embodiment of the present disclosure can efficiently generate a column address in response to a command set with fewer clock cycles.

[0096] The above description is intended only to exemplarily describe the technical spirit of the present disclosure, and those skilled in the art to which the present disclosure belongs can make various changes and modifications without departing from the essential features of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but are intended to describe the present disclosure. The scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of the present disclosure should be interpreted by the attached claims, and all technical spirits falling within their equivalent scopes should be interpreted as included within the scope of the present disclosure.

Claims

1. A column address generation circuit, comprising: a command set conversion section that generates column address information based on sector information included in a first command set synchronized with a first clock signal, and outputs a second command set according to the first command set by replacing information on a column address cycle of the first clock signal with the column address information in response to a conversion signal; as well as The column address output unit outputs the column address based on the second command set. 2 . The column address generation circuit according to claim 1 , further comprising a control signal output section that outputs the conversion signal in response to a random data output command included in the first command set.

3. The column address generation circuit according to claim 2, wherein: The control signal output section outputs the sector information as the selection signal during a selection period, and outputs a predetermined value as the selection signal during a period other than the selection period.

4. The column address generation circuit according to claim 3, wherein: The control signal output section identifies sector information included in the first command set in response to a predetermined column address cycle of the first clock signal.

5. The column address generation circuit according to claim 3, wherein: The control signal output section changes the conversion signal from a disabled state to an enabled state before the selection period starts, and changes the conversion signal from an enabled state to a disabled state after the selection period starts.

6. The column address generating circuit according to claim 2, wherein: The control signal output section changes the conversion signal from a disable state to an enable state in response to a command cycle of the first clock signal, and changes the conversion signal from an enable state to a disable state in response to a confirmation command cycle of the first clock signal.

7. The column address generating circuit according to claim 2, wherein: The control signal output section outputs a conversion signal in an enabled state at least during a column address period of the first clock signal.

8. The column address generation circuit according to claim 2, wherein: The control signal output section maintains the conversion signal in a disabled state when the first command set includes a predetermined command, and The command set conversion section outputs the first command set as the second command set without replacing with the column address information in response to a conversion signal in a disabled state.

9. The column address generating circuit according to claim 1, wherein: The command set conversion unit comprises: a decoder that outputs a decoded value based on the sector information; and The column address information output unit outputs either the decoded value or the fixed value as the column address information based on a selection signal.

10. The column address generation circuit according to claim 9, wherein: The column address information output section outputs any one selected value of the decoded value and the fixed value as the column address information based on the selection signal during a selection period, and outputs the fixed value as the column address information during a period other than the selection period.

11. The column address generation circuit according to claim 1, wherein: The command set conversion unit further comprises: The second command set output section outputs the information included in the first command set to be included in the second command set in response to the conversion signal in the disabled state, and outputs the column address information to be included in the second command set in response to the conversion signal in the enabled state.

12. The column address generation circuit according to claim 1, wherein: The column address output unit outputs the value sampled in the second command set as the lower part of the column address in response to the first column address cycle of the second clock, and outputs the value sampled in the second command set as the upper part of the column address in response to the second column address cycle of the second clock signal.

13. A column address generation circuit, comprising: a command set conversion section that determines a selection value based on the sector information and, in response to a conversion signal, continuously outputs the selection value and a fixed value that is independent of the sector information as column address information; as well as The column address output section outputs the fixed value as a lower portion of the column address and outputs the selection value as an upper portion of the column address in response to the column address information.

14. The column address generation circuit according to claim 13, further comprising: The control signal output section outputs the conversion signal and outputs the sector information included in the command set as a selection signal in response to a random data output command included in the command set during a selection period.

15. The column address generation circuit according to claim 14, wherein: The control signal output section receives a command set synchronized with a clock signal, and identifies sector information included in the command set in response to a predetermined column address cycle of the clock signal.

16. The column address generation circuit according to claim 14, wherein: The control signal output section changes the conversion signal from a disabled state to an enabled state before the selection period starts.

17. The column address generating circuit according to claim 14, wherein: The control signal output section receives a command set synchronized with a clock signal and changes the conversion signal from a disabled state to an enabled state in response to a command cycle of the clock signal.

18. The column address generation circuit according to claim 14, wherein: The control signal output section receives a command set synchronized with a clock signal and outputs a conversion signal in an enabled state at least during a column address period of the clock signal.

19. The column address generating circuit according to claim 14, wherein: The control signal output section outputs a predetermined value as the selection signal during a period before the selection period, and The command set conversion section outputs the fixed value as the column address information in response to a selection signal having the predetermined value during a period before the selection period, and outputs the selection value as the column address information in response to a selection signal of the sector information during the selection period.

20. The column address generation circuit according to claim 13, wherein: The column address output section identifies the fixed value from the column address information in response to a first column address cycle of a clock signal, and identifies the selection value from the column address information in response to a second column address cycle of the clock signal.

21. A column address generation circuit, comprising: a control signal output section that outputs a conversion signal in an enabled state when the command set includes a random data output command, and outputs sector information included in the command set during a selection period; as well as A command set conversion section outputs a lower portion of a column address during a period before the selection period and outputs an upper portion of the column address corresponding to the sector information during the selection period in response to a conversion signal in an enabled state and the sector information.

22. The column address generating circuit according to claim 21, wherein: The control signal output section receives a command set synchronized with a clock signal, and identifies sector information included in the command set in response to a predetermined column address cycle of the clock signal.

23. The column address generating circuit according to claim 21, wherein: The control signal output section changes the conversion signal from a disabled state to an enabled state before the selection period starts.

24. The column address generating circuit according to claim 21, wherein: The control signal output section receives a command set synchronized with a clock signal and changes the conversion signal from a disabled state to an enabled state in response to a command cycle of the clock signal.

25. The column address generating circuit according to claim 21, wherein: The control signal output section receives a command set synchronized with a clock signal and outputs a conversion signal in an enabled state at least during a column address period of the clock signal.

26. The column address generating circuit according to claim 21, wherein: The control signal output section outputs a predetermined value instead of the sector information during a period before the selection period, and The command set conversion section outputs a lower portion of the column address in response to the predetermined value during a period before the selection period.

27. The column address generation circuit according to claim 21, wherein: The lower portion of the column address is a fixed value that is independent of the sector information.

28. The column address generation circuit according to claim 21, wherein: The control signal output section maintains the conversion signal in a disabled state when the command set includes a predetermined command other than a random data output command, and The command set conversion section outputs the lower part and the upper part of the column address included in the command set as they are in response to the conversion signal being in a disabled state.

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