Storage device and electronic equipment

Abstract

The invention provides a storage device and an electronic apparatus which are long in data holding time and high in reliability. A memory device includes a driver circuit and a plurality of memory cells, each memory cell including a transistor and a capacitor, the transistor including a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and a negative potential is applied to the first gate and the second gate of the transistor during a period in which the memory cell holds data.

Description

[0001] This application is a divisional application of the invention patent application with application number 201980023236.8, application date March 20, 2019, and invention name “Storage device and electronic device”. Technical Field

[0002] One embodiment of the present invention relates to a storage device. In particular, one embodiment of the present invention relates to a storage device that can operate by utilizing semiconductor characteristics.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification, etc. relates to an object, method or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product or composition of matter. Background Art

[0004] DRAM (Dynamic Random Access Memory) is widely used as a storage device (also called memory) built into various electronic devices. In addition, examples have been proposed for applying transistors using oxide semiconductors (also called oxide semiconductor transistors, OS transistors) to memory cells of DRAM (for example, Patent Document 1, Non-Patent Document 1).

[0005] Since the leakage current (off-state current) of the oxide semiconductor transistor in the off state is extremely small, by applying the oxide semiconductor transistor to the memory cell of DRAM, a memory with a low refresh frequency and low power consumption can be manufactured.

[0006] In this specification and the like, a DRAM in which an oxide semiconductor transistor is applied to a memory cell is referred to as an "oxide semiconductor DRAM" or a "DOSRAM (registered trademark, Dynamic Oxide Semiconductor Random Access Memory)".

[0007] On the other hand, oxide semiconductors have attracted attention as semiconductors that can be used in transistors in recent years. As oxide semiconductors, in addition to single metal oxides such as indium oxide and zinc oxide, multinary metal oxides are also known. Among multinary metal oxides, research on In-Ga-Zn oxide (also called IGZO) is particularly hot.

[0008] Through research on IGZO, a CAAC (c-axis aligned crystalline) structure and a nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been discovered in oxide semiconductors (see Non-Patent Documents 2 to 4).

[0009] Non-Patent Documents 2 and 3 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. In addition, Non-Patent Documents 5 and 6 disclose that an oxide semiconductor having a lower crystallinity than a CAAC structure and an nc structure also has minute crystals.

[0010] Non-Patent Document 7 reports that a transistor using an oxide semiconductor has an extremely small off-state current, and Non-Patent Documents 8 and 9 report LSIs and displays that utilize the extremely small off-state current property.

[0011] [Prior technical literature]

[0012] [Patent Document]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 2012-256820

[0014] [Non-patent literature]

[0015] [Non-patent document 1] T. Onuki et al., "DRAM with Storage Capacitance of 3.9fFusing CAAC-OS Transistor with L of 60nm and having More Than 1-h RetentionCharacteristics", Ext.Abstr.SSDM, 2014, pp.430-431.

[0016] [Non-patent document 2] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186

[0017] [Non-patent document 3] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0018] [Non-patent document 4] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154

[0019] [Non-patent document 5] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022

[0020] [Non-patent document 6] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164

[0021] [Non-patent document 7] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7

[0022] [Non-patent document 8] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217

[0023] [Non-patent document 9] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention

[0024] Technical problem to be solved by the invention

[0025] OS transistors apply a negative potential to the back gate, and the threshold voltage drifts in the positive direction, which can reduce the current Ids (also called cut-off current) flowing between the source and the drain when the gate voltage Vgs to the source is 0 V. In other words, in DRAM (DOSRAM) in which OS transistors are applied to memory cells, the data retention time can be extended.

[0026] However, in order for the potential applied to the back gate of the transistor to affect the electrical characteristics of the transistor, a relatively large potential may be required. In addition, increasing the potential applied to the back gate of the transistor may reduce the reliability of the transistor.

[0027] One object of one embodiment of the present invention is to provide a storage device having a long data retention time and high reliability. One object of one embodiment of the present invention is to provide a novel storage device. One object of one embodiment of the present invention is to provide an electronic device including a novel storage device.

[0028] Note that one embodiment of the present invention does not need to achieve all of the above-mentioned purposes, as long as at least one purpose can be achieved. In addition, the recording of the above-mentioned purpose does not prevent the existence of other purposes. The purposes other than the above-mentioned purposes can be obvious from the description of the specification, claims, drawings, etc., and the purposes other than the above-mentioned purposes can be extracted from the description of the specification, claims, drawings, etc.

[0029] Solutions to technical problems

[0030] One embodiment of the present invention is a storage device, comprising: a driver circuit; and a plurality of storage cells. The storage cell comprises a transistor and a capacitor, one of the source and the drain of the transistor is electrically connected to an electrode of the capacitor, and the transistor contains a metal oxide in a channel formation region. The transistor comprises a first gate and a second gate, and the first gate and the second gate include regions overlapping each other across the channel formation region. The driver circuit has a function of driving the first gate, and during the period when the storage cell holds data, the driver circuit outputs a first potential lower than the potential applied to the source and the drain of the transistor to the first gate, and applies a second potential lower than the potential applied to the source and the drain of the transistor to the second gate.

[0031] In the above embodiment, the second potential is lower than the first potential.

[0032] One embodiment of the present invention is a storage device, comprising: a driver circuit; and a plurality of storage cells. The storage cell comprises a transistor and a capacitor, one of the source and the drain of the transistor is electrically connected to an electrode of the capacitor, and the transistor contains a metal oxide in a channel formation region. The transistor comprises a first gate and a second gate, and the first gate and the second gate include regions overlapping each other across the channel formation region. The driver circuit has a function of driving the first gate and the second gate, and during a period when the storage cell holds data, the driver circuit outputs a first potential lower than the potential applied to the source and the drain of the transistor to the first gate, and during a period when the storage cell holds data, the driver circuit outputs a second potential lower than the potential applied to the source and the drain of the transistor to the second gate.

[0033] In the above embodiment, the metal oxide contains at least one or both of In (indium) and Zn (zinc).

[0034] In the above embodiment, the metal oxide contains Ga (gallium).

[0035] One embodiment of the present invention is an electronic device including the storage device described in the above embodiment.

[0036] Effects of the Invention

[0037] According to one embodiment of the present invention, a storage device having a long data retention time and high reliability can be provided. According to one embodiment of the present invention, a novel storage device can be provided. According to one embodiment of the present invention, an electronic device including a novel storage device can be provided.

[0038] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. Effects other than the above are obvious from the description of the specification, claims, drawings, etc., and can be extracted from the description of the specification, claims, drawings, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] [ Figure 1 ]A block diagram showing an example of the structure of a memory.

[0040] [FIG. 2] A is a diagram illustrating a memory cell array, and B is a circuit diagram showing a structural example of a memory cell. [FIG. 2] FIG.

[0041] [Fig. 3] A, B, and C are circuit diagrams showing structural examples of memory cells.

[0042] [FIG. 4] A is a block diagram showing a configuration example of a word line driver circuit, and B is a circuit diagram showing a configuration example of a circuit LVB. [FIG. 4] FIG.

[0043] [Fig. 5] A and B are diagrams showing input and output examples of a word line driver circuit.

[0044] [Fig. 6] A and B are circuit diagrams showing a configuration example of a potential generating circuit.

[0045] [ Figure 7 ]A diagram illustrating a structural example of a memory cell array and a bit line driver circuit.

[0046] [ Figure 8 ]A diagram illustrating an example of a circuit configuration.

[0047] [ Fig. 9 ]A timing diagram illustrating an example of the operation of a storage device.

[0048] [ Fig.10 ]A timing diagram illustrating an example of the operation of a storage device.

[0049] [ Fig.11 ]A timing diagram illustrating an example of the operation of a storage device.

[0050] [ Fig.12] shows a cross-sectional view of a structural example of a semiconductor device.

[0051] [Fig. 13] A, B, and C are cross-sectional views showing structural examples of transistors.

[0052] [Figure 14] A is a top view showing a structural example of a transistor, and B and C are cross-sectional views showing a structural example of a transistor.

[0053] [Figure 15] A is a top view showing a structural example of a transistor, and B and C are cross-sectional views showing a structural example of a transistor.

[0054] [Figure 16] A is a top view showing a structural example of a transistor, and B and C are cross-sectional views showing a structural example of a transistor.

[0055] [Figure 17] A is a top view showing a structural example of a transistor, and B and C are cross-sectional views showing a structural example of a transistor.

[0056] [Figure 18] A is a top view showing a structural example of a transistor, and B and C are cross-sectional views showing a structural example of a transistor.

[0057] [Figure 19] A is a top view showing a structural example of a transistor, and B is a stereoscopic view showing a structural example of a transistor.

[0058] [Fig. 20] A and B are cross-sectional views showing structural examples of transistors.

[0059] [Figure 21] A and C are cross-sectional views of a transistor, and B and D are graphs showing electrical characteristics of the transistor.

[0060] [ Fig. 22 ]Diagram illustrating the concept of the product.

[0061] [Figure 23] A, B, C, D, E1, and E2 are diagrams showing structural examples of electronic devices.

[0062] [ Fig.24 ]Describes the V G -I D Plot of the temperature dependence of the properties.

[0063] [Fig. 25] A, B, and C are diagrams illustrating a method for calculating an operating frequency.

[0064] [ Fig.26 ]A diagram showing the calculation results of the operating frequency.

[0065] [Figure 27] A is a three-dimensional diagram of a transistor structure, and B is a diagram of the back gate voltage dependence of Id-Vg characteristics.

[0066] [ FIG. 28 ] A is a diagram showing the back gate voltage Vbg dependency of the field effect mobility μFE, and B is a diagram showing the back gate voltage Vbg dependency of the threshold voltage Vth.

[0067] [ Fig.29 ]Block diagram of 64kb DOSRAM.

[0068] [Fig. 30] A is a graph showing the Id-Vg characteristics of CAAC-IGZO FET, and B and C are graphs showing the operating voltage.

[0069] [ Fig.31 ]A diagram showing the evaluation results of the data retention status of DOSRAM.

[0070] [Fig. 32] A and B show the evaluation results of the holding time and yield at an ambient temperature of 85°C.

[0071] [Figure 33]A is a block diagram of a negative potential generating circuit, and B is a diagram of an operating waveform of the negative potential generating circuit.

[0072] [Figure 34] A is a diagram showing the operating conditions of the ring oscillator, and B is a diagram showing the operating conditions of the charge pump.

[0073] [Fig. 35]A is a circuit diagram of a comparator, and B is a diagram of an operating waveform of the comparator.

[0074] [Figure 36] Estimation of the power consumption and area occupied by 1Mb DOSRAM.

[0075] [ Fig.37 ]Photo of the DOSRAM chip being trial-produced. DETAILED DESCRIPTION

[0076] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0077] The plurality of embodiments described below can be combined as appropriate. In addition, when a plurality of configuration examples are described in one embodiment, these configuration examples can be combined as appropriate with each other.

[0078] The block diagrams in this specification show components classified according to their functions in independent blocks; however, actual components are difficult to be clearly divided according to their functions, and one component may have a plurality of functions.

[0079] In the drawings, for the sake of convenience, the size, thickness of the layer or the region are sometimes exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings. In the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0080] In the drawings and the like, the same reference numerals may be used to indicate the same components, components having the same functions, components formed of the same material, components formed at the same time, and the like, and repeated descriptions may be omitted.

[0081] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0082] In this specification, etc., words and phrases expressing arrangement such as "on" or "below" are not limited to the positional relationship of components being "directly above" or "directly below". For example, "a gate electrode on a gate insulating layer" includes a case where another component is included between the gate insulating layer and the gate electrode.

[0083] In addition, ordinal numbers such as “first”, “second”, and “third” in this specification and the like are provided to avoid confusion among constituent elements and are not used to limit the number.

[0084] In this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0085] Note that in this specification, etc., "voltage" often refers to a potential difference between a certain potential and a reference potential (eg, ground potential). Therefore, voltage and potential difference can be interchanged.

[0086] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the drain and the source through the channel formation region. Note that in this specification, etc., the channel formation region refers to a region where current mainly flows.

[0087] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and the drain may be interchanged. Therefore, in this specification, etc., the source and the drain may be interchanged.

[0088] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state where the voltage Vgs of the gate to the source is lower than the threshold voltage Vth, and in a p-channel transistor, the off state refers to a state where the voltage Vgs of the gate to the source is higher than the threshold voltage Vth. In other words, the off-state current of an n-channel transistor sometimes refers to the drain current when the voltage Vgs of the gate to the source is lower than the threshold voltage Vth.

[0089] In the above description of the off-state current, the drain can be referred to as the source. That is, the off-state current sometimes refers to the source current when the transistor is in the off state. In addition, the leakage current sometimes means the same as the off-state current. In this specification, etc., the off-state current sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

[0090] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors), and the like.

[0091] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide has at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). That is, a transistor containing a metal oxide in a channel formation region can be referred to as an "oxide semiconductor transistor" or "OS transistor". Similarly, the above-mentioned "transistor using an oxide semiconductor" is also a transistor containing a metal oxide in a channel formation region.

[0092] In addition, in this specification, etc., a metal oxide containing nitrogen may also be referred to as a metal oxide. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride. The details of the metal oxide will be described later.

[0093] (Implementation Method 1)

[0094] In this embodiment, a configuration example of a storage device according to one embodiment of the present invention is described. A storage device according to one embodiment of the present invention is a storage device that can operate using semiconductor characteristics, and is also called a memory.

[0095] <Memory Configuration Example>

[0096] Figure 1 1 is a block diagram showing a configuration example of a memory 100 according to one embodiment of the present invention. The memory 100 includes a peripheral circuit 111 and a memory cell array 201 (in Figure 1 The peripheral circuit 111 includes a row decoder 121, a word line driver circuit 122, a bit line driver circuit 130, an output circuit 140, a negative potential generating circuit 150, a negative potential generating circuit 151, and a control logic circuit 160. Note that in the drawings described in this specification, etc., the flow of main signals is shown by arrows or lines, and power lines and the like are sometimes omitted.

[0097] The bit line driver circuit 130 includes a column decoder 131, a precharge circuit 132, a sense amplifier 133, and an input-output circuit 134. The precharge circuit 132 has a function of precharging the wiring BL. The sense amplifier 133 has a function of amplifying a data signal read from the wiring BL, and the input-output circuit 134 has a function of writing a data signal to the wiring BL and a function of outputting the data signal read from the wiring BL to the output circuit 140. Note that the column decoder 131, the precharge circuit 132, the sense amplifier 133, and the like are described in detail in Embodiment 2.

[0098] The wiring BL, the wiring WL, and the wiring WLB are connected to the memory cell 211 (in the memory cell array 201) Figure 1 The amplified data signal is output to the outside of the memory 100 as a digital data signal RDATA through the output circuit 140.

[0099] As power supplies, the memory 100 is supplied from the outside with a low power supply potential VSS, a high power supply potential VDD for the peripheral circuit 111, and a high power supply potential VIH for the memory cell array 201. Here, the high power supply potential VDD is a potential higher than the low power supply potential VSS. In addition, for example, the high power supply potential VIH may be a potential higher than the high power supply potential VDD or a potential equal to the high power supply potential VDD.

[0100] The negative potential generating circuit 150 generates a low power supply potential VLL from a power supply supplied from the outside, and the negative potential generating circuit 151 generates a low power supply potential VBL. The low power supply potential VLL and the low power supply potential VBL are lower than the low power supply potential VSS. Note that the memory 100 does not include the negative potential generating circuit 150 and the negative potential generating circuit 151, and the low power supply potential VLL and the low power supply potential VBL may be supplied from the outside of the memory 100.

[0101] Control signals (CE, WE, RE), address signals ADDR, and data signals WDATA are input from the outside to the memory 100. The address signal ADDR is input to the row decoder 121 and the column decoder 131, and WDATA is input to the input / output circuit 134.

[0102] The control logic circuit 160 processes the input signals (CE, WE, RE) from the outside to generate control signals for the row decoder 121 and the column decoder 131. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 160 are not limited to these, and other control signals may be input as needed.

[0103] In the memory 100, the above-mentioned circuits, signals, and potentials may be appropriately used or omitted as necessary. Alternatively, other circuits, other signals, or other potentials may be added.

[0104] Here, an OS transistor can be applied to the transistor constituting the memory cell 211. Since the off-state current of the OS transistor is very small, the data written in the memory cell 211 can be retained for a long time. Therefore, the refresh frequency of the memory cell 211 can be reduced, and the memory 100 with low power consumption can be realized. Note that the details of the OS transistor are described in Embodiments 3 and 4.

[0105] In addition, the OS transistor is a thin film transistor and can be stacked on a semiconductor substrate. For example, a Si transistor formed on a single crystal silicon substrate can be applied to the transistor constituting the peripheral circuit 111. The peripheral circuit 111 using the Si transistor can operate at high speed. In addition, the memory cell 211 using the OS transistor can be stacked above the peripheral circuit 111.

[0106] Figure 2A Detailed structure of the memory cell array 201 is shown. The memory cell array 201 includes m×n memory cells 211 per column (m is an integer greater than or equal to 1) and n memory cells 211 per row (n is an integer greater than or equal to 1), and the memory cells 211 are arranged in a matrix. Figure 2AThe address of the storage unit 211 is also shown, and [1, 1], [m, 1], [i, j], [1, n], [m, n] (i is an integer greater than 1 and less than m, j is an integer greater than 1 and less than n) is the address of the storage unit 211.

[0107] In addition, each memory cell 211 is connected to a wiring BL, a wiring WL, and a wiring WLB. The memory cell array 201 includes n wirings BL (BL(1) to BL(n)), m wirings WL (WL(1) to WL(m)), and m wirings WLB (WLB(1) to WLB(m)). Figure 2A As shown, the memory cell 211 of the address [i, j] is electrically connected to the word line driver circuit 122 through the wiring WL(i) and the wiring WLB(i), and is electrically connected to the bit line driver circuit 130 through the wiring BL(j).

[0108] 〈Memory cell structure example〉

[0109] Figure 2B is a circuit diagram showing a configuration example of the storage unit 211.

[0110] The memory cell 211 includes a transistor M11 and a capacitor CA. The transistor M11 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0111] One of the source and drain of the transistor M11 is electrically connected to the first terminal of the capacitor CA, and the other of the source and drain of the transistor M11 is connected to the wiring BL. The gate of the transistor M11 is connected to the wiring WL, and the back gate of the transistor M11 is connected to the wiring WLB. The second terminal of the capacitor CA is connected to the wiring CAL.

[0112] Wiring BL is used as a bit line, and wiring WL is used as a word line. Wiring CAL is used as wiring for applying a predetermined potential to the second terminal of capacitor CA. In addition, wiring WLB is used as wiring for applying a potential to the back gate of transistor M11. By applying an arbitrary potential to wiring WLB, the threshold voltage of transistor M11 can be increased or decreased.

[0113] The transistor M11 has a switch function that turns the first terminal of the capacitor CA and the wiring BL into a conductive state or a non-conductive state. By applying a high-level potential to the wiring WL, the first terminal of the capacitor CA and the wiring BL are turned into a conductive state, and data is written or read. That is, the memory cell 211 is a memory that stores data by accumulating charge in the capacitor CA, and the data stored in the memory cell 211 is written or read through the wiring BL and the transistor M11.

[0114] As the transistor M11, a transistor (OS transistor) containing a metal oxide in the channel formation region can be used. For example, in the channel formation region of the transistor M11, a metal oxide containing any one of indium, element M (element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium) and zinc can be used. In particular, a metal oxide composed of indium, gallium and zinc is preferably used.

[0115] Since the off-state current of the OS transistor is very small, the data written in the memory cell 211 can be retained for a long time by using the OS transistor as the transistor M11. Therefore, the refresh frequency of the memory cell 211 can be reduced, and the memory 100 with low power consumption can be realized.

[0116] Alternatively, by using an OS transistor as the transistor M11 , it is not necessary to perform a refresh operation of the memory cell 211 . Alternatively, by using an OS transistor as the transistor M11 , multi-valued data or analog data can be held in the memory cell 211 .

[0117] By using an OS transistor as the transistor M11, the above-mentioned DOSRAM can be configured.

[0118] <Memory cell structure example 2>

[0119] The structure of the storage unit 211 is not limited to the above-described structure. Figure 3A The storage unit 212 shown is another structural example of the storage unit 211.

[0120] The memory cell 212 includes a transistor M12, a transistor M13, and a capacitor CB. The transistor M12 includes a front gate and a back gate.

[0121] One of the source and drain of the transistor M12 is electrically connected to the first terminal of the capacitor CB and the gate of the transistor M13, and the other of the source and drain of the transistor M12 is connected to the wiring WBL. The gate of the transistor M12 is connected to the wiring WL, and the back gate of the transistor M12 is connected to the wiring WLB. The second terminal of the capacitor CB is connected to the wiring CAL. One of the source and drain of the transistor M13 is connected to the wiring SL, and the other of the source and drain of the transistor M13 is connected to the wiring RBL.

[0122] Wiring WBL is used as a write bit line, wiring RBL is used as a read bit line, and wiring WL is used as a word line. Wiring CAL is used as wiring for applying a predetermined potential to the second terminal of capacitor CB. In addition, wiring WLB is used as wiring for applying a potential to the back gate of transistor M12. By applying an arbitrary potential to wiring WLB, the threshold voltage of transistor M12 can be increased or decreased.

[0123] The transistor M12 has a switch function for connecting or disconnecting the first terminal of the capacitor CB and the wiring WBL.

[0124] By applying a high-level potential to the wiring WL, the transistor M12 is turned on, and the first terminal of the capacitor CB is electrically connected to the wiring WBL to write data. Specifically, when the transistor M12 is turned on, a potential corresponding to the written data is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M13. Then, a low-level potential is applied to the wiring WL, and the transistor M12 is turned off to maintain the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M13.

[0125] The data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M13 depends on the potential of the gate of the transistor M13 and the potential of one of the source and drain of the transistor M13 (wiring SL), and the potential of the other of the source and drain of the transistor M13 is determined according to the above current. Therefore, by reading the potential of the wiring RBL connected to the other of the source and drain of the transistor M13, the potential maintained at the first terminal of the capacitor CB (or the gate of the transistor M13) can be read. In other words, the data written in the storage unit 212 can be read according to the potential maintained at the first terminal of the capacitor CB (or the gate of the transistor M13).

[0126] In addition, as the transistor M12, a transistor (OS transistor) containing a metal oxide in the channel formation region can be used. The off-state current of the OS transistor is very small, so by using the OS transistor as the transistor M12, the data written in the memory cell 212 can be retained for a long time. In addition, there is no particular limitation on the transistor M13. For example, as the transistor M13, both an OS transistor and a Si transistor can be used.

[0127] The memory cell 212 is a gain unit type memory cell of 2 transistors and 1 capacitor. The gain unit type memory cell can work as a memory by amplifying the accumulated charge using the closest transistor even when the capacitance of the capacitor is small. In addition, by using an OS transistor with a very small off-state current as the transistor M12, the accumulated charge can be maintained even during the period when the power supply is stopped, so that the memory cell 212 has the properties of a non-volatile memory. In this specification, etc., a memory composed of a gain unit type memory cell using an OS transistor is referred to as a "NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory)". NOSRAM rewrites data by using the charge and discharge of a capacitor, so in principle there is no limit to the number of times it can be rewritten.

[0128] Alternatively, the memory cell 212 may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BL. Figure 3B A structural example in which the wiring WBL and the wiring RBL are combined into one wiring BL is shown.

[0129] exist Figure 3B In the memory cell 213 shown, the other of the source and drain of the transistor M12 and the other of the source and drain of the transistor M13 are connected to the wiring BL. That is, in the memory cell 213, the write bit line and the read bit line work as one wiring BL. At this time, when writing data, it is preferable to make the wiring SL in an electrically floating state.

[0130] <Memory cell structure example 3>

[0131] Alternatively, the memory cell 212 may be a gain unit type memory cell having three transistors and one capacitor. Figure 3C A configuration example is shown in which a gain unit type memory cell having three transistors and one capacitor is used as the memory cell 212 .

[0132] Figure 3C The memory cell 214 shown includes transistors M14 to M16 and a capacitor CC. The transistor M14 includes a front gate and a back gate.

[0133] One of the source and drain of the transistor M14 is electrically connected to the first terminal of the capacitor CC and the gate of the transistor M15, and the other of the source and drain of the transistor M14 is connected to the wiring BL. The gate of the transistor M14 is connected to the wiring WL, and the back gate of the transistor M14 is connected to the wiring WLB. The second terminal of the capacitor CC is electrically connected to the wiring CAL and one of the source and drain of the transistor M15, and the other of the source and drain of the transistor M15 is electrically connected to one of the source and drain of the transistor M16. The other of the source and drain of the transistor M16 is connected to the wiring BL, and the gate of the transistor M16 is connected to the wiring RWL.

[0134] Wiring BL is used as a bit line, wiring WL is used as a write word line, and wiring RWL is used as a read word line. Wiring CAL is used as wiring for applying a predetermined potential to the second terminal of capacitor CC (for example, applying a low-level potential as a predetermined potential). In addition, wiring WLB is used as wiring for applying a potential to the back gate of transistor M14. By applying an arbitrary potential to wiring WLB, the threshold voltage of transistor M14 can be increased or decreased.

[0135] The transistor M14 has a switch function for connecting or disconnecting the first terminal of the capacitor CC and the wiring BL, and the transistor M16 has a switch function for connecting or disconnecting the other of the source and the drain of the transistor M15 and the wiring BL.

[0136] By applying a high-level potential to the wiring WL, the transistor M14 is turned on, and the first terminal of the capacitor CC is electrically connected to the wiring BL to write data. Specifically, when the transistor M14 is turned on, a potential corresponding to the written data is applied to the wiring BL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M15. Then, a low-level potential is applied to the wiring WL, and the transistor M14 is turned off to maintain the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M15.

[0137] Data is read by applying a predetermined potential (precharge) to the wiring BL, then making the wiring BL electrically floating, and applying a high-level potential to the wiring RWL. By applying a high-level potential to the wiring RWL, the transistor M16 is turned on, and the other of the source and drain of the transistor M15 is electrically connected to the wiring BL. At this time, a voltage corresponding to the potential difference between the wiring BL and the wiring CAL is applied between the source and drain of the transistor M15, and the current flowing between the source and drain of the transistor M15 depends on the potential of the gate of the transistor M15 and the voltage applied between the source and drain.

[0138] Here, since the potential of the wiring BL changes according to the current flowing between the source and the drain of the transistor M15, the potential of the first terminal of the capacitor CC (or the gate of the transistor M15) can be read by reading the potential of the wiring BL. In other words, the data written in the memory cell 214 can be read according to the potential held at the first terminal of the capacitor CC (or the gate of the transistor M15).

[0139] As the transistor M14, a transistor (OS transistor) containing a metal oxide in the channel formation region can be used. The off-state current of the OS transistor is very small, so by using the OS transistor as the transistor M14, the data written in the memory cell 214 can be retained for a long time. In addition, there is no particular limitation on the transistor M15 and the transistor M16. For example, as the transistor M15 and the transistor M16, both the OS transistor and the Si transistor can be used.

[0140] Note that although the reference FIG. 3A to FIG. 3C Although other configuration examples of the memory cell 211 have been described, the configuration examples of the memory cell 211 are not limited to these examples, and the circuit configuration can be changed as appropriate.

[0141] 〈Configuration Example of Word Line Driver Circuit〉

[0142] Figure 4A is a block diagram showing a configuration example of the word line driver circuit 122.

[0143] The word line driver circuit 122 has a function of driving the wiring WL used as the word line. The word line driver circuit 122 receives the signal WI and the signal WIB for driving the wiring WL and the wiring WLB from the row decoder 121. Here, the signal WI and the signal WIB are digital signals represented by a high level or a low level, and the signal WIB is an inversion signal obtained by inverting the logic of the signal WI.

[0144] Note that there are m wirings WL and WLB, so the number of signals WI and WIB is also m. Figure 4A In the example, they are denoted as WI(1) to WI(m) and WIB(1) to WIB(m).

[0145] Furthermore, since the row decoder 121 is supplied with the low power supply potential VSS and the high power supply potential VDD, the potential corresponding to the high level of the signals WI and WIB is the high power supply potential VDD, and the potential corresponding to the low level of the signals WI and WIB is the low power supply potential VSS.

[0146] On the other hand, in the memory cell array 201, the high power supply potential VIH is used as the potential corresponding to the high level of the wiring WL, and the low power supply potential VLL is used as the potential corresponding to the low level of the wiring WL. In addition, the low power supply potential VBL is supplied to the wiring WLB.

[0147] Therefore, the word line driver circuit 122 has a function of adjusting the high level and / or low level of the input signal (also referred to as a level adjustment function) and a function of adding a drive wiring WL to the input signal (in Figure 4A The word line driver circuit 122 includes m circuits LVB. Figure 4A In the figure, they are denoted as LVB(1) to LVB(m).

[0148] The word line driver circuit 122 receives the low power supply potential VBL as input, and outputs the low power supply potential VBL to the wiring WLB (in Figure 4A are denoted as WLB(1) to WLB(m)).

[0149] <Configuration Example of Circuit LVB>

[0150] Figure 4B is a circuit diagram showing a configuration example of the circuit LVB.

[0151] The circuit LVB includes n-channel transistors 13 to 21 and p-channel transistors 33 to 41. The circuit LVB also includes an input terminal WI_IN, an input terminal WIB_IN, a wiring VIH_IN, a wiring VSS_IN, a wiring VLL_IN, and an output terminal WL_OUT.

[0152] In the circuit LVB, the input terminal WI_IN receives the signal WI, the input terminal WIB_IN receives the signal WIB, the wiring VIH_IN receives the high power supply potential VIH, the wiring VSS_IN receives the low power supply potential VSS, and the wiring VLL_IN receives the low power supply potential VLL. In the circuit LVB, the output terminal WL_OUT outputs the signal for driving the wiring WL.

[0153] Furthermore, in the circuit LVB, one of the source and the drain of the transistor 13 is electrically connected to the wiring VSS_IN, the other of the source and the drain of the transistor 13 is electrically connected to one of the source and the drain of the transistor 34 and the gate of the transistor 35, and the gate of the transistor 13 is electrically connected to the input terminal WI_IN and the gate of the transistor 34. The other of the source and the drain of the transistor 34 is electrically connected to one of the source and the drain of the transistor 33, and the other of the source and the drain of the transistor 33 is electrically connected to the wiring VIH_IN.

[0154] One of the source and drain of the transistor 14 is electrically connected to the wiring VSS_IN, the other of the source and drain of the transistor 14 is electrically connected to one of the source and drain of the transistor 36 and the gate of the transistor 33, and the gate of the transistor 14 is electrically connected to the input terminal WIB_IN and the gate of the transistor 36. The other of the source and drain of the transistor 36 is electrically connected to one of the source and drain of the transistor 35, and the other of the source and drain of the transistor 35 is electrically connected to the wiring VIH_IN. Here, the connection portion between the other of the source and drain of the transistor 36 and one of the source and drain of the transistor 35 is referred to as a node N11, and other elements electrically connected to the node N11 will be described later.

[0155] The transistor 13 , the transistor 14 , and the transistors 33 to 36 have a level adjustment function of converting the potential corresponding to the high level of the inputted signals WI and WIB from the high power supply potential VDD to the high power supply potential VIH.

[0156] In the circuit LVB, one of the source and the drain of the transistor 15 is electrically connected to the wiring VSS_IN, the other of the source and the drain of the transistor 15 is electrically connected to one of the source and the drain of the transistor 37, the gate of the transistor 16, and the gate of the transistor 38, and the gate of the transistor 15 is electrically connected to the node N11 and the gate of the transistor 37. The other of the source and the drain of the transistor 37 is electrically connected to the wiring VIH_IN. Here, the connection portion of the other of the source and the drain of the transistor 15, one of the source and the drain of the transistor 37, the gate of the transistor 16, and the gate of the transistor 38 is referred to as a node N12, and other elements electrically connected to the node N12 will be described later.

[0157] One of the source and the drain of the transistor 16 is electrically connected to the wiring VSS_IN, the other of the source and the drain of the transistor 16 is electrically connected to one of the source and the drain of the transistor 38, and the other of the source and the drain of the transistor 38 is electrically connected to the wiring VIH_IN. Here, the connection portion between the other of the source and the drain of the transistor 16 and one of the source and the drain of the transistor 38 is referred to as a node N13, and other elements electrically connected to the node N13 will be described later.

[0158] The transistor 15 and the transistor 37 have a function of generating an inversion signal of the signal at the node N11 .

[0159] In addition, in the circuit LVB, one of the source and the drain of the transistor 18 is electrically connected to the wiring VLL_IN, the other of the source and the drain of the transistor 18 is electrically connected to one of the source and the drain of the transistor 17, the other of the source and the drain of the transistor 17 is electrically connected to one of the source and the drain of the transistor 39 and the gate of the transistor 20, and the other of the source and the drain of the transistor 39 is electrically connected to the wiring VIH_IN. The gate of the transistor 17 is electrically connected to the node N12 and the gate of the transistor 39.

[0160] One of the source and drain of the transistor 20 is electrically connected to the wiring VLL_IN, the other of the source and drain of the transistor 20 is electrically connected to one of the source and drain of the transistor 19, the other of the source and drain of the transistor 19 is electrically connected to one of the source and drain of the transistor 40 and the gate of the transistor 18, and the other of the source and drain of the transistor 40 is electrically connected to the wiring VIH_IN. The gate of the transistor 19 is electrically connected to the node N13 and the gate of the transistor 40. Here, the connection portion between the other of the source and drain of the transistor 20 and one of the source and drain of the transistor 19 is referred to as a node N14, and other elements electrically connected to the node N14 will be described later.

[0161] The transistors 17 to 20 , the transistor 39 , and the transistor 40 have a function of level adjustment to convert the potential of the low level corresponding to the signal of the node N12 and the node N13 from the low power supply potential VSS to the low power supply potential VLL.

[0162] Furthermore, in the circuit LVB, one of the source and the drain of the transistor 21 is electrically connected to the wiring VLL_IN, the other of the source and the drain of the transistor 21 is electrically connected to one of the source and the drain of the transistor 41 and the output terminal WL_OUT, and the gate of the transistor 21 is electrically connected to the node N14 and the gate of the transistor 41. The other of the source and the drain of the transistor 41 is electrically connected to the wiring VIH_IN.

[0163] The transistor 21 and the transistor 41 have a function as a buffer for outputting a signal of the node N14 from the output terminal WL_OUT.

[0164] 〈Input and output examples of word line driver circuit〉

[0165] Figure 5A 1 is a diagram showing an example of input and output of the word line driver circuit 122 .

[0166] Reference Figure 5AThe relationship between the signal WI and the signal WIB input to the word line driver circuit 122 and the potential of the wiring WL and the wiring WLB driven by the word line driver circuit 122 is described. There are m signals WI, WIB, wiring WL, and wiring WLB, and thus, one of them (WI(i), WIB(i), wiring WL(i), and WLB(i)) is used as an example for description (i is an integer greater than 1 and less than m).

[0167] Figure 5A The vertical axis represents potentials, and represents, in order of increasing potential, a high power supply potential VIH, a high power supply potential VDD, a low power supply potential VSS, a low power supply potential VLL, and a low power supply potential VBL.

[0168] Figure 5A T1 and T2 in the figure represent time, and show that the wiring WL(i) is driven at almost the same time as the input of the signal WI(i) and the signal WIB(i). Note that in reality, there may be a delay time between the input of the signal WI(i) and the signal WIB(i) and the driving of the wiring WL(i), and the signal may have distortion or noise. Figure 5A The waveform of the ideal case is shown.

[0169] like Figure 5A As shown, the signal WI(i) and the signal WIB(i) are digital signals that represent a high level or a low level by using a high power supply potential VDD or a low power supply potential VSS. When data is written or read from the memory cell 211 electrically connected to the wiring WL(i) and the wiring WLB(i), the signal WI(i) becomes a high level (the signal WIB is an inverted signal of the signal WI, and thus becomes a low level).

[0170] The word line driver circuit 122 outputs a low power supply potential VLL to the wiring WL(i) when the signal WI(i) is at a low level, and outputs a high power supply potential VIH to the wiring WL(i) when the signal WI(i) is at a high level. In addition, the word line driver circuit 122 outputs a low power supply potential VBL to the wiring WLB(i).

[0171] Alternatively, the word line driver circuit 122 may drive the wiring WLB in addition to the wiring WL. When the word line driver circuit 122 drives the wiring WLB, for example, the word line driver circuit 122 is driven by adding a circuit LVB.

[0172] and Figure 5A same, Figure 5B 1 is a diagram showing an example of input and output of the word line driver circuit 122. Figure 5BAs shown, for example, the word line driver circuit 122 can output a low power supply potential VBL to the wiring WLB(i) when the signal WI(i) is at a low level, and output a potential between the high power supply potential VDD and the low power supply potential VSS to the wiring WLB(i) when the signal WI(i) is at a high level.

[0173] In this way, the word line driver circuit 122 changes the high level and / or low level of the signal WI(i) and the signal WIB(i) to drive the wiring WL(i) or the wiring WL(i) and the wiring WLB(i).

[0174] <Negative Potential Generating Circuit>

[0175] Then, in Fig. 6A and Figure 6B 2 shows configuration examples of a circuit 54 and a circuit 55 that can be applied to the negative potential generating circuit 150 and the negative potential generating circuit 151 .

[0176] Circuit 54 and circuit 55 are step-down charge pumps, and low power supply potential VSS is input to their input terminal IN, and low power supply potential VLL or low power supply potential VBL is output from their output terminal OUT. Here, as an example, the number of stages of the basic circuit of the charge pump circuit is 4, but it is not limited to this, and the charge pump circuit can also be configured with any number of stages.

[0177] Fig. 6A The circuit 54 shown includes transistors M21 to M24 and capacitors C21 to C24. Note that the transistors M21 to M24 are n-channel transistors.

[0178] The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT. In the transistors M21 to M24, each gate is electrically connected to one of the source and the drain, so that the transistors M21 to M24 are used as diodes. In addition, the gates of the transistors M21 to M24 are electrically connected to the capacitors C21 to C24, respectively.

[0179] The clock signal CLK is input to one electrode of the capacitors C21 and C23 of the odd number stages, and the clock signal CLKB is input to one electrode of the capacitors C22 and C24 of the even number stages. The clock signal CLKB is an inverted clock signal obtained by inverting the phase of the clock signal CLK.

[0180] The circuit 54 has a function of stepping down the low power supply potential VSS input to the input terminal IN to generate a low power supply potential VLL or a low power supply potential VBL. The circuit 54 can generate the low power supply potential VLL or the low power supply potential VBL by stepping down the low power supply potential VSS only by using the supply of the clock signal CLK and the clock signal CLKB.

[0181] Figure 6B The circuit 55 shown is composed of transistors M31 to M34 which are p-channel transistors. The description of the circuit 54 is used for the other components.

[0182] <Transistor M11>

[0183] As described above, OS transistors including back gates can be used as transistors M11, transistor M12, and transistor M14. In OS transistors, the threshold voltage can be increased or decreased by applying a potential to the back gate. Specifically, in OS transistors, when the potential applied to the back gate is increased, the threshold voltage drifts in the negative direction, and when the potential applied to the back gate is reduced, the threshold voltage drifts in the positive direction.

[0184] That is, by lowering the potential applied to the back gate (low power supply potential VBL in this specification, etc.), the current Ids (also referred to as the off-current) between the source and the drain when the voltage Vgs of the gate to the source is 0 V can be reduced. By reducing the off-current, the retention time of the data written in the memory cell 211 can be extended.

[0185] Furthermore, by applying a potential lower than the low power supply potential VSS (low power supply potential VLL in this specification, etc.) to the front gate when the transistor is in non-conduction (off state), the current flowing between the source and the drain can be reduced. That is, by applying the low power supply potential VLL to the front gate when the transistor is in non-conduction, even if the potential difference between the low power supply potential VBL and the low power supply potential VSS is reduced, the current flowing between the source and the drain of the transistor can be reduced.

[0186] By reducing the potential difference between the low power supply potential VBL and the low power supply potential VSS, the electric field strength of the insulating film (also referred to as gate insulating film or gate insulating layer) applied between the back gate and the channel formation region of the transistor can be reduced, thereby improving the reliability of the transistor. In other words, since the electric field stress applied to the transistor can be reduced, the reliability of the transistor can be improved. The memory 100 can be a storage device with a long data retention time and high reliability.

[0187] In addition, this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0188] (Implementation Method 2)

[0189] In this embodiment, a configuration example of the memory cell array 201 included in the memory 100 and an operation example thereof will be described.

[0190] Figure 7 Shows different from Figure 2A An example of a memory cell array 201. Figure 7 It is a folded bit-line memory cell array. Note that the memory cell 221 can also be used in an open bit-line memory cell array. Figure 7 The wiring WLB is omitted.

[0191] exist Figure 7 In the memory cell array 201 shown, there are m memory cells 221 in one column and n memory cells in one row, for a total of m×n memory cells 221, and the memory cells 221 are arranged in rows and columns. Figure 7 In FIG. 2 , the address of the storage unit 221 is also marked. For example, [i, j] represents the storage unit 221 at the i-th row and the j-th column.

[0192] in addition, Figure 7 The memory cell array 201 shown includes m wirings WL electrically connected to the word line driving circuit 122. The wiring WL(1) is electrically connected to the memory cell 221 of the first row. Similarly, the wiring WL(i) is electrically connected to the memory cell 221 of the i-th row.

[0193] In addition, Figure 7 In the memory cell array 201 shown in the figure, two wirings BIL (wiring BILa and wiring BILb) are included in one column. Figure 7 In the figures, the wiring BILa in the first column is represented as the wiring BILa(1), and the wiring BILb in the j-th column is represented as the wiring BILb(j).

[0194] The memory cells 221 arranged in the odd-numbered rows are electrically connected to one of the wiring BILa and the wiring BILb, and the memory cells 221 arranged in the even-numbered rows are electrically connected to the other of the wiring BILa and the wiring BILb.

[0195] In addition, the wiring BILa and the wiring BILb are electrically connected to the precharge circuit 132, the sense amplifier 133, and the input-output circuit 134 provided in each column. In addition, the input-output circuit 134 is electrically connected to the wiring SALa and the wiring SALb in each column. Figure 7 In the above description, the precharge circuit 132 of the first column is represented as the precharge circuit 132(1), and the precharge circuit 132 of the j-th column is represented as the precharge circuit 132(j). The same is true for the sense amplifier 133 and the input / output circuit 134. Note that the bit line driver circuit 130 includes a column decoder 131 (see Figure 1 ).

[0196] <Circuit Configuration Example>

[0197] Figure 8An example of the circuit configuration of the memory cell 221 in the J-th column, the precharge circuit 132, the sense amplifier 133, and the input / output circuit 134 is shown.

[0198] <Precharge Circuit 132>

[0199] The precharge circuit 132(j) includes n-channel transistors Tr21 to Tr23. In addition, transistors Tr21 to Tr23 may also be p-channel transistors. One of the source and drain of transistor Tr21 is connected to wiring BILa(j), and the other of the source and drain is connected to wiring PRE. One of the source and drain of transistor Tr22 is connected to wiring BILb(j), and the other of the source and drain is connected to wiring PRE. One of the source and drain of transistor Tr23 is connected to wiring BILa(j), and the other of the source and drain is connected to wiring BILb(j). The gate of transistor Tr21, the gate of transistor Tr22, and the gate of transistor Tr23 are connected to wiring PL. The precharge circuit PRC has a function of initializing the potential of wiring BILa(j) and wiring BILb(j).

[0200] <Sense Amplifier 133>

[0201] The sense amplifier 133(j) includes a p-channel transistor Tr31 and a transistor Tr32, and an n-channel transistor Tr33 and a transistor Tr34. One of the source and the drain of the transistor Tr31 is connected to the wiring SP, and the other of the source and the drain is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BILa(j). One of the source and the drain of the transistor Tr33 is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BLa(j), and the other of the source and the drain is connected to the wiring SN. One of the source and the drain of the transistor Tr32 is connected to the wiring SP, and the other of the source and the drain is connected to the gate of the transistor Tr31, the gate of the transistor Tr33, and the wiring BLb(j). One of the source and the drain of the transistor Tr34 is connected to the gate of the transistor Tr31, the gate of the transistor Tr33, and the wiring BLb(j), and the other of the source and the drain is connected to the wiring SN. The sense amplifier 133(j) has a function of amplifying the potential of the wirings BLa(j) and BILb(j). The sense amplifier 133(j) is used as a latch type sense amplifier.

[0202] <Input / Output Circuit 134>

[0203] The input / output circuit 134(j) includes an n-channel transistor Tr41 and a transistor Tr42. In addition, the transistor Tr41 and the transistor Tr42 may also be p-channel transistors. One of the source and the drain of the transistor Tr41 is connected to the wiring BILa(j), and the other of the source and the drain is connected to the wiring SALa(j). One of the source and the drain of the transistor Tr42 is connected to the wiring BILb(j), and the other of the source and the drain is connected to the wiring SALb(j). The gate of the transistor Tr41 and the gate of the transistor Tr42 are connected to the wiring CSEL.

[0204] The input / output circuit 134(j) has a function of controlling the conduction state of the wiring BILa(j) and the wiring SALa(j) and the conduction state of the wiring BILb(j) and the wiring SALb(j) according to the potential supplied to the wiring CSEL. That is, the input / output circuit 134(j) can be used to select whether to output a potential to the wiring SALa(j) and the wiring SALb(j).

[0205] The wiring SP, wiring SN, wiring CSEL, wiring PRE, and wiring PL have the function of transmitting signals for controlling the operation of the precharge circuit 132, the sense amplifier 133, and the input / output circuit 134. The wiring SP, wiring SN, wiring CSEL, wiring PRE, and wiring PL are connected to the wiring SP. Figure 1 The wirings SP, SN, CSEL, PRE, and PL are connected to the control logic circuit 160. The control logic circuit 160 has a function of supplying control signals to the wirings SP, SN, CSEL, PRE, and PL.

[0206] <Working Example>

[0207] use Figure 8 The illustrated memory cell 221[i,j], precharge circuit 132(j), sense amplifier 133(j), and input / output circuit 134(j) illustrate the operation mode of the memory 100. In addition, it is assumed that -3V is supplied to the wiring BGL(i).

[0208] <Read Mode>

[0209] First, use Fig. 9 The timing diagram of illustrates an example of the operation of the sense amplifier 133(j) when reading data from the memory cell 221[i,j].

[0210] [Period T11]

[0211] During period T11, the precharge circuit 132 (j) is operated to initialize the potentials of the wirings BILa (j) and the wirings BILb (j). Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the potential Vpre of the wiring PRE is supplied to the wirings BILa (j) and BILb (j). Note that the potential Vpre may be, for example, (VH_SP+VL_SN) / 2. VH_SP is a high level potential supplied to the wiring SP, and VL_SN is a low level potential supplied to the wiring SN.

[0212] During the period T11, the potential of the wiring CSEL is at a low level (VL_CSEL), and the transistors Tr41 and Tr42 in the input / output circuit 134(j) are in an off state. In addition, the potential of the wiring WL(i) is at a low level (VL_WL), and the transistor M11 included in the storage unit 221[i,j] is in an off state. Similarly, although Figure 8 Although not shown, the potential of the wiring WL[i+1] is low level (VL_WL), and the transistor M11 included in the memory cell 221[i+1,j] is in the off state. In addition, the potentials of the wirings SP and SN are the potential Vpre, and the sense amplifier 133(j) is in the stopped state.

[0213] Note that VL_WL is preferably a potential lower than VL_SN. In addition, VL_WL is preferably a potential lower than a potential obtained by subtracting the Vth of the transistor M11 from VL_SN. In other words, when VL_SN is set to a reference potential (0V), VL_WL can be set to a negative potential (also called a "negative potential" or a "negative bias").

[0214] By supplying a negative bias voltage to the wiring WL(i), the transistor M11 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0215] In addition, the transistor M11 can also be turned off by supplying a negative bias to the wiring BGL(i). In particular, by supplying a negative bias to both the wiring WL(i) and the wiring BGL(i), the same effect can be achieved with a smaller bias than when only one of them is supplied with a negative bias. In addition, since the electric field stress applied to the transistor M11 can be reduced, the reliability of the transistor M11 can be improved. Furthermore, the power consumption of the transistor M11 can be reduced. In other words, the reliability of the memory 100 can be improved and the power consumption can be reduced.

[0216] [Period T12]

[0217] During period T12, the potential of wiring PL is set to a low level (VL_PL), and transistors Tr21 to Tr23 are turned off. In addition, wiring WL(i) is selected. Specifically, by changing the potential of wiring WL(i) to a high level (VH_WL), transistor M11 included in storage unit 221[i,j] is turned on. As a result, in storage unit 221[i,j], wiring BILa(j) and capacitor CA are turned on through transistor M11, and the potential of wiring BILa(j) changes according to the amount of charge held by capacitor CA.

[0218] Here, VH_WL is preferably a potential higher than VH_SP. Specifically, VH_WL is preferably a potential higher than a potential obtained by adding Vth of the transistor M11 to VH_SP.

[0219] exist Fig. 9 , the case where data "1" is stored in the storage unit 221[i,j] and the amount of charge stored in the capacitor CA is large. Specifically, when the amount of charge stored in the capacitor CA is large, the charge is released from the capacitor CA to the wiring BILa(j), causing the potential of the wiring BILa(j) to rise by △V1 from the potential Vpre. On the other hand, when data "0" is stored in the storage unit 221[i,j] and the amount of charge stored in the capacitor CA is small, the charge flows from the wiring BILa(j) into the capacitor CA, causing the potential of the wiring BILa(j) to drop by △V2 (not shown).

[0220] During period T12, the potential of wiring CSEL is at low level (VL_CSEL), and transistors Tr41 and Tr42 in input / output circuit 134(j) are in off state. Also, the potentials of wiring SP and wiring SN are at potential Vpre, and sense amplifier 133(j) remains in stopped state.

[0221] [Period T13]

[0222] During period T13, the potential of wiring SP is changed to a high level (VH_SP), and the potential of wiring SN is changed to a low level (VL_SN). Then, the sense amplifier 133(j) is turned on. The sense amplifier 133(j) has a potential difference (VL_S) between the wiring BILa(j) and the wiring BILb(j). Fig. 9 Since the sense amplifier 133(j) is in the operating state, the potential of the wiring BILa(j) approaches the potential of the wiring SP (VH_SP) from Vpre+ΔV1. In addition, the potential of the wiring BILb(j) approaches the potential of the wiring SN (VL_SN) from Vpre.

[0223] Note that at the beginning of period T13, when the potential of wiring BILa(j) is Vpre-ΔV2, the sense amplifier 133(j) is in operation, so the potential of wiring BILa(j) approaches the potential of wiring SN (VL_SN) from Vpre-ΔV2. In addition, the potential of wiring BILb(j) approaches the potential of wiring SP (VH_SP) from the potential Vpre.

[0224] In addition, during the period T13, the potential of the wiring PL is low level (VL_PL), and the transistors Tr21 to Tr23 in the precharge circuit 132 (j) are in the off state. In addition, the potential of the wiring CSEL is low level (VL_CSEL), and the transistors Tr41 and Tr42 in the input-output circuit 134 (j) are in the off state. In addition, the potential of the wiring WL (i) is high level (VH_WL), and the transistor M11 included in the storage unit 221 [i, j] is in the on state. Therefore, in the storage unit 221 [i, j], the charge amount corresponding to the potential (VH_SP) of the wiring BILa (j) is stored in the capacitor CA.

[0225] [Period T14]

[0226] During the period T14, the potential of the wiring CSEL is controlled to turn on the input / output circuit 134(j). Specifically, the potential of the wiring CSEL is set to a high level (VH_CSEL), so that the transistor Tr41 and the transistor Tr42 are turned on. As a result, the potential of the wiring BILa(j) is supplied to the wiring SALa(j), and the potential of the wiring BILb(j) is supplied to the wiring SALb(j).

[0227] In addition, during the period T14, the potential of the wiring PL is at a low level (VL_PL), and in the precharge circuit 132 (j), the transistors Tr21 to Tr23 are turned off. In addition, the potential of the wiring WL (i) is at a high level (VH_WL), and the transistor M11 of the memory cell 221 [i, j] is turned on. In addition, the potential of the wiring SP is at a high level (VH_SP), the potential of the wiring SN is at a low level (VL_SN), and the sense amplifier 133 (j) is in an operating state. As a result, in the memory cell 221 [i, j], a charge corresponding to the potential (VH_SP) of the wiring BILa (j) is stored in the capacitor CA.

[0228] [Period T15]

[0229] In the period T15, the potential of the wiring CSEL is controlled to turn off the input / output circuit 134(j). Specifically, the potential of the wiring CSEL is set to a low level (VL_CSEL), so that the transistor Tr41 and the transistor Tr42 are turned off.

[0230] In addition, during period T15, VL_WL is supplied to the wiring WL(i), so that the wiring WL(i) is in a non-selected state. Specifically, the potential of the wiring WL(i) is low level (VL_WL). As a result, the transistor of the memory cell 221[i,j] is turned off. As a result, the charge amount corresponding to the potential (VH_SP) of the wiring BLa is stored in the capacitor CA of the memory cell 221[i,j]. Therefore, even after the data is read, the data is retained in the memory cell 221[i,j].

[0231] By setting VL_WL supplied to the word line WL(i) to a negative potential, the transistor M11 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0232] Furthermore, during period T15, even if the input / output circuit 134(j) is turned off, the potentials of the wirings BILa(j) and BILb(j) are held by the sense amplifier 133(j) as long as the sense amplifier 133(j) is in operation. Thus, the sense amplifier 133(j) has a function of temporarily holding the data read from the memory cell 221[i,j].

[0233] By performing the above operation, data can be read from the memory cell 221[i,j]. The read data is supplied to the output circuit 140 (see Figure 1 ). Note that data can also be read from the storage unit 221[i+1,j] in the same manner as the storage unit 221[i,j].

[0234] <Write Mode>

[0235] Next, use Fig.10 The timing diagram shown illustrates an example of the operation of the sense amplifier 133(j) when writing data to the memory cell 221[i,j]. Data can be written to the memory cell 221[i+1,j] based on the same principle as above.

[0236] [Period T21]

[0237] During the period T21, the transistors Tr21 to Tr23 included in the precharge circuit 132 (j) are turned on, and the potentials of the wirings BILa (j) and BILb (j) are initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the wiring BILa (j) and the wiring BILb (j) are supplied with the potential Vpre of the wiring PRE. In addition, the potential Vpre may be, for example, (VH_SP+VL_SN) / 2.

[0238] [Period T22]

[0239] Then, during period T22, the potential of wiring PL is set to a low level (VL_PL), so that transistors Tr21 to Tr23 are turned off. In addition, the wiring WL(i) connected to the storage unit 221[i,j] to which data is written is selected. Specifically, the potential of wiring WL(i) is set to a high level (VH_WL), so that the transistor M11 of the storage unit 221[i,j] is turned on. As a result, in the storage unit 221[i,j], wiring BILa(j) and capacitor CA are turned on through transistor M11.

[0240] Note that during operation in the write mode, a negative bias may be constantly supplied to the wiring BGL(i), or the potential of the wiring BGL(i) may be raised when the potential of the wiring WL(i) reaches VH_WL. Fig.10 In the period T22, the potential of the wiring BGL(i) is set to an L potential (for example, 0 V).

[0241] As the potential of the wiring BGL(i) rises with the potential of the wiring WL(i), the threshold voltage Vth of the transistor M11 decreases, thereby increasing the operating speed. As a result, the time required for the write operation can be shortened. Therefore, the operating speed of the memory 100 can be increased.

[0242] In addition, by raising the potential of both the wiring WL(i) and the wiring BGL(i), the same operating speed can be achieved with less potential rise than when only one of the potentials is raised. In addition, since the electric field stress applied to the transistor M11 can be reduced, the reliability of the transistor M11 can be improved. Furthermore, the power consumption of the transistor M11 can be reduced. In other words, the reliability of the memory 100 can be improved and the power consumption can be reduced.

[0243] At this time, when data “1” has been stored in the memory cell 221 [i, j], charge is discharged from the capacitor CA to the wiring BILa(j), so that the potential of the wiring BILa(j) rises from the potential Vpre by ΔV1.

[0244] [Period T23]

[0245] In the period T23, the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to a low level (VL_SN), so that the sense amplifier 133 (j) is in an operating state.

[0246] [Period T24]

[0247] In period T24, the potential of wiring CSEL is controlled to turn on the input / output circuit 134(j), thereby bringing wiring BILa(j) and wiring SALa(j) into conduction, and bringing wiring BILb(j) and wiring SALb(j) into conduction.

[0248] The data signal WDATA is supplied to the input-output circuit 134(j) through the wiring SALa(j) and the wiring SALb(j). By supplying a write potential corresponding to the data signal WDATA to the wiring SALa(j) and the wiring SALb(j), the write potential is supplied to the wiring BILa(j) and the wiring BILb(j) through the input-output circuit 134(j). For example, when data "0" is stored in the memory cell 221[i,j], a low level (VL_SN) is supplied to the wiring SALa(j), and a high level (VH_SP) is supplied to the wiring SALb(j).

[0249] Then, the switching states of the transistors Tr31 to Tr34 included in the sense amplifier 133(j) are reversed, the potential (VL_SN) of the wiring SN is supplied to the wiring BILa(j), and the potential (VL_SP) of the wiring SP is supplied to the wiring BILb(j). Thus, the charge amount corresponding to the potential (VL_SN) indicating data "0" is stored in the capacitor CA. By performing the above operation, data can be written to the memory cell 221[i,j].

[0250] [Period T25]

[0251] During period T25, VL_WL is supplied to the wiring WL(i) to make the wiring WL(i) in a non-selected state. Thus, the charge written into the memory cell 221[i, j] is retained. When the potential of the wiring BGL(i) rises with the rise of the potential of the wiring WL(i), the potential of the wiring BGL(i) is lowered when the potential of the wiring WL(i) reaches VL_WL. For example, -3V is supplied to the wiring BGL(i).

[0252] Furthermore, by setting the potential of the wiring CSEL to a low level (VL_CSEL), the transistor Tr41 and the transistor Tr42 are turned off.

[0253] Furthermore, even if the transistors Tr41 and Tr42 in the input / output circuit 134(j) are turned off after the potential of the wiring SALa(j) is supplied to the wiring BILa(j), the potentials of the wiring BILa(j) and the wiring BILb(j) can be maintained by the sense amplifier 133(j) as long as the sense amplifier 133(j) is in operation. Thus, the timing at which the transistors Tr41 and Tr42 are turned off from the on state can be either before or after the wiring WL(i) is selected.

[0254] By performing the above operation, data can be written to the memory cell 221 [i, j]. Note that data can also be written to the memory cell 221 [i+1, j] in the same manner as the memory cell 221 [i, j].

[0255] By setting VL_WL supplied to the wiring VL(i) to a negative potential, the transistor M11 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0256] <Refresh Mode>

[0257] In order to maintain the data written to the memory cell 221[i,j], a refresh operation (re-write operation) is performed at fixed intervals. Fig.11 The timing chart shown illustrates an example of the operation of the sense amplifier 133(j) in the refresh operation. The refresh operation can be performed based on the same principle as above.

[0258] [Period T31]

[0259] During the period T31, the transistors Tr21 to Tr23 included in the precharge circuit 132 (j) are turned on, and the potentials of the wirings BILa (j) and BILb (j) are initialized. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the potential Vpre of the wiring PRE is supplied to the wirings BILa (j) and BILb (j).

[0260] [Period T32]

[0261] During period T32, the potential of wiring PL is set to a low level (VL_PL), so that transistors Tr21 to Tr23 are turned off. In addition, the wiring WL(i) connected to the storage unit 221[i,j] to which data is written is selected. Specifically, the potential of wiring WL(i) is set to a high level (VH_WL), so that the transistor M11 of the storage unit 221[i,j] is turned on. As a result, in the storage unit 221[i,j], wiring BILa(j) and capacitor CA are turned on through transistor M11.

[0262] Note that during operation in the refresh mode, a negative bias may be constantly supplied to the wiring BGL(i), or the potential of the wiring BGL(i) may be raised when the potential of the wiring WL(i) reaches VH_WL. Fig.11 In the period T32, the potential of the wiring BGL(i) is set to an L potential (for example, 0 V).

[0263] By increasing the potential of the wiring BGL(i) as the potential of the wiring WL(i) increases, the operating speed of the transistor M11 can be increased. Thus, the time required for the refresh operation can be shortened. Therefore, the operating speed of the memory 100 can be increased.

[0264] In addition, by raising the potential of both the wiring WL(i) and the wiring BGL(i), the same operating speed can be achieved with less potential rise than when only one of the potentials is raised. In addition, since the electric field stress applied to the transistor M11 can be reduced, the reliability of the transistor M11 can be improved. Furthermore, the power consumption of the transistor M11 can be reduced.

[0265] At this time, when data “1” has been stored in the memory cell 221 [i, j], charge is discharged from the capacitor CA to the wiring BILa(j), so that the potential of the wiring BILa(j) rises from the potential Vpre by ΔV1.

[0266] [Period T33]

[0267] During the period T33, the potential of the wiring SP is set to a high level (VH_SP), and the potential of the wiring SN is set to a low level (VL_SN), so that the sense amplifier 133 (j) is in an operating state. By making the sense amplifier 133 (j) in an operating state, the potential of the wiring BILa (j) approaches the potential of the wiring SP (VH_SP) from Vpre+ΔV1. In addition, the potential of the wiring BILb (j) approaches the potential of the wiring SN (VL_SN) from Vpre. Note that in this specification, etc., the time required for the period T33 is referred to as "write time".

[0268] [Period T34]

[0269] During period T34, VL_WL is supplied to the wiring WL(i), and the wiring WL(i) is put into a non-selected state. Specifically, the potential of the wiring WL(i) is set to a low level (VL_WL), so that the transistor included in the memory cell 221[i,j] is turned off. As a result, the charge amount corresponding to the potential (VH_SP) of the wiring BLa is stored in the capacitor CA included in the memory cell 221[i,j].

[0270] By setting VL_WL to a negative potential, the transistor M11 can be more reliably turned off. In particular, a memory device having a long data retention time can be provided even under high temperature operation.

[0271] In addition, as the potential of the wiring WL(i) reaches VL_WL, the potential of the wiring BGL(i) is lowered. For example, -3 V is supplied to the wiring BGL(i).

[0272] In the refresh mode, since data is not read or written, the input / output circuit 134(j) can be kept in the off state. Therefore, the refresh mode can be performed in a shorter time than the read mode and the write mode. Note that the refresh mode of the memory cell 221[i+1,j] can also be performed in the same manner as the memory cell 221[i,j].

[0273] In addition, this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0274] (Implementation 3)

[0275] In this embodiment, a structural example of the Si transistor described in the above embodiment which can be applied to the peripheral circuit 111 and the OS transistor which can be applied to the memory cell 211 is described. Note that in this embodiment, the above Si transistor and OS transistor are collectively referred to as a semiconductor device.

[0276] <Structural example of semiconductor device>

[0277] Fig.12 The semiconductor device shown includes a transistor 300 , a transistor 500 , and a capacitor 600 . Fig.13A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 13B is a cross-sectional view of the transistor 500 in the channel width direction, Fig. 13C is a cross-sectional view of the transistor 300 in the channel width direction.

[0278] The transistor 500 is a transistor (OS transistor) including a metal oxide in a channel formation region. Since the off-state current of the transistor 500 is small, the storage content can be retained for a long period of time by using the OS transistor in a semiconductor device. In other words, the frequency of the refresh operation is low or the refresh operation is not required, so the power consumption of the semiconductor device can be reduced.

[0279] like Fig.12 As shown in FIG. 1 , the semiconductor device described in this embodiment includes a transistor 300 , a transistor 500 , and a capacitor 600 . The transistor 500 is provided above the transistor 300 , and the capacitor 600 is provided above the transistor 300 and the transistor 500 .

[0280] The transistor 300 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed by a portion of the substrate 311, and low resistance regions 314a and 314b used as source regions or drain regions.

[0281] like Fig. 13C As shown, in the transistor 300, the conductor 316 covers the top surface and the side surface in the channel width direction of the semiconductor region 313 via the insulator 315. In this way, by making the transistor 300 have a Fin-type structure, the effective channel width increases, so the on-state characteristics of the transistor 300 can be improved. In addition, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved.

[0282] In addition, transistor 300 may be a p-channel transistor or an n-channel transistor.

[0283] The channel formation region of the semiconductor region 313 or the region near it, the low resistance region 314a and the low resistance region 314b used as the source region or the drain region preferably include semiconductors such as silicon-based semiconductors, and more preferably include single crystal silicon. In addition, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that applies stress to the lattice and changes the interplanar spacing to control the effective mass can be used. In addition, the transistor 300 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0284] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0285] As the conductor 316 used as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0286] In addition, since the material of the conductor determines the work function, Vth can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embeddability, a laminate of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferred in terms of heat resistance.

[0287] Notice, Fig.12 The structure of the transistor 300 shown is only an example, and the structure is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or the driving method. For example, similar to the transistor 500, an oxide semiconductor may be used in the transistor 300.

[0288] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 300 .

[0289] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0290] The insulator 322 may also be used as a planarization film for planarizing a step generated by the transistor 300 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0291] As the insulator 324 , a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 311 , the transistor 300 , or the like into a region where the transistor 500 is provided is preferably used.

[0292] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 300. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0293] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0294] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0295] In addition, conductors 328 and 330 connected to capacitor 600 and transistor 500 are embedded in insulators 320, 322, 324, and 326. In addition, conductors 328 and 330 have the function of plugs or wiring. Note that the same reference numeral is sometimes used to represent a plurality of conductors having the function of plugs or wiring. In addition, in this specification, wiring and a plug connected to wiring may also be one component. That is, a part of a conductor is sometimes used as wiring, and a part of a conductor is sometimes used as a plug.

[0296] As the material of each plug and wiring (conductor 328 and conductor 330, etc.), a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferred. Alternatively, it is preferred to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0297] A wiring layer may be formed on the insulator 326 and the conductor 330. Fig.12 In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function of a plug or wiring connected to the transistor 300. The conductor 356 can be formed using the same material as the conductor 328 and the conductor 330.

[0298] In addition, similar to the insulator 324, the insulator 350 preferably uses an insulator having a barrier property to hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening of the insulator 350 having a barrier property to hydrogen. By adopting this structure, the transistor 300 and the transistor 500 can be separated by using a barrier layer, so that the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0299] Note that as a conductor having a barrier property to hydrogen, for example, tantalum nitride is preferably used. Furthermore, by stacking tantalum nitride and tungsten having high conductivity, it is possible to maintain conductivity as a wiring and suppress diffusion of hydrogen from the transistor 300. At this time, the tantalum nitride layer having a barrier property to hydrogen is preferably in contact with the insulator 350 having a barrier property to hydrogen.

[0300] Alternatively, a wiring layer may be formed on the insulator 354 and the conductor 356. Fig.12 In the embodiment, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function of a plug or wiring. In addition, the conductor 366 can be formed using the same material as the conductor 328 and the conductor 330.

[0301] In addition, similar to the insulator 324, the insulator 360 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening of the insulator 360 having a barrier property to hydrogen. By adopting this structure, the transistor 300 and the transistor 500 can be separated by using a barrier layer, so that the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0302] Alternatively, a wiring layer may be formed on the insulator 364 and the conductor 366. Fig.12 In the embodiment, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function of a plug or wiring. In addition, the conductor 376 can be formed using the same material as the conductor 328 and the conductor 330.

[0303] In addition, similar to the insulator 324, the insulator 370 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening of the insulator 370 having a barrier property to hydrogen. By adopting this structure, the transistor 300 and the transistor 500 can be separated by using a barrier layer, so that the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0304] Alternatively, a wiring layer may be formed on the insulator 374 and the conductor 376. Fig.12 In the embodiment, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 has a function of a plug or wiring. In addition, the conductor 386 can be formed using the same material as the conductor 328 and the conductor 330.

[0305] In addition, similar to the insulator 324, the insulator 380 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening of the insulator 380 having a barrier property to hydrogen. By adopting this structure, the transistor 300 and the transistor 500 can be separated by using a barrier layer, so that the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0306] In the above description, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described, but the semiconductor device of this embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

[0307] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As at least any one of the insulator 510, the insulator 512, the insulator 514, and the insulator 516, a substance having a barrier property against oxygen or hydrogen is preferably used.

[0308] For example, a film having a barrier property that can prevent hydrogen or impurities from diffusing from the substrate 311 or a region where the transistor 300 is provided into a region where the transistor 500 is provided is preferably used as the insulator 510 and the insulator 514. Therefore, the insulator 510 and the insulator 514 can use the same material as the insulator 324.

[0309] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 300 and transistor 500. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0310] For example, as a film having a barrier property against hydrogen, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0311] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from passing through. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0312] For example, the insulator 512 and the insulator 516 can use the same material as the insulator 320. In addition, by forming the interlayer film with a material having a low dielectric constant, the parasitic capacitance generated between the wirings can be reduced. For example, the insulator 512 and the insulator 516 can use a silicon oxide film, a silicon oxynitride film, or the like.

[0313] In addition, a conductor 518 and a conductor (conductor 503) constituting the transistor 500 are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using the same material as the conductors 328 and 330.

[0314] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. By adopting this structure, the transistor 300 and the transistor 500 can be separated by a layer having a barrier property to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 300 to the transistor 500.

[0315] The transistor 500 is provided above the insulator 516 .

[0316] like Fig.13A and Fig. 13BAs shown, transistor 500 includes: a conductor 503 embedded in insulators 512 and 516; an insulator 521 disposed on insulators 516 and conductor 503; an insulator 522 disposed on insulator 521; an insulator 524 disposed on insulator 522; an oxide 530a disposed on insulator 524; an oxide 530b disposed on oxide 530a; and conductors 542a and 542b disposed on oxide 530b and separated from each other. ; an insulator 580 disposed on the conductor 542a and the conductor 542b and having an opening overlapping with the conductor 542a and the conductor 542b; a conductor 560 disposed in the opening; an insulator 550 disposed between the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580 and the conductor 560; an oxide 530c disposed between the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580 and the insulator 550.

[0317] In addition, if Fig.13A and Fig. 13B As shown in FIG. 5 , an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Fig.13A and Fig. 13B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 550 and a conductor 560b embedded inside the conductor 560a. Fig.13A and Fig. 13B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 550 .

[0318] Note that hereinafter, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as an oxide 530. Also, the conductor 542a and the conductor 542b may be collectively referred to as a conductor 542.

[0319] In transistor 500, three layers of oxide 530a, oxide 530b, and oxide 530c are stacked in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. In addition, in transistor 500, conductor 560 has a two-layer structure, but the present invention is not limited to this. For example, conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that, Fig.12 , Fig.13A , Fig. 13BThe structure of the transistor 500 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0320] Here, the conductor 560 is used as the gate electrode of the transistor, and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode. As described above, the conductor 560 is buried in the opening of the insulator 580 and in the area sandwiched between the conductor 542a and the conductor 542b. The configuration of the conductor 560, the conductor 542a and the conductor 542b relative to the opening of the insulator 580 is selected in a self-aligned manner. In other words, in the transistor 500, the gate electrode can be configured in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 500 can be reduced. Thus, miniaturization and high integration of semiconductor devices can be achieved.

[0321] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not include a region overlapping with the conductor 542a and the conductor 542b. Thus, the parasitic capacitance formed between the conductor 560 and the conductor 542a and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be increased, so that the transistor 500 can have high frequency characteristics.

[0322] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate or back gate) electrode. In this case, the Vth of transistor 500 can be controlled by independently changing the potential supplied to conductor 503 without linking it with the potential supplied to conductor 560. In particular, by supplying a negative potential to conductor 503, the Vth of transistor 500 can be made greater than 0V and the off-state current can be reduced. Therefore, compared to when a negative potential is not applied to conductor 503, when a negative potential is applied to conductor 503, the drain current when the potential supplied to conductor 560 is 0V can be reduced.

[0323] The conductor 503 is arranged in a manner overlapping the oxide 530 and the conductor 560. Thus, when a potential is supplied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification, etc., the structure of a transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is called a surrounded channel (S-channel: surrounded channel) structure. In addition, in this specification, etc., the surrounded channel (S-channel) structure has the following characteristics, that is, the side and periphery of the oxide 530 that contacts the conductor 542a and the conductor 542b used as the source electrode and the drain electrode are I-type, as in the channel formation region. In addition, since the side and periphery of the oxide 530 that contacts the conductor 542a and the conductor 542b are in contact with the insulator 580, it is possible to become I-type, as in the channel formation region. Note that in this specification, etc., the I type can be said to be the same as the high-purity intrinsic described later. In addition, the S-channel structure disclosed in this specification, etc. is different from the Fin type structure and the planar type structure. By adopting the S-channel structure, the resistance to the short channel effect can be improved. In other words, a transistor that is not prone to the short channel effect can be realized.

[0324] The conductor 503 has the same structure as the conductor 518 , and the conductor 503 a is formed so as to be in contact with the inner walls of the openings of the insulator 514 and the insulator 516 , and the conductor 503 b is formed inside the conductor 503 a .

[0325] The insulator 521 , the insulator 522 , the insulator 524 , and the insulator 550 are used as gate insulating films.

[0326] Here, the insulator 524 in contact with the oxide 530 preferably contains oxygen exceeding the stoichiometric composition. In other words, it is preferable to form an excess oxygen region in the insulator 524. By providing the insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, thereby improving the reliability of the transistor 500.

[0327] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 In addition, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0328] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0329] When the insulator 522 has a function of suppressing diffusion of oxygen or impurities, it is preferable because oxygen included in the oxide 530 does not diffuse to the insulator 521. In addition, reaction between the conductor 503 and oxygen included in the insulator 524 or the oxide 530 can be suppressed.

[0330] As the insulator 522, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0331] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing the diffusion of impurities and oxygen (not allowing the above oxygen to pass easily). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 522 is formed using such a material, the insulator 522 is used as a layer that suppresses the release of oxygen from the oxide 530 or the entry of impurities such as hydrogen into the oxide 530 from the surrounding part of the transistor 500.

[0332] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0333] The insulator 521 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 521 having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0334] The insulator 521, the insulator 522, and the insulator 524 may have a stacked structure of two or more layers. In this case, the insulator 521, the insulator 522, and the insulator 524 are not limited to stacked structures made of the same material, and may be stacked structures made of different materials.

[0335] In the transistor 500, a metal oxide used as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the oxide 530. In addition, In-Ga oxide and In-Zn oxide may also be used as the oxide 530.

[0336] The metal oxide used as the channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0337] In the oxide 530, when the oxide 530a is provided below the oxide 530b, impurities can be prevented from diffusing from the structure formed below the oxide 530a to the oxide 530b. When the oxide 530c is provided above the oxide 530b, impurities can be prevented from diffusing from the structure formed above the oxide 530c to the oxide 530b.

[0338] In addition, the oxide 530 preferably has a stacked structure of oxides having different atomic number ratios of each metal atom. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530b. In addition, the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 530b is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 530a. In addition, the metal oxide that can be used for the oxide 530a or the oxide 530b can be used for the oxide 530c.

[0339] It is preferable that the energy of the conduction band bottom of the oxide 530a and the oxide 530c is higher than the energy of the conduction band bottom of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably lower than the electron affinity of the oxide 530b.

[0340] Here, in the junction of oxide 530a, oxide 530b, and oxide 530c, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of oxide 530a, oxide 530b, and oxide 530c continuously changes or continuously joins. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b and the interface between oxide 530b and oxide 530c.

[0341] Specifically, by making the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. are preferably used as the oxide 530a and the oxide 530c.

[0342] At this time, the main path of the carrier is oxide 530b. By making oxide 530a and oxide 530c have the above structure, the defect state density at the interface between oxide 530a and oxide 530b and the interface between oxide 530b and oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0343] A conductor 542 (conductor 542a and conductor 542b) used as a source electrode and a drain electrode is provided on the oxide 530b. As the conductor 542, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, and therefore are preferred.

[0344] In addition, if Fig.13AAs shown, a region 543 (region 543a and region 543b) is sometimes formed as a low resistance region at the interface between the oxide 530 and the conductor 542 and in the vicinity thereof. In this case, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0345] By forming the conductor 542 in contact with the oxide 530, the oxygen concentration of the region 543 may be reduced. In addition, a metal compound layer including a metal contained in the conductor 542 and a component of the oxide 530 may be formed in the region 543. In this case, the carrier density of the region 543 increases, and the region 543 becomes a low resistance region.

[0346] The insulator 544 is provided so as to cover the conductor 542 and suppress oxidation of the conductor 542. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0347] As the insulator 544, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0348] In particular, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing oxides of one or both of aluminum and hafnium, are preferably used. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, when the conductor 542 is a material with oxidation resistance or its conductivity does not significantly decrease even if oxygen is absorbed, it is not necessary to provide the insulator 544. It can be designed appropriately according to the required transistor characteristics.

[0349] The insulator 550 is used as a gate insulating film. The insulator 550 is preferably arranged in contact with the inner side (top surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that releases oxygen by heating. For example, the amount of oxygen released in thermal desorption spectroscopy (TDS analysis) is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3In addition, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C.

[0350] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, etc. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0351] By providing an insulator that releases oxygen by heating so as to be in contact with the top surface of the oxide 530c as the insulator 550, oxygen can be efficiently supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. In addition, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water or hydrogen in the insulator 550. The thickness of the insulator 550 is preferably not less than 1 nm and not more than 20 nm.

[0352] In order to efficiently supply the excess oxygen contained in the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, the reduction of excess oxygen supplied to the oxide 530 can be suppressed. In addition, the oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0353] exist Fig.13A and Fig. 13B In the embodiment, the conductor 560 used as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0354] As the conductor 560a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity due to oxidation of the conductor 560b caused by the oxygen contained in the insulator 550. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, etc., are preferably used.

[0355] As the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper or aluminum. Since the conductor 560b is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0356] The insulator 580 is preferably provided on the conductor 542 via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, silicon oxide and silicon oxide with pores are preferred because they are easy to form an excess oxygen region in the subsequent process.

[0357] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 that releases oxygen by heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. In addition, the concentration of impurities such as water and hydrogen in the insulator 580 is preferably reduced.

[0358] The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is embedded in the opening of the insulator 580 and in the region between the conductor 542a and the conductor 542b.

[0359] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. For this reason, when the thickness of the conductor 560 is increased, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, since the conductor 560 is buried in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 does not collapse during the process.

[0360] The insulator 574 is preferably provided so as to be aligned with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be formed in the insulator 550 and the insulator 580. Thus, oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0361] For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0362] In particular, aluminum oxide has high barrier properties and can inhibit the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can be used as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0363] In addition, an insulator 581 used as an interlayer film is preferably provided over the insulator 574. As with the insulator 524 and the like, the concentration of impurities such as water and hydrogen in the insulator 581 is preferably reduced.

[0364] In addition, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are arranged to face each other via conductor 560. Conductors 540a and 540b have the same structure as conductors 546 and 548 described later.

[0365] An insulator 582 is provided on the insulator 581. A substance having a barrier property against oxygen or hydrogen is preferably used for the insulator 582. Therefore, the insulator 582 can be made of the same material as the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0366] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from penetrating. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0367] In addition, an insulator 586 is provided on the insulator 582. As the insulator 586, the same material as the insulator 320 can be used. In addition, by forming the interlayer film with a material having a low dielectric constant, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film or a silicon oxynitride film can be used.

[0368] In addition, the conductor 546 and the conductor 548 are buried in the insulator 521 , the insulator 522 , the insulator 524 , the insulator 544 , the insulator 580 , the insulator 574 , the insulator 581 , the insulator 582 , and the insulator 586 .

[0369] The conductor 546 and the conductor 548 are used as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using the same material as the conductor 328 and the conductor 330.

[0370] Next, a capacitor 600 is provided above the transistor 500 . The capacitor 600 includes a conductor 610 , a conductor 620 , and an insulator 630 .

[0371] In addition, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 is used as a plug or wiring connected to the transistor 500. The conductor 610 is used as an electrode of the capacitor 600. In addition, the conductor 612 and the conductor 610 may be formed at the same time.

[0372] As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements as a component (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used.

[0373] exist Fig.12 In the embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto and they may have a stacked structure of two or more layers. For example, a conductor having high compactness with the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0374] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Conductive materials such as metal materials, alloy materials, and metal oxide materials can be used as the conductor 620. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0375] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. In addition, the insulator 650 can be used as a planarization film that covers the concavo-convex shape thereunder.

[0376] By adopting this structure, the reliability of a semiconductor device using a transistor including an oxide semiconductor can be improved while suppressing the variation of the electrical characteristics. In addition, a transistor including an oxide semiconductor having a large on-state current can be provided. In addition, a transistor including an oxide semiconductor having a small off-state current can be provided. In addition, a semiconductor device with reduced power consumption can be provided. In addition, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved.

[0377] 〈Transistor Structure Example〉

[0378] Note that the structure of the transistor 500 of the semiconductor device described in this embodiment is not limited to the above-described structure.

[0379] <Transistor Structure Example 1>

[0380] Reference Fig.14A , Fig. 14B and Fig. 14C A structural example of the transistor 510A is described. Fig.14A is a top view of transistor 510A. Fig. 14B is Fig.14A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 14C is Fig.14A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.14A In the top view, for the sake of clarity, part of the components are omitted and shown.

[0381] exist Fig.14A , Fig. 14B and Fig. 14C 2 shows a transistor 510A, an insulator 511 used as an interlayer film, an insulator 512, an insulator 514, an insulator 516, an insulator 580, an insulator 582, and an insulator 584. In addition, a conductor 546 (a conductor 546a and a conductor 546b) electrically connected to the transistor 510A and used as a contact plug, and a conductor 503 used as a wiring are shown.

[0382] Transistor 510A includes: a conductor 560 (conductor 560a and conductor 560b) used as a first gate electrode; a conductor 505 (conductor 505a and conductor 505b) used as a second gate electrode; an insulator 550 used as a first gate insulating film; insulators 521, 522, and 524 used as a second gate insulating film; an oxide 530 (oxide 530a, oxide 530b, and oxide 530c) including a region forming a channel; a conductor 542a used as one of a source and a drain; a conductor 542b used as the other of a source and a drain; and an insulator 574.

[0383] In addition, Fig.14A , Fig. 14B and Fig. 14C In the transistor 510A shown in the figure, an oxide 530c, an insulator 550, and a conductor 560 are arranged in an opening provided in an insulator 580 via an insulator 574. In addition, the oxide 530c, the insulator 550, and the conductor 560 are arranged between the conductor 542a and the conductor 542b.

[0384] The insulator 511 and the insulator 512 serve as an interlayer film.

[0385] As the interlayer film, a single layer or a stack of insulators such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide can be added to these insulators. In addition, these insulators can also be nitrided. Silicon oxide, silicon oxynitride or silicon nitride can also be stacked on the above-mentioned insulators.

[0386] For example, the insulator 511 is preferably used as a barrier film that suppresses impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, as the insulator 511, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In addition, for example, it is preferable to use aluminum oxide or silicon nitride as the insulator 511. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulator 511 to the side of the transistor 510A.

[0387] For example, the dielectric constant of the insulator 512 is preferably lower than that of the insulator 511. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0388] The conductor 503 is formed in a manner embedded in the insulator 512. Here, the height of the top surface of the conductor 503 and the height of the top surface of the insulator 512 may be substantially the same. The conductor 503 has a single-layer structure, but the present invention is not limited thereto. For example, the conductor 503 may also have a multilayer film structure of two or more layers. As the conductor 503, a highly conductive conductive material having tungsten, copper or aluminum as a main component is preferably used.

[0389] In transistor 510A, conductor 560 is sometimes used as a first gate (also referred to as a top gate) electrode. Conductor 505 is sometimes used as a second gate (also referred to as a bottom gate) electrode. In this case, by independently changing the potential supplied to conductor 505 without interlocking it with the potential supplied to conductor 560, the threshold voltage of transistor 510A can be controlled. In particular, by supplying a negative potential to conductor 505, the threshold voltage of transistor 510A can be made greater than 0V and the off-state current can be reduced. Therefore, compared to when a negative potential is not applied to conductor 505, when a negative potential is applied to conductor 505, the drain current when the potential supplied to conductor 560 is 0V can be reduced.

[0390] In addition, for example, by overlapping the conductor 505 with the conductor 560 , when a potential is supplied to the conductor 560 and the conductor 505 , the electric field generated from the conductor 560 and the electric field generated from the conductor 505 are connected, so that the channel formation region formed in the oxide 530 can be covered.

[0391] That is, the channel formation region can be electrically surrounded by the electric field of the conductor 560 used as the first gate electrode and the electric field of the conductor 505 used as the second gate electrode. In this specification, the structure of the transistor in which the channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is called a surrounded channel (S-channel) structure.

[0392] Insulators 514 and 516 are used as interlayer films, similarly to insulators 511 and 512. For example, insulator 514 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from entering transistor 510A from the substrate side. By adopting this structure, impurities such as hydrogen and water can be suppressed from diffusing from the side closer to the substrate than insulator 514 to the transistor 510A side. For example, insulator 516 preferably has a lower dielectric constant than insulator 514. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0393] In the conductor 505 used as the second gate, a conductor 505a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and a conductor 505b is formed inside the conductor 505a. Here, the height of the top surface of the conductor 505a and the conductor 505b can be substantially the same as the height of the top surface of the insulator 516. In addition, in the transistor 510A, the conductor 505a and the conductor 505b are stacked, but the present invention is not limited to this. For example, the conductor 505 may have a single-layer structure or a stacked structure of three or more layers.

[0394] Here, as the conductor 505a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (not allowing the above impurities to pass through easily). In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In this specification, "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0395] For example, by providing the conductor 505a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 505b can be suppressed.

[0396] In addition, when the conductor 505 also has a wiring function, it is preferable to use a highly conductive conductive material with tungsten, copper or aluminum as a main component as the conductor 505b. In this case, it is not necessary to provide the conductor 503. In the drawings, the conductor 505b has a single-layer structure, but it may also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials may be used.

[0397] The insulator 521 , the insulator 522 , and the insulator 524 function as a second gate insulating film.

[0398] The insulator 522 preferably has a barrier property. When the insulator 522 has a barrier property, the insulator 522 is used as a layer for suppressing impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

[0399] As the insulator 522, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium silicate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0400] For example, the insulator 521 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 521 having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0401] Note that Fig. 14B and Fig. 14C In the embodiment, the second gate insulating film has a three-layer stacked structure, but may also have a single-layer structure or a double-layer structure or a stacked structure of more than four layers. In this case, the stacked structure is not limited to being made of the same material, but may also be a stacked structure formed of different materials.

[0402] The oxide 530 including the region used as the channel formation region includes an oxide 530a, an oxide 530b on the oxide 530a, and an oxide 530c on the oxide 530b. When the oxide 530a is provided below the oxide 530b, it is possible to prevent impurities from being diffused from the structure formed below the oxide 530a to the oxide 530b. When the oxide 530c is provided above the oxide 530b, it is possible to prevent impurities from being diffused from the structure formed above the oxide 530c to the oxide 530b. As the oxide 530, an oxide semiconductor of one of the above-mentioned metal oxides can be used.

[0403] The oxide 530 c is preferably provided in the opening provided in the insulator 580 via the insulator 574. When the insulator 574 has a barrier property, diffusion of impurities from the insulator 580 into the oxide 530 can be suppressed.

[0404] One of the conductors 542 is used as a source electrode, and the other is used as a drain electrode.

[0405] Conductors 542a and 542b may be made of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys containing these elements as main components. In particular, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen and oxygen and have high oxidation resistance.

[0406] In addition, although Fig. 14B Although a single-layer structure is shown in the figure, a stacked structure of two or more layers may be adopted. For example, a tantalum nitride film and a tungsten film are preferably stacked. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure of stacking an aluminum film on a tungsten film, a two-layer structure of stacking a copper film on a copper-magnesium-aluminum alloy film, a two-layer structure of stacking a copper film on a titanium film, and a two-layer structure of stacking a copper film on a tungsten film may also be adopted.

[0407] Alternatively, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, or an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0408] Alternatively, a barrier layer may be provided on the conductor 542. The barrier layer is preferably made of a substance that has a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductor 542 can be suppressed when the insulator 574 is formed.

[0409] The barrier layer may be made of, for example, a metal oxide. In particular, it is preferable to use an insulating film having barrier properties to oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Alternatively, silicon nitride formed by CVD may be used.

[0410] By including the barrier layer, the range of choices of the material of the conductor 542 can be expanded. For example, a material with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductor 542. In addition, for example, a conductor that is easy to deposit or process can be used.

[0411] The insulator 550 is used as a first gate insulating film. The insulator 550 is preferably provided in an opening provided in the insulator 580 via the oxide 530 c and the insulator 574 .

[0412] When miniaturization and high integration of transistors are performed, leakage current and other problems may occur due to the thin film of the gate insulating film. In this case, the insulator 550 may also have a laminated structure, similar to the second gate insulating film. By making the insulator used as the gate insulating film have a laminated structure of a high-k material and a material having thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a laminated structure having thermal stability and a high relative dielectric constant can be realized.

[0413] The conductor 560 used as the first gate electrode includes a conductor 560a and a conductor 560b on the conductor 560a. As with the conductor 505a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms as the conductor 560a. In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0414] When the conductor 560a has a function of suppressing the diffusion of oxygen, the selectivity of the material of the conductor 560b can be improved. That is, by including the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0415] As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be used for the oxide 530 can be used. In this case, by forming the conductor 560b by sputtering, the resistivity of the conductor 560a can be reduced to make it a conductor. The conductor can be called an OC (Oxide Conductor) electrode.

[0416] As the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper or aluminum. Since the conductor 560 is used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0417] An insulator 574 is disposed between the insulator 580 and the transistor 510A. An insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulator 574. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0418] By including the insulator 574, impurities such as water and hydrogen contained in the insulator 580 can be prevented from diffusing into the oxide 530b through the oxide 530c and the insulator 550. In addition, oxidation of the conductor 560 by excess oxygen contained in the insulator 580 can be prevented.

[0419] Insulator 580 , insulator 582 , and insulator 584 are used as interlayer films.

[0420] Similar to the insulator 514, the insulator 582 is preferably used as a block insulating film for preventing impurities such as water and hydrogen from entering the transistor 510A from the outside.

[0421] As with the insulator 516, the dielectric constants of the insulators 580 and 584 are preferably lower than that of the insulator 582. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0422] In addition, the transistor 510A may be electrically connected to other structures through a plug or wiring such as a conductor 546 embedded in the insulator 580 , the insulator 582 , and the insulator 584 .

[0423] In addition, as with the conductor 505, as the material of the conductor 546, a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. For example, a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used. Alternatively, a low resistance conductive material such as aluminum or copper is preferably used. By using a low resistance conductive material, wiring resistance can be reduced.

[0424] For example, by using a stacked structure of tantalum nitride or the like, which is a conductor having a barrier property against hydrogen and oxygen, and tungsten having high conductivity as the conductor 546, diffusion of impurities from the outside can be suppressed while maintaining the conductivity of the wiring.

[0425] By having the above structure, a semiconductor device using a transistor including an oxide semiconductor with a large on-state current can be provided. Alternatively, a semiconductor device using a transistor including an oxide semiconductor with a small off-state current can be provided. Alternatively, a semiconductor device having improved reliability while suppressing variations in electrical characteristics and having stable electrical characteristics can be provided.

[0426] <Transistor Structure Example 2>

[0427] Reference Fig.15A , Fig. 15B and Fig. 15C A structural example of the transistor 510B is described. Fig.15A is a top view of transistor 510B. Fig. 15B is Fig.15A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 15C is Fig.15A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.15A In the top view, part of the components are omitted for clarity.

[0428] The transistor 510B is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0429] The transistor 510B includes a region where the conductor 542 (conductor 542a and conductor 542b) overlaps with the oxide 530c, the insulator 550, and the conductor 560. With this structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0430] The conductor 560 used as the first gate electrode includes a conductor 560a and a conductor 560b on the conductor 560a. As with the conductor 505a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms as the conductor 560a. In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0431] When the conductor 560a has a function of suppressing the diffusion of oxygen, the selectivity of the material of the conductor 560b can be improved. That is, by including the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0432] In addition, it is preferable to provide an insulator 574 so as to cover the top surface and side surfaces of the conductor 560, the side surfaces of the insulator 550, and the side surfaces of the oxide 530c. As the insulator 574, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0433] By providing the insulator 574, oxidation of the conductor 560 can be suppressed. In addition, by including the insulator 574, diffusion of impurities such as water and hydrogen contained in the insulator 580 into the transistor 510B can be suppressed.

[0434] Alternatively, an insulator 576 (insulator 576a and insulator 576b) having a barrier property may be provided between the conductor 546 and the insulator 580. By providing the insulator 576, it is possible to suppress the oxidation of the conductor 546 caused by the reaction of oxygen in the insulator 580 with the conductor 546.

[0435] In addition, by providing an insulator 576 having a barrier property, the range of choices for the material of the conductor used for the plug or wiring can be expanded. For example, by using a metal material having a property of absorbing oxygen and having high conductivity as the conductor 546, a semiconductor device with low power consumption can be provided. Specifically, a material with low oxidation resistance and high conductivity such as tungsten or aluminum can be used. In addition, for example, a conductor that is easy to form a film or process can be used.

[0436] <Transistor Structure Example 3>

[0437] Reference Fig.16A , Fig. 16B and Fig. 16C A structural example of the transistor 510C is described. Fig.16A is a top view of transistor 510C. Fig. 16B is Fig.16A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 16C is Fig.16A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.16A In the top view, part of the components are omitted for clarity.

[0438] The transistor 510C is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0439] Fig.16A , Fig. 16B and Fig. 16C The transistor 510C shown has a conductor 547a disposed between the conductor 542a and the oxide 530b, and a conductor 547b disposed between the conductor 542b and the oxide 530b. Here, the conductor 542a (conductor 542b) has a region extending beyond the top surface of the conductor 547a (conductor 547b) and the side surface on one side of the conductor 560 and in contact with the top surface of the oxide 530b. Here, as the conductor 547, a conductor that can be used for the conductor 542 can be used. In addition, the thickness of the conductor 547 is preferably at least thicker than that of the conductor 542.

[0440] because Fig.16A , Fig. 16B and Fig. 16C The transistor 510C shown has the above structure, and compared with the transistor 510A, the conductor 542 can be closer to the conductor 560. Alternatively, the end of the conductor 542a and the end of the conductor 542b can overlap with the conductor 560. Thus, the substantial channel length of the transistor 510C can be reduced, and the on-state current and frequency characteristics can be improved.

[0441] In addition, the conductor 547a (conductor 547b) preferably overlaps the conductor 542a (conductor 542b). With this structure, when etching is performed to form an opening to fill the conductor 546a (conductor 546b), the conductor 547a (conductor 547b) is used as an etching stop layer to prevent overetching of the oxide 530b.

[0442] In addition, Fig.16A , Fig. 16B and Fig. 16CIn the transistor 510C shown in the figure, an insulator 545 may be arranged in contact with the insulator 544. The insulator 544 is preferably used as a blocking insulating film for suppressing impurities such as water or hydrogen or excess oxygen from entering the transistor 510C from the side of the insulator 580. As the insulator 545, an insulator that can be used for the insulator 544 can be used. In addition, as the insulator 544, for example, a nitride insulator such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon oxynitride can also be used.

[0443] In addition, Fig.16A , Fig. 16B and Fig. 16C The transistor 510C shown in FIG. Fig.14A , Fig. 14B and Fig. 14C Unlike the transistor 510A shown, the conductor 505 may also have a single-layer structure. In this case, an insulating film that becomes the insulator 516 may be formed on the conductor 505 that has been formed into a pattern, and the top of the insulating film may be removed by using a CMP method or the like until the top surface of the conductor 505 is exposed. Here, it is preferred to improve the flatness of the top surface of the conductor 505. For example, the average surface roughness (Ra) of the top surface of the conductor 505 may be less than 1 nm, preferably less than 0.5 nm, and more preferably less than 0.3 nm. Thus, the flatness of the insulating layer formed on the conductor 505 can be improved, and the crystallinity of the oxide 530b and the oxide 530c can be improved.

[0444] <Transistor Structure Example 4>

[0445] Reference Fig.17A , Fig. 17B and Fig. 17C A structural example of the transistor 510D is described. Fig.17A is a top view of transistor 510D. Fig. 17B is Fig.17A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 17C is Fig.17A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.17A In the top view, part of the components are omitted for clarity.

[0446] The transistor 510D is a modified example of the above-described transistor, and thus, in order to avoid duplication of descriptions, the description will be mainly focused on differences from the above-described transistor.

[0447] exist 17A to 17CIn the embodiment, the conductor 505 having the function of the second gate is also used as a wiring without providing the conductor 503. In addition, an insulator 550 is included on the oxide 530c, and a metal oxide 552 is included on the insulator 550. In addition, a conductor 560 is included on the metal oxide 552, and an insulator 570 is included on the conductor 560. In addition, an insulator 571 is included on the insulator 570.

[0448] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses oxygen diffusion between the insulator 550 and the conductor 560, oxygen diffusion to the conductor 560 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to oxygen can be suppressed.

[0449] In addition, the metal oxide 552 can be used as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 530 can be used as the metal oxide 552. In this case, by forming the conductor 560 by sputtering, the resistance value of the metal oxide 552 can be reduced to make it a conductive layer. This can be called an OC (Oxide Conductor) electrode.

[0450] In addition, the metal oxide 552 is sometimes used as a part of the gate insulating film. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide 552. By adopting this stacked structure, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as the gate insulating film can be reduced.

[0451] Although the metal oxide 552 in the transistor 510D is shown as a single-layer structure, a stacked structure of two or more layers may be employed. For example, a metal oxide used as a part of the gate electrode and a metal oxide used as a part of the gate insulating film may be stacked.

[0452] When the metal oxide 552 is used as a gate electrode, the on-state current of the transistor 510D can be increased without weakening the influence of the electric field from the conductor 560. In addition, when the metal oxide 552 is used as a gate insulating film, the distance between the conductor 560 and the oxide 530 can be maintained by utilizing the physical thickness of the insulator 550 and the metal oxide 552, so that the leakage current between the conductor 560 and the oxide 530 can be suppressed. Thus, by providing a stacked structure of the insulator 550 and the metal oxide 552, the physical distance between the conductor 560 and the oxide 530 and the electric field strength applied from the conductor 560 to the oxide 530 can be easily adjusted.

[0453] Specifically, an oxide semiconductor that can be used for the oxide 530 can be used as the metal oxide 552 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0454] In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as an insulating layer containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. Note that the metal oxide 552 is not an essential component and can be appropriately designed according to the desired transistor characteristics.

[0455] An insulating material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen is preferably used as the insulator 570. For example, aluminum oxide or hafnium oxide is preferably used. Thus, the conductor 560 can be prevented from being oxidized by oxygen from above the insulator 570. In addition, impurities such as water or hydrogen from above the insulator 570 can be inhibited from entering the oxide 530 through the conductor 560 and the insulator 550.

[0456] The insulator 571 is used as a hard mask. By providing the insulator 571, the conductor 560 can be processed in such a way that the side surface of the conductor 560 is approximately perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductor 560 and the substrate surface can be made greater than 75 degrees and less than 100 degrees, preferably greater than 80 degrees and less than 95 degrees.

[0457] Alternatively, the insulator 571 may also function as a barrier layer by using an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the insulator 571. In this case, the insulator 570 may not be provided.

[0458] By using the insulator 571 as a hard mask, the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and a portion of the oxide 530c are selectively removed, so that their side surfaces can be roughly aligned and a portion of the surface of the oxide 530b can be exposed.

[0459] In addition, the transistor 510D has a region 531a and a region 531b in a portion of the surface of the exposed oxide 530b. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region.

[0460] For example, the regions 531a and 531b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed oxide 530b by ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. Note that in this embodiment mode, "impurity element" refers to an element other than a main component element.

[0461] Alternatively, after a portion of the surface of the oxide 530 b is exposed, a metal film may be formed, and then heat treatment may be performed to diffuse elements included in the metal film into the oxide 530 b , thereby forming the regions 531 a and 531 b .

[0462] The resistivity of the region into which the impurity element is introduced in the oxide 530b decreases. Therefore, the region 531a and the region 531b are sometimes referred to as “impurity regions” or “low resistance regions”.

[0463] By using the insulator 571 and / or the conductor 560 as a mask, the region 531a and the region 531b can be formed in a self-aligned manner. Therefore, the region 531a and / or the region 531b do not overlap with the conductor 560, and the parasitic capacitance can be reduced. In addition, the bias region is not formed between the channel formation region and the source and drain region (region 531a or region 531b). By forming the region 531a and the region 531b in a self-aligned manner, an increase in the on-state current, a decrease in the threshold voltage, an increase in the operating frequency, etc. can be achieved.

[0464] In addition, in order to further reduce the off-state current, a bias region may be provided between the channel formation region and the source / drain region. The bias region is a region with high resistivity and is a region where the above-mentioned impurity elements are not introduced. The bias region can be formed by introducing the above-mentioned impurity elements after forming the insulator 575. In this case, the insulator 575 is also used as a mask as insulator 571. Therefore, the region of the oxide 530b overlapping with the insulator 575 is not introduced with impurity elements, thereby maintaining the resistivity of the region high.

[0465] The transistor 510D includes an insulator 575 on the side of the insulator 570, the conductor 560, the metal oxide 552, the insulator 550, and the oxide 530c. The insulator 575 is preferably an insulator with a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores is used for the insulator 575, it is preferred because an excess oxygen region can be easily formed in the insulator 575 in the subsequent process. In addition, silicon oxide and silicon oxynitride are thermally stable, so they are preferred. In addition, the insulator 575 preferably has a function of diffusing oxygen.

[0466] The transistor 510D includes an insulator 574 over the insulator 575 and the oxide 530. The insulator 574 is preferably formed by sputtering. By using the sputtering method, an insulator with less impurities such as water and hydrogen can be formed. For example, aluminum oxide is preferably used as the insulator 574.

[0467] Oxide films formed by sputtering may extract hydrogen from the structure being formed. Therefore, the insulator 574 extracts hydrogen and water from the oxide 530 and the insulator 575 to reduce the hydrogen concentration of the oxide 530 and the insulator 575.

[0468] <Transistor Structure Example 5>

[0469] Reference 18A to 18C A structural example of the transistor 510E is described. Fig.18A is a top view of transistor 510E. Fig.18B is Fig.18A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig.18C is Fig.18A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.18A In the top view, part of the components are omitted for clarity.

[0470] The transistor 510E is a modified example of the above-described transistor. Therefore, in order to avoid duplication of descriptions, the differences from the above-described transistor will be mainly described.

[0471] exist 18A to 18C In the embodiment, a portion of the surface of the exposed oxide 530b includes a region 531a and a region 531b without providing a conductor 542. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region. In addition, an insulator 573 is included between the oxide 530b and the insulator 574.

[0472] Fig.18BThe region 531 (region 531a and region 531b) shown is a region in which the oxide 530b is doped with the following elements. The region 531 can be formed by using a dummy gate, for example.

[0473] Specifically, a dummy gate is provided on the oxide 530b, and the dummy gate is used as a mask to add an element that makes the oxide 530b low in resistance. That is, the element is added to the region of the oxide 530 that does not overlap with the dummy gate, thereby forming a region 531. As a method for adding the element, an ion implantation method in which the ionized source gas is mass-separated and added; an ion doping method in which the ionized source gas is not mass-separated and added; and a plasma immersion ion implantation method, etc. can be used.

[0474] In addition, as an element that reduces the resistance of the oxide 530, boron or phosphorus is typical. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. can also be used. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. The concentration of the element can be measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or the like.

[0475] In particular, boron and phosphorus are preferred because they can be used in the production line of amorphous silicon or low-temperature polysilicon. Existing equipment can be used, thereby reducing equipment investment.

[0476] Next, an insulating film serving as an insulator 573 and an insulating film serving as an insulator 574 may be formed over the oxide 530b and the dummy gate. By providing a stack of the insulating film serving as the insulator 573 and the insulating film serving as the insulator 574, a region where the region 531 overlaps with the oxide 530c and the insulator 550 can be provided.

[0477] Specifically, an insulating film that becomes an insulator 580 is provided on an insulating film that becomes an insulator 574, and then a CMP (Chemical Mechanical Polishing) process is performed on the insulating film that becomes the insulator 580 to remove a portion of the insulating film that becomes the insulator 580, thereby exposing the dummy gate. Next, when removing the dummy gate, it is preferable to also remove a portion of the insulator 573 that is in contact with the dummy gate. As a result, the insulator 574 and the insulator 573 are exposed on the side of the opening provided in the insulator 580, and a portion of the region 531 provided in the oxide 530b is exposed on the bottom surface of the opening. Next, an oxide film that becomes an oxide 530c, an insulating film that becomes an insulator 550, and a conductive film that becomes a conductor 560 are sequentially formed in the opening, and then a portion of the oxide film that becomes the oxide 530c, the insulating film that becomes the insulator 550, and the conductive film that becomes the conductor 560 are removed by CMP treatment or the like until the insulator 580 is exposed, thereby forming 18A to 18C The transistor shown.

[0478] Note that the insulator 573 and the insulator 574 are not necessarily provided and may be appropriately designed according to required transistor characteristics.

[0479] 18A to 18C The transistor shown can utilize existing devices and does not include the conductor 542 , thereby reducing costs.

[0480] <Transistor Structure Example 6>

[0481] Although in Fig.12 , Fig.13A and Fig. 13B 2 shows a structural example in which a conductor 560 used as a gate is formed inside an opening of an insulator 580, but, for example, a structure in which the insulator is provided above the conductor may be employed. Fig.19A , Fig.19B , Fig. 20A , Fig. 20B A structural example of such a transistor is shown.

[0482] Fig.19A is a top view of the transistor, Fig.19B is a three-dimensional diagram of a transistor. In addition, Fig. 20A Shown along Fig.19A The cross-sectional view of X1-X2 in Fig. 20B Shown along Fig.19A Cross-sectional view of Y1-Y2 in FIG.

[0483] Fig.19A , Fig.19B , Fig. 20A , Fig. 20BThe transistor shown includes a conductor BGE having a back gate function, an insulator BGI having a gate insulating film function, an oxide semiconductor S, an insulator TGI having a gate insulating film function, a conductor TGE having a front gate function, and a conductor WE having a wiring function. In addition, the conductor PE has a plug function that connects the conductor WE to the oxide S, the conductor BGE, or the conductor TGE. Note that an example in which the oxide semiconductor S is composed of three layers of oxides S1, S2, and S3 is shown here.

[0484] 〈Electrical Characteristics of Transistors〉

[0485] Next, the electrical characteristics of the OS transistor are described. As an example, a transistor including a first gate and a second gate is described below. In a transistor including a first gate and a second gate, the threshold voltage can be controlled by applying different potentials to the first gate and the second gate. For example, by applying a negative potential to the second gate, the threshold voltage of the transistor can be made greater than 0V, thereby reducing the off-state current. In other words, by applying a negative potential to the second gate, the drain current when the potential applied to the first gate is 0V can be reduced.

[0486] In addition, when impurities such as hydrogen are added to an oxide semiconductor, its carrier density sometimes increases. For example, when hydrogen is added to an oxide semiconductor, the hydrogen sometimes reacts with oxygen bonded to a metal atom to generate water, thereby forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, the carrier density increases. In addition, sometimes electrons as carriers are generated due to a portion of hydrogen bonding to oxygen bonded to a metal atom. In other words, an oxide semiconductor to which impurities such as hydrogen are added becomes n-type, and its resistance decreases.

[0487] Therefore, the resistance of the oxide semiconductor can be selectively reduced. In other words, a region of the semiconductor having low carrier density and used as a channel formation region and a low resistance region having high carrier density and used as a source region or a drain region can be provided in the oxide semiconductor.

[0488] Here, the influence of the configuration of a low resistance region and a high resistance region provided in an oxide semiconductor on the electrical characteristics of a transistor when different potentials are applied to a first gate and a second gate is evaluated.

[0489] [Transistor structure]

[0490] Fig.21A and Fig. 21C is a cross-sectional view of a transistor used for evaluation of electrical characteristics. Fig.21A and Fig. 21C For the sake of clarity, some components are not shown in the figure.

[0491] Fig.21A and Fig. 21C The transistor shown includes a conductor TGE used as a first gate, an insulator TGI used as a first gate insulating film, an insulator SW used as a sidewall provided on the side of the first gate, an oxide semiconductor S, a conductor BGE used as a second gate, and an insulator BGI used as a second gate insulating film. The insulator BGI has a three-layer structure consisting of a first layer in contact with the conductor BGE, a second layer on the first layer, and a third layer on the second layer. The third layer is in contact with the oxide semiconductor S.

[0492] Here, Fig.21A The oxide semiconductor S included in the transistor shown includes an n+ region and an i region overlapping with the conductor TGE. Fig. 21C The transistor shown includes an oxide semiconductor S including an n+ region, an i region overlapping with the conductor TGE, and an n− region between the n+ region and the i region.

[0493] The n+ region is a low resistance region used as a source region or a drain region and has a high carrier density. The i region is a high resistance region used as a channel formation region and has a lower carrier density than the n+ region. The n- region is a region whose carrier density is lower than that of the n+ region and higher than that of the i region.

[0494] Although not shown in the figure, the n+ region of the oxide semiconductor S is in contact with an S / D electrode used as a source or a drain.

[0495] [Evaluation results of electrical characteristics]

[0496] right Fig.21A The transistor shown and Fig. 21C The Id-Vg characteristics of the transistor shown were calculated to evaluate the electrical characteristics of the transistor.

[0497] Here, as an indicator of the electrical characteristics of the transistor, the change amount (hereinafter also referred to as ΔVsh) of the threshold voltage (hereinafter also referred to as Vsh) of the transistor is used. Note that in the Id-Vg characteristic, Vsh is defined as Id=1.0×10 -12 [A] Vg value.

[0498] Note that the Id-Vg characteristic refers to the variation characteristic of the current between the source and the drain (hereinafter also referred to as the drain current (Id)) when the potential applied to the conductor TGE used as the first gate of the transistor (hereinafter also referred to as the gate potential (Vg)) changes from a first value to a second value.

[0499] Here, the potential between the source and the drain (hereinafter also referred to as the drain potential Vd) is set to +0.1V, and the potential between the source and the conductor TGE used as the first gate is changed from -1V to +4V, and the change in the drain current (Id) is evaluated under this condition.

[0500] In addition, the calculation was performed using the device simulator ATLAS manufactured by Silvaco. In addition, the following table shows the parameters used for the calculation. Note that Eg represents the energy gap, Nc represents the effective state density of the conduction band, and Nv represents the effective state density of the valence band.

[0501] [Table 1]

[0502]

[0503]

[0504] exist Fig.21A In the transistor shown, one n+ region is set to 700nm and one n- region is set to 0nm. Fig. 21C In the transistor shown, an n+ region is set to 655nm and an n- region is set to 45nm. Fig.21A The transistor shown and Fig. 21C In the transistor shown, the second gate is larger than the i region. In this evaluation, the potential of the conductor BGE used as the second gate (hereinafter also referred to as back gate potential (Vbg)) was set to 0.00V, -3.00V, or -6.00V.

[0505] Fig.21B Show Fig.21A The results of the Id-Vg characteristics of the transistor shown are obtained based on the calculation. When the back gate potential is -3.00V, the change in the threshold voltage of the transistor (△Vsh) is +1.2V compared to the case of 0.00V. In addition, when the back gate potential is -6.00V, the change in the threshold voltage of the transistor (△Vsh) is +2.3V compared to the case of 0.00V. That is, when the back gate potential is -6.00V, the change in the threshold voltage of the transistor (△Vsh) is +1.1V compared to the case of -3.00V. Therefore, even if the potential of the conductor BGE used as the second gate increases, the change in the threshold voltage of the transistor hardly changes. In addition, even if the back gate potential increases, the rising characteristics do not change.

[0506] Fig.21D Show Fig. 21CThe results of the Id-Vg characteristics of the transistor shown are obtained based on calculations. When the back gate potential is -3.00V, the change in the threshold voltage of the transistor (△Vsh) is +1.2V compared to the case of 0.00V. In addition, when the back gate potential is -6.00V, the change in the threshold voltage of the transistor (△Vsh) is +3.5V compared to the case of 0.00V. That is, when the back gate potential is -6.00V, the change in the threshold voltage of the transistor (△Vsh) is +2.3V compared to the case of -3.00V. Therefore, the greater the potential of the conductor BGE used as the second gate, the greater the change in the threshold voltage of the transistor. On the other hand, the greater the back gate potential, the lower the rise characteristic.

[0507] Therefore, it is confirmed that: Fig. 21C In the transistor shown in FIG. 1 , the greater the potential of the conductor BGE used as the second gate, the greater the variation in the threshold voltage of the transistor. Fig.21A In the transistor shown, even if the potential of the conductor BGE used as the second gate increases, the amount of change in the threshold voltage of the transistor does not change.

[0508] In addition, this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0509] (Implementation 4)

[0510] In this embodiment, the structure of a metal oxide which can be used for the OS transistor described in the above embodiment is described.

[0511] 〈Composition of Metal Oxides〉

[0512] In this specification, etc., it may be described as CAAC (c-axis aligned crystal) or CAC (Cloud-Aligned Composite). Note that CAAC is an example of a crystal structure, and CAC is an example of a function or a material composition.

[0513] CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and has a semiconductor function as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (function of controlling On / Off). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0514] In addition, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated with a nanoparticle level. In addition, the conductive region and the insulating region are sometimes distributed unevenly in the material. In addition, sometimes the conductive region whose edge is fuzzy and connected with a cloud shape is observed.

[0515] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0516] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. In addition, the component with the narrow gap interacts with the component with the narrow gap through the complementary effect with the component with the wide gap, so that the carriers flow through the component with the wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on-state of the transistor.

[0517] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0518] 〈Structure of Metal Oxides〉

[0519] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductor.

[0520] As an oxide semiconductor used as a semiconductor for a transistor, a thin film with high crystallinity is preferably used. By using this thin film, the stability or reliability of the transistor can be improved. As the thin film, for example, a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film can be cited. However, forming a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film on a substrate requires a high temperature or laser heating process. Therefore, the cost of the manufacturing process becomes high and the processing volume decreases.

[0521] Non-patent Documents 2 and 3 report that In-Ga-Zn oxide (also called CAAC-IGZO) with a CAAC structure was discovered in 2009. Non-patent Documents 2 and 3 report that CAAC-IGZO has c-axis orientation, unclear grain boundaries, and can be formed on a substrate at low temperatures. In addition, it is also reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

[0522] In addition, In-Ga-Zn oxide (called nc-IGZO) with nc structure was discovered in 2013 (see Non-Patent Document 4). In Non-Patent Document 4, it is reported that the atomic arrangement of nc-IGZO in a tiny region (e.g., a region of 1 nm or more and 3 nm or less) is periodic, and no regularity of crystal orientation is observed between different regions.

[0523] Non-patent literature 5 and non-patent literature 6 show the change of the average crystal size when the thin films of the above-mentioned CAAC-IGZO, nc-IGZO and IGZO with low crystallinity are irradiated with electron beams, respectively. In the IGZO thin film with low crystallinity, crystalline IGZO of about 1 nm can be observed before it is irradiated with an electron beam. Therefore, it is reported in non-patent literature 5 and non-patent literature 6 that the existence of a completely amorphous structure (completely amorphous structure) has not been confirmed in IGZO. Furthermore, it is disclosed that the stability of CAAC-IGZO thin films and nc-IGZO thin films relative to electron beam irradiation is higher than that of IGZO thin films with low crystallinity. Therefore, it is preferable to use a CAAC-IGZO thin film or a nc-IGZO thin film as a semiconductor of a transistor.

[0524] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the lattice arrangement direction changes between the region where the multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0525] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, in the distortion, there is sometimes a lattice arrangement such as a pentagon or a heptagon. In addition, in CAAC-OS, no clear grain boundary is observed even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This may be because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms due to the substitution of metal elements.

[0526] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be represented as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0527] CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, no clear grain boundaries are observed in CAAC-OS, so a decrease in electron mobility caused by grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, the degree of freedom of the manufacturing process can be expanded.

[0528] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0529] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0530] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0531] <Transistor having an oxide semiconductor>

[0532] Next, a case where the above-mentioned oxide semiconductor is used in a transistor is described.

[0533] By using the above oxide semiconductor in a transistor, a transistor having high field effect mobility can be realized. In addition, a transistor having high reliability can be realized.

[0534] Non-patent document 7 discloses that the leakage current of the transistor using the above oxide semiconductor in the non-conducting state is extremely low. Specifically, the off-state current of the transistor per channel width of 1 μm is yA / μm (10 -24For example, a low-power CPU or the like that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Non-Patent Document 8).

[0535] In addition, there are reports that use transistors using oxide semiconductors to apply the transistor to display devices by taking advantage of the low leakage current characteristic of the transistor (see non-patent document 9). In a display device, the displayed image is switched dozens of times in 1 second. The number of image switches per 1 second is called the "refresh frequency". In addition, the refresh frequency is sometimes referred to as the "drive frequency". Such high-speed screen switching that is difficult for the human eye to recognize is believed to be a cause of eye fatigue. Therefore, a technology has been proposed to reduce the refresh frequency of the display device to reduce the number of image rewrites. In addition, the drive with a reduced refresh frequency can reduce the power consumption of the display device. This driving method is called "idle stop (IDS) drive".

[0536] In addition, it is preferable to use an oxide semiconductor with a low carrier density for a transistor. In the case where the carrier density of an oxide semiconductor film is to be reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in an oxide semiconductor can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and is 1×10 -9 / cm 3 above.

[0537] In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density and thus sometimes has a lower trap state density.

[0538] Furthermore, it takes a long time for charges trapped in trap states of an oxide semiconductor to disappear, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor having a high trap state density may be unstable.

[0539] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0540] 〈Impurities〉

[0541] Here, the influence of each impurity in the oxide semiconductor is described.

[0542] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or near the interface of the oxide semiconductor (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0543] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect energy level is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0544] When an oxide semiconductor contains nitrogen, electrons as carriers are easily generated, which increases the carrier density and turns into n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Therefore, it is preferable to reduce the nitrogen in the oxide semiconductor as much as possible. For example, the nitrogen concentration in the oxide semiconductor measured by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0545] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, thereby sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to a metal atom. Therefore, transistors using an oxide semiconductor containing hydrogen tend to have a normally-on characteristic. Therefore, it is preferred to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 .

[0546] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0547] The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of transistors using the CAAC structure or oxide semiconductors having the nc structure, the reduction of the cost of the manufacturing process, and the increase of the throughput. In addition, research has been conducted on applying the transistors to display devices and LSIs by utilizing the low leakage current characteristic of the transistors.

[0548] In addition, this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0549] (Implementation method 5)

[0550] In this embodiment, a concept of a product and an example of an electronic device to which the storage device described in the above embodiment can be applied will be described.

[0551] 〈Product Concept〉

[0552] first, Fig. 22 The concept of a product to which a storage device according to one embodiment of the present invention can be applied is shown. Fig. 22 Region 701 shows a high temperature characteristic (High T operate), region 702 shows a high frequency characteristic (High foperate), region 703 shows a low off characteristic (Ioff), and region 704 shows a region where regions 701 , 702 , and 703 overlap.

[0553] When region 701 is to be satisfied, carbides or nitrides such as silicon carbide or gallium nitride are used for the channel formation region of the transistor, which is generally satisfied. In addition, when region 702 is to be satisfied, silicides such as single crystal silicon or crystalline silicon are used for the channel formation region of the transistor, which is generally satisfied. In addition, when region 703 is to be satisfied, oxide semiconductors or metal oxides are used for the channel formation region of the transistor, which is generally satisfied.

[0554] The storage device according to one embodiment of the present invention can be applied to products within the range shown in the area 704, for example.

[0555] It is difficult for existing products to satisfy all of the regions 701, 702, and 703. However, a transistor included in a memory device according to one embodiment of the present invention includes a crystalline OS in a channel formation region. When a crystalline OS is included in a channel formation region, a memory device and an electronic device that satisfy high temperature characteristics, high frequency characteristics, and low off characteristics can be provided.

[0556] As products within the range shown in area 704, for example, electronic devices with low power consumption and high performance CPUs, and in-vehicle electronic devices that are required to have high reliability in high temperature environments can be cited. More specifically, Fig.23A , Fig. 23B , Fig.23C , Fig.23D , Fig.23E1 and Fig.23E2 An example of an electronic device in which a storage device according to one embodiment of the present invention is mounted is shown.

[0557] <Electronic equipment>

[0558] The storage device according to one embodiment of the present invention can be installed in various electronic devices. In particular, the storage device according to one embodiment of the present invention can be used as a memory built into an electronic device. As examples of electronic devices, in addition to electronic devices with larger screens such as television devices, desktop or notebook personal computers, displays for computers, etc., digital signage (Digital Signage), large game machines such as pinball machines, etc., digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, etc. can also be cited.

[0559] The electronic device of one embodiment of the present invention may also include an antenna. By receiving a signal through the antenna, an image or information can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0560] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0561] An electronic device of one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc. Fig.23A , Fig. 23B , Fig.23C , Fig.23D , Fig.23E1 and Fig.23E2 An example of an electronic device is shown.

[0562] Fig.23A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display unit 5511 . The display unit 5511 has a touch screen as an input interface, and the housing 5510 is provided with buttons.

[0563] Fig. 23B The tabletop information terminal 5300 is shown. The tabletop information terminal 5300 includes an information terminal body 5301 , a display 5302 , and a keyboard 5303 .

[0564] Note that in the above example, Fig.23A and Fig. 23B Smartphones and desktop information terminals are shown as examples of electronic devices, but information terminals other than smart phones and desktop information terminals may also be applied. Examples of information terminals other than smart phones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0565] Fig.23C An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0566] In the above example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0567] Fig.23D A portable game machine 5200 as an example of a game machine is shown. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0568] Although Fig.23D A portable game console is shown as an example of a game console, but the game console to which the storage device according to one embodiment of the present invention can be applied is not limited thereto. Examples of game consoles to which the storage device according to one embodiment of the present invention can be applied include home-use fixed game consoles, arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0569] Fig.23E1 A car 5700 is shown as an example of a moving object. Fig.23E2 It is a diagram showing the periphery of the front windshield in the interior of a vehicle. Fig.23E2 Display panel 5701, display panel 5702, display panel 5703 installed on the instrument panel, and display panel 5704 installed on the pillar are shown.

[0570] Display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a driving distance, a fuel gauge, a gear status, and an air conditioning setting. In addition, the user can appropriately change the display content and layout of the display panel, etc., which can improve the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0571] By displaying the image captured by the camera device (not shown) installed in the car 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillar can be supplemented. In other words, by displaying the image captured by the camera device installed outside the car 5700, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the image that supplements the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0572] Although the above example describes a car as an example of a mobile body, the mobile body is not limited to the car. For example, a tram, a monorail, a ship, an airplane (helicopter, unmanned aerial vehicle (UAV), an airplane, a rocket), etc. can also be cited as a mobile body, and the storage device according to one embodiment of the present invention can be applied to these mobile bodies.

[0573] The storage device according to one embodiment of the present invention can retain data for a long time even in a high temperature environment, and can operate at high speed even in a low temperature environment. By applying the storage device according to one embodiment of the present invention to the above-mentioned various electronic devices, it is possible to provide an electronic device with high reliability that can reliably operate in a high temperature environment or a low temperature environment. In addition, the power consumption of the electronic device can be reduced.

[0574] In addition, this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0575] [Example 1]

[0576] In this embodiment, the operating frequency of the memory cell 211 described in Embodiment 1 is estimated. Note that in this embodiment, since an OS transistor is used as the transistor M11 included in the memory cell 211, the memory cell 211 configures a DOSRAM.

[0577] One of the specifications required of DOSRAM is the "allowable voltage variation", which refers to the allowable value of the amount of variation of the voltage applied to the capacitor of DOSRAM after data is written. In addition, the "data retention time" of DOSRAM refers to the time required for the variation of the voltage applied to the capacitor included in DOSRAM to reach the allowable voltage variation. In the present embodiment, the "allowable voltage variation" is set to 0.2V, and the "data retention time" is set to the time required for the voltage applied to the capacitor (maintaining the capacitance of 3.5fF) to drop by 0.2V from the state after data is written. For example, in the present embodiment, "the data retention of DOSRAM is 1 hour" means that the time for the potential applied to the capacitor included in DOSRAM to drop by 0.2V after data is written is 1 hour.

[0578] The data retention time of DOSRAM depends on the cut-off current of the transistor included in DOSRAM. Here, the cut-off current of the transistor can be replaced by the gate voltage V G =Leakage current I at 0V D (Hereinafter, referred to as Icut.) For example, when the data retention characteristics of a DOSRAM depend only on the size of the Icut of the transistor included in the DOSRAM, the data retention time of the DOSRAM is inversely proportional to the size of the Icut of the transistor included in the DOSRAM.

[0579] When the Icut of the transistor included in the DOSRAM is known, the data retention time of the DOSRAM can be calculated as follows: the amount of charge that disappears from the capacitor when retaining data (equivalent to 0.7fC, which is the product of the retention capacitance of the capacitor (3.5fF) and the amount of voltage drop applied to the capacitor (0.2V)) is divided by Icut. In addition, by setting the target retention time of the DOSRAM and dividing the above charge amount 0.7fC by the retention time, the Icut value required by the transistor included in the DOSRAM (hereinafter referred to as Icut0) is estimated. When the retention time target is set to 1 hour, the Icut required by the transistor is approximately 200zA (200×10 -21 A) By Fig.24 By adjusting the back gate voltage in the manner shown in FIG. 200 , the DOSRAM having high data retention characteristics and high operating frequency in a wide temperature range can be realized. In this embodiment, the relationship between the back gate voltage and the operating frequency of the DOSRAM is evaluated.

[0580] When estimating the operating frequency of DOSRAM, it is necessary to manufacture Fig.13A and Fig. 13B A transistor having the same structure as the transistor 500 shown in FIG. 1 (hereinafter referred to as sample 1) is used, and parameters required for estimation are extracted from its electrical characteristics. Figure 2B The transistor M11 of the transistor 500 is assumed to estimate the operating frequency of the DOSRAM.

[0581] First, the structure of Sample 1 is described. Fig.13A , Fig. 13B As shown, sample 1 includes an insulator 524 configured on a substrate (not shown), an oxide 530a configured on the insulator 524, an oxide 530b configured on the oxide 530a, an oxide 530c configured on the oxide 530b, an insulator 550 configured on the oxide 530c, and a conductor 560 (conductor 560a and conductor 560b) configured on the insulator 550.

[0582] As the insulator 524, silicon oxynitride with a thickness of 35 nm is used.

[0583] As the oxide 530a, an In-Ga-Zn oxide having a thickness of 5 nm formed by a DC sputtering method was used. When forming the oxide 530a, a target material with an In:Ga:Zn ratio of 1:3:4 [atomic number ratio] was used, an oxygen gas of 45 sccm was used as a deposition gas, a film forming pressure of 0.7 Pa, a deposition power of 500 W, a deposition temperature of 200°C, and a distance between the target material and the substrate of 60 mm was used.

[0584] As the oxide 530b, an In-Ga-Zn oxide having a thickness of 20 nm formed by a DC sputtering method was used. When forming the oxide 530b, a target material having an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio] was used, argon gas 30 sccm and oxygen gas 15 sccm were used as deposition gases, the deposition pressure was set to 0.7 Pa, the deposition power was set to 500 W, the substrate temperature was set to 200°C, and the distance between the target material and the substrate was set to 60 mm.

[0585] As the oxide 530c, an In-Ga-Zn oxide having a thickness of 5 nm formed by a DC sputtering method was used. When forming the oxide 530c, a target material having an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio] was used, an oxygen gas of 45 sccm was used as a deposition gas, a deposition pressure of 0.7 Pa, a deposition power of 500 W, a substrate temperature of 130° C., and a distance between the target material and the substrate of 60 mm was used.

[0586] Silicon oxynitride with a thickness of 8 nm was used as the insulator 550. Titanium nitride with a thickness of 10 nm was used as the conductor 560a. Tungsten was used as the conductor 560b.

[0587] Sample 1 having the above structure is a transistor having a channel length of 0.37 μm and a channel width of 0.24 μm. In addition, like transistor 500, sample 1 also includes insulator 514, insulator 516, conductor 503, insulator 522, conductor 542, insulator 554, conductor 540, insulator 580, insulator 574, insulator 581, etc. in addition to the above structure.

[0588] Next, in Sample 1, the I D -V G Measurement. D -V G Measure the drain potential of the transistor by placing V D Set to +1.08V, source potential V S Set to 0V and set the gate potential V G The back gate voltage V BG At -7.1V, I D -V G The measurement temperature is -37°C, 27°C, 83°C, 121°C, 144°C, and 192°C. Specifically, the I D -V G The measurement was performed with a 5-inch square substrate on which the transistor to be measured was formed being fixed on a heat chuck set to the above-mentioned respective temperatures.BG The three components of sample 1 were measured at the measurement temperature.

[0589] From the obtained I D -V G The drift voltage (Vsh) and subthreshold swing value (Svalue) of the transistor are calculated from the curve. In addition, Svalue refers to the change in gate voltage in the subthreshold region when the drain current value changes by one digit at a fixed drain voltage.

[0590] As shown in the above embodiment, the channel formation region of the transistor 500 uses metal oxide. For example, compared with a transistor using Si in the channel formation region, the transistor using metal oxide in the channel formation region has a very small leakage current in the non-conducting state. Therefore, it is sometimes difficult to detect the Icut of the transistor using metal oxide in the channel formation region by actual measurement. It is also difficult to measure Icut in the transistor 500, so by using the above Icut D -V G The Vsh and Svalue obtained from the curve are extrapolated using formula (1) to estimate Icut. In addition, as shown in formula (1), it is assumed that until the off-state current of the transistor reaches V G =0V until I D Decreases monotonically according to Svalue.

[0591] [Number 1]

[0592]

[0593] Next, the I D -V S Measurement.

[0594] Here, the estimation method of the operating frequency of the DOSRAM is described. The operating frequency of the DOSRAM is defined as the reciprocal of the data write cycle time of the DOSRAM. The data write cycle time of the DOSRAM is a parameter set according to the charging time of the capacitor included in the DOSRAM, etc. In this embodiment, the time equivalent to 40% of the data write cycle time of the DOSRAM (the reciprocal of the operating frequency of the DOSRAM) is set as the charging time of the capacitor included in the DOSRAM.

[0595] The operating frequency of DOSRAM depends on the charging time of the capacitor included in DOSRAM. Therefore, when estimating the operating frequency of DOSRAM, the charging time of the capacitor included in DOSRAM must be known in advance. In this embodiment, the state in which the capacitor included in DOSRAM (holding capacitance is 3.5fF) is supplied with a potential of 0.52V or more is defined as the capacitor being in a "charged state". Therefore, in this embodiment, the time from the start of the data writing operation of DOSRAM until the potential supplied to the capacitor reaches 0.52V is equivalent to the charging time of the capacitor included in DOSRAM.

[0596] The charging time of the capacitor included in the DOSRAM depends on the I of the transistor included in the DOSRAM when the data of the DOSRAM is written. D Therefore, in this embodiment, by assuming that the potential supplied to the transistor included in the DOSRAM when the data is written to the DOSRAM (refer to Fig.25A ) is actually supplied to a transistor (L / W=0.37 / 0.24 μm) according to one embodiment of the present invention to reproduce the data writing operation of the DOSRAM, and the I D . Fig.25A It is assumed that data is written to Figure 2B The case of capacitor CA (in Fig.25A Lieutenant General is equivalent to Figure 2B The capacitor of the capacitor CA is denoted as Cs). D represents the drain, G represents the gate, and S represents the source. The potential of the source of the transistor Tr1 (the voltage applied to the capacitor Cs) is V s By turning on transistor Tr1, the current I D Specifically, the gate potential Vg of the transistor is set to +2.97V, the drain potential Vd is set to +1.08V, and the source potential V S The transistor's I is swept from 0V to +1.2V. D Measure the back gate voltage V BG At -7.1V, I D The standard temperature for measurement is -37℃, 27℃, 83℃, 121℃, 144℃, and 192℃.

[0597] In addition, as the structure of the DOSRAM, a structure including a transistor having a channel length (L) of 60 nm and a channel width (W) of 60 nm and a capacitor having a holding capacitance of 3.5 fF is assumed. Therefore, the I obtained from the transistor 500 (L / W = 0.37 μm / 0.24 μm) is corrected with the size of the transistor (L / W = 60 / 60 nm) assumed to be included in the DOSRAM.D value.

[0598] After the DOSRAM charging starts, V S Reaching the write determination voltage V CS The charging is considered to be completed when W (Refer to Fig.25B ). Let the charge stored in the capacitor of the holding capacitor Cs[F] included in the DOSRAM be Q[C], and the charging time be t W [sec], the potential applied to the capacitor by charging is set to V CS (=Vs)[V], the drain current of the transistor included in the DOSRAM is set to I D [A], each parameter satisfies the relationship of the following formula (2).

[0599] [Number 2]

[0600]

[0601] By changing equation (2), the charging time t of the capacitor included in the DOSRAM can be expressed as follows (3): W (Refer to Fig.25C ).

[0602] [Number 3]

[0603]

[0604] In this embodiment, 3.5fF is substituted into Cs in equation (3), and +0.52V is substituted into V cs , substitute the above I D -V S The measured I D , to calculate the charging time t of the capacitor included in the DOSRAM W .

[0605] The operating frequency f and charging time t of DOSRAM can be expressed by equation (4): W relationship.

[0606] [Number 4]

[0607]

[0608] In equation (4), A is a coefficient. Assuming that the time required for writing accounts for 40% of one operating time of the DOSRAM, in this embodiment, the operating frequency f is calculated by setting the coefficient A to 0.4.

[0609] Fig.26The operating frequency of the DOSRAM is shown when the power supply voltage is set to 3.3V and the back gate voltage is set to -7.1V in Sample 1. Fig.26 The horizontal axis shows the inverse of temperature [K -1 ](exist Fig.26 In the example, it is expressed as "1000 / Temperature[1 / K]"), and the vertical axis shows the operating frequency [MHz]. Fig.26 As shown in , it can be confirmed that the higher the temperature, the higher the operating frequency. Fig.26 As shown, the operating frequency at 192°C is calculated to be 1053MHz.

[0610] It can be seen from this that by using metal oxide in the channel formation region of the transistor included in the DOSRAM, the operating frequency of the DOSRAM increases as the temperature increases.

[0611] At least a part of the structure, method, etc. described in this embodiment can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0612] [Example 2]

[0613] In recent years, AI (Deep Learning) has developed significantly and the processing power of processors has been improved, so there is a demand for large-capacity and low-power operation memory. In the existing DOSRAM, a 3.3V power supply is used to ensure the off state and on state of the unit transistor.

[0614] A DOSRAM with a storage capacitance of 64kb was prototyped by combining a 65nm CAAC-IGZO FET (a transistor containing In-Ga-Zn oxide with a CAAC structure in the semiconductor layer) and a 60nm Si CMOS process. The measured data of this DOSRAM was used to explore the possibility of reducing the power supply voltage by optimizing the word line potential and the back gate potential.

[0615] Fig.27A : is a perspective view showing the device structure of a CAAC-IGZO FET included in a memory cell. The transistor has the same structure as the transistor 500 shown in the above embodiment. Therefore, the transistor includes a top gate electrode (TGE), a gate insulating layer (TGI) on one side of the top gate electrode, a back gate electrode (BGE), a gate insulating layer (BGI) on one side of the back gate electrode, etc. The transistor is an S-channel structure transistor.

[0616] Fig.27B The measured results of the Id-Vg characteristics when the back gate voltage Vbg of the CAAC-IGZO FET is changed from 0V to -18V by 2V. Fig.28AThe back gate voltage Vbg dependency of the field effect mobility μFE is shown. Fig.28B The back gate voltage Vbg dependency of the threshold voltage Vth is shown.

[0617] from Fig.27A , Fig.27B , Fig.28A and Fig.28B It can be seen that in Si FET, the threshold voltage is controlled by channel doping, and in CAAC-IGZO FET, the threshold voltage Vth is controlled in a wider range by the back gate voltage Vbg. On the other hand, when the back gate voltage Vbg is too large in the negative direction, the field effect mobility decreases. Fig.28A It can be seen that when Vbg is less than -8 V, the field effect mobility μFE decreases significantly.

[0618] Fig.29 The block diagram of the trial-produced 64kb DOSRAM is shown. The trial-produced 64kb DOSRAM includes a memory cell array 801 and a peripheral circuit 802. The peripheral circuits 802 such as a word line driver circuit 803 and a bit line driver circuit are driven at 1.2V. In addition, the word line driver circuit 803 includes a level converter 804 and a buffer 805. The low potential side power supply of these two circuits utilizes the negative potential (VSSL) generated in the negative potential generating circuit 811 for the top gate described later. The word line WL is connected to the output of the buffer. The back gate of the CAAC-IGZO FET included in the memory cell 806 constituting the memory cell array 801 is connected to the output of the negative potential generating circuit 821 for the back gate described later, and is applied with the negative potential (Vbg) supplied by the generating circuit.

[0619] The refresh frequency of the memory cell mainly depends on the leakage current of the cell transistor. When refreshing once every hour, the drain current Id in the non-selected state needs to be very low, that is, less than 200zA / FET at 85°C (z is 10- 21 When the back gate voltage Vbg is adjusted and the drain current Id is set to less than 200zA when Vg is 0V, Vbg needs to be set to less than -7V.

[0620] In order to reduce the power supply voltage, the composite optimization of the word line potential (top gate potential) and the back gate potential is discussed. Three operating conditions among the operating conditions for the optimization of the word line potential and the back gate potential are explained. The first condition is the driving condition A, in which the voltage supplied to the top gate voltage Vtg (equivalent to the voltage supplied to the word line WL) is set to 3.3V on the high potential side voltage VDDH and 0V on the low potential side voltage VSSL, and the back gate voltage Vbg is set to -7V. The second condition is the driving condition B, in which the high potential side voltage VDDH is set to 2.5V and the low potential side voltage VSSL is set to -0.8V, and the back gate voltage Vbg is set to -3V. The third condition is the driving condition C, in which the high potential side voltage VDDH is set to 1.8V and the low potential side voltage VSSL is set to -1.5V, and the back gate voltage Vbg is set to 0V. Note that in order to obtain an operating frequency of about 100MHz, at least a few μA of on-state current is required. Therefore, in this study, the potential difference of the word line (VDDH-VSSL) is fixed to 3.3V.

[0621] Fig. 30A The Id-Vg characteristics of the CAAC-IGZO FET driven under driving condition A, driving condition B, and driving condition C are shown. Fig. 30B and Fig. 30C 1 is a diagram showing operating voltages under driving condition A, driving condition B, and driving condition C. FIG.

[0622] When maintaining the data written into the memory cell, the drain current Id needs to be sufficiently reduced. In addition, when writing data to the memory cell, in order to increase the write speed, the drain current Id needs to be increased. The thickness of the gate insulating layer (BGI) on the back gate electrode side is about 5 times the thickness of the gate insulating layer (TGI) on the top gate electrode side when converted to EOT. Therefore, in driving condition A, in order to achieve a very small drain current, i.e. 1zA, the back gate voltage Vbg needs to be set to -7V.

[0623] On the other hand, in driving condition B, a negative voltage is applied not only to the back gate electrode but also to the top gate electrode. In driving condition B, since the back gate voltage Vbg is -3V, the variation of the threshold voltage Vth is less than that in driving condition A. By supplying a negative potential to the top gate electrode as VSSL, the drain current of the CAAC-IGZO FET can be sufficiently reduced. Furthermore, in driving condition C, the back gate voltage Vbg can be set to 0V.

[0624] By supplying a negative potential as the low potential side voltage VSSL to the top gate electrode, the absolute value of the back gate voltage Vbg can be reduced, thereby improving the reliability of the memory device.

[0625] Fig.31 The following table shows the evaluation results of VDDH, VSSL, Vbg, and data retention of a DOSRAM produced by combining a 65nm CAAC-IGZO FET and a 60nm Si CMOS process. Fig.37 A chip photograph of a DOSRAM produced by trial is shown. The potential difference between VDDH and VSSL was set to 3.3V at an ambient temperature of 25°C, and various combinations of VDDH, VSSL, and Vbg were evaluated.

[0626] Specifically, write information to the entire 64kb DOSRAM memory cell array and read the information after holding it for 1 second ( Fig.31 It is expressed as "write→1s hold→read") to determine whether the written information is accurately held (Pass or Fail). Note that the write time (charging time for the storage cell capacity) is set to 200ns, and the read time is set to 150ns.

[0627] Before evaluation, the error bits under the conditions of VDDH = 1.7V, VSSL = -1.2V and Vbg = 0V were removed as initial failures ( Fig.31 In the figure, it is indicated that "the initial defect is removed and the area ○ is assumed to be error-free"). This condition is a condition under which error bits are not likely to occur. Therefore, this error is caused by the manufacturing process of DOSRAM.

[0628] Fig.32A , Fig.32B The evaluation results of the retention time at an ambient temperature of 85°C (indicated as "dataretention at 85°C", "write→hold→read" in FIG. 32) and the yield rate are shown. The evaluation was performed under VDDH=1.8V, VSSL=-1.5V and Vbg=0V. The yield rate at each retention time was calculated with the yield rate at a retention time of 1 second as 100%. Fig.31 It can be seen that a high yield can be achieved even when the holding time is 1 hour.

[0629] from Fig.31 and Fig.32A , Fig.32B It can be seen that by adjusting Vbg, normal operation and retention characteristics of 85°C for 1 hour are obtained under any conditions including driving condition B (Vbg = -3V) and driving condition C (Vbg = 0V). In addition, from the perspective of operation and retention performance, it is confirmed that the power supply voltage can be reduced from 3.3V to 1.8V. At this time, Vbg can be changed from -7V to 0V. Therefore, the load of the unit transistor or the Vbg generation circuit is reduced, which is beneficial to reliability.

[0630] Assume the unit area is 3.696um2 The influence of the above different operating voltages is estimated for a 1Mb DOSRAM (the minimum array is 128×128). Since the absolute value of the voltage is larger in driving condition A, that is, Vbg is -7V, and a high-voltage withstand transistor is required, driving condition B is compared with driving condition C.

[0631] Fig.33A 1 is a block diagram of a negative potential generating circuit (negative potential generating circuit 811 and / or negative potential generating circuit 821). The negative potential generating circuit 811 is composed of a ring oscillator 812, a charge pump 813, and a comparator 814. The negative potential generating circuit 811 has a function of supplying VSSL. The negative potential generating circuit 821 is composed of a ring oscillator 822, a charge pump 823, and a comparator 824. The negative potential generating circuit 821 has a function of supplying Vbg.

[0632] Fig.33B 1 and 2 show the operating waveform of the negative potential generating circuit (negative potential generating circuit 811 and / or negative potential generating circuit 821). Fig.34A The working verification conditions of the ring oscillator are shown. Fig.34B 811, the intermittent operation of the ring oscillator 812 is controlled by the output signal EN of the comparator 814. The output ROOUT of the ring oscillator 812 is supplied to the charge pump 813. Similarly, in the negative potential generating circuit 821, the intermittent operation of the ring oscillator 822 is controlled by the output signal EN of the comparator 824. The output ROOUT of the ring oscillator 822 is supplied to the charge pump 823.

[0633] That is, when the output of the charge pump (charge pump 813 and / or charge pump 823) is higher than the specified potential, the ring oscillator (ring oscillator 812 and / or ring oscillator 822) and the charge pump work (also called "Active state"), and when the output is lower than the specified potential, the operation stops (also called "hibernation state" or "Sleep state").

[0634] In the negative potential generating circuit 811 generating VSSL, the load current (at Fig.34B The average load current is 8uA (in Fig.34B Since the back gate electrode has a floating structure, the load current of the negative potential generating circuit 821 in the driving condition A is small (in Fig.34B The number of stages of inverters constituting the negative potential generating circuit 811 and the negative potential generating circuit 821 (in Fig.34A The number of charge pump stages (in Fig.34B The "# of stages" in the table are all six stages, with the lowest output voltage (at Fig.34B The minimum output voltage is -5V. Fig.34B is recorded as "about -5V").

[0635] Fig.35A A circuit diagram of a comparator (comparator 814 and / or comparator 824 ) is shown. Fig.35B The comparator operating waveform is shown in Figure 1. Fig.35A In the example, CAAC-IGZO FET is used as a differential pair for comparison, and the negative potential VIN (VSSL or Vbg) for comparison is applied to the back gate, and Vref is applied to the top gate. When using Si FET, the negative potential needs to be converted to a positive potential for comparison due to the voltage division of the resistor string, but when using CAAC-IGZO FET, a negative potential is supplied to the back gate, and negative potential comparison can be performed without adding the remaining circuit or power consumption current for conversion to a positive potential. VIN = -1.5V can be determined at Vref = 1.18V.

[0636] FIG. 36A to FIG. 36C shows a simulated 1Mb (storage capacitor, at Fig.36C The estimated results of power consumption and area occupied by DOSRAM (recorded as "density") in 1Mb DOSRAM. The number of memory cells per word line of 1Mb DOSRAM (recorded as "density") in 1Mb DOSRAM Fig.36C Recorded as “storage units per WL”) is 128. Fig.36A The estimated results of the power consumption of 1Mb DOSRAM when it is working (also called "working power" or "Active Power") and when it is in standby (also called "standby power" or "Standby Power") are shown. By adopting the driving condition C of 1.8V power supply, compared with the driving condition B of 2.5V, the standby power is reduced by about 50%, which is 120.2nW.

[0637] Fig.36B FIG. 8 shows the estimated results of the power consumption and operation time of the negative potential generating circuit 811 in the driving condition B. Fig.36B It can be seen that the working time (also called "Active Time") for generating negative potential is 2.48μ seconds, and the sleep time (also called "Sleep Time") is 28.4 seconds. In other words, the generation of negative potential (VSSL = -1.5V) occurs once every 28.4 seconds, and the impact on standby power can be almost ignored (in Fig.36B Also called average power (“Average Power”)).

[0638] In 1Mb DOSRAM, the power supply of the circuits other than the storage unit (also called "Memory") including the memory cell array and the negative potential generating circuit (also called "Neg.Bias") can be turned off (less than 1nW) (In addition, Fig.36A Therefore, the power consumption of the negative potential generating circuit during sleep (also called "sleep power") accounts for almost 100% of the power consumption of the 1Mb DOSRAM.

[0639] Note that in the negative potential generating circuit 811, the power consumption of the driving condition C (VSSL = -1.5 V) is greater than that of the driving condition B (VSSL = -0.8 V). However, the operating power of the negative potential generating circuit in the driving condition C is 132 μW (see Fig.36A ) is small, that is, 2.68% of the power consumption of 4.83mW when 1Mb DOSRAM works at 100MHz.

[0640] Fig.36C The estimated results of the occupied area of ​​the storage unit including the memory cell array (also referred to as "Area A") and the occupied area of ​​the negative potential generating circuit (also referred to as "Area B") are shown. The occupied area of ​​1Mb DOSRAM is estimated assuming that one word line WL is connected to 128 memory cells. Fig.36C As shown, the ratio of the occupied area of ​​the negative potential generating circuit to the occupied area of ​​the 1 Mb DOSRAM (described as "ratio A / (A+B)" in FIG. 36) is relatively small, namely, 0.209%.

[0641] 1.8V power supply DOSRAM is a low-power embedded memory suitable for IoT or AI edge computers.

[0642] [Explanation of symbols]

[0643] C21: Capacitor, C22: Capacitor, C24: Capacitor, M11: Transistor, M12: Transistor, M13: Transistor, M14: Transistor, M15: Transistor, M16: Transistor, M21: Transistor, M24: Transistor, M31: Transistor, M34: Transistor, N11: Node, N12: Node, N13: Node, N14: Node, S1: Oxide, Tr21: Transistor, Tr22: Transistor, Tr23: Transistor, Tr31: Transistor, Tr3 2: transistor, Tr33: transistor, Tr34: transistor, Tr41: transistor, Tr42: transistor, 13: transistor, 14: transistor, 15: transistor, 16: transistor, 17: transistor, 18: transistor, 19: transistor, 20: transistor, 21: transistor, 33: transistor, 34: transistor, 35: transistor, 36: transistor, 37: transistor, 38: transistor, 39: transistor, 40: transistor, 41: transistor, 54: circuit, 55: circuit

Claims

1. A semiconductor device having a plurality of circuits arranged in a matrix, wherein: The circuits each have at least a first transistor, One of the circuits has: a first conductive layer having a region used as a first gate electrode of the first transistor; a first insulating layer on the first conductive layer; an oxide semiconductor layer located on the first insulating layer and having a channel formation region of the first transistor; a second insulating layer on the oxide semiconductor layer; a second conductive layer located on the second insulating layer and having a region used as a second gate electrode of the first transistor; a third insulating layer located on the second conductive layer; a third conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the oxide semiconductor layer; a fourth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the first conductive layer; and a fifth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the second conductive layer, The fourth conductive layer has a region extending in the first direction, The fifth conductive layer has a region extending in the first direction, The fifth conductive layer is electrically connected to a second gate electrode of a first transistor included in a circuit adjacent to one of the circuits in a row direction.

2. A semiconductor device having a plurality of circuits arranged in a matrix, wherein: The circuits each have at least a first transistor, One of the circuits has: a first conductive layer having a region used as a first gate electrode of the first transistor; a first insulating layer on the first conductive layer; an oxide semiconductor layer located on the first insulating layer and having a channel formation region of the first transistor; a second insulating layer on the oxide semiconductor layer; a second conductive layer located on the second insulating layer and having a region used as a second gate electrode of the first transistor; a third insulating layer located on the second conductive layer; a third conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the oxide semiconductor layer; a fourth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the first conductive layer; and a fifth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the second conductive layer, The fourth conductive layer has a region extending in the first direction, The fifth conductive layer has a region extending in the first direction, The third conductive layer has a region extending in a direction intersecting the first direction, The third insulating layer has at least a first opening, a second opening, and a third opening. The oxide semiconductor layer and the third conductive layer are electrically connected via the first opening. The first conductive layer and the fourth conductive layer are electrically connected via the second opening. The second conductive layer and the fifth conductive layer are electrically connected via the third opening. The first opening has an overlapping portion with the oxide semiconductor layer, The second opening has no overlapping portion with the oxide semiconductor layer and has no overlapping portion with the second conductive layer. The third opening has no overlapping portion with the oxide semiconductor layer and has no overlapping portion with the first conductive layer. The fifth conductive layer is electrically connected to a second gate electrode of a first transistor included in a circuit adjacent to one of the circuits in a row direction.

3. A semiconductor device having a transistor, comprising: a first conductive layer having a region used as a first gate electrode of the transistor; a first insulating layer on the first conductive layer; an oxide semiconductor layer located on the first insulating layer and having a channel formation region of the transistor; a second insulating layer on the oxide semiconductor layer; a second conductive layer located on the second insulating layer and having a region used as a second gate electrode of the transistor; a third insulating layer located on the second conductive layer; a third conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the oxide semiconductor layer; a fourth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the first conductive layer; and a fifth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the second conductive layer, The fourth conductive layer has a region extending in the first direction, The fifth conductive layer has a region extending in the first direction.

4. A semiconductor device having a transistor, comprising: a first conductive layer having a region used as a first gate electrode of the transistor; a first insulating layer on the first conductive layer; an oxide semiconductor layer located on the first insulating layer and having a channel formation region of the transistor; a second insulating layer on the oxide semiconductor layer; a second conductive layer located on the second insulating layer and having a region used as a second gate electrode of the transistor; a third insulating layer located on the second conductive layer; a third conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the oxide semiconductor layer; a fourth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the first conductive layer; and a fifth conductive layer having a region in contact with a top surface of the third insulating layer and electrically connected to the second conductive layer, The fourth conductive layer has a region extending in the first direction, The fifth conductive layer has a region extending in the first direction, The third conductive layer has a region extending in a direction intersecting the first direction, The third insulating layer has at least a first opening, a second opening, and a third opening. The oxide semiconductor layer and the third conductive layer are electrically connected via the first opening. The first conductive layer and the fourth conductive layer are electrically connected via the second opening. The second conductive layer and the fifth conductive layer are electrically connected via the third opening. The first opening has an overlapping portion with the oxide semiconductor layer, The second opening has no overlapping portion with the oxide semiconductor layer and has no overlapping portion with the second conductive layer. The third opening has no overlapping portion with the oxide semiconductor layer and has no overlapping portion with the first conductive layer.

5. The semiconductor device according to claim 3 or 4, wherein: In a cross-sectional view in a channel length direction of the transistor, both end portions of the second insulating layer have overlapping portions with the oxide semiconductor layer.

Images