Method of detecting open circuit of semiconductor device including detection structure and semiconductor device

Abstract

A method of detecting an open circuit of a semiconductor device includes: generating a clock signal based on a probe of a measurement circuit contacting an end of a detection structure via a switch; measuring the period of the clock signal; counting a number of cycles of the clock signal during the reference time interval; and determining a position of an open circuit of the semiconductor device based on the number of cycles of the clock signal. The detection structure is formed in a ring shape in a semiconductor die of a semiconductor device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0098160 filed in the Korean Intellectual Property Office on July 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to semiconductor integrated circuits, and more particularly, to a method of detecting an open circuit of a semiconductor device including a detection structure and a semiconductor device performing the method. Background Art

[0004] Related integrated circuits can be manufactured by forming a repeating pattern in a wafer of semiconductor material. The wafer can be cut and / or segmented into a plurality of semiconductor dies, and the individual semiconductor dies can be packaged into semiconductor chips. However, during the cutting and / or packaging process, manufacturing defects such as open circuits may occur in the semiconductor dies. In order to increase the manufacturing yield of semiconductor dies (e.g., reduce the yield of defective products), semiconductors can be inspected to accurately detect and / or locate open circuits. Summary of the invention

[0005] One or more example embodiments of the present disclosure may provide a method of detecting an open circuit of a semiconductor device including a detection structure, the method being capable of accurately determining a location of the open circuit.

[0006] Furthermore, one or more example embodiments of the present disclosure may provide a semiconductor device capable of performing the method of detecting an open circuit.

[0007] According to one aspect of the present disclosure, a method for detecting an open circuit of a semiconductor device includes: generating a clock signal based on a probe of a measurement circuit contacting an end of a detection structure via a switch, measuring a cycle of the clock signal, counting the number of cycles of the clock signal during a reference time interval, and determining a location of the open circuit of the semiconductor device based on the number of cycles of the clock signal. The detection structure is formed in a semiconductor die of the semiconductor device in a ring shape.

[0008] According to one aspect of the present disclosure, a method for detecting an open circuit of a semiconductor device includes: generating a first number by counting a first cycle of a first clock signal during a reference time interval, the first clock signal being generated by contacting a probe of a measurement circuit with a first end of a detection structure via a first switch; generating a second number by counting a second cycle of a second clock signal during the reference time interval, the second clock signal being generated by contacting a probe of the measurement circuit with a second end of the detection structure via a second switch; and determining a location of the open circuit in the detection structure based on a first difference between the first number and the second number, and a second difference between a first cycle of the first clock signal and a second cycle of the second clock signal. The detection structure is formed in a semiconductor die of the semiconductor device in a ring shape.

[0009] According to one aspect of the present disclosure, a semiconductor device includes: a first semiconductor die including a first central region and a first outer region, the first outer region at least partially surrounding the first central region; a second semiconductor die including a second central region and a second outer region, the second outer region at least partially surrounding the second central region; a memory cell structure formed in the first central region of the first semiconductor die; a peripheral circuit formed in the second central region of the second semiconductor die along a first direction and a second direction; a first detection structure formed in the second central region of the second semiconductor die to at least partially surround a first subcircuit region and a second subcircuit region, the first subcircuit region and the second subcircuit region being spaced apart from each other along the second direction in the peripheral circuit; and a measurement circuit configured to measure a first cycle of a first clock signal generated by contacting a probe with a first end of the first detection structure by a first switch, and to determine a first position of a first open circuit in the first detection structure by counting a first number of first cycles of the first clock signal during a reference time interval. The first semiconductor die is at least partially stacked on the second semiconductor die in a vertical direction.

[0010] In some embodiments, the measurement circuit can determine whether there is an open circuit in the detection structure based on the cycle of the clock signal generated by contacting the probe with the end of the detection structure. When the open circuit exists, the measurement circuit can determine the location of the open circuit in the detection structure by counting the number of cycles of the clock signal during the reference time interval. Therefore, the measurement circuit can detect an open circuit that may be difficult to detect based on a correlation scheme.

[0011] Additional aspects may be set forth in part in the description which follows and, in part, may be apparent from the description which follows, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of certain embodiments of the present disclosure may be more clearly understood from the following description in conjunction with the accompanying drawings, in which:

[0013] Figure 1A is a top view showing a layout of a semiconductor device according to an example embodiment;

[0014] Figure 1B is a top view showing a layout of a semiconductor device according to an example embodiment;

[0015] Figure 2 is a diagram showing a method according to an example embodiment Figure 1A Top view of the detection structure in;

[0016] Figure 3 is a flow chart illustrating a method of detecting an open circuit of a semiconductor device including a detection structure according to an example embodiment;

[0017] Figure 4 is a flow chart illustrating a method of detecting an open circuit of a semiconductor device including a detection structure according to an example embodiment;

[0018] Figure 5 According to an example embodiment, Figure 2 Examples of resistance and parasitic capacitance in the sensing structure in ;

[0019] Figure 6 According to an example embodiment, Figure 2 An example of parasitic capacitance in a sensing structure in FIG.

[0020] Fig. 7A and Figure 7B The following are respectively shown according to example embodiments. Figure 6 A clock signal measured in a detection structure;

[0021] Figure 8 shows a method according to an example embodiment depending on Figure 6 An example of a number of cycles of a clock signal for detecting the location of an open circuit in a structure;

[0022] Fig. 9 shows a method according to an example embodiment depending on Figure 6 An example of a number of cycles of a clock signal and a cycle of the clock signal for detecting the location of an open circuit in a structure;

[0023] Fig.10 is a perspective view of a three-dimensional (3D) detection structure according to an example embodiment;

[0024] Fig.11 , Fig.12 and Fig.13is a cross-sectional view showing a vertical structure of a 3D detection structure according to an example embodiment;

[0025] Fig.14 is a perspective view of a 3D crack detection structure according to an example embodiment;

[0026] Fig.15 and Fig.16 is a cross-sectional view showing a vertical structure of a 3D detection structure according to an example embodiment;

[0027] Fig.17 is a perspective view of a 3D detection structure according to an example embodiment;

[0028] Fig.18 is a block diagram illustrating a semiconductor device according to an example embodiment;

[0029] Fig.19 Schematically illustrates a Fig.18 The structure of the non-volatile memory device;

[0030] Fig. 20 is a diagram showing a method according to an example embodiment Fig.18 A block diagram of an example of a memory cell array in;

[0031] Fig.21 is a diagram showing a method according to an example embodiment Fig. 20 A circuit diagram of one of the memory blocks;

[0032] Fig. 22 is a layout diagram of a nonvolatile memory device according to example embodiments;

[0033] Fig.23 is along the lines of an exemplary embodiment Fig. 22 A cross-sectional view taken along line II';

[0034] Fig.24 is a diagram for describing a manufacturing process of a stacked semiconductor device according to example embodiments;

[0035] Fig.25 and Fig.26 is a cross-sectional view showing a vertical structure of a 3D detection structure according to an example embodiment;

[0036] Fig. 27 is a diagram showing a method according to an example embodiment Figure 1A and Figure 1B A block diagram of an example of a semiconductor device in;

[0037] Fig.28 According to an example embodiment, Fig. 27 An example of a first memory bank array in a semiconductor device;

[0038] Fig.29 is a plan view for explaining a semiconductor device according to an example embodiment;

[0039] Fig.30 is a plan view showing a semiconductor device according to an example embodiment;

[0040] Fig.31 is along the lines of an exemplary embodiment Fig.30 A cross-sectional view taken along line III-III';

[0041] Fig.32 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0042] Fig.33 is a diagram showing a method according to an example embodiment Fig.32 A plan view of a peripheral circuit region in a semiconductor device;

[0043] Fig.34 The arrangement according to the exemplary embodiment is shown in Fig.33 A detection structure in a peripheral circuit area;

[0044] Fig.35 According to an example embodiment, Fig.34 a portion of a first detection structure in; and

[0045] Fig.36 is a cross-sectional view of a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0046] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, it will be appreciated by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, descriptions of well-known functions and structures have been omitted for the purpose of clarity and conciseness.

[0047] In the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that the singular form of the noun corresponding to the project may include one or more things, unless the relevant context clearly indicates otherwise. As used herein, each phrase such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B or C" may include any one or all possible combinations of the items listed together in a corresponding phrase. As used herein, terms such as "1st" and "2nd" or "first" and "second" may be used to simply distinguish the corresponding component from other components, and do not limit the component in other aspects (e.g., importance or order). It should be understood that if the term "operably" or "communicatively" is used or not to mention that an element (e.g., a first element) is "coupled", "coupled to" another element, "connected" or "connected to" another element with another element, it means that the element can be directly (e.g., wired), wirelessly or via a third element coupled to the other element.

[0048] It should be understood that when an element or layer is referred to as being "above", "over", "up", "below", "under", "below", "connected to" or "coupled to" another element or layer, it can be directly above, above, above, below, below, below, directly connected to or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly above", "over", "up", "below", "below", "under", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0049] Throughout this disclosure, references to "one embodiment," "an embodiment," "an example embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, throughout this disclosure, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language may, but do not necessarily, all refer to the same embodiment.

[0050] It should be understood that the specific order or hierarchy of blocks in the disclosed process / flow diagram is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the process / flow diagram can be rearranged. In addition, some blocks can be combined or omitted. The attached claims present the elements of the various blocks in a sample order, but are not meant to be limited to the specific order or hierarchy presented.

[0051] The embodiments of the present invention may be described and illustrated in terms of blocks as shown in the accompanying drawings, which perform one or more functions described. These blocks (which may be referred to herein as units or modules, etc., or by names such as devices, logic circuits, circuits, controllers, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits (including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.).

[0052] As used herein, each of the terms “SiO”, “SiON”, “SiN” and the like may refer to a material made of elements included in each term rather than a chemical formula indicating a stoichiometric relationship.

[0053] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0054] Figure 1A is a top view illustrating a layout of a semiconductor device according to example embodiments.

[0055] refer to Figure 1A , the semiconductor device 1000 may include at least one semiconductor die. The semiconductor die may include a central region CTREG and an outer region EREG at least partially surrounding the central region CTREG.

[0056] Various semiconductor integrated circuits may be formed in the central region CTREG depending on the kind and / or type of the semiconductor device 1000. For example, the semiconductor device 1000 may be and / or may include a nonvolatile memory device, and a memory integrated circuit may be formed in the central region CTREG of the semiconductor die. However, the present disclosure is not limited thereto, and the semiconductor device 1000 may be and / or may include other kinds and / or types of devices and / or integrated circuits without departing from the scope of the present disclosure.

[0057] According to example embodiments, the detection structure DS, which may have a ring shape, may be configured to detect an open circuit and / or may be formed in the outer region EREG.

[0058] The detection structure DS may include a first conductive segment passing through a lower left corner area CLB of the external area EREG, a second conductive segment passing through an upper left corner area CLU of the external area EREG, a third conductive segment passing through an upper right corner area CLU of the external area EREG, and a fourth conductive segment passing through a lower right corner area CRB of the external area EREG. However, the present disclosure is not limited thereto, and the detection structure DS may include fewer conductive segments (e.g., less than four (4)) and / or more conductive segments (e.g., more than four (4)). Alternatively or additionally, the conductive segments of the detection structure DS may be configured in different configurations and / or arrangements. For example, the first to fourth conductive segments may pass through the same and / or different areas of the external area EREG.

[0059] A probe 921 of a measurement circuit 920 (e.g., an oscilloscope circuit) may be in contact (e.g., connected, coupled) with an end of the detection structure DS through the switch 910. The measurement circuit 920 may measure a cycle of a clock signal CLK generated by contacting the probe of the measurement circuit 920 with the end of the detection structure DS, and may determine the location of the open circuit in the detection structure DS by counting the number of cycles of the clock signal CLK during a reference time interval.

[0060] The detection structure DS may include a first end ET1 and a second end ET2 , the first conductive segment may include the first end ET1 , and the fourth conductive segment may include the second end ET2 .

[0061] When an open circuit occurs in the detection structure DS, the period of the clock signal CLK may vary depending on where the open circuit occurs (e.g., the position of the open circuit), and since the period of the clock signal CLK varies, the number of periods of the clock signal CLK may vary depending on the position of the open circuit. When an open circuit occurs in the detection structure DS, the period of the clock signal CLK may be greater than a reference period determined by the inherent capacitance of the measurement circuit 920 and the inherent resistance of the measurement circuit 920.

[0062] Hereinafter, for ease of illustration and description, an orthogonal set of X-direction, Y-direction, and Z-direction may be used to describe example embodiments. The X-direction, Y-direction, and Z-direction may be used to indicate three perpendicular directions along the three directions, and may not be limited to a specific direction. The X-direction may correspond to a first horizontal direction and / or a row direction, the Y-direction may correspond to a second horizontal direction and / or a column direction, and the Z-direction may correspond to a vertical direction. If no special instructions are mentioned, the Z-direction may indicate a vertical direction perpendicular to the conductive layer.

[0063] As used herein, "upper", "bottom", "left", and "right" may not be used to indicate a specific fixed position, but rather to indicate a relative position. Accordingly, example embodiments may include left-right symmetrical structures, top- and bottom-symmetrical structures, rotated structures, etc., relative to the detection structures disclosed herein.

[0064] Figure 1B is a top view illustrating a layout of a semiconductor device according to example embodiments.

[0065] refer to Figure 1B , the semiconductor device 1000a may include at least one semiconductor die. The semiconductor die may include a central region CTREG and an outer region EREG at least partially surrounding the central region CTREG.

[0066] According to example embodiments, the detection structure DS1 , which may have a ring shape, may be configured to detect an open circuit, and / or may be formed in an edge portion of the center region CTREG.

[0067] The detection structure DS1 may have Figure 1A The detection structure in DS is similar to the structure in DS.

[0068] The detection structure DS1 may include a first conductive segment passing through a lower left corner area of ​​the central region CTREG, a second conductive segment passing through an upper left corner area of ​​the central region CTREG, a third conductive segment passing through an upper right corner area of ​​the central region CTREG, and a fourth conductive segment passing through a lower right corner area of ​​the central region CTREG.

[0069] The probe 921 of the measurement circuit 920 may be in contact with (e.g., connected to, coupled to) an end of the detection structure DS1 through the switch 910. The measurement circuit 920 may measure a cycle of a clock signal CLK generated by contacting the probe of the measurement circuit 920 with the end of the detection structure DS, and may determine the location of the open circuit in the detection structure DS by counting the number of cycles of the clock signal CLK during a reference time interval.

[0070] The detection structure DS1 may include a first end ET1 and a second end ET2 , the first conductive segment may include the first end ET1 , and the fourth conductive segment may include the second end ET2 .

[0071] When an open circuit occurs in the detection structure DS1, the period of the clock signal CLK may vary depending on the location where the open circuit occurs (e.g., the location of the open circuit), and since the period of the clock signal CLK varies, the number of periods of the clock signal CLK may vary depending on the location of the open circuit. When an open circuit occurs in the detection structure DS1, the period of the clock signal CLK may be greater than a reference period determined by the inherent capacitance of the measurement circuit 920 and the inherent resistance of the measurement circuit 920.

[0072] Therefore, according to an example embodiment, Figure 1A The detection structure DS and / or Figure 1B The sensing structure DS1 may have a ring shape and / or may be formed adjacent to an edge portion of the central region CTREG in the semiconductor die.

[0073] Figure 2 is a diagram showing a method according to an example embodiment Figure 1A Top view of the detection structure in .

[0074] exist Figure 2 , for the convenience of description, switch 910 is shown.

[0075] refer to Figure 2 , the detection structure DS may include a first conductive segment CSG11 , a second conductive segment CSG12 , a third conductive segment CSG13 and a fourth conductive segment CSG14 .

[0076] The first conductive segment CSG11 may include a first end ET1 that may be connected to the switch 910 and may pass through the lower left corner region CLB of the external region EREG. The second conductive segment VSG12 may be connected to the first conductive segment CSG11 at a first node AN and may pass through the upper left corner region CLU of the external region EREG. The third conductive segment CSG13 may be connected to the second conductive segment CSG12 at a second node BN and may pass through the upper right corner region CRU of the external region EREG. The fourth conductive segment CSG14 may be connected to the third conductive segment CSG13 at a third node CN and may pass through the lower right corner region CRB of the external region EREG, and may include a second end ET2 that may be connected to the switch 910.

[0077] Figure 3 is a flow chart illustrating a method of detecting an open of a semiconductor device including a detection structure according to example embodiments.

[0078] refer to Figures 1A to 3, measuring the period of the clock signal CLK generated by contacting the probe 921 of the measurement circuit 920 with the end of the detection structure DS through the switch 911 (operation S110). The position of the open circuit in the detection structure DS is determined by counting the number of periods of the clock signal CLK during the reference time interval (operation S130).

[0079] Figure 4 is a flow chart illustrating a method of detecting an open of a semiconductor device including a detection structure according to example embodiments.

[0080] refer to Figure 1A to Figure 2 as well as Figure 4 The first number may be generated by counting a first cycle of a first clock signal during a reference time interval, the first clock signal being generated by contacting a probe 921 of a measurement circuit 920 with a first end ET1 of a detection structure DS or DS1 through a switch 910 (operation S210). The second number may be generated by counting a second cycle of a second clock signal during a reference time interval, the second clock signal being generated by contacting a probe 921 of a measurement circuit 920 with a second end ET2 of a detection structure DS or DS1 through a switch 910 (operation S230).

[0081] The location of the open circuit in the detection structure DS or DS1 is determined based on a difference between the first number and the second number, a difference between a first period of the first clock signal and a second period of the second clock signal (operation S250 ).

[0082] Figure 5 According to an example embodiment, Figure 2 Example of resistance and parasitic capacitance in the sensing structure.

[0083] refer to Figure 5 , it can be assumed that no open circuit occurs in the detection structure DS.

[0084] like Figure 5 As shown, the detection structure DS can be modeled as having a resistor R1 in the first conductive segment CSG11 and a parasitic capacitor CP1 between the first conductive segment CSG11 and the ground voltage VSS. The detection structure DS can be further modeled as having a resistor R2 in the second conductive segment CSG12 and a parasitic capacitor CP2 between the second conductive segment CSG12 and the ground voltage VSS.

[0085] The detection structure DS can be further modeled as having a resistor R3 in the third conductive segment CSG13 and a parasitic capacitor CP3 between the third conductive segment CSG13 and the ground voltage VSS. The detection structure DS can be further modeled as having a resistor R4 in the fourth conductive segment CSG14 and a parasitic capacitor CP4 between the fourth conductive segment CSG14 and the ground voltage VSS.

[0086] Figure 6 According to an example embodiment, Figure 2 Example of parasitic capacitance in a sensing structure.

[0087] refer to Figure 6 , it can be assumed that an open circuit (eg, a first open circuit OP1 , a second open circuit OP2 , a third open circuit OP3 , and a fourth open circuit OP4 ) occurs in the detection structure DS.

[0088] like Figure 6 As shown, when the first open circuit OP1 appears in the first conductive segment CSG11, the detection structure DS can be modeled as having a parasitic capacitor CP1 in the first conductive segment CSG11, and the parasitic capacitor CP1 can be coupled between the first conductive segment CSG11 and the ground voltage VSS. The first open circuit OP1 can represent one of a plurality of open circuits that can appear at various locations of the first conductive segment CSG11.

[0089] When the second open circuit OP2 appears in the second conductive segment CSG12, the detection structure DS can be modeled as having a parasitic capacitance CP2 in the second conductive segment CSG12, and the parasitic capacitance CP2 can be coupled between the second conductive segment CSG12 and the ground voltage VSS. The second open circuit OP2 can represent one of a plurality of open circuits that can appear at various locations of the second conductive segment CSG12.

[0090] When the third open circuit OP3 appears in the third conductive segment CSG13, the detection structure DS can be modeled as having a parasitic capacitance CP3 in the third conductive segment CSG13, and the parasitic capacitance CP3 can be coupled between the third conductive segment CSG13 and the ground voltage VSS. The third open circuit OP3 can represent one of a plurality of open circuits that can appear at various locations of the third conductive segment CSG13.

[0091] When the fourth open circuit OP4 appears in the fourth conductive segment CSG14, the detection structure DS can be modeled as having a parasitic capacitance CP4 in the fourth conductive segment CSG14, and the parasitic capacitance CP4 can be coupled between the fourth conductive segment CSG14 and the ground voltage VSS. The fourth open circuit OP4 can represent one of a plurality of open circuits that can appear at various locations of the fourth conductive segment CSG14.

[0092] When the probe 921 of the measurement circuit 920 is connected to the first terminal ET1, the clock signal CLK may be generated in the forward direction FWD of the detection structure DS. When the probe 921 of the measurement circuit 920 is connected to the second terminal ET2, the clock signal CLK may be generated in the backward direction BWD of the detection structure DS.

[0093] In some embodiments, all of the first open circuit OP1, the second open circuit OP2, the third open circuit OP3, and the fourth open circuit OP4 may exist in the detection structure DS. In some optional or additional embodiments, at least one of the first open circuit OP1, the second open circuit OP2, the third open circuit OP3, and the fourth open circuit OP4 may exist in the detection structure DS. That is, one or more of the first open circuit OP1, the second open circuit OP2, the third open circuit OP3, and the fourth open circuit OP4 may not exist in the detection structure DS.

[0094] When at least one of the first open circuit OP1 , the second open circuit OP2 , the third open circuit OP3 , and the fourth open circuit OP4 occurs in the detection structure DS, the period of the clock signal CLK output from the detection structure DS may be expressed as an equation similar to Equation 1.

[0095] T = Rosc × (Cosc + Cmet) (Equation 1)

[0096] Referring to Equation 1, T may represent a period of the clock signal CLK, Rosc may represent an intrinsic resistance of the measurement circuit 920, Cosc may represent an intrinsic capacitance of the measurement circuit 920, and Cmet may represent a capacitance of the detection structure DS, which may vary based on the location of the open circuit in the detection structure DS.

[0097] When an open circuit occurs in the detection structure DS, the period T of the clock signal CLK may vary based on the location of the open circuit in the detection structure DS. Therefore, the location of the open circuit may be determined by measuring the period T of the clock signal CLK and by counting the number of periods of the clock signal CLK during a reference time interval.

[0098] Fig. 7A and Figure 7B The following are respectively shown according to example embodiments. Figure 6 The clock signal measured in the detection structure. Figure 8 shows a method according to an example embodiment depending on Figure 6 An example of the number of cycles of a clock signal that detects the location of an open circuit in a structure.

[0099] Fig. 7A An example of a clock signal when the probe 921 of the measurement circuit 920 is in contact with the first end ET1 of the detection structure DS is shown. Figure 7BAn example of a clock signal when the probe 921 of the measurement circuit 920 is in contact with the second end ET2 of the detection structure DS is shown. Figure 8 Shown in Fig. 7A The situation depends on Figure 6 An example of the number of cycles of a clock signal that detects the location of an open circuit in a structure.

[0100] refer to Figure 8 , it can be assumed that the inherent resistance Rosc of the measurement circuit 920 can have a resistance value Rv.

[0101] refer to Figure 6 , Fig. 7A and Figure 8 , when the first open circuit OP1 appears in the first conductive segment CSG11 of the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to the first capacitance C11 and may vary according to the distance from the first end ET1 to the first open circuit OP1. Therefore, the clock signal CLK may have a first period T1, and the number of periods of the clock signal CLK during the reference time interval RINT may be a first number corresponding to the first count value CV1.

[0102] When the second open circuit OP2 appears in the second conductive segment CSG12 of the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to the second capacitance C12 and may vary according to the distance from the first end ET1 to the second open circuit OP2. Therefore, the clock signal CLK may have a second period T2, and the number of periods of the clock signal CLK during the reference time interval RINT may be a second number corresponding to the second count value CV2.

[0103] When the third open circuit OP3 appears in the third conductive segment CSG13 of the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to the third capacitance C13 and may vary according to the distance from the first end ET1 to the third open circuit OP3. Therefore, the clock signal CLK may have a third period T3, and the number of periods of the clock signal CLK during the reference time interval RINT may be a third number corresponding to the third count value CV3.

[0104] When a fourth open circuit OP4 appears in the fourth conductive segment CSG14 of the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to the fourth capacitance C14 and may vary according to the distance from the first end ET1 to the fourth open circuit OP4. Therefore, the clock signal CLK may have a fourth period T4, and the number of periods of the clock signal CLK during the reference time interval RINT may be a fourth number corresponding to the fourth count value CV4.

[0105] As the distance from the first terminal ET1 to the location where the open circuit occurs increases, the capacitance Cmet of the detection structure DS can increase based on Equation 1, and the period T of the clock signal CLK can also increase. In addition, as the period T of the clock signal CLK increases, the number of periods of the clock signal CLK counted during the reference time interval RINT can decrease.

[0106] Accordingly, the second period T2 may be greater than the first period T1, the third period T3 may be greater than the second period T2, and the fourth period T4 may be greater than the third period T3. The second count value CV2 may be less than the first count value CV1, the third count value CV3 may be less than the second count value CV2, and the fourth count value CV4 may be less than the third count value CV3.

[0107] refer to Figure 6 and Figure 7B , when a first open circuit 0P1 appears in the first conductive segment CSG11 of the detection structure DS, according to the distance from the second end ET2 to the first open circuit 0P1, the clock signal CLK1 can have a fourth period T4a due to the capacitance Cmet of the detection structure DS, and the number of cycles of the clock signal CLK1 during the reference time interval RINT can be the fourth number.

[0108] When a second open circuit OP2 appears in the second conductive segment CSG12 of the detection structure DS, according to the distance from the second end ET2 to the second open circuit OP2, the clock signal CLK1 can have a third period T3a due to the capacitance Cmet of the detection structure DS, and the number of cycles of the clock signal CLK1 during the reference time interval RINT can be a third number.

[0109] When a third open circuit OP3 appears in the third conductive segment CSG13 of the detection structure DS, according to the distance from the second end ET2 to the third open circuit OP3, the clock signal CLK1 can have a second period T2a due to the capacitance Cmet of the detection structure DS, and the number of cycles of the clock signal CLK1 during the reference time interval RINT can be the second number.

[0110] When a fourth open circuit OP4 appears in the fourth conductive segment CSG14 of the detection structure DS, according to the distance from the second end ET2 to the fourth open circuit OP4, the clock signal CLK1 can have a first period T1a due to the capacitance Cmet of the detection structure DS, and the number of cycles of the clock signal CLK1 during the reference time interval RINT can be the first number.

[0111] The fourth period T4a may be greater than the third period T3a, the third period T3a may be greater than the second period T2a, and the second period T2a may be greater than the first period T1a.

[0112] Fig. 9 shows a method according to an example embodiment depending on Figure 6 An example of detecting the location of an open circuit in a structure, the number of cycles of a clock signal and the period of the clock signal.

[0113] Fig. 9 The diagram shows a first number CLK1# and a first period Ta of a first clock signal CLK1 generated by contacting a probe 921 of a measuring circuit 920 with a first end ET1 of a detection structure DS through switch 910, a second number CLK2# and a second period Tb of a second clock signal CLK2 generated by contacting a probe 921 of a measuring circuit 920 with a second end ET2 of a detection structure DS through switch 910, and a difference between the first number CLK1# and the second number CLK2#.

[0114] When the first open circuit OP1 appears in the first conductive segment CSG11 of the detection structure DS, the first number CLK1# of the first clock signal CLK1 has a first count value CV11, the second number CLK2# of the second clock signal CLK2 has a second count value CV12, the first period Ta has a first value T11, and the second period Tb has a second value T12. Figure 8 As described above, the first value T11 may be smaller than the second value T12, the sign of the difference between the first count value CV11 and the second count value CV12 may be positive, and the absolute value of the difference may be greater than the reference value. Therefore, the measurement circuit 920 may determine that an open circuit occurs in the first conductive segment CSG11.

[0115] When the second open circuit OP2 appears in the second conductive segment CSG12 of the detection structure DS, the first number CLK1# of the first clock signal CLK1 has a first count value CV21, the second number CLK2# of the second clock signal CLK2 has a second count value CV22, the first period Ta has a first value T21, and the second period Tb has a second value T22. Figure 8 As described above, the first value T21 may be smaller than the second value T22, the sign of the difference between the first count value CV21 and the second count value CV22 may be positive, and the absolute value of the difference may be equal to or smaller than the reference value. Therefore, the measurement circuit 920 may determine that an open circuit occurs in the second conductive segment CSG12.

[0116] When the third open circuit OP3 appears in the third conductive segment CSG13 of the detection structure DS, the first number CLK1# of the first clock signal CLK1 has a first count value CV31, the second number CLK2# of the second clock signal CLK2 has a second count value CV32, the first period Ta has a first value T31, and the second period Tb has a second value T32. Figure 8As described above, the first value T31 may be greater than the second value T32, the sign of the difference between the first count value CV31 and the second count value CV32 may be negative, and the absolute value of the difference may be equal to or less than the reference value. Therefore, the measurement circuit 920 may determine that an open circuit occurs in the third conductive segment CSG13.

[0117] When the fourth open circuit OP4 appears in the fourth conductive segment CSG14 of the detection structure DS, the first number CLK1# of the first clock signal CLK1 has a first count value CV41, the second number CLK2# of the second clock signal CLK2 has a second count value CV42, the first period Ta has a first value T41, and the second period Tb has a second value T42. Figure 8 As described above, the first value T41 may be greater than the second value T42, the sign of the difference between the first count value CV41 and the second count value CV42 may be negative, and the absolute value of the difference may be greater than the reference value. Therefore, the measurement circuit 920 may determine that an open circuit occurs in the fourth conductive segment CSG14.

[0118] Accordingly, the measurement circuit 920 may generate a first number CLK1# of the first clock signal CLK1 by counting the number of cycles of the first clock signal CLK1 during the reference time interval, and the first clock signal CLK1 may be generated by contacting the probe 921 of the measurement circuit 920 with the first end ET1 of the detection structure DS through the switch 910. In addition, the measurement circuit 920 may generate a second number CLK2# of the second clock signal CLK2 by counting the number of cycles of the second clock signal CLK2 during the reference time interval, and the second clock signal CLK2 may be generated by contacting the probe 921 of the measurement circuit 920 with the second end ET2 of the detection structure DS through the switch 910. In such an embodiment, the measurement circuit 920 may determine the location of the open circuit in the detection structure DS based on the difference between the first number CLK1# and the second number CLK2#, and the difference between the first period Ta of the first clock signal CLK1 and the second period Tb of the first clock signal CLK2.

[0119] Fig.10 is a perspective view of a three-dimensional (3D) detection structure according to an example embodiment.

[0120] refer to Fig.10 , the 3D detection structure DSa may include a single conductive loop. As described below, the semiconductor die may include a first conductive layer and a second conductive layer that may be disposed below the first conductive layer. The conductive layer may include a metal layer in which metal segments may be patterned and / or a polysilicon layer in which polysilicon segments may be patterned. The 3D detection structure DSa may be extended in the vertical direction Z by the first conductive layer and the second conductive layer.

[0121] The 3D detection structure DSa may include a plurality of top horizontal line segments HLT formed in a first conductive layer, a plurality of bottom horizontal line segments HLB formed in a second conductive layer, and a plurality of vertical line segments VL respectively connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the 3D detection structure DSa. The top horizontal line segments HLT, the bottom horizontal line segments HLB, and the vertical line segments VL may be alternately arranged along the 3D detection structure DSa, and may connect the first end ET1 and the second end ET2 in a ring shape to at least partially surround the central area of ​​the semiconductor die.

[0122] In example embodiments, one of the first terminal ET1 and the second terminal ET2 may be connected to a probe 921 of a measurement circuit 920 , and / or the first terminal ET1 and the second terminal ET2 may be sequentially connected to the probe 921 of the measurement circuit 920 through a switch 910 , and a clock signal CLK may be provided to the measurement circuit 920 .

[0123] Fig.11 , Fig.12 and Fig.13 is a cross-sectional view illustrating a vertical structure of a 3D detection structure according to example embodiments.

[0124] refer to Fig.11 , the semiconductor die may include a semiconductor substrate SUB and a dielectric layer in which an upper structure may be formed. The dielectric layer may include a plurality of conductive layers (e.g., a first metal layer ML1, a second metal layer ML2, a third metal layer ML3, a gate polysilicon layer PL1, and a bit line polysilicon layer PL2) in which conductive line patterns may be formed. The conductive layer may include one or more metal layers (e.g., a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3) and one or more polysilicon layers (e.g., a gate polysilicon layer PL1 and a line polysilicon layer PL2). The polysilicon layer may include a gate polysilicon layer PL1, in which a gate of a transistor in a semiconductor integrated circuit may be formed. If the semiconductor integrated circuit is a semiconductor memory device, the polysilicon layer may further include a bit line polysilicon layer PL2, in which a bit line in the semiconductor integrated circuit may be formed.

[0125] The 3D sensing structure DSa may include a plurality of top horizontal line segments HLT formed in the first metal layer ML1, a plurality of bottom horizontal line segments HLB formed in the bit line polysilicon layer PL2, and a plurality of vertical line segments VL respectively connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the 3D sensing structure DSb.

[0126] like Fig.11As shown, the first metal layer ML1 may correspond to the uppermost metal layer among the first metal layer ML1 to the third metal layer ML3 that may be formed over the semiconductor substrate SUB, and the bit line polysilicon layer PL2 may correspond to the bit line polysilicon layer that may be formed between the semiconductor substrate SUB and the first metal layer ML1 to the third metal layer ML3. The top horizontal line segment HLT may include a first metal line pattern MP1 that may be formed in the uppermost first metal layer ML1, and the bottom horizontal line segment HLB may include a polysilicon line pattern PP that may be formed in the bit line polysilicon layer PL2.

[0127] The vertical line segment VL may include vertical contacts (e.g., a first vertical contact VC1, a second vertical contact VC2, and a third vertical contact VC3) to provide electrical connection between the first metal line pattern MP1 in the topmost first metal layer ML1 and the polysilicon line pattern PP in the bit line polysilicon layer PL2. The vertical line segment VL may also include conductive line patterns (e.g., a second metal line pattern MP2 and a third metal line pattern MP3) in each intermediate conductive layer (e.g., a second metal layer ML2 and a third metal layer ML3). In some embodiments, the conductive line patterns in one or both of the intermediate conductive layers ML2 and ML3 may be omitted. For example, the second metal line pattern MP2 in the intermediate second metal layer ML2 may be omitted, and two vertical contacts (e.g., a first vertical contact VC1 and a second vertical contact VC2) may be combined into a longer vertical contact.

[0128] In the following, for the sake of brevity, references to Fig.11 Repeated description of the described 3D detection structure DSa.

[0129] refer to Fig.12 The 3D detection structure DSa may include a plurality of top horizontal line segments HLT formed in the first metal layer ML1, a plurality of bottom horizontal line segments HLB formed in the gate polysilicon layer PL1, and a plurality of vertical line segments VL respectively connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the 3D detection structure DSa.

[0130] like Fig.12 As shown, the first metal layer ML1 may correspond to the uppermost metal layer among the first to third metal layers ML1 to ML3 that may be formed over the semiconductor substrate SUB, and the gate polysilicon layer PL1 may correspond to the gate polysilicon layer that may be formed between the semiconductor substrate SUB and the first to third metal layers ML1 to ML3. The top horizontal line segment HLT may include a first metal line pattern MP1 that may be formed in the uppermost first metal layer ML1, and the bottom horizontal line segment HLB may include a polysilicon line pattern PP1 that may be formed in the gate polysilicon layer PL1.

[0131] refer to Fig.13 The 3D detection structure DSa may include a plurality of top horizontal line segments HLT that may be formed in the first metal layer ML1, a plurality of bottom horizontal line segments HLB that may be formed in the second conductive layer MLB, and a plurality of vertical line segments VL that respectively connect the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the 3D detection structure DSa.

[0132] like Fig.13 As shown, the first metal layer ML1 may correspond to the uppermost metal layer among the first to third metal layers ML1 to ML3 that may be formed over the semiconductor substrate SUB, and the bottom metal layer MLB corresponds to a metal layer that may be formed on the bottom surface of the semiconductor substrate SUB. The top horizontal line segment HLT may include a first metal line pattern MP1 formed in the uppermost first metal layer ML1, and the bottom horizontal line segment HLB may include a bottom metal line pattern MPB that may be formed in the bottom metal layer MLB on the bottom surface of the semiconductor substrate SUB.

[0133] As reference Fig.11 , Fig.12 and Fig.13 As described above, the 3D detection structure according to example embodiments may be extended to various depths in the vertical direction Z. When compared with a related semiconductor device, opens located at various positions may be detected more accurately using the 3D detection structure.

[0134] Fig.11 , Fig.12 and Fig.13 The 3D detection structure DSa can be applied to Figure 1B Detection structure DS1.

[0135] Fig.14 is a perspective view of a 3D crack detection structure according to an example embodiment.

[0136] refer to Fig.14 , the 3D detection structure DSb may include a first conductive loop LOOPa and a second conductive loop LOOPb. The semiconductor die may include a first conductive layer, a second conductive layer below the first conductive layer, and a third conductive layer below the second conductive layer. The conductive layer may include a metal layer in which a metal line segment may be patterned and / or a polysilicon layer in which a polysilicon line segment may be patterned. The first conductive loop LOOPa may be extended in a 3D shape along a vertical direction Z between the second conductive layer and the third conductive layer. The second conductive loop LOOPb may be formed in a two-dimensional (2D) shape in the first conductive layer.

[0137] The first conductive loop LOOPa may include a plurality of first top horizontal line segments HLT that may be formed in the second conductive layer, a plurality of bottom horizontal line segments HLB that may be formed in the third conductive layer, and a plurality of vertical line segments VL that respectively connect the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPa. The second conductive loop LOOPb may include a plurality of second top horizontal line segments HL that may be formed on the first conductive layer. The first top horizontal line segment HLT, the bottom horizontal line segment HLB, and the vertical line segment VL may be alternately arranged along the first conductive loop LOOPa, and connect the first end ET11 and the second end ET12 in a ring shape to at least partially surround the center area of ​​the semiconductor die. The second top horizontal line segment HL may connect the first end ET21 and the second end ET222 in a ring shape to at least partially surround the center area of ​​the semiconductor die.

[0138] In an example embodiment, at least one of the first terminal ET11 and the second terminal ET12 may be connected to the probe 921 of the measurement circuit 920 through the switch 910. Alternatively or additionally, the first terminal ET11 and the second terminal ET12 may be sequentially connected to the probe 921 of the measurement circuit 920 through the switch 910. A clock signal may be provided to the measurement circuit 920. The measurement circuit 920 may determine the position of the open circuit in the first conductive loop LOOPa based on the cycle of the clock signal and the number of cycles of the clock signal counted during the reference time interval. In addition, at least one of the first terminal ET21 and the second terminal ET22 may be connected to the probe 921 of the measurement circuit 920 through the switch 910. Alternatively or additionally, the first terminal ET21 and the second terminal ET22 may be sequentially connected to the probe 921 of the measurement circuit 920 through the switch 910. A clock signal may be provided to the measurement circuit 920. The measurement circuit 920 determines the position of the open circuit in the second conductive loop LOOPb based on the cycle of the clock signal and the number of cycles of the clock signal counted during the reference time interval.

[0139] Fig.15 and Fig.16 is a cross-sectional view showing a vertical structure of a 3D detection structure according to an example embodiment. Figures 10 to 14 Repeated description of the 3D detection structure described.

[0140] refer to Fig.15The first conductive loop LOOPa may include a plurality of first top horizontal line segments HLT that may be formed in the second metal layer ML2, a plurality of bottom horizontal line segments HLB that may be formed in the third conductive layer PL2, and a plurality of vertical line segments VL that respectively connect the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPa. The second conductive loop LOOPb may include a plurality of second top horizontal line segments HL that may be formed in the first metal layer ML1 above the second metal layer ML2.

[0141] exist Fig.15 In an embodiment of the present invention, the first metal layer ML1 may correspond to the uppermost metal layer among the first to third metal layers ML1 to ML3 formed above the semiconductor substrate SUB, and the second metal layer ML2 may be a metal layer below the uppermost first metal layer ML1, and the third conductive layer PL2 may correspond to a bit line polysilicon layer that may be formed between the semiconductor substrate SUB and the first to third metal layers ML1 to ML3. The first top horizontal line segment HLT may include a second metal line pattern MP2 that may be formed in the second metal layer ML2, and the bottom horizontal line segment HLB may include a polysilicon line pattern PP that may be formed in the bit line polysilicon layer PL2. The second top horizontal line segment HL may include a first metal line pattern MP1 that may be formed in the first metal layer ML1.

[0142] refer to Fig.16 The first conductive loop LOOPa may include a plurality of first top horizontal line segments HLT that may be formed in the second metal layer ML2, a plurality of bottom horizontal line segments HLB that may be formed in the third conductive layer PL1, and a plurality of vertical line segments VL that respectively connect the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPa. The second conductive loop LOOPb may include a plurality of second top horizontal line segments HL that are formed in the first metal layer ML1 above the second metal layer ML2.

[0143] like Fig.16As shown, the first metal layer ML1 may correspond to the uppermost metal layer among the first metal layer ML1 to the third metal layer ML3 that may be formed above the semiconductor substrate SUB, and the second metal layer ML2 may be a metal layer below the uppermost first metal layer ML1, and the third conductive layer PL1 may correspond to a gate polysilicon layer that may be formed between the semiconductor substrate SUB and the first metal layer ML1 to the third metal layer ML3. The first top horizontal line segment HLT may include a second metal line pattern MP2 that may be formed in the second metal layer ML2, and the bottom horizontal line segment HLB may include a polysilicon line pattern PP1 that may be formed in the gate polysilicon layer PL1. The second top horizontal line segment HL may include a first metal line pattern MP1 that may be formed in the first metal layer ML1.

[0144] As reference Fig.15 and Fig.16 As described above, the 3D detection structure according to example embodiments may be extended to various depths in the vertical direction Z. When compared with a related semiconductor device, opens located at various positions may be detected more accurately using the 3D detection structure.

[0145] Fig.14 , Fig.15 and Fig.16 The 3D detection structure DSb can be applied to the reference Figure 1B Described detection structure DS1.

[0146] Fig.17 is a perspective view of a 3D detection structure according to example embodiments.

[0147] refer to Fig.17 , the 3D detection structure DSc may include a first conductive loop LOOPc and a second conductive loop LOOPd. The semiconductor die may include a first conductive layer, a second conductive layer below the first conductive layer, and a third conductive layer below the second conductive layer. The conductive layer may include a metal layer in which a metal line segment may be patterned and / or a polysilicon layer in which a polysilicon line segment may be patterned. The first conductive loop LOOPc may be extended in a 3D shape along a vertical direction Z between the second conductive layer and the third conductive layer. The second conductive loop LOOPd may be formed in a 2D shape in the first conductive layer.

[0148] The first conductive loop LOOPc may include a plurality of first top horizontal line segments HLT that may be formed in the second conductive layer, a plurality of bottom horizontal line segments HLB that may be formed in the third conductive layer, and a plurality of vertical line segments VL that respectively connect the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPc. The second conductive loop LOOPd may include a plurality of second top horizontal line segments HL that may be formed on the first conductive layer. The first top horizontal line segments HLT, the bottom horizontal line segments HLB, and the vertical line segments VL may be alternately arranged along the first conductive loop LOOPc, and connect the first end ET1 and the second end ET12 in a ring shape to at least partially surround the central area of ​​the semiconductor die. Fig.17 As shown, the third node N3 and the fourth node N4 of the first conductive loop LOOPc may be connected to the first node N1 and the second node N2 of the second conductive loop LOOPd, respectively, so that the first conductive loop LOOPc and the second conductive loop LOOPd may form a combined conductive loop.

[0149] In example embodiments, at least one of the first terminal ET1 and the second terminal ET2 may be connected to the probe 921 of the measurement circuit 920, and / or the first terminal ET1 and the second terminal ET2 may be sequentially connected to the probe 921 of the measurement circuit 920 through the switch 910. The clock signal CLK may be provided to the measurement circuit 920.

[0150] Fig.17 The description of the 3D detection structure DSc can be adapted to reference Figure 1B Described detection structure DS1.

[0151] Fig.18 is a block diagram illustrating a semiconductor device according to example embodiments.

[0152] In some embodiments, reference Fig.18 The described semiconductor device 100 may correspond to a nonvolatile memory device. However, the present disclosure is not limited thereto, and the semiconductor device 100 may be and / or may include other types of devices without departing from the scope of the present disclosure.

[0153] refer to Fig.18 The nonvolatile memory device 100 may include a memory cell array 200 and a peripheral circuit 300. The peripheral circuit 300 may include a page buffer circuit 310, a data input / output (I / O) circuit 320, a control circuit 350, a voltage generator 340, and an address decoder 330.

[0154] The memory cell array 200 may be coupled to the address decoder 330 through a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL.

[0155] The memory cell array 200 may be coupled to the page buffer circuit 310 through a plurality of bit lines BL. The memory cell array 200 may include a plurality of nonvolatile memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL.

[0156] The memory cell array 200 may include a plurality of memory blocks (e.g., a first memory block BLK1 to a zth memory block BLKz, where z is a positive integer greater than or equal to two (2)). Each of the plurality of memory blocks may have a 3D structure. The memory cell array 200 may include a plurality of (vertical) cell strings (e.g., NAND strings), and each cell string may include a plurality of memory cells stacked on each other.

[0157] The control circuit 350 may receive a command CMD, an address ADDR, and a control signal CTRL from an external memory controller, and may control, for example, an erase cycle, a program cycle, and a read operation of the semiconductor device 100. A program cycle may include a program operation and a program verification operation, and an erase cycle may include an erase operation and an erase verification operation.

[0158] In an example embodiment, the control circuit 350 may generate a control signal CTL that may be used to control the voltage generator 340 based on the command CMD, may generate a page buffer control signal PCTL for controlling the page buffer circuit 310, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit 350 may provide the row address R_ADDR to the address decoder 330, may provide the column address C_ADDR to the data I / O circuit 320, may provide the control signal CTL to the voltage generator 340, and may provide the page buffer control signal PCTL to the page buffer circuit 310.

[0159] The address decoder 330 may be coupled to the memory cell array 200 through the string selection line SSL, the plurality of word lines WL, and the ground selection line GSL. During a program operation or a read operation, the address decoder 330 may determine one of the plurality of word lines WL as a selected word line based on the row address R_ADDR, and may determine the remaining word lines of the plurality of word lines WL except the selected word line as unselected word lines.

[0160] The voltage generator 340 may generate a word line voltage VWL associated with the operation of the nonvolatile memory device 100 using an external voltage EVC that may be provided from a memory controller based on a control signal CTL from the control circuit 350. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 330.

[0161] For example, during an erase operation, the voltage generator 340 may apply an erase voltage to the well of the selected memory block, and may apply a ground voltage to all word lines of the selected memory block. During an erase verification operation, the voltage generator 340 may apply an erase verification voltage to all word lines of the selected memory block, and / or may apply an erase verification voltage to the word lines of the selected memory block on a word line by word line basis.

[0162] As another example, during a program operation, the voltage generator 340 may apply a program voltage to a selected word line and may apply a program pass voltage to unselected word lines. As another example, during a program verification operation, the voltage generator 340 may apply a program verification voltage to a selected word line and may apply a verification pass voltage to unselected word lines. As another example, during a read operation, the voltage generator 340 may apply a read voltage to a selected word line and may apply a read pass voltage to unselected word lines.

[0163] The page buffer circuit 310 may be coupled to the memory cell array 200 through a plurality of bit lines BL. The page buffer circuit 310 may include a plurality of page buffers. The page buffer circuit 310 may temporarily store data to be programmed in a selected page and / or data read out from a selected page of the memory cell array 200.

[0164] In an example embodiment, the page buffer units included in each of the plurality of page buffers PB (and the cache latches included in each of the plurality of page buffers PB) may be spaced apart from each other and may have separate structures. Accordingly, the degree of freedom of wiring on the page buffer units may be increased, and the complexity of the layout may be reduced. In addition, since the cache latch is adjacent to the data I / O line, the distance between the cache latch and the data I / O line may be reduced, thereby increasing the data I / O speed.

[0165] The data I / O circuit 320 may be coupled to the page buffer circuit 410 through a plurality of data lines DL. During a program operation, the data I / O circuit 320 may receive program data DATA from the memory controller and may provide the program data DATA to the page buffer circuit 310 based on the column address C_ADDR received from the control circuit 450. During a read operation, the data I / O circuit 320 may provide read data DATA to the memory controller based on the column address C_ADDR received from the control circuit 350.

[0166] Fig.19 Schematically illustrates a Fig.18 The structure of a non-volatile memory device.

[0167] refer to Fig.19 , the nonvolatile memory device 100 may include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 in the vertical direction Z. The second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in the vertical direction Z, and accordingly, the second semiconductor layer L2 may be close to the substrate. For example, between the first semiconductor layer L1 and the second semiconductor layer L2, the second semiconductor layer L2 may be disposed closer to the substrate.

[0168] In an example embodiment, Fig.18 The memory cell array 200 in the embodiment may be formed (or disposed) on the first semiconductor layer L1, and Fig.18 The peripheral circuit 300 in the embodiment may be formed (or disposed) on the second semiconductor layer L2.

[0169] Accordingly, the nonvolatile memory device 100 may have a structure in which the memory cell array 200 is disposed on the peripheral circuit 300. That is, the nonvolatile memory device 100 may have a cell on periphery (COP) structure. When compared with related semiconductor devices, the COP structure can effectively reduce the area in the horizontal direction and increase the integration of the nonvolatile memory device 100.

[0170] In example embodiments, the second semiconductor layer L2 may include a substrate, and a peripheral circuit 300 may be formed in the second semiconductor layer L2 by forming a transistor and a metal pattern for wiring the transistor on the substrate. After the peripheral circuit 300 is formed on the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 200 may be formed, and a metal pattern for connecting the word line WL and the bit line BL of the memory cell array 200 to the peripheral circuit 300 formed in the second semiconductor layer L2 may be formed. For example, the word line WL may extend in the first direction X, and the bit line BL may extend in the second direction Y.

[0171] Fig. 20 is a diagram showing a method according to an example embodiment Fig.18 A block diagram of an example of a memory cell array in FIG.

[0172] refer to Fig. 20 , the memory cell array 200 may include a plurality of memory blocks (eg, first to z-th memory blocks BLK1 to BLKz) that may extend in a plurality of directions including a first direction X, a second direction Y, and a vertical direction. In an embodiment, the plurality of memory blocks BLK1 to BLKz may be formed by Fig.18 For example, the address decoder 330 may select a memory block BLK corresponding to the block address from among a plurality of memory blocks BLK1 to BLKz.

[0173] Fig.21 is a diagram showing a method according to an example embodiment Fig. 20 Circuit diagram of one of the memory blocks.

[0174] Fig.21 The memory block BLKi may be formed in a 3D structure (or a vertical structure) on a substrate SUB. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a vertical direction VD substantially perpendicular to the substrate SUB. The memory block BLKi may correspond to any one of the plurality of memory blocks BLK1 to BLKz.

[0175] refer to Fig.21 , the memory block BLKi may include cell strings (or NAND strings) NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. Fig.21 As shown, each of the cell strings NS11 to NS33 is shown to include eight memory cells MC1 to MC8. However, the embodiments of the present disclosure are not limited thereto. For example, in some example embodiments, each of the cell strings NS11 to NS33 may include any number of memory cells.

[0176] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8, respectively. A ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0177] Word lines (eg, WL1 ) having substantially similar and / or identical heights may be commonly connected, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated.

[0178] Fig. 22 is a layout diagram of a nonvolatile memory device according to example embodiments. Fig.23 is along the lines of an exemplary embodiment Fig. 22 A cross-sectional view taken along line II'.

[0179] refer to Fig. 22 , the nonvolatile memory device 100 may include a peripheral logic structure PS, a horizontal conductive substrate USB, and an electrode structure ST. The peripheral logic structure PS may correspond to Fig.19 The second semiconductor layer L2 in the stacked structure ST may correspond to Fig.19 The stacked structure ST may include a cell array region CR and a cell extension region CER.

[0180] A memory cell array including a plurality of memory cells (eg, Fig.18 The memory cell array 200 in FIG. 2 may be formed in the cell array region CR. In example embodiments, a vertical structure VS and a bit line BL may be formed in the cell array region CR.

[0181] The cell extension region CER may be around the cell array region CR. In example embodiments, the cell array region CR and the cell extension region CER may extend in a direction in which the word line cutting region WLC extends. In example embodiments, the cell array region CR and the cell extension region CER may extend in a first direction X. A plurality of electrode pads EP1 to EP8 may be stacked in a stepwise manner in the cell extension region CER.

[0182] The electrode structure ST may include memory blocks (eg, memory blocks BLK1 to BLKz) separated by the word line cutting region WLC.

[0183] In an example embodiment, if Fig. 22 As shown, the cell extension region CER may be on one side of the cell array region CR. In example embodiments, the cell extension region CER may be disposed on both sides of the cell array region CR with the cell array region CR interposed therebetween.

[0184] In example embodiments, a single electrode structure ST may be on the peripheral logic structure PS. In example embodiments, two or more electrode structures ST may be on the peripheral logic structure PS.

[0185] The first through-electrode region THV_R1 may be defined by the peripheral logic structure PS, which may not overlap with the horizontal conductive substrate USB in the vertical direction Z. The first through-electrode region THV_R1 may extend in the second direction Y.

[0186] The second through-electrode region THV_R2 may be defined by the electrode structure ST. In example embodiments, the second through-electrode region THV_R2 may be referred to as a region extending in the first direction X. In example embodiments, the second through-electrode region THV_R2 may be designated only in the cell array region CR and not defined in the cell extension region CER. In example embodiments, the second through-electrode region THV_R2 may be defined in all memory blocks BLK1 to BLKz.

[0187] The board contact plug region PCC_R may be defined on the horizontal conductive substrate USB which may not overlap the electrode structure ST. The board contact plug region PCC_R may extend along the second direction Y. The board contact plug region PCC_R may be defined closer to the electrode structure ST than the first through-electrode region THV_R1 .

[0188] The first through-electrode region THV_R1 and the second through-electrode region THV_R2 may be regions in which through-electrodes (eg, Fig.23 The board contact plug region PCC_R may be a region where a board contact plug (eg, Fig.23 The area of ​​the first board contact plug PCC1). Fig.23 The first through-electrode region THV_R1 and the second through-electrode region THV_R2 are described.

[0189] refer to Fig. 22 and Fig.23 , the nonvolatile memory device 100 may include a peripheral logic structure PS and a cell array structure CS.

[0190] The peripheral logic structure PS may include a pass transistor PTR, a lower connection wiring body PW, and a peripheral logic insulating film 110. The pass transistor PTR may be on the substrate 101. The pass transistor PTR may be included in Fig.18 The page buffer circuit 310 in, or may be included in Fig.18 In the address decoder 330.

[0191] The substrate 101 may be and / or may include bulk silicon and / or silicon on insulator (SOI). In example embodiments, the substrate 101 may be and / or may include a silicon substrate, and / or may include another material. A peripheral logic insulating film 110 may be formed on the substrate 101. The peripheral logic insulating film 110 may include, but is not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a low dielectric constant material.

[0192] The lower connection wiring body PW may be in the peripheral logic insulating film 110. The lower connection wiring body PW may be connected to the pass transistor PTR.

[0193] The cell array structure CS may include a horizontal conductive substrate USB on the peripheral logic structure PS, and an electrode structure ST on the horizontal conductive substrate USB.

[0194] The horizontal conductive substrate USB may be on the peripheral logic structure PS. The horizontal conductive substrate USB may include a first opening OP11. The first opening OP11 may expose a portion of the peripheral logic structure PS and / or open a portion of the peripheral logic structure PS.

[0195] The horizontal conductive substrate USB may be a common source plate. In an example embodiment, the horizontal conductive substrate USB may serve as Fig.21 The horizontal conductive substrate USB may include, but is not limited to, a conductive semiconductor film, a metal silicide film and / or a metal film.

[0196] In example embodiments, the horizontal conductive substrate USB may be formed in a plurality of layers or in a single layer.

[0197] The filling insulating film 148 may be on the peripheral logic structure PS. The filling insulating film 148 may fill the first opening OP1. The electrode structure ST may be on the horizontal conductive substrate USB. The electrode structure ST may cover a portion of the horizontal conductive substrate USB. In example embodiments, the horizontal conductive substrate USB may include a first region and a second region, the first region may at least partially overlap with the electrode structure ST in the vertical direction Z, and the second region may not overlap with the electrode structure ST in the vertical direction Z. The second region of the horizontal conductive substrate USB may include Fig. 22 The board contact plug region PCC_R in the.

[0198] The electrode structure ST may include a plurality of electrode pads (e.g., a first electrode pad EP1, a second electrode pad EP2, a third electrode pad EP3, a fourth electrode pad EP4, a fifth electrode pad EP5, a sixth electrode pad EP6, a seventh electrode pad EP7, and an eighth electrode pad EP8) stacked in a vertical direction Z. The electrode structure ST may include an inter-electrode insulating film ILD between the plurality of electrode pads EP1 to EP8.

[0199] The electrode structure ST may include an insulating mold portion IMS. The insulating mold portion IMS may at least partially overlap the first opening OP1 of the horizontal conductive substrate USB in the vertical direction Z. The insulating mold portion IMS may include Fig. 22 The second through-electrode region THV_R2 in the insulating mold portion IMS may include an inter-electrode insulating film ILD and a sacrificial mold insulating film ILD_SC having an etching selection ratio. The inter-electrode insulating film ILD and the sacrificial mold insulating film ILD_SC may be alternately stacked. For example, the inter-electrode insulating film ILD may include silicon oxide (SiO), and the sacrificial mold insulating film ILD_SC may include silicon nitride (SiN).

[0200] The word line cutting region WLC may be disposed in the electrode structure ST. The word line cutting region WLC may extend in the first direction X. Each word line cutting region WLC may be spaced apart from each other in the second direction Y. Each word line cutting region WLC may completely cut the electrode structure ST. The electrode structure ST cut by two adjacent word line cutting regions WLC may form one of the memory blocks BLK1 to BLKz.

[0201] A plurality of vertical structures VS may be on the horizontal conductive substrate USB. A plurality of vertical structures VS may at least partially penetrate the electrode structure ST. A plurality of vertical structures VS may be electrically connected to the horizontal conductive substrate USB. The vertical structure VS may include a sidewall portion that may extend in the vertical direction Z, and a bottom portion to which the sidewall portion of the vertical structure VS may be connected. The sidewall portion of the vertical structure VS may have a tubular shape (e.g., a cylindrical shape or a macaroni shape) having a hollow space therein.

[0202] The first interlayer insulating film 142 may be on the peripheral logic structure PS. The first interlayer insulating film 142 may at least partially cover the electrode structure ST and the horizontal conductive substrate USB. The second interlayer insulating film 144 and the third interlayer insulating film 146 may be sequentially formed on the first interlayer insulating film 142. A portion of the word line cutting region WLC may extend to the second interlayer insulating film 144.

[0203] The bit line BL may be on the stack structure ST. The bit line BL may extend in the second direction Y. The bit line BL may be electrically connected to at least one of the plurality of vertical structures VS.

[0204] The bit line BL may be on the third interlayer insulating film 146. The bit line BL may be electrically connected to the vertical structure VS via the bit line pad BL_PAD and the bit line plug BL_PG. The bit line BL, the bit line pad BL_PAD, and the bit line plug BLPG may each include a conductive material.

[0205] The plurality of electrode plugs WL_PG may be in the first to third interlayer insulating films (eg, the first to third interlayer insulating films 142 , 144 , and 146 ). The plurality of electrode plugs WL_PG may be in the cell extension region CER.

[0206] Each electrode plug WL_PG may be electrically connected to the corresponding electrode pad EP1 to EP8. The corresponding electrode plug WL_PG may connect the corresponding electrode pad EP1 to EP8 and the word line connection wiring WL_CW.

[0207] The first through-electrode THV1 may be in the first through-electrode region THV_R1. The first through-electrode THV1 may extend in the vertical direction Z. The first through-electrode THV1 may be in the first to third interlayer insulating films 142 to 146 and the peripheral logic insulating film 110. The first through-electrode THV1 may not completely penetrate the electrode structure ST. The first through-electrode THV1 may be connected to the lower connection wiring body PW and the first through-electrode connection wiring THV1_CW.

[0208] The first plate contact plug PCC1 may be in the plate contact plug region PCC_R. The first plate contact plug PCC1 may extend in the vertical direction Z. The first plate contact plug PCC1 may be in the first to third interlayer insulating films 142 to 146. The first plate contact plug PCC1 may not completely penetrate the stack structure ST.

[0209] The first board contact plug PCC1 may be connected to the horizontal conductive substrate USB. The first board contact plug PCC1 may be electrically connected to the horizontal conductive substrate USB in the second region of the horizontal conductive substrate USB. The first board contact plug PCC1 may be connected to the first board contact connection wiring PCC1_CW. A portion of the first board contact plug PCC1 may be in the horizontal conductive substrate USB.

[0210] The second through-electrode THV2 may be in the second through-electrode region THV_R2. The second through-electrode THV2 may extend in the vertical direction Z. The second through-electrode THV2 may be in the insulating mold portion IMS, the filling insulating film 148, and the peripheral logic insulating film 110. The second through-electrode THV2 may at least partially penetrate the stacked structure ST (e.g., the insulating mold portion IMS). The second through-electrode THV2 may be in the cell array region CR. The second through-electrode THV2 may pass through the first opening OP1. The second through-electrode THV2 may be connected to the lower connection wiring body PW and the second through-electrode connection wiring THV2_CW.

[0211] Fig.24 2 is a diagram for describing a manufacturing process of a stacked semiconductor device according to example embodiments.

[0212] refer to Fig.24 , various integrated circuits may be formed in the first wafer WF1 and the second wafer WF2. The same circuits may be integrated in the first wafer WF1 and the second wafer WF2, and / or different circuits may be integrated in the first wafer WF1 and the second wafer WF2. For example, a memory cell array may be formed in the first wafer WF1, and other circuits may be formed in the second wafer WF2. Although Fig.24A vertical stack of two wafers WF1 and WF2 is shown (eg, a first wafer WF1 stacked on a second wafer WF2), but three or more wafers may be vertically stacked.

[0213] After forming integrated circuits in the first wafer WF1 and the second wafer WF2, the first wafer WF1 and the second wafer WF2 may be bonded. The bonded first wafer WF1 and the second wafer WF2 may be cut and divided into a plurality of chips, wherein each chip corresponds to a semiconductor device 1003 including a vertically stacked first semiconductor die SD1 and a second semiconductor die SD2 (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2). Each cut portion of the first wafer WF1 may correspond to the first semiconductor die SD1, and each cut portion of the second wafer WF2 may correspond to the second semiconductor die SD2.

[0214] According to example embodiments, the semiconductor device 1003 may include a first semiconductor die SD1 and a second semiconductor die SD2 that may be stacked in a vertical direction. Each of the first semiconductor die SD1 and the second semiconductor die SD2 may include a central region and an outer region at least partially surrounding the central region. The semiconductor integrated circuit may be formed in the central region of the first semiconductor die SD1. The 3D detection structure may be formed in the outer regions of the first semiconductor die SD1 and the second semiconductor die SD2. In some example embodiments, as described above, the 3D detection structure may include a single conductive loop, and / or may include two conductive loops.

[0215] Fig.25 and Fig.26 is a cross-sectional view illustrating a vertical structure of a 3D detection structure according to example embodiments.

[0216] refer to Fig.25, the 3D detection structure DSd may be formed in the first semiconductor die SD1 and the second semiconductor die SD2. The memory cell structure may be formed in the first semiconductor die SD1, and the peripheral circuit may be formed in the second semiconductor die SD2. The second semiconductor die SD2 may include a semiconductor substrate SUB2 and a dielectric layer DLY2, in which an upper structure of the second semiconductor substrate SUB2 may be formed. The first semiconductor die SD1 and the second semiconductor die SD2 may include a plurality of conductive layers. For example, the first semiconductor die SD1 may include a first metal layer ML1, and the dielectric layer DLY2 may include a second metal layer ML2 and a second polysilicon layer PL2. The first metal layer ML1 and the second metal layer ML2 may be the topmost metal layers in the respective semiconductor dies SD1 and SD2. The second polysilicon layer PL2 may include a gate polysilicon layer, in which a gate of a transistor in a semiconductor integrated circuit may be formed.

[0217] The 3D detection structure DSd may include a plurality of top horizontal line segments HLT formed in a first conductive layer ML1 of a first semiconductor die SD1 (e.g., the topmost semiconductor die in a stacked structure), a plurality of lower horizontal line segments HLB formed in a second conductive layer PL2 of a second semiconductor die SD2 (e.g., the bottommost semiconductor die in the stacked structure), and a plurality of vertical line segments VL that respectively connect the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the 3D detection structure DSd.

[0218] exist Fig.25 In an embodiment of the present invention, the first conductive layer ML1 may correspond to the uppermost metal layer among the metal layers of the first semiconductor die SD1, and the second conductive layer PL2 may correspond to the polysilicon layer of the second semiconductor die SD2. The top horizontal line segment HLT may include a first metal line pattern MP1 formed in the metal layer ML1 of the first semiconductor die SD1, and the bottom horizontal line segment HLB may include a polysilicon line pattern PP2 formed in the polysilicon layer PL2 of the second semiconductor die SD2.

[0219] The vertical line segment VL may include a first vertical contact portion VC1, a through substrate via TSV, and a second vertical contact portion VC2 to connect the metal line pattern MP1 in the first metal layer ML1 with the polysilicon line pattern PP in the polysilicon layer PL2. Fig.25 As shown, the vertical contact portion may include a through substrate via TSV at least partially penetrating the first semiconductor die SD1. The vertical line segment VL may also include a second conductive line pattern MP2 formed in the middle second metal layer ML2.

[0220] refer to Fig.26The 3D detection structure DSd may include a plurality of top horizontal line segments HLT that may be formed in a first conductive layer ML1 of a first semiconductor die SD1 (e.g., an uppermost semiconductor die in a stacked structure), a plurality of lower horizontal line segments HLB that may be formed in a second conductive layer MLB of a second semiconductor die SD2 (e.g., a lowermost semiconductor die in a stacked structure), and a plurality of vertical line segments VL that respectively connect the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the 3D detection structure DSd.

[0221] exist Fig.26 In an embodiment of the present invention, the first conductive layer ML1 may correspond to the uppermost metal layer among the metal layers of the first semiconductor die SD1, and the second conductive layer PL2 may correspond to the metal layer on the bottom surface of the second semiconductor die SD2. The top horizontal line segment HLT may include a metal line pattern MP1 that may be formed in the metal layer ML1 of the first semiconductor die SD1, and the bottom horizontal line segment HLB may include a bottom metal line pattern MPB formed in the bottom metal layer MLB on the bottom surface of the second semiconductor die SD2.

[0222] The vertical line segment VL may include a first vertical through-substrate via TSV1, a second vertical contact VC2, and a second through-substrate via TSV2 to connect the first metal line pattern MP1 in the first metal layer ML1 with the bottom metal line pattern MPB in the bottom metal layer MLB. Fig.30 As shown, the vertical contact may include first and second through substrate vias TSV1 and TSV2 respectively at least partially penetrating the first and second semiconductor dies SD1 and SD2. The vertical line segment VL may also include second conductor patterns MP2 and PP2 respectively formed in the middle conductive layers ML2 and PL2.

[0223] As reference Fig.25 and Fig.26 As described above, according to example embodiments, the 3D detection structure DSd may be extended to various depths in the vertical direction Z.

[0224] Fig. 27 is a diagram showing a method according to an example embodiment Figure 1A and Figure 1B A block diagram of an example of a semiconductor device in FIG.

[0225] refer to Fig. 27, the semiconductor device 500 may be a volatile memory device and may include a control logic circuit 510, an address register 520, a memory body control logic circuit 530, a refresh control circuit 700, a row address multiplexer 540, a column address latch 550, a row decoder 560, a column decoder 570, a memory cell array 610, a sense amplifier unit 585, an I / O selection circuit 590, an error correction code (ECC) engine 650, a clock buffer 625, a selection signal generator 235 and a data I / O buffer 620.

[0226] The memory cell array 610 may include first to sixteenth memory cell arrays 610a to 610s. The row decoder 560 may include first to sixteenth row decoders 560a to 560s respectively coupled to the first to sixteenth memory cell arrays 610a to 610s, the column decoder 570 may include first to sixteenth column decoders 570a to 570s respectively coupled to the first to sixteenth memory cell arrays 610a to 610s, and the sense amplifier unit 585 may include first to sixteenth sense amplifiers 585a to 585s respectively coupled to the first to sixteenth memory cell arrays 610a to 610s.

[0227] The first to sixteenth memory bank arrays 610a to 610s, the first to sixteenth row decoders 560a to 560s, the first to sixteenth column decoders 570a to 570s, and the first to sixteenth sense amplifiers 585a to 585s may form the first to sixteenth memory banks. Each of the first to sixteenth memory bank arrays 610a to 610s may include a plurality of memory cells MC that may be formed at intersections of a plurality of word lines WL and a plurality of bit lines BL.

[0228] The address register 520 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from an external memory controller. The address register 520 may provide the received bank address BANK_ADDR to the bank control logic 530, may provide the received row address ROW_ADDR to the row address multiplexer 540, and may provide the received column address COL_ADDR to the column address latch 550.

[0229] The bank control logic 530 may generate a bank control signal in response to the bank address BANK_ADDR, activate a row decoder corresponding to the bank address BANK_ADDR among the first row decoders 560a to the sixteenth row decoders 560h in response to the bank control signal, and activate a column decoder corresponding to the bank address BANK_ADDR among the first column decoders 570a to the sixteenth column decoders 570h in response to the bank control signal.

[0230] The row address multiplexer 540 may receive a row address ROW_ADDR from the address register 520 and may receive a refresh row address REF_ADDR from the refresh control circuit 700. The row address multiplexer 540 may selectively output the row address ROW_ADDR and / or the refresh row address REF_ADDR as the row address SRA. The row address SRA output from the row address multiplexer 540 may be applied to the first row decoder 560a to the sixteenth row decoder 560s.

[0231] The refresh control circuit 700 may sequentially increase and / or decrease the refresh row address REF_ADDR in the normal refresh mode under the control of the control logic circuit 510 .

[0232] One row decoder of the first row decoder 560a to the sixteenth row decoder 560s activated by the bank control logic circuit 530 may decode the row address SRA that may be output from the row address multiplexer 540, and may activate a word line corresponding to the row address SRA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address.

[0233] The column address latch 550 may receive the column address COL_ADDR from the address register 520 and may temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 550 may generate a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 550 may apply the temporarily stored or generated column address COL_ADDR' to the first column decoder 570a to the sixteenth column decoder 570s.

[0234] The activated one of the first to sixteenth column decoders 570 a to 570 s may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 590 .

[0235] The I / 0 selection circuit 590 may include a circuit for selecting I / 0 data, and may also include an input data masking logic circuit, a read data latch for storing data output from the first memory array 610a to the sixteenth memory array 610s, and a write driver for writing data to the first memory array 610a to the sixteenth memory array 610s.

[0236] The codeword CW that may be read from a selected one of the first to sixteenth memory bank arrays 610a to 610s may be sensed by a sense amplifier coupled to the selected memory bank array from which data is to be read, and may be stored in a read data latch of the I / O strobe circuit 290. After the ECC engine 650 performs ECC decoding on the codeword CW, the codeword CW stored in the read data latch may be provided as data DTA to the data I / O buffer 620. The data I / O buffer 620 may convert the data DTA into a data signal DQ, and may transmit the data signal DQ to the memory controller together with the data strobe signal DQS.

[0237] The data signal DQ to be written into the selected one of the first to sixteenth memory bank arrays 610a to 610s may be provided from the memory controller to the data I / O buffer 620. The data I / O buffer 620 may convert the data signal DQ into data DTA, and may provide the data DTA to the ECC engine 650. The ECC engine 650 may perform ECC encoding on the data DTA to generate parity bits, and the ECC engine 650 may provide a codeword CW including the data DTA and the parity bits to the I / O strobe circuit 590. The I / O strobe circuit 590 may write the codeword CW into a subpage in the selected one of the memory bank arrays through a write driver.

[0238] The data I / O buffer 620 can provide a data signal DQ from a storage controller to an ECC engine 650 by converting the data signal DQ into data DTA during a write operation of the semiconductor device 500, can convert the data DTA into a data signal DQ from the ECC engine 650, and can send the data signal DQ and a data selection signal DQS to the storage controller during a read operation of the semiconductor device 500.

[0239] Based on the second control signal CTL2 from the control logic circuit 510 , the ECC engine 650 may perform ECC encoding on the data DTA, and may perform ECC decoding on the codeword CW.

[0240] The clock buffer 525 may receive the clock signal CK, may generate an internal clock signal ICK by buffering the clock signal CK, and may provide the internal clock signal ICK to a circuit component processing a command CMD and an address ADDR.

[0241] The strobe signal generator 535 may receive the clock signal CK, may generate a data strobe signal DQS based on the clock signal CK, and may provide the data strobe signal DQS to the data I / O buffer 620 .

[0242] The control logic circuit 510 may control the operation of the semiconductor device 500. For example, the control logic circuit 510 may generate a control signal for the semiconductor device 500 so as to perform a write operation, a read operation, a normal refresh operation. The control logic circuit 510 may include a command decoder 511 that may decode a command CMD received from a memory controller and a mode register 512 that may set an operation mode of the semiconductor device 500.

[0243] For example, the command decoder 511 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 510 may provide a first control signal CTL1 to the I / O strobe circuit 590 and provide a second control signal CTL2 to the ECC engine 650.

[0244] Fig.28 According to an example embodiment, Fig. 27 An example of a first memory array in a semiconductor device.

[0245] refer to Fig.28 , the first memory bank array 610a may include a plurality of word lines WL0 to WLm-1 (where m is a positive integer greater than or equal to two (2)), a plurality of bit lines BL0 to BLn-1 (where n is a positive integer greater than or equal to two (2)), and a plurality of memory cells MC disposed at intersections between the word lines WL0 to WLm-1 and the bit lines BL0 to BLn-1. Each of the memory cells MC may include a cell transistor coupled to each of the word lines WL0 to WLm-1 and each of the bit lines BL0 to BLn-1, and a cell capacitor coupled to the cell transistor. Each of the memory cells MC may have a dynamic random access memory (DRAM) cell structure. Each of the word lines WL0 to WLm-1 may extend in a first direction X, and each of the bit lines BL1 to BLn-1 may extend in a second direction Y intersecting the first direction X.

[0246] Fig.29is a plan view illustrating a semiconductor device according to example embodiments. Fig.30 is a plan view illustrating a semiconductor device according to example embodiments. Fig.31 is along the lines of an exemplary embodiment Fig.30 A cross-sectional view taken along line III-III'.

[0247] refer to Fig.29 , a wafer WF for describing a manufacturing process of a semiconductor device according to an example embodiment is shown. A plurality of chip regions CPR and scribe lanes SL at least partially surrounding the chip regions CPR may be formed in the wafer WF. The wafer WF may be cut along the scribe lanes SL and may be divided into a plurality of dies.

[0248] Multiple wafers can be bonded to form multiple semiconductor devices. Fig.30 A target portion TG in the wafer WF is depicted.

[0249] Fig.30 is a method for describing a semiconductor device according to example embodiments Fig.29 A magnified view of the target part TG in FIG.

[0250] refer to Fig.30 , the semiconductor device 800 may include a chip region CPR, a scribe line SL along the edge of the chip region CPR, a detection structure 820, and a measurement circuit OSC 850 connected to the detection structure 820 through a switch SW. The measurement circuit OSC850 may be an oscilloscope circuit. The semiconductor device 800 may also include a dam-shaped region DM, which includes a dam-shaped structure 830 that may be arranged between the chip region CPR and the scribe line SL. The dam-shaped region DM may isolate the chip region CPR from the scribe line SL and may have a ring shape or a closed curve in a plan view. A dam-shaped structure 830 including at least one dam (e.g., a first dam-shaped 831 and a second dam-shaped 832) may be arranged in the dam-shaped region DM.

[0251] The chip region CPR may be a region in which elements operating on a chip may be formed. The chip region CPR may have a ring shape and / or a rectangular ring shape, but the present disclosure is not limited thereto.

[0252] The scribe lane SL at least partially surrounding the chip region CPR may be a region having a space margin in case of a damaged portion when cutting the wafer WF into chips. The scribe lane SL may have an annular shape and / or a rectangular annular shape that may correspond to the shape of the chip region CPR.

[0253] In the scribe lanes SL, various patterns for manufacturing monitoring and device testing, such as but not limited to a mark pattern and a key pattern, may be formed.

[0254] In an exemplary embodiment, a bonding metal (eg, Fig.31 A bonding metal pattern including a first bonding metal 861a and a second bonding metal 861b may be formed in the scribe lane SL. A detection structure 820 may be disposed in the scribe lane SL, and the bonding metal pattern may constitute the detection structure 820.

[0255] The chip area CPR can correspond to Figure 1A The central region CTREG in the SL can correspond to Figure 1A The detection structure 820 may be formed in a scribe line SL around the chip region CPR in the outer region. The detection structure 820 may include a first end ET1 and a second end ET2.

[0256] The semiconductor device 800 may have a chip-to-chip (C2C) structure in which a first chip CP1 is located on a second chip CP2. Fig.31 , a bonding surface BS is shown at which the first chip CP1 is coupled to the second chip CP2.

[0257] refer to Fig.31 , in the scribe lane SL, the first chip CP1 may include a first bonding metal pattern, and the second chip CP2 may include a second bonding metal pattern. The first chip CP1 and the second chip CP2 may be coupled to each other by bonding the first bonding metal and the second bonding metal to each other. When the first bonding metal 861a constituting the first bonding metal pattern and the second bonding metal 862a constituting the second bonding metal pattern are not properly connected to each other due to manufacturing problems and / or cracks, the electrical signal may not be transmitted to the detection structure 820 in the scribe lane SL, or an abnormality may occur in the electrical signal. Therefore, the measurement circuit OSC 850 can determine whether an open circuit occurs in the scribe lane SL based on the electrical signal in the detection structure 820.

[0258] Continue to refer Fig.31, the detection structure 820 disposed on the scribe line SL may include a first bonding metal 861a, a second bonding metal 862a, a first horizontal line 881a and a second horizontal line 882a, and a first contact plug 871a and a second contact plug 871b. The first horizontal line 881a and the second horizontal line 882a may be electrically connected to the measurement circuit OSC 850. The first contact plug 871a and the second contact plug 871b may connect the first horizontal line 881a and the second horizontal line 882a to the first bonding metal 861a and the second bonding metal 862a, respectively. At least one of the first horizontal line 881a and the second horizontal line 882a may be connected to a connection line structure extending from the chip region CPR to the scribe line SL for electrical connection with the first bonding metal 861a and the second bonding metal 862a. For example, at least one of the first horizontal line 881a and the second horizontal line 882a may at least partially penetrate the dam structure 830. At least one of the first horizontal line 881 a and the second horizontal line 882 a may be insulated from the dam structure 830 .

[0259] The dam-shaped structure 830 may be a region separating the chip region CPR and the scribe lane SL. The dam-shaped structure 830 may define the chip region CPR and the scribe lane SL by at least partially surrounding the chip region CPR. The dam-shaped structure 830 may separate the chip region CPR and the scribe lane SL by at least partially vertically penetrating the first chip CP1 and the second chip CP2. The dam-shaped structure 830 may prevent cracks occurring in the scribe lane SL from entering the chip region CPR. The dam-shaped structure 830 may prevent external moisture from entering the chip region CPR.

[0260] The dam structure 830 may include at least one dam. For example, the dam structure 830 may include an inner dam 831 and an outer dam 832. The inner dam 831 may at least partially surround the chip region CPR adjacent to the chip region CPR, and the outer dam 832 may at least partially surround the inner dam 831 adjacent to the scribe line. Each of the inner dam 831 and the outer dam 832 may have a shape corresponding to the shape of the chip region CPR.

[0261] The dam structure 830 may include a through electrode via (THV) through which the sensing structure 820 may pass. For example, each of the inner dam 831 and the outer dam 832 includes a THV. The inner dam 831 may include a first THV TH1, and the outer dam 832 may include a second THV TH2.

[0262] In the semiconductor device 800, at least one of the first terminal ET1 and the second terminal ET2 of the detection structure 820 may be connected to a probe of the measurement circuit OSC 850, and / or the first terminal ET1 and the second terminal ET2 may be sequentially connected to the probe of the measurement circuit OSC 850 through the switch SW, and the clock signal CLK may be provided to the measurement circuit OSC 850. The measurement circuit OSC850 may determine the position of the open circuit in the slice lane SL based on the cycle of the clock signal CLK and the number of cycles of the clock signal CLK during the reference time interval.

[0263] Fig.32 is a cross-sectional view of a semiconductor device according to example embodiments.

[0264] refer to Fig.32 , the semiconductor device 2000 may be a non-volatile memory device and may have a C2C structure. Hereinafter, the semiconductor device 2000 may be referred to as a non-volatile memory device. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell area or a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other. As used herein, a bonding process may include a method of electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding process may use Cu to Cu bonding. However, the present disclosure may not be limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W), and / or may include but is not limited to aluminum (Al) or tungsten (W).

[0265] Each of the peripheral circuit region PERI and the cell region CELL of the nonvolatile memory device 2000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0266] The peripheral circuit region PERI may include a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements (e.g., 2220a, 2220b, and 2220c) formed on the first substrate 2210, first metal layers (e.g., 2230a, 2230b, and 2230c) respectively connected to the plurality of circuit elements 2220a to 2220c, and second metal layers (e.g., 2240a, 2240b, and 2240c) formed on the first metal layers 2230a to 2230c. In example embodiments, the first metal layers 2230a to 2230c may be formed of tungsten (W) having a relatively high resistivity and / or may include tungsten (W) having a relatively high resistivity, and the second metal layers 2240a to 2240c may be formed of copper (Cu) having a relatively low resistivity and / or may include copper (Cu) having a relatively low resistivity.

[0267] exist Fig.32 In the illustrated example embodiment, although only the first metal layers 2230a to 2230c and the second metal layers 2240a to 2240c are illustrated and described, example embodiments are not limited thereto, and one or more additional metal layers may be further formed on the first metal layers 2230a to 2230c and / or the second metal layers 2240a to 2240c. At least a portion of the one or more additional metal layers formed on the second metal layers 2240a to 2240c may be formed of aluminum or the like having a lower resistivity than copper forming the second metal layers 2240a to 2240c.

[0268] The interlayer insulating layer 2215 may be disposed on the first substrate 2210 and at least partially cover the plurality of circuit elements 2220a to 2220c, the first metal layers 2230a to 2230c, and the second metal layers 2240a to 2240c. The interlayer insulating layer 2215 may include an insulating material such as, but not limited to, silicon oxide (SiO), silicon nitride (SiN), and the like.

[0269] The lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit area PERI may be electrically bonded to the upper bonding metals 2371b and 2372b of the cell area CELL. The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum (Al), copper (Cu), tungsten (W), etc., and / or may include aluminum (Al), copper (Cu), tungsten (W), etc. As used herein, the upper bonding metals 2371b and 2372b in the cell area CELL may be referred to as first metal pads, and the lower bonding metals 2271h and 2272b in the peripheral circuit area PERI may be referred to as second metal pads.

[0270] The cell region CELL may include at least one storage block. The cell region CELL may include a second substrate 2310 and a common source line 2320. On the second substrate 2310, a plurality of word lines (e.g., a first word line 2331, a second word line 2332, a third word line 2333, a fourth word line 2334, a fifth word line 2335, a sixth word line 2336, a seventh word line 2337, and an eighth word line 2338, hereinafter collectively referred to as "2330") may be stacked in a vertical direction Z (e.g., a Z-axis direction) perpendicular to the upper surface of the second substrate 2310. At least one string selection line and at least one ground selection line may be arranged above and below the plurality of word lines 2330, respectively, and the plurality of word lines 2330 may be arranged between at least one string selection line and at least one ground selection line.

[0271] In the bit line bonding area BLBA, the channel structure CH may extend in a third direction D3 perpendicular to the upper surface of the second substrate 2310, and pass through a plurality of word lines 2330, at least one string selection line, and at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In example embodiments, the bit line 2360c may extend in a second direction Y (e.g., a Y-axis direction) parallel to the upper surface of the second substrate 2310.

[0272] exist Fig.32In the illustrated example embodiment, the region in which the channel structure CH, the bit line 2360c, etc. are disposed may be referred to as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 2360c may be electrically connected to the circuit element 2220c providing the page buffer 2393 in the peripheral circuit region PERI. The bit line 2360c may be connected to the upper bonding metals 2371c and 2372c in the cell region CELL, and the upper bonding metals 2371c and 2372c may be connected to the lower bonding metals 2271c and 2272c, which are connected to the circuit element 2220c of the page buffer 2393.

[0273] In the word line bonding area WLBA, a plurality of word lines 2330 may extend in a first direction X (e.g., an X-axis direction) parallel to the upper surface of the second substrate 2310 and perpendicular to the second direction Y, and may be connected to a plurality of cell contact plugs (e.g., a first cell contact plug 2341, a second cell contact plug 2342, a third cell contact plug 2343, a fourth cell contact plug 2344, a fifth cell contact plug 2345, a sixth cell contact plug 2346, and a seventh cell contact plug 2347, hereinafter collectively referred to as "2340"). The plurality of word lines 2330 and the plurality of cell contact plugs 2340 may be connected to each other in a pad provided by at least a portion of the plurality of word lines 2330 extending in different lengths along the first direction X. The first metal layer 2350b and the second metal layer 2360b may be sequentially connected to upper portions of the plurality of cell contact plugs 2340 connected to the plurality of word lines 2330. In the word line bonding area WLBA, a plurality of cell contact plugs 2340 may be connected to the peripheral circuit area PERI through upper bonding metals 2371 b and 2372 b of the cell area CELL and lower bonding metals 2271 b and 2272 b of the peripheral circuit area PERI.

[0274] The plurality of cell contact plugs 2340 may be electrically connected to the circuit elements 2220b forming the row decoder 2394 in the peripheral circuit region PERI. In example embodiments, the operating voltage of the circuit elements 2220b forming the row decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. For example, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be greater than the operating voltage of the circuit elements 2220b forming the row decoder 2394.

[0275] The common source line contact plug 2380 may be disposed in the external pad bonding area PA. The common source line contact plug 2380 may be formed of a conductive material such as, but not limited to, a metal, a metal compound, polysilicon, etc., and may be electrically connected to the common source line 2320. The first metal layer 2350a and the second metal layer 2360a may be sequentially stacked on the upper portion of the common source line contact plug 2380. For example, the region in which the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be referred to as the external pad bonding area PA.

[0276] Input / output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating film 2201 at least partially covering the lower surface of the first substrate 2210 may be formed below the first substrate 2210, and the first I / O pad 2205 may be formed on the lower insulating film 2201. The first I / O pad 2205 may be connected to at least one of the plurality of circuit elements 2220a to 2220c disposed in the peripheral circuit region PERI through the first I / O contact plug 2203, and may be separated from the first substrate 2210 by the lower insulating film 2201. In addition, a side insulating film may be disposed between the first I / O contact plug 2203 and the first substrate 2210 to electrically separate the first I / O contact plug 2203 and the first substrate 2210.

[0277] An upper insulating layer 2301 at least partially covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and a second I / O pad 2305 may be disposed on the upper insulating layer 2301. The second I / O pad 2305 may be connected to at least one of a plurality of circuit elements 2220a to 2220c disposed in the peripheral circuit region PERI through a second I / O contact plug 2303 and / or lower bonding metals 2271a and 2272, etc. In example embodiments, the second I / O pad 2305 may be electrically connected to the circuit element 2220a.

[0278] According to example embodiments, the second substrate 2310 and the common source line 2320 may not be disposed in a region in which the second I / O contact plug 2303 is disposed. Alternatively or additionally, the second I / O pad 2305 may not overlap with the word line 2330 in the vertical direction Z. The second I / O contact plug 2303 may be separated from the second substrate 2310 in a direction parallel to an upper surface of the second substrate 2310, and may pass through an interlayer insulating layer 2315 of the cell region CELL to be connected to the second I / O pad 2305.

[0279] According to example embodiments, the first I / O pad 2205 and the second I / O pad 2305 may be selectively formed. For example, the nonvolatile memory device 2000 may include only the first I / O pad 2205 disposed on the first substrate 2210 or the second I / O pad 2305 disposed on the second substrate 2310. Alternatively or additionally, the memory device 2000 may include both the first I / O pad 2205 and the second I / O pad 2305.

[0280] In each of the external pad bonding area PA and the bit line bonding area BLBA respectively included in the cell area CELL and the peripheral circuit area PERI, a metal pattern provided in the uppermost metal layer may be provided as a dummy pattern, or the uppermost metal layer may not exist.

[0281] In the external pad bonding area PA, the nonvolatile memory device 2000 may include a lower metal pattern 2273a, which corresponds to the upper metal pattern 2372a formed in the uppermost metal layer of the cell area CELL, and has a cross-sectional shape substantially similar and / or the same as the upper metal pattern 2372a of the cell area CELL in the uppermost metal layer of the peripheral circuit area PERI so as to be connected to each other. In the peripheral circuit area PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to the contact portion. Similarly, in the external pad bonding area PA, an upper metal pattern 2372a may be formed in the uppermost metal layer of the cell area CELL, the upper metal pattern 2372a corresponding to the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit area PERI, and having a shape substantially similar and / or the same as the lower metal pattern 2273a of the peripheral circuit area PERI. The upper metal pattern 2372 a may be included in the upper bonding metals 2371 b and 2372 b .

[0282] The lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by Cu-to-Cu bonding.

[0283] In the bit line bonding area BLBA, an upper metal pattern 2392 may be formed in the uppermost metal layer of the cell area CELL, the upper metal pattern 2392 corresponds to the lower metal pattern 2252 that may be formed in the uppermost metal layer of the peripheral circuit area PERI, and has a cross-sectional shape substantially similar and / or the same as the lower metal pattern 2252 of the peripheral circuit area PERI. No contact may be formed on the upper metal pattern 2392, which is formed in the uppermost metal layer of the cell area CELL. The lower metal pattern 2252 may be included in the lower bonding metals 2271b and 2272b.

[0284] In example embodiments, a reinforcement metal pattern corresponding to and having a substantially similar and / or identical cross-sectional shape to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI may be formed in an uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI. No contact may be formed on the reinforcement metal pattern.

[0285] A word line voltage may be applied to at least one memory block in the cell region CELL through the lower bonding metals 2271 b and 2272 b in the peripheral circuit region PERI and the upper bonding metals 2371 b and 2372 b of the cell region CELL.

[0286] Fig.33 is a diagram showing a method according to an example embodiment Fig.32 A plan view of a peripheral circuit region in a semiconductor device.

[0287] refer to Fig.33 The peripheral circuit area PERI may include: a row decoder area (for example, a first row decoder area RDR1, a second row decoder area RDR2, and a third row decoder area RDR3), which are arranged in the first direction X; a first page buffer driver area PBD1, a first page buffer area PGR1, a first internal peripheral circuit area IPER1, a second page buffer area PGR2, and a second page buffer driver area PBD2, which are arranged between the first row decoder area RDR1 and the second row decoder area RDR2 in the second direction Y; a third page buffer driver area PBD3, a third page buffer area PGR3, a second internal peripheral circuit area IPER2, a fourth page buffer area PGR4, and a fourth page buffer driver area PBD4, which are arranged between the second row decoder area RDR2 and the third row decoder area RDR3 and the pad area PDR in the second direction Y, and the pad area PDR is adjacent to the first row decoder area RDR1 to the third row decoder area RDR3 in the second direction Y.

[0288] The first and second page buffer regions PGR1 and PGR2 may be spaced apart from each other in the second direction Y, and the page buffer regions PGR3 and PGR4 may be spaced apart from each other in the second direction Y. The buffer regions PGR1 and PGR2 may be spaced apart from the page buffer regions PGR3 and PGR4 in the first direction X.

[0289] A row decoder may be provided in each of the first row decoder region RDR1 to the third row decoder region RDR3, a page buffer circuit including a plurality of page buffers may be provided in the first page buffer region PGR1 to the fourth page buffer region PGR4, a page buffer driver may be provided in each of the first page buffer driver region PBD1 to the fourth page buffer driver region PBD4, and a pump and selection circuit may be provided in each of the first internal peripheral circuit region IPER1 and the second internal peripheral circuit region IPER2.

[0290] The first to third row decoder regions RDR1 to RDR3, the first to fourth page buffer regions PGR1 to PGR4, the first to fourth page buffer driver regions PBD1 to PBD4, and the first to second internal peripheral circuit regions IPER1 and IPER2 may correspond to a central region of the peripheral circuit region PERI.

[0291] The first to fourth page buffer regions PGR1 to PGR4 may be referred to as a first sub-circuit region, a second sub-circuit region, a third sub-circuit region, and a fourth sub-circuit region, respectively.

[0292] The first to fourth page buffer regions PGR1 to PGR4 may be disposed at Fig.32 In the area corresponding to the bit line bonding area.

[0293] Fig.34 The arrangement according to the exemplary embodiment is shown in Fig.33 The detection structure in the peripheral circuit area.

[0294] refer to Fig.34 , the first detection structure DS1 may be formed to at least partially surround the first and second page buffer regions PGR1 and PGR2 in the central region, and may be connected to the first switch SWa disposed in the pad region PDR. The second detection structure DS2 may be formed to at least partially surround the third and fourth page buffer regions PGR3 and PGR4 in the central region, and may be connected to the second switch SWb disposed in the pad region PDR.

[0295] Each of the first switch SWa and the second switch SWb may be connected to Figure 1A and Figure 1B . Therefore, the measurement circuit 920 can measure the period of the first clock signal generated by contacting the probe of the measurement circuit 920 with the end of the first detection structure DS1 through the first switch SWa, and the position of the first open circuit in the first detection structure DS1 can be determined by counting the number of periods of the first clock signal during the reference time interval. Alternatively or additionally, the measurement circuit 920 can measure the period of the second clock signal generated by contacting the probe of the measurement circuit 920 with the end of the second detection structure DS2 through the second switch SWb, and the position of the second open circuit in the second detection structure DS2 can be determined by counting the number of periods of the second clock signal during the reference time interval.

[0296] Fig.35 According to an example embodiment, Fig.34 in the first detection structure.

[0297] refer to Fig.35 , the first detection structure DS1 may be provided in the following manner: at the edges of the page buffer region PGR1 (e.g., the first sub-circuit region) and the page buffer region PGR2 (e.g., the second sub-circuit region), the upper bonding metal 2371 of the cell region CELL is alternately connected to the upper metal layer 2360 above the upper bonding metal 2371 in the first direction X or the second direction Y, and at the edges of the page buffer region PGR1 (e.g., the first sub-circuit region) and the page buffer region PGR2 (e.g., the second sub-circuit region), the lower bonding metal 2271 of the peripheral circuit region PERI is alternately connected to the lower metal layer 2240 below the lower bonding metal 2271 in the first direction X or the second direction Y. The first detection structure DS1 may alternately cross the boundaries of the cell region CELL and the peripheral circuit region PERI, such as in a chain configuration. At least one of the first end and the second end of the first detection structure DS1 may be connected to Fig.34 The first switch SWa in.

[0298] The second detection structure DS2 may be provided in the following manner: at the edges of the page buffer region PGR3 (e.g., the third sub-circuit region) and the page buffer region PGR4 (e.g., the fourth sub-circuit region), the upper bonding metal 2371 of the cell region CELL is alternately connected to the upper metal layer 2360 above the upper bonding metal 2371 in the first direction X or the second direction Y, and at the edges of the page buffer region PGR3 (e.g., the third sub-circuit region) and the page buffer region PGR4 (e.g., the fourth sub-circuit region), the lower bonding metal 2271 of the peripheral circuit region PERI is alternately connected to the lower metal layer 2240 below the lower bonding metal 2271 in the first direction X or the second direction Y. The second detection structure DS2 may alternately cross the boundaries of the cell region CELL and the peripheral circuit region PERI, such as in a chain configuration. At least one of the first end and the second end of the second detection structure DS2 may be connected to Fig.34 The second switch SWb in.

[0299] Fig.36 is a cross-sectional view of a semiconductor device according to example embodiments.

[0300] refer to Fig.36 , the semiconductor device 5000 may be a non-volatile memory device. Hereinafter, the semiconductor device 5000 may be referred to as a memory device. The memory device 5000 may have a C2C structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PREG may be manufactured separately, and then the at least one upper chip and the lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may refer to a method of electrically and / or physically connecting a bonding metal pattern formed in the topmost metal layer of the upper chip to a bonding metal pattern formed in the topmost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be referred to as a Cu-Cu bonding method. Alternatively or additionally, the bonding metal pattern may be formed of aluminum (Al) and / or tungsten (W).

[0301] The memory device 5000 may include at least one upper chip including a cell region. Fig.36As shown, the memory device 5000 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 5000 includes two upper chips, a first upper chip including a first cell region CREG1, a second upper chip including a second cell region CREG2, and a lower chip including a peripheral circuit region PREG may be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 5000. The first upper chip may be flipped over and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped over and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip may be referenced based on the orientation of the chip before each of the first upper chip and the second upper chip is flipped over. That is, in Fig.36 In the embodiment, the upper portion of the lower chip may refer to the upper portion based on the +ZZ axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to the upper portion based on the -Z axis direction. However, the present disclosure is not limited thereto. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0302] The peripheral circuit region PREG and the first and second cell regions CREG1 and CREG2 of the memory device 5000 may be referred to as a first layer, a second layer, and a third layer, respectively, and the memory device 5000 may include M layers stacked in a vertical direction, where M is a positive integer greater than or equal to two (2).

[0303] According to an example embodiment, a detection structure may be provided in each of the M layers, and a measurement circuit may determine whether an open circuit occurs in each of the M layers and / or the entire M layers based on a clock signal. For example, the detection structure may include a conductive loop, and the conductive loop may include a bonding metal that connects a portion of a top horizontal line segment of an upper layer of an adjacent layer among the M layers with a portion of a bottom horizontal line segment of a lower layer of the adjacent layer.

[0304] Each of the peripheral circuit region PREG and the first and second cell regions CREG1 and CREG2 of the memory device 5000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0305] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements (e.g., 5220a, 5220b, and 5220c) formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more layer insulating layers may be disposed on the plurality of circuit elements 5220a to 5220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 5220a to 5220c may be disposed in the interlayer insulating layer 5215. For example, the plurality of metal lines may include a first metal line (e.g., 5230a, 5230b, and 5230c) connected to the plurality of circuit elements 5220a to 5220c and a second metal line (e.g., 5240a, 5240b, and 5240c) formed on the first metal line 5230a to 5230c. The plurality of metal lines may be formed of at least one conductive material among various conductive materials. For example, the first metal wires 5230a to 5230c may be formed of tungsten (W) having a relatively high resistivity, and the second metal wires 5240a to 5240c may be formed of copper (Cu) having a relatively low resistivity.

[0306] In the present embodiment, the first metal lines 5230a to 5230c and the second metal lines 5240a to 5240c are shown and described. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may also be formed on the second metal lines 5240a to 5240c. Alternatively or additionally, the second metal lines 5240a to 5240c may be formed of aluminum (Al), and at least some of the additional metal lines formed on the second metal lines 5240a to 5240c may be formed of copper (Cu) having a resistivity lower than the resistivity of the aluminum (Al) of the second metal lines 5240a to 5240c.

[0307] The interlayer insulating layer 5215 may be disposed on the first substrate 5210 and may include an insulating material such as, but not limited to, silicon oxide (SiO) and / or silicon nitride (SiN).

[0308] Each of the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. A plurality of word lines (e.g., a first word line 5331, a second word line 5332, a third word line 5333, a fourth word line 5334, a fifth word line 5335, a sixth word line 5336, a seventh word line 5337, and an eighth word line 5338, hereinafter collectively referred to as "5330") may be stacked on the second substrate 5310 in a direction perpendicular to the top surface of the second substrate 5310 (e.g., a Z-axis direction). String selection lines and ground selection lines may be disposed on and below the plurality of word lines 5330, and the plurality of word lines 5330 may be disposed between the string selection lines and the ground selection lines. Typically, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and a plurality of word lines (e.g., a first word line 5431, a second word line 5432, a third word line 5433, a fourth word line 5434, a fifth word line 5435, a sixth word line 5436, a seventh word line 5437, and an eighth word line 5438, hereinafter collectively referred to as "5430") may be stacked on the third substrate 5410 in a direction perpendicular to the top surface of the third substrate 5410 (e.g., a Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of various materials, and the various materials may include, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CREG1 and the second cell region CREG2.

[0309] In some embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 5310 to at least partially penetrate the word line 5330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 5350c and the second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH through the first metal line 5350c. The bit line 5360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 5310.

[0310] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming a lower channel LCH and a process of forming an upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 5310 to at least partially penetrate the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may at least partially penetrate the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 5000 according to the present embodiment may include channels having improved width uniformity due to the lower channel LCH and the upper channel UCH formed through processes performed sequentially.

[0311] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in area "A2", the word line near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, the second word line 5332 and the third word line 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, the data may not be stored in the memory cell connected to the dummy word line. Alternatively or additionally, the number of pages corresponding to the memory cell connected to the dummy word line may be less than the number of pages corresponding to the memory cell connected to the normal word line. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the normal word line, thereby reducing the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0312] At the same time, in region "A2", the number of lower word lines 5331 and 5332 penetrated by the lower channel LCH may be less than the number of upper word lines 5333 to 5338 penetrated by the upper channel UCH. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be greater than or equal to the number of upper word lines penetrated by the upper channel UCH. Alternatively or additionally, the structural features and connection relationships of the channel structure CH disposed in the second cell region CREG2 may be substantially similar and / or identical to the structural features and connection relationships of the channel structure CH disposed in the first cell region CREG1.

[0313] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell region CREG1, and the second through electrode THV2 may be disposed in the second cell region CREG2. Fig.36 As shown, the first through electrode THV1 may at least partially penetrate the common source line 5320 and the plurality of word lines 5330. In some embodiments, the first through electrode THV1 may also penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Alternatively or additionally, the first through electrode THV1 may include a conductive material at least partially surrounded by an insulating material. The second through electrode THV2 may have a substantially similar and / or identical shape and structure to the first through electrode THV1.

[0314] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 5372d and the second through metal pattern 5472d. The first through metal pattern 5372d may be formed at the bottom end of the first upper chip including the first unit region CREG1, and the second through metal pattern 5472d may be formed at the top end of the second upper chip including the second unit region CREG2. The first through electrode THV1 may be electrically connected to the first metal line 5350c and the second metal line 5360c. The lower via 5371d may be formed between the first through electrode THV1 and the first through metal pattern 5372d, and the upper via 5471d may be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d may be connected to each other by a bonding method.

[0315] In addition, in the bit line bonding area BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 5392 having a shape substantially similar and / or identical to that of the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell area CREG1. The upper metal pattern 5392 of the first cell area CREG1 and the upper metal pattern 5252 of the peripheral circuit area PREG may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 5360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some circuit elements 5220c of the peripheral circuit area PREG may constitute a page buffer, and the bit line 5360c may be electrically connected to the circuit element 5220c constituting the page buffer by the upper bonding metal pattern 5370c of the first cell area CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit area PERI.

[0316] Continue to refer Fig.36In the word line bonding area WLBA, the word line 5330 of the first cell region CREG1 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate 5310, and may be connected to a plurality of cell contact plugs (e.g., a first cell contact plug 5341, a second cell contact plug 5342, a third cell contact plug 5343, a fourth cell contact plug 5344, a fifth cell contact plug 5345, a sixth cell contact plug 5346, and a seventh cell contact plug 5347, hereinafter collectively referred to as "5340"). The first metal line 5350b and the second metal line 5360b may be sequentially connected to the plurality of cell contact plugs 5340 connected to the plurality of word lines 5330. In the word line bonding area WLBA, the plurality of cell contact plugs 5340 may be connected to the peripheral circuit region PREG through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI.

[0317] A plurality of cell contact plugs 5340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 5220b of the peripheral circuit region PREG may constitute a row decoder, and the cell contact plugs 5340 may be electrically connected to the circuit elements 5220b constituting the row decoder through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG. In some embodiments, the operating voltage of the circuit elements 5220b constituting the row decoder may be different from the operating voltage of the circuit elements 5220c constituting the page buffer. For example, the operating voltage of the circuit elements 5220c constituting the page buffer may be greater than the operating voltage of the circuit elements 5220b constituting the row decoder.

[0318] Similarly, in the word line bonding area WLBA, the plurality of word lines 5430 of the second cell region CREG2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 5410, and may be connected to a plurality of cell contact plugs (e.g., a first cell contact plug 5441, a second cell contact plug 5442, a third cell contact plug 5443, a fourth cell contact plug 5444, a fifth cell contact plug 5445, a sixth cell contact plug 5446, and a seventh cell contact plug 5447, hereinafter collectively referred to as "5440"). The plurality of cell contact plugs 5440 may be connected to the peripheral circuit region PREG through the upper metal pattern of the second cell region CREG2, the lower metal pattern and the upper metal pattern of the first cell region CREG1, and the cell contact plugs 5340.

[0319] In the word line bonding area WLBA, the upper bonding metal pattern 5370b may be formed in the first cell region CREG1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit region PERI. The upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. The upper bonding metal pattern 5370b and the upper bonding metal pattern 5270b may be formed of aluminum, copper, or tungsten.

[0320] In the external pad bonding area PA, the lower metal pattern 5371e may be formed in the lower portion of the first unit region CREG1, and the upper metal pattern 5472a may be formed in the upper portion of the second unit region CREG2. In the external pad bonding area PA, the lower metal pattern 5371e of the first unit region CREG1 and the upper metal pattern 5472a of the second unit region CREG2 may be connected to each other by a bonding method. Similarly, the upper metal pattern 5372a may be formed in the upper portion of the first unit region CREG1, and the upper metal pattern 5272a may be formed in the upper portion of the peripheral circuit region PERI. The upper metal pattern 5372a of the first unit region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by a bonding method.

[0321] The common source line contact plugs 5380 and 5480 may be disposed in the external pad bonding area PA. The common source line contact plugs 5380 and 5480 may be formed of a conductive material, such as but not limited to a metal, a metal compound and / or doped polysilicon. The common source line contact plug 5380 of the first cell region CREG1 may be electrically connected to the common source line 5320, and the common source line contact plug 5480 of the second cell region CREG2 may be electrically connected to the common source line 5420. The first metal line 5350a and the second metal line 5360a may be sequentially stacked on the common source line contact plug 5380 of the first cell region CELL1, and the first metal line 5450a and the second metal line 5460a may be sequentially stacked on the common source line contact plug 5480 of the second cell region CREG2.

[0322] Input / output (I / O) pads (eg, first I / O pad 5205, second I / O pad 5405, and third I / O pad 5406) ​​may be disposed in the external pad landing area PA. Fig.36, a lower insulating layer 5201 may at least partially cover a bottom surface of the first substrate 5210, and a first I / O pad 5205 may be formed on the lower insulating layer 5201. The first I / O pad 5205 may be connected to at least one circuit element among a plurality of circuit elements 5220a provided in the peripheral circuit region PREG through a first I / O contact plug 5203, and may be separated from the first substrate 5210 by the lower insulating layer 5201. In addition, a side insulating layer may be provided between the first I / O contact plug 5203 and the first substrate 5210 to electrically isolate the first I / O contact plug 5203 from the first substrate 5210.

[0323] An upper insulating layer 5401 at least partially covering the top surface of the third substrate 5410 may be formed on the third substrate 5410. A second I / O pad 5405 and / or a third I / O pad 5406 may be disposed on the upper insulating layer 5401. The second I / O pad 5405 may be connected to at least one circuit element among a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through second I / O contact plugs 5403 and 5303, and the third I / O pad 5406 may be connected to at least one circuit element among a plurality of circuit elements 220a disposed in the peripheral circuit region PREG through third I / O contact plugs 404 and 304.

[0324] In some embodiments, the third substrate 5410 may not be disposed in a region in which the I / O contact plug is disposed. For example, as shown in region "B", the third I / O contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410, and may at least partially penetrate the interlayer insulating layer 5415 of the second cell region CREG2 to be connected to the third I / O pad 5406. In this case, the third I / O contact plug 5404 may be formed by at least one of various processes.

[0325] In some embodiments, as shown in region “B1”, the third I / O contact plug 5404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third I / O contact plug 5404 may gradually increase toward the upper insulating layer 5401. In other words, the diameter of the channel structure CH described in region “A1” may gradually decrease toward the upper insulating layer 5401, but the diameter of the third I / O contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third I / O contact plug 5404 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other by a bonding method.

[0326] In some embodiments, as shown in region "B2", the third I / O contact plug 5404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third I / O contact plug 5404 may gradually decrease toward the upper insulating layer 5401. In other words, similar to the channel structure CH, the diameter of the third I / O contact plug 5404 may gradually decrease toward the upper insulating layer 5401. For example, the third I / O contact plug 5404 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0327] In some embodiments, the I / O contact plug may at least partially overlap the third substrate 5410. For example, as shown in region 'C', the second I / O contact plug 5403 may at least partially penetrate the interlayer insulating layer 5415 of the second cell region CREG2 in a third direction (e.g., Z-axis direction), and may be electrically connected to the second I / O pad 5405 through the third substrate 5410. In this case, the connection structure of the second I / O contact plug 5403 and the second I / O pad 5405 may be implemented by various methods.

[0328] In some embodiments, as shown in region "C1", the opening 5408 may be formed to at least partially penetrate the third substrate 5410, and the second I / O contact plug 5403 may be directly connected to the second I / O pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as shown in region "C1", the diameter of the second I / O contact plug 5403 may gradually increase toward the second I / O pad 5405. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the diameter of the second I / O contact plug 5403 may gradually decrease toward the second I / O pad 5405.

[0329] In some embodiments, as shown in region 'C2', an opening 5408 at least partially penetrating the third substrate 5410 may be formed, and a contact portion 5407 may be formed in the opening 5408. An end of the contact portion 5407 may be connected to the second I / O pad 5405, and the other end of the contact portion 5407 may be connected to the second I / O contact plug 5403. Therefore, the second I / O contact plug 5403 may be electrically connected to the second I / O pad 5405 through the contact portion 5407 in the opening 5408. In this case, as shown in region 'C2', the diameter of the contact portion 5407 may gradually increase toward the second I / O pad 5405, and the diameter of the second I / O contact plug 5403 may gradually decrease toward the second I / O pad 5405. For example, the second I / O contact plug 5403 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other, and the contact portion 5407 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0330] In some embodiments, as shown in region "C3", compared to the embodiment of region "C2", the stopper 409 may also be formed on the bottom end of the opening 408 of the third substrate 410. The stopper 5409 may be a metal line formed in the same layer as the common source line 5420. Alternatively or additionally, the stopper 5409 may be a metal line formed in the same layer as at least one of the word lines 5430. The second I / O contact plug 5403 may be electrically connected to the second I / O pad 5405 through the contact portion 5407 and the stopper 5409.

[0331] Similar to the second I / O contact plug 5403 and the third I / O contact plug 5404 of the second unit region CREG2, a diameter of each of the second I / O contact plug 5303 and the third I / O contact plug 5304 of the first unit region CREG1 may gradually decrease toward the lower metal pattern 5371e or may gradually increase toward the lower metal pattern 5371e.

[0332] In some embodiments, the slit 5411 may be formed in the third substrate 5410. For example, the slit 5411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed in a plan view, the slit 5411 may be located between the second I / O pad 5405 and the cell contact plug 5440. Alternatively or additionally, when viewed in a plan view, the second I / O pad 5405 may be located between the slit 5411 and the cell contact plug 5440.

[0333] In some embodiments, as shown in region "D1", the slit 5411 may be formed to at least partially penetrate the third substrate 5410. For example, the slit 5411 may be used to prevent the third substrate 5410 from being finely cracked when forming the opening 5408. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the slit 5411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 5410.

[0334] In some embodiments, as shown in region 'D2', a conductive material 5412 may be formed in the slit 5411. For example, the conductive material 5412 may be used to discharge leakage current occurring when driving the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 5412 may be connected to an external ground line.

[0335] In some embodiments, as shown in region "D3", an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second I / O pad 5405 and the second I / O contact plug 5403 disposed in the external pad bonding area PA from the word line bonding area WLBA. Since the insulating material 5413 is formed in the slit 5411, it is possible to prevent a voltage provided through the second I / O pad 5405 from affecting a metal layer on the third substrate 5410 disposed in the word line bonding area WLBA.

[0336] In some embodiments, the first to third I / O pads 5205, 5405, and 5406 may be selectively formed. For example, the memory device 5000 may be implemented to include only the first I / O pad 5205 disposed on the first substrate 5210, only the second I / O pad 5405 disposed on the third substrate 5410, or only the third I / O pad 5406 disposed on the upper insulating layer 5401.

[0337] In some embodiments, at least one of the second substrate 5310 of the first cell region CREG1 and the third substrate 5410 of the second cell region CREG2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 5310 of the first cell region CREG1 may be removed before or after the bonding process of the peripheral circuit region PREG and the first cell region CREG1, and then an insulating layer at least partially covering the top surface of the common source line 5320 or a conductive layer for connection may be formed. Similarly, the third substrate 5410 of the second cell region CREG2 may be removed before or after the bonding process of the first cell region CREG1 and the second cell region CREG2, and then an upper insulating layer 5401 at least partially covering the top surface of the common source line 5420 or a conductive layer for connection may be formed.

[0338] The detection structure according to the example embodiment can be applied to electronic devices and systems formed using semiconductor die. For example, the present disclosure can be applied to systems such as, but not limited to, personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automotive devices, etc.

[0339] The foregoing description is an illustration of the example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, it will be appreciated by those skilled in the art that various modifications may be made in the example embodiments without substantially departing from the teachings and advantages of the present disclosure. Accordingly, such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. A method for detecting an open circuit of a semiconductor device, the method comprising: generating a clock signal based on a probe of a measurement circuit contacting an end of a detection structure via a switch, the detection structure being formed in a semiconductor die of the semiconductor device in a ring shape; measuring a period of the clock signal; counting a number of cycles of the clock signal during a reference time interval; as well as A location of the open circuit of the semiconductor device is determined based on a number of cycles of the clock signal.

2. The method according to claim 1, wherein: Measuring the period of the clock signal comprises: The result of the sum of the inherent capacitance of the measurement circuit and the capacitance of the detection structure is multiplied by the inherent resistance of the measurement circuit, wherein the capacitance of the detection structure varies based on the position of the open circuit.

3. The method according to claim 1, wherein: Generating the clock signal comprises: The clock signal is generated based on the probe contacting the end of the detection structure via the switch, the detection structure being further formed in an outer region of the semiconductor die, the outer region at least partially surrounding a central region of the semiconductor die.

4. The method according to claim 1, wherein: Generating the clock signal comprises: The clock signal is generated based on the probe contacting the end of the detection structure via the switch, the detection structure being further formed in an edge portion of a central region of the semiconductor die.

5. The method according to claim 1, wherein: Generating the clock signal comprises: generating the clock signal based on the probe contacting the end of the detection structure via the switch, the detection structure further formed in a scribe lane in an outer region of the semiconductor die, the outer region at least partially surrounding a central region of the semiconductor die, and Wherein, the scribe line is formed around the central area.

6. The method according to claim 1, wherein: The detection structure comprises: a first conductive segment coupled to the switch via a first end and passing through a lower left corner region of an outer region of the semiconductor die, the outer region at least partially surrounding a central region of the semiconductor die; a second conductive segment coupled to the first conductive segment at a first node and passing through an upper left corner region of the outer region; a third conductive segment coupled to the second conductive segment at a second node and passing through an upper right corner region of the outer region; and A fourth conductive segment is coupled to the third conductive segment at a third node and passes through a lower right corner region of the outer region, and the fourth conductive segment is coupled to the switch through a second end.

7. The method according to claim 6, further comprising: using the measurement circuit, determining that a location of the open circuit occurs in the first conductive segment based on a number of cycles of a clock signal having a first cycle corresponding to a first number; using the measurement circuit, determining that the location of the open circuit occurs in the second conductive segment based on the number of cycles of the clock signal having a second cycle corresponding to a second number; using the measurement circuit, determining that the location of the open circuit occurs in the third conductive segment based on the number of cycles of the clock signal having a third cycle corresponding to a third number; as well as using the measurement circuit, determining that the position of the open circuit occurs in the fourth conductive segment based on the number of cycles of the clock signal having a fourth cycle corresponding to a fourth number, wherein the second period is greater than the first period, wherein the third period is greater than the second period, wherein the fourth period is greater than the third period, wherein the third number is greater than the fourth number, wherein the second number is greater than the third number, and Wherein, the first number is greater than the second number.

8. The method according to claim 1, wherein: The detection structure is a three-dimensional 3D detection structure formed adjacent to an edge portion of a central region of the semiconductor die, and the 3D detection structure extends in a vertical direction, The semiconductor die includes a first conductive layer and a second conductive layer below the first conductive layer. The 3D detection structure includes a conductive loop extending through the first conductive layer and the second conductive layer along the vertical direction, and Wherein, the conductive loop comprises: a plurality of top horizontal line segments formed in the first conductive layer; a plurality of bottom horizontal line segments formed in the second conductive layer; and A plurality of vertical line segments couple the plurality of top horizontal line segments and the plurality of bottom horizontal line segments to form the conductive loop.

9. The method according to claim 8, further comprising: Using the measurement circuit, a location of the open circuit is determined among the plurality of top horizontal line segments, the plurality of bottom horizontal line segments, and the plurality of vertical line segments based on a number of cycles of the clock signal.

10. The method according to claim 1, wherein: The detection structure is a 3D detection structure formed adjacent to an edge portion of a central region of the semiconductor die, the 3D detection structure extending in a vertical direction, The semiconductor die includes M layers stacked in a vertical direction, where M is a positive integer greater than 2. Each of the M layers includes a first conductive layer and a second conductive layer below the first conductive layer, The detection structure includes a conductive loop extending vertically through the first conductive layer and the second conductive layer of the M layers, and Wherein, the conductive loop comprises: a plurality of top horizontal line segments formed in the first conductive layer; a plurality of bottom horizontal line segments formed in the second conductive layer; a plurality of vertical line segments coupling the plurality of top horizontal line segments and the plurality of bottom horizontal line segments to form the conductive loop; and The bonding metal couples a portion of a top horizontal line segment of an upper layer of adjacent layers among the M layers with a portion of a bottom horizontal line segment of a lower layer of the adjacent layer.

11. The method according to claim 10, further comprising: Using the measurement circuit, a location of the open circuit is determined among at least a portion of the M layers based on a number of cycles of the clock signal.

12. A method for detecting an open circuit of a semiconductor device, the method comprising: generating a first number by counting first cycles of a first clock signal during a reference time interval, the first clock signal being generated by contacting a probe of a measurement circuit with a first end of a detection structure formed in a semiconductor die of the semiconductor device in a ring shape via a first switch; generating a second number by counting second cycles of a second clock signal during the reference time interval, the second clock signal being generated by contacting the probe of the measurement circuit with a second end of the detection structure via a second switch; as well as The location of the open circuit in the detection structure is determined based on a first difference between the first number and the second number and a second difference between a first period of the first clock signal and a second period of the second clock signal.

13. The method according to claim 12, wherein: The detection structure is formed in an outer region of the semiconductor die, the outer region at least partially surrounding a central region of the semiconductor die.

14. The method according to claim 12, wherein: The detection structure is formed in an edge portion of a central region of the semiconductor die.

15. The method according to claim 12, wherein: The detection structure is formed in a scribe street in an outer region of the semiconductor die, the outer region at least partially surrounding a central region of the semiconductor die, and Wherein, the scribe line is formed around the central area.

16. The method according to claim 12, wherein: The detection structure comprises: a first conductive segment coupled to the first switch via the first end and passing through a lower left corner region of an outer region of the semiconductor die, the outer region at least partially surrounding a central region of the semiconductor die; a second conductive segment coupled to the first conductive segment at a first node and passing through an upper left corner region of the outer region; a third conductive segment coupled to the second conductive segment at a second node and passing through an upper right corner region of the outer region; and a fourth conductive segment coupled to the third conductive segment at a third node and passing through a lower right corner region of the outer region, The fourth conductive segment is coupled to the second switch via the second end.

17. The method according to claim 16, further comprising: Using the measurement circuit, the location of the open circuit is determined among the first conductive segment, the second conductive segment, the third conductive segment, and the fourth conductive segment based on a first comparison of the first cycle of the first clock signal and the second cycle of the second clock signal, a second comparison of the first quantity and the second quantity, and a third comparison of the difference between the first quantity and the second quantity and a reference value.

18. A semiconductor device comprising: a first semiconductor die comprising a first central region and a first outer region, the first outer region at least partially surrounding the first central region; a second semiconductor die including a second central region and a second outer region, the second outer region at least partially surrounding the second central region, the first semiconductor die at least partially stacked on the second semiconductor die in a vertical direction; a memory cell structure formed in the first central region of the first semiconductor die; a peripheral circuit formed in the second central region of the second semiconductor die along a first direction and a second direction; a first detection structure formed in the second central region of the second semiconductor die to at least partially surround a first sub-circuit region and a second sub-circuit region, the first sub-circuit region and the second sub-circuit region being spaced apart from each other in the second direction in the peripheral circuit; as well as The measurement circuit is configured as: measuring a first cycle of a first clock signal generated by contacting a probe with a first end of the first detection structure through a first switch; as well as A first position of a first open circuit in the first detection structure is determined by counting a first number of cycles of the first clock signal during a reference time interval.

19. The semiconductor device according to claim 18, further comprising: a second detection structure formed in the second central region of the second semiconductor die to at least partially surround a third sub-circuit region and a fourth sub-circuit region, the third sub-circuit region and the fourth sub-circuit region being spaced apart from the first sub-circuit region and the second sub-circuit region in the first direction in the peripheral circuit, wherein the third sub-circuit region and the fourth sub-circuit region are spaced apart from each other in the second direction, and Wherein, the measuring circuit is further configured as: measuring a second period of a second clock signal generated by contacting the probe with the second end of the second detection structure through a second switch; and A second position of a second open circuit in the second detection structure is determined by counting a second number of cycles of the second clock signal during the reference time interval.

20. The semiconductor device according to claim 18, wherein The first detection structure is set in the following manner: alternately coupling an upper bonding metal of the first semiconductor die to an upper metal layer above the upper bonding metal along at least one of the first direction and the second direction at edges of the first sub-circuit region and the second sub-circuit region; as well as alternately coupling a lower bonding metal of the second semiconductor die to a lower metal layer below the lower bonding metal along at least one of the first direction and the second direction at edges of the first sub-circuit region and the second sub-circuit region, wherein the first semiconductor die is formed in a first semiconductor wafer, wherein the second semiconductor die is formed in a second semiconductor wafer, and The semiconductor device is provided after the first semiconductor wafer and the second semiconductor wafer are bonded and the bonded first semiconductor wafer and the second semiconductor wafer are diced.

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