Switched capacitor type SAR ADC circuit with low electric leakage

Abstract

The invention discloses a low-leakage switched capacitor type SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) circuit, which relates to the field of integrated circuit design, increases the minimum voltage of a positive input end of a comparator during conversion by adding a capacitor at the positive input end of the comparator, and increases the minimum voltage of the positive input end of the comparator by adding a voltage dividing switch circuit between a common-mode signal and the ground. The common-mode voltage during conversion is improved, so that the voltage difference Vsb between the source electrode and the base electrode of the common-mode switch is increased, and the threshold voltage of the NMOS switch tube is increased due to the substrate bias effect always existing during conversion, so that the leakage current Ioff is reduced. The added capacitor is beneficial to solving the problem of electric leakage, and can also separate the original shunt capacitor from other circuits, thereby reducing the interference of other circuits to the charge redistribution process. According to the scheme, the cost is low, the system complexity is low, the conversion error caused by electric leakage is reduced, and the conversion precision is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a low-leakage switched capacitor type SAR ADC circuit. Background Art

[0002] Analog-to-digital converters are often used in integrated circuit design, among which the successive approximation analog-to-digital converter (SAR ADC) is widely used due to its advantages of low power consumption, high resolution and small size. Due to its small area, low cost and low power consumption, SAR ADC has gradually become the mainstream ADC in deep submicron integrated circuit design. However, since SAR ADC uses a switched capacitor circuit, it is difficult to solve the switch leakage problem, which leads to conversion errors.

[0003] At present, the solutions to switch leakage include increasing the length of the switch tube and converting the sampling control signal into negative voltage through a charge pump, which is equivalent to increasing the threshold voltage of the switch tube in disguise, thereby reducing leakage. Increasing the length of the switch tube will increase the on-resistance, affecting the sampling accuracy, and the charge injection effect when the switch is closed will also increase; while adding a charge pump greatly increases the complexity of the system, and if the charge pump design performance is poor, the control signal is unstable and will be coupled to the capacitor array, introducing additional errors. Summary of the invention

[0004] In order to improve the leakage problem of SAR ADC capacitor array in low power consumption applications, the present invention comprehensively considers the design difficulty, cost and whether there is additional accuracy impact, and provides a low leakage switched capacitor SAR ADC circuit.

[0005] The low leakage switched capacitor SAR ADC circuit provided by the present invention comprises a capacitor array, a comparator, a SAR logic circuit, and a level conversion circuit, wherein the operating voltage of the capacitor array input side switch and the level conversion circuit is VDDA, and the operating voltage of the comparator and the SAR logic circuit is VDD;

[0006] The capacitor array includes a low-bit capacitor group composed of multiple capacitors connected in parallel and a high-bit capacitor group composed of multiple capacitors connected in parallel, and each capacitor of the low-bit capacitor group and the high-bit capacitor group is separately connected to the input signal Vin, VREFP or VREFN; the other end of the low-bit capacitor group and the high-bit capacitor group is connected to the positive input end of the comparator, and is also connected to the sampling control signal SAMP_B through the first capacitor, the capacitance value of the first capacitor is C1+ΔC1, and the value of C1 is equal to the equivalent capacitance value Ctot when all the low-bit and high-bit capacitors are connected in parallel;

[0007] The level conversion circuit working voltage VDDA is connected to the positive input terminal of the comparator through the second capacitor C2;

[0008] The two input terminals of the comparator are connected to the common mode signal Vcm0 through the common mode switch sw_cm;

[0009] A voltage divider switch circuit is connected between the common mode signal Vcm0 and the ground, and the circuit includes: a first resistor, a second resistor, a first switch K1, and a first NMOS tube M1, wherein one end of the first resistor is connected to the SAR logic circuit working voltage VDD, and the other end is connected to the drain of the first NMOS tube M1 through the second resistor, and one end of the first resistor connected to the second resistor is also connected to the common mode signal Vcm0 and grounded through the first switch K1, the source of the first NMOS tube M1 is grounded, and the gate is connected to the sampling control signal SAMP_B; during sampling, the first switch K1 is turned on, the first NMOS tube M1 is turned off, and Vcm0=0, and during conversion, the first switch K1 is turned off, and the first NMOS tube M1 is turned on.

[0010] Preferably, the calculation formula of the comparator positive input voltage Vdac is as follows:

[0011]

[0012] Where a is the ratio of the capacitor connected to VREFP to Ctot, VREFP and VREFN are the reference positive and negative inputs respectively, VREF=VERFP, Vin is the input voltage, and according to the above formula, the values ​​of ΔC1 and C2 are adjusted so that the value of Vdac satisfies Vsbth≤Vdac<1.2*VDD, where the range of Vsbth is as follows:

[0013] 0.15V≤Vsbth≤0.3V.

[0014] Preferably, the resistance values ​​of the first resistor and the second resistor need to be set so that the value of Vcm0 during conversion meets the following range:

[0015] 0.2V <Vcm0<VDD。

[0016] Preferably, the resistance values ​​of the first resistor and the second resistor should be as large as possible, so that the additional power consumption of the voltage divider switch circuit where the first resistor and the second resistor are located is less than one tenth of the overall minimum power consumption of the SAR ADC circuit.

[0017] Preferably, the second capacitor C2 is always connected to the positive input terminal of the comparator through the working voltage VDDA of the level conversion circuit, and the connection of the second capacitor C2 does not need to be controlled by a switch.

[0018] Preferably, the capacitance values ​​in the low-bit capacitor group are C, C, 2C, 4C, 8C, 16C and 32C respectively.

[0019] Preferably, the high-bit capacitor group includes 63 capacitors connected in parallel with a capacitance value of 64C.

[0020] Preferably, each capacitor of the low-bit capacitor group and the high-bit capacitor group is separately connected to a switch and then connected to the input signal Vin, VREFP or VREFN.

[0021] The present invention increases the minimum voltage of the positive input terminal of the comparator during conversion by adding a capacitor to the input terminal of the comparator, and at the same time increases the common mode voltage during conversion by adding a voltage divider switch circuit between the common mode signal and the ground, thereby increasing the voltage difference Vsb between the source and the base of the common mode switch, and the bias effect that always exists during the conversion causes the threshold voltage of the NMOS switch tube to increase, thereby reducing the leakage current Ioff. The increased capacitance is not only conducive to solving the leakage problem, but also can separate the original parallel capacitor from other circuits, reducing the interference of other circuits on the charge redistribution process. This solution has low cost and low system complexity, reduces the conversion error caused by leakage, and improves the conversion accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0023] Figure 1 A schematic diagram of a 12-bit switched capacitor SAR ADC circuit provided by a low leakage switched capacitor SAR ADC circuit of the present invention.

[0024] Figure 2 for Figure 1 The equivalent circuit diagram of the SAR ADC circuit shown.

[0025] Figure 3 for Figure 1 The NMOS switch leakage diagram of the SAR ADC circuit is shown in Figure 2.

[0026] Figure 4 For Figure 1 Schematic diagram of a leakage reduction technology solution for a SAR ADC circuit shown in FIG.

[0027] Figure 5 for Figure 4 The NMOS switch leakage diagram of the SAR ADC improvement circuit is shown.

[0028] Figure 6 This is a schematic diagram of the change of Ioff with Vds for different Vsb values ​​under 55nm COMS process.

[0029] Figure 7 for Figure 1 SAR ADC circuit with Figure 4 Schematic diagram of the conversion error of the improved circuit changing with input voltage. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] like Figure 1 The figure shows a schematic diagram of a conventional 12-bit switched capacitor SAR ADC circuit provided by an embodiment of the present invention, wherein the circuit includes a capacitor array, a comparator, a SAR logic circuit, and a level conversion circuit, wherein the operating voltage of the capacitor array input side switch and the level conversion circuit is VDDA, and the operating voltage of the comparator and the SAR logic circuit is VDD. The circuit adopts a pseudo-differential structure, the upper capacitor array and the lower capacitor array are symmetrical, the lower 6 bits are binary coded, and the upper 6 bits are thermometer coded to optimize the switch logic circuit and reduce the switching frequency.

[0032] The upper half of the capacitor array is used as an example for explanation. The capacitor array includes a low-bit capacitor group composed of multiple capacitors in parallel and a high-bit capacitor group composed of multiple capacitors in parallel. The capacitors of the low-bit capacitor group and the high-bit capacitor group are separately connected to the input signal Vin, VREFP or VREFN; the other end of the low-bit capacitor group and the high-bit capacitor group are connected to the positive input end of the comparator, and the sampling control signal SAMP_B is also connected through the first capacitor. The capacitance value of the first capacitor is C1, and the value of C1 is equal to the equivalent capacitance value Ctot when all low-bit and high-bit capacitors are connected in parallel.

[0033] The two input terminals of the comparator are connected to the common mode signal Vcm0 through the common mode switch sw_cm.

[0034] The capacitance values ​​of the low-bit capacitor group are C, C, 2C, 4C, 8C, 16C and 32C respectively.

[0035] The high-bit capacitor group includes 63 capacitors connected in parallel with a capacitance value of 64C.

[0036] Each capacitor of the low-bit capacitor group and the high-bit capacitor group is separately connected to a switch and then connected to the input signal Vin, VREFP or VREFN.

[0037] The low-bit capacitor group is connected to Vin, VREFP or VREFN through switches L0-L6, and the high-bit capacitor group is connected to Vin, VREFP or VREFN through switches M1-M63.

[0038] Figure 1 In the example, Vin is the input voltage, VREFP and VREFN are the reference positive and negative inputs respectively, the minimum unit capacitance is C = 1fF, and the total sampling capacitance is Ctot = 2 12 C=4.096pF. The upper capacitor is connected to Vin during sampling and to VREFP or VREFN according to the SAR logic control during conversion; the lower capacitor is always connected to VREFN. Vcm0 is the common mode voltage. Considering the input range and speed, the operating voltage of the ADC analog part is set to a higher VDDA to achieve a larger input range; the comparator and SAR logic circuit use low-voltage devices, and the operating voltage is VDD to achieve a faster conversion speed; SAMP is the sampling control signal under the VDDA power domain; and SAMP_B is the sampling control signal under the VDD power domain, which is obtained by SAMP after delay and inversion. The voltages of the positive input and negative input of the comparator are Vdac and Vcm respectively.

[0039] like Figure 2 Shown Figure 1 The equivalent circuit of the SAR ADC capacitor array is as follows: VREFN = 0, Vcm0 = 0, VREF = VREFP = VDDA = 3.6V, VDD = 1.2V.

[0040] In the sampling phase, SAMP=1 (VDDA power domain), SAMP_B=0, Vcm0=0, all capacitors in the upper capacitor array are connected to Vin, the total parallel capacitance is Ctot, the common-mode switch is closed, the voltage across C1 is zero, so C1 can be ignored, which is equivalent to Vin connected to the positive input of the comparator through capacitor Ctot, and the negative input of the comparator is grounded through capacitor Ctot.

[0041] During the conversion phase, SAMP = 0, SAMP_B = 1 (VDD power domain), Vcm0 = 0, the common mode switch is off, a is the ratio of the capacitor connected to VREFP to Ctot, and the initial value is It is equivalent to a*VREFP connected to the positive input of the comparator through Ctot, VDD connected to the positive and negative inputs of the comparator through C1, and the negative input of the comparator is grounded through Ctot.

[0042] Ideally, according to the law of charge conservation, the Vdac formula can be calculated as:

[0043]

[0044]

[0045] The comparator outputs the comparison result based on Vdac-Vcm, and the SAR logic circuit sets the switch in the capacitor array to change the value of a. After 12 comparisons, the final result is:

[0046]

[0047]

[0048] Finally, we get a*2 12 That is, the ADC conversion result code value.

[0049] C1 is set to ensure 0≤Vdac≤VDD, and its design principle is as follows:

[0050] In order to increase the sampling speed, the common mode voltage Vcm0 node should be a low resistance node. The simplest method is to make Vcm0 = 0. While increasing the sampling speed, the noise impact will also be smaller. If there is no C1, Formula 1 becomes V dac =a·VREF-V in When Vin takes the maximum value, Vin=VDDA=3.6V, Vdac=-1.8V, the switch will be directly turned on and the charge cannot be kept constant; when Vin takes the minimum value, Vin=0V, Vdac=1.8V>VDD, which exceeds the working voltage of the low-voltage device; therefore, it is necessary to ensure that 0≤Vdac≤VDD. The input amplitude of the comparator in the last comparison is The amplitude is related to the size of C1. The smaller the amplitude, the greater the difficulty in designing the comparator. In order to reduce the difficulty in designing the comparator, C1 is adjusted in combination with formulas 1 and 2 so that Vdac_min=0, Vdac_max=VDD, and finally: C1=Ctot.

[0051] In the actual circuit, due to the leakage of the common-mode voltage side switch sw_cm in the deep submicron process, the charge in the capacitor array cannot be kept constant. The most serious leakage occurs when the input voltage is at the minimum and maximum values, that is, Vin = 0V and Vin = VDDA. After the sampling is completed, the first charge redistribution obtains the Vdac voltages:

[0052]

[0053] If sw_cm is composed of NMOS only, Vin=VDDA, and the output voltage obtained by the first charge redistribution after sampling is Vdac=0, the switch source-drain voltage |Vds|=|Vdac-Vcm|=Vcm. When Vin=VDDA and Vin=0, the schematic diagram of the first charge redistribution switch Vds and leakage direction after sampling is as follows Figure 3 As shown, the three NMOS tubes are M0, M1, and M2. When Vin=VDDA, the Vds of the NMOS tubes M0 and M2 are both Vcm, and there is leakage; when Vin=0, the Vds of M0=VDD-Vcm, the Vds of M1=VDD, and the Vds of M2=Vcm, and there is leakage in the three NMOS tubes.

[0054] The charge loss of the capacitor array due to switch leakage and the resulting conversion error are:

[0055] Q leak =I off_ave .T conv (Formula 6)

[0056]

[0057] T conv is the ADC conversion time; I off_ave is the average value of switch leakage during conversion; it can be seen that for lower operating frequencies, ADC common-mode voltage switch leakage will cause conversion errors, and because the Ioff and source-drain voltage of the MOS tube are nonlinear, the error is also nonlinear relative to the input and cannot be calibrated. Therefore, it is necessary to study how to reduce SARADC capacitor array leakage in low-power applications.

[0058] In order to solve the problem of capacitor array leakage in traditional circuits at high power supply voltage and low operating frequency, the embodiment of the present invention proposes a low-cost and low-design difficulty solution, such as Figure 4 As shown:

[0059] (1) increasing the capacitance of the first capacitor connected to the sampling control signal SAMP_B so that its capacitance increases from C1 to C1+ΔC1;

[0060] (2) adding a second capacitor C2, one end of which is connected to the working voltage VDDA of the level conversion circuit, and the other end is connected to the positive input terminal of the comparator;

[0061] (3) A voltage divider switch circuit is connected between the common mode signal Vcm0 and the ground. The circuit includes: a first resistor, a second resistor, a first switch K1, and a first NMOS transistor M1. One end of the first resistor is connected to the logic circuit working voltage VDD, and the other end is connected to the drain of the first NMOS transistor M1 through the second resistor. The end of the first resistor connected to the second resistor is also connected to Vcm0 and grounded through the first switch K1. The source of the first NMOS transistor M1 is grounded, and the gate is connected to the sampling control signal SAMP_B. During sampling, the first switch K1 is turned on, the first NMOS transistor M1 is turned off, and Vcm0=0. During conversion, the first switch K1 is turned off, the first NMOS transistor M1 is turned on, and Vcm0=VDD / 2.

[0062] The capacitor array is a pseudo-differential structure. In order to make the capacitance at the positive and negative ends of the comparator symmetrical, the same ΔC1 and C2 are added to the positive and negative input ends of the comparator.

[0063] The purpose of adding the second capacitor C2 is to make the maximum value of Vdac not exceed 1.2*VDD to protect the comparator input pair. The second capacitor C2 is connected to the positive input terminal of the comparator through the working voltage VDDA of the level conversion circuit during the sampling and conversion stages, and there is no need to control the access of the second capacitor C2 through a switch.

[0064] The resistance values ​​of the first resistor and the second resistor need to be set so that the value of Vcm0 during conversion meets the following range:

[0065] 0.2V <Vcm0<VDD。

[0066] exist Figure 4 In the illustrated embodiment, the resistance values ​​of the first resistor and the second resistor are set to be equal, and during conversion, Vcm0 = VDD / 2.

[0067] The resistance values ​​of the first resistor and the second resistor should be as large as possible, so that the additional power consumption of the voltage divider switch circuit where the first resistor and the second resistor are located is less than one tenth of the overall minimum power consumption of the SAR ADC circuit. For example, when the original overall minimum power consumption of the SAR ADC circuit is 20uA at low speed, the resistance values ​​of the first resistor and the second resistor can both be selected to be 0.6MΩ, so that the current of the voltage divider switch circuit is less than 1uA.

[0068] The modified Vdac and Vcm voltage expressions are:

[0069]

[0070]

[0071] According to the above formula, the values ​​of ΔC1 and C2 are adjusted so that the value of Vdac satisfies Vsbth≤Vdac<1.2*VDD, where the range of Vsbth is as follows:

[0072] 0.15V ≤ Vsbth ≤ 0.3V

[0073] Vsbth within the above range provides a sufficiently strong body bias effect while not increasing too much capacitance.

[0074] The capacitance adjustment and matching operations here are simple and feasible because the additional capacitances ΔC1 and C2 are designed as the fill area (dummy) of Ctot in the layout, which can be achieved by increasing only a small amount of area. These additional capacitances are used to enclose the parallel capacitances of the low-bit and high-bit in the original circuit, which is beneficial for solving leakage and can also isolate the original parallel capacitance from other circuits, reducing the interference of other circuits on the charge redistribution process.

[0075] Taking Vsbth = 0.2 as an example, after improvement, during conversion, 0.2V ≤ Vdac < 1.2*VDD and Vcm0 = VDD / 2, then the source and drain voltages of the common-mode switch will not be 0. There must be Vsb ≥ 0.2V. The body bias effect that always exists during conversion causes the threshold voltage of the NMOS switch transistor to increase, thereby reducing Ioff. The comparison of the working states of the first charge redistribution switch after sampling when Vin = VDDA is as Figure 5 shown. For NMOS transistor M0, |Vds| = |Vcm - 0.2| < Vcm, Vsb = 0.2; for NMOS transistor M1, |Vds| = |VDD / 2 - Vcm| < Vcm, Vsb = VDD / 2; for NMOS transistor M2, |Vds| = |VDD / 2 - 0.2|, Vsb = VDD / 2. The threshold voltages of all three NMOS transistors increase due to the body bias effect, thereby reducing Ioff.

[0076] Verification was carried out under the 55nm CMOS process. Under the most severe conditions, that is, at fast corner and high temperature of 125°C, the variation of Ioff leakage with Vds for the two cases of Vsb = 0 and Vsb = 0.2 is as Figure 6 shown. It can be seen that when there is a body bias effect (Vsb = 0.2V), the leakage current of the MOS is significantly reduced; when Vds = VDD / 2 = 0.6V, the leakage current of the MOS without body bias effect is 23.65nA, and the leakage current of the MOS with body bias effect (Vsb = 0.2V) is 93pA, with a difference of hundreds of times. According to the derivation formula in the previous text, we can get:

[0077]

[0078] Fclk is the working frequency of the ADC. Since Ioff is reduced by hundreds of times, the error can be significantly reduced at the same working frequency.

[0079] In the actual circuit design, the ADC resolution is 12 bits, VREF=VDDA=3.6V, VDD=1.2V, the minimum operating frequency is 40KHz, and the process is 55nm CMOS. Figure 7 The conversion error data of the traditional structure and the improved structure are compared. It can be seen that when Vin is at its maximum value, the conversion error of the traditional scheme reaches its maximum value, Err_max (LSB) ≈6.375, the conversion effective bit is less than 10 bits; and after improvement, Err (LSB) <0.25, and still maintain 12-bit conversion accuracy.

[0080] In the embodiment of the present invention, by adding a capacitor to the input end of the comparator, the minimum voltage of the positive input end of the comparator during conversion is increased. At the same time, by adding a voltage divider switch circuit between the common mode signal and the ground, the common mode voltage during conversion is increased, so that the voltage difference between the source and the base of the common mode switch Vsb≥Vsbth, and the bias effect that always exists during the conversion causes the threshold voltage of the NMOS switch tube to increase, thereby reducing the leakage current Ioff. The added capacitance is not only conducive to solving the leakage problem, but also can separate the original parallel capacitor from other circuits, reducing the interference of other circuits on the charge redistribution process. This solution has low cost and low system complexity, reduces the conversion error caused by leakage, and improves the conversion accuracy.

[0081] The above are only specific implementations of the present invention, which cannot be used to limit the scope of the present invention. Equivalent changes made by ordinary technicians in this technical field based on this creation, as well as changes known to technicians in this field, should still fall within the scope of the present invention.

Claims

1. A low leakage switched capacitor SAR ADC circuit, comprising a capacitor array, a comparator, a SAR logic circuit, and a level conversion circuit, wherein: The operating voltage of the switch and level conversion circuit on the input side of the capacitor array is VDDA, and the operating voltage of the comparator and SAR logic circuit is VDD, which is characterized by: The capacitor array includes a low-bit capacitor group composed of multiple capacitors connected in parallel and a high-bit capacitor group composed of multiple capacitors connected in parallel, and each capacitor of the low-bit capacitor group and the high-bit capacitor group is separately connected to the input signal Vin, VREFP or VREFN; the other end of the low-bit capacitor group and the high-bit capacitor group is connected to the positive input end of the comparator, and is also connected to the sampling control signal (SAMP_B) through the first capacitor, the capacitance value of the first capacitor is C1+ΔC1, and the value of C1 is equal to the equivalent capacitance value (Ctot) when all the low-bit and high-bit capacitors are connected in parallel; The level conversion circuit operating voltage (VDDA) is connected to the positive input terminal of the comparator through the second capacitor (C2); The two input terminals of the comparator are connected to a common mode signal (Vcm0) through a common mode switch (sw_cm); A voltage divider switch circuit is connected between the common mode signal (Vcm0) and the ground, and the circuit comprises: a first resistor, a second resistor, a first switch (K1), and a first NMOS transistor (M1), wherein one end of the first resistor is connected to the SAR logic circuit working voltage (VDD), and the other end is connected to the drain of the first NMOS transistor (M1) through the second resistor, one end of the first resistor connected to the second resistor is also connected to the common mode signal (Vcm0) and is grounded through the first switch (K1), the source of the first NMOS transistor (M1) is grounded, and the gate is connected to a sampling control signal (SAMP_B); during sampling, the first switch (K1) is turned on, the first NMOS transistor (M1) is turned off, and Vcm0=0; during conversion, the first switch (K1) is turned off, and the first NMOS transistor (M1) is turned on.

2. The low leakage switched capacitor SAR ADC circuit according to claim 1, characterized in that: The calculation formula of the comparator positive input voltage (Vdac) is as follows: Where a is the ratio of the capacitor connected to VREFP to Ctot, VREFP and VREFN are the reference positive and negative inputs respectively, VREF=VERFP, Vin is the input voltage, and according to the above formula, the values ​​of ΔC1 and C2 are adjusted so that the value of Vdac satisfies Vsbth≤Vdac<1.2*VDD, where the range of Vsbth is as follows: 0.15V≤Vsbth≤0.3V.

3. The low leakage switched capacitor SAR ADC circuit according to claim 1, characterized in that: The resistance values ​​of the first resistor and the second resistor need to be set so that the value of Vcm0 during conversion meets the following range: 0.2V <Vcm0<VDD。 4. The low leakage switched capacitor SAR ADC circuit according to claim 3, characterized in that: The resistance values ​​of the first resistor and the second resistor should be as large as possible, so that the additional power consumption of the voltage divider switch circuit where the first resistor and the second resistor are located is less than one tenth of the overall minimum power consumption of the SAR ADC circuit.

5. The low leakage switched capacitor SAR ADC circuit according to claim 1, characterized in that: The second capacitor (C2) is always connected to the positive input terminal of the comparator through the working voltage (VDDA) of the level conversion circuit, and the connection of the second capacitor (C2) does not need to be controlled by a switch.

6. The low leakage switched capacitor SAR ADC circuit according to claim 1, characterized in that: The capacitance values ​​of the low-bit capacitor group are C, C, 2C, 4C, 8C, 16C and 32C respectively.

7. The low leakage switched capacitor SAR ADC circuit according to claim 1, characterized in that: The high-bit capacitor group includes 63 capacitors connected in parallel with a capacitance value of 64C.

8. The low leakage switched capacitor SAR ADC circuit according to claim 1, characterized in that: Each capacitor of the low-bit capacitor group and the high-bit capacitor group is separately connected to a switch and then connected to the input signal Vin, VREFP or VREFN.

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