Electronic device and method of operating same

Abstract

An electronic device and a method of operating the same are provided. The electronic device may include: a receiving circuit configured to generate a plurality of received data bits based on a voltage level of an analog signal received through a link, and generate a plurality of bit reliability values indicating a probability of an error of the plurality of received data bits based on the voltage level of the analog signal; an alignment circuit configured to group the plurality of received data bits into a plurality of error correction code (ECC) symbols, and generate a plurality of symbol reliability values indicating error occurrence probabilities of the plurality of ECC symbols based on the plurality of bit reliability values; and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

Description

Technical Field

[0001] Aspects of the present disclosure relate to semiconductor integrated circuits, and more particularly, to electronic devices and methods of operating electronic devices having enhanced error correction performance. Background Art

[0002] In recent years, as the transmission speed between electronic devices has increased, the error rate of data during transmission has also increased. For example, since the Peripheral Component Interconnect Express (PCIe) 6.0 adopts Pulse Amplitude Modulation 4 (PAM4), the existing bit error rate (BER) requirement of non-return to zero (NRZ) has changed from 10-12 to 10-6. Therefore, error correction code (ECC) and cyclic redundancy code (CRC) can be used in the physical layer. ECC can be used to correct errors, and if the error is not correctly corrected or is uncorrectable by ECC, a protocol can be used to request error detection and data retransmission by CRC.

[0003] The ECC of PCIe 6.0 includes one symbol composed of an 8-bit Reed-Solomon (RS) code, and can be configured by concatenating and interleaving three symbols. Since each RS code can only correct one symbol, three errors that occur consecutively due to a burst error can be corrected, but there is a limitation that two errors that occur in one ECC cannot be corrected. Summary of the invention

[0004] Some exemplary embodiments may provide an electronic device and a method of operating the electronic device, which are capable of enhancing error correction performance by selecting symbols having a high probability of error occurrence.

[0005] According to some embodiments, an electronic device may include: a receiving circuit, which is configured to generate multiple received data bits based on the voltage level of an analog signal received through a link, and generate multiple bit reliability values ​​indicating the error occurrence probability of the multiple received data bits based on the voltage level of the analog signal; an alignment circuit, which is configured to group the multiple received data bits into multiple error correction code (ECC) symbols, and generate multiple symbol reliability values ​​indicating the error occurrence probability of multiple ECC symbols based on the multiple bit reliability values; and a decoding circuit, which is configured to correct errors of the multiple ECC symbols based on the multiple symbol reliability values.

[0006] According to some embodiments, an electronic device may include: a receiving circuit, the receiving circuit being configured to generate a plurality of received data bits based on a voltage level of a pulse amplitude modulation 4 (PAM4) signal received through a link, and to generate a plurality of bit reliability values ​​indicating error occurrence probabilities of the plurality of received data bits based on the voltage level of the PAM4 signal; an alignment circuit, the alignment circuit being configured to: generate a synchronization position value indicating a position of a data block by monitoring a data pattern included in the plurality of received data bits, wherein the data block indicates a unit of error correction; group the plurality of received data bits into a plurality of error correction code (ECC) symbols based on the synchronization position value; and generate a plurality of symbol reliability values ​​based on the synchronization position value and the plurality of bit reliability values, wherein the plurality of symbol reliability values ​​indicate error occurrence probabilities of the plurality of ECC symbols and are aligned with the plurality of ECC symbols; and a decoding circuit, the decoding circuit being configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

[0007] According to an exemplary embodiment, a method of operating an electronic device may include: generating a plurality of received data bits based on a voltage level of an analog signal received through a link; generating a plurality of bit reliability values ​​indicating error occurrence probabilities of the plurality of received data bits based on the voltage level of the analog signal; grouping the plurality of received data bits into a plurality of error correction code (ECC) symbols; generating a plurality of symbol reliability values ​​indicating error occurrence probabilities of a plurality of ECC symbols based on the plurality of bit reliability values; and correcting errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

[0008] An electronic device and a method of operating the electronic device according to an exemplary embodiment may effectively extract error symbol candidates and enhance error correction performance by generating a symbol reliability value of an ECC symbol based on a voltage level of an analog signal received through a link. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a system according to some embodiments.

[0011] Figure 2 is a flow chart illustrating a method of operating an electronic device according to some embodiments.

[0012] Figure 3A , Figure 3B , Figure 3C and Figure 3D Is used to describe Figure 1 Diagram of the signal transmission of the system.

[0013] Figure 4 is a diagram illustrating some embodiments of hard decisions and soft decisions of an electronic device according to some embodiments.

[0014] Figure 5 is a block diagram illustrating an example of a transmission circuit included in an electronic device according to some embodiments.

[0015] Figure 6 is a block diagram illustrating an example of a receiving circuit included in an electronic device according to some embodiments.

[0016] Figure 7 It is shown Figure 6 0014-07-05 14:57:42 is a block diagram of an exemplary embodiment of a hard decision circuit included in a receiving circuit of .

[0017] Figure 8 It is shown Figure 6 A block diagram of an exemplary embodiment of a soft decision circuit included in a receiving circuit of FIG.

[0018] Fig. 9 is a diagram illustrating an example of received data bits output from a receiving circuit included in an electronic device and corresponding bit reliability values ​​according to some embodiments.

[0019] Fig.10 and Fig.11 is a diagram illustrating an exemplary embodiment of an interconnect architecture applied to a system according to some embodiments.

[0020] Fig.12 is a block diagram illustrating an encoding circuit included in an electronic device according to some embodiments.

[0021] Fig.13 is a block diagram illustrating a decoding circuit included in an electronic device according to some embodiments.

[0022] Fig.14 A diagram used to describe the flit mode supported by a logical sub-block.

[0023] Fig.15 is a diagram showing error correction code (ECC) symbols for each channel.

[0024] Fig.16A , Fig. 16B and Fig. 16C is a diagram used to describe erasure decoding according to some embodiments.

[0025] Fig.17 is a flow chart illustrating an exemplary embodiment of a method of aligning ECC symbols and symbol reliability values ​​in an electronic device in accordance with some embodiments.

[0026] Fig.18 It is shown by Fig.17 A diagram of examples of method for aligning ECC symbols and symbol reliability values.

[0027] Fig.19 is a block diagram illustrating an exemplary embodiment of an alignment circuit included in an electronic device according to some embodiments.

[0028] Fig. 20 , Fig.21 and Fig. 22 is a diagram for describing an exemplary embodiment of a method of aligning ECC symbols and symbol reliability values ​​in an electronic device according to some embodiments.

[0029] Fig.23 It is shown Fig.19 FIG. 1 is a diagram of an exemplary embodiment of a symbol reliability generator included in an alignment circuit.

[0030] Fig.24 is a diagram illustrating a PAM8 scheme in an electronic device according to some embodiments.

[0031] Fig.25 is a diagram illustrating an exemplary embodiment of a method of generating a bit reliability value in an electronic device according to some embodiments.

[0032] Fig.26 It shows execution Fig.25 A block diagram of an example of a receiving circuit of the method.

[0033] Fig. 27 is a diagram illustrating error correction performance of an electronic device according to some embodiments of the inventive concept.

[0034] Fig.28 is a diagram illustrating an electronic device according to an exemplary embodiment. Specific embodiments

[0035] Various examples of embodiments will be described more fully below with reference to the accompanying drawings, in which some embodiments are shown. In the accompanying drawings, like reference numerals always represent like elements, and for the sake of brevity, repeated descriptions of some elements will be omitted here.

[0036] Figure 1 is a block diagram illustrating a system according to some embodiments.

[0037] Reference Figure 1 , the system 50 may include a first electronic device ( DEV1 ) 10 and a second electronic device ( DEV2 ) 20 connected via a link 30 . Figure 1 Only some components are shown to explain certain embodiments. The first electronic device 10 and the second electronic device 20 may also include various components depending on their respective configurations.

[0038] The first electronic device 10 may include a first receiving circuit RX1 , a first alignment circuit AL1 , a first decoding circuit DEC1 , a first transmitting circuit TX1 , and a first encoding circuit ENC1 .

[0039] The first receiving circuit RX1, the first alignment circuit AL1, and the first decoding circuit DEC1 may correspond to a receiving block that receives the analog signal RS transmitted from the second electronic device 20 through the link 30. The first transmitting circuit TX1 and the first encoding circuit ENC1 may correspond to a transmitting block that transmits the analog signal RS to the second electronic device 20 through the link 30.

[0040] The second electronic device 20 may include a second receiving circuit RX2, a second alignment circuit AL2, a second decoding circuit DEC2, a second transmitting circuit TX2, and a second encoding circuit ENC2.

[0041] The second receiving circuit RX2, the second alignment circuit AL2, and the second decoding circuit DEC2 may correspond to a receiving block that receives the analog signal RS transmitted from the first electronic device 10 through the link 30. The second transmitting circuit TX2 and the second encoding circuit ENC2 may correspond to a transmitting block that transmits the analog signal RS to the first electronic device 10 through the link 30.

[0042] In some exemplary embodiments, the first electronic device 10 and the second electronic device 20 may be connected via a peripheral component interconnect express (PCIe) link 30 conforming to the PCIe standard. However, the present disclosure and its inventive concepts are not limited to a specific link and may be applied to any link that transmits data and / or signals through multi-stage signaling.

[0043] exist Figure 1 In the embodiment, the first electronic device 10 and the second electronic device 20 may be connected via a bidirectional link 30, and each electronic device 10 and 20 may include a receiving block and a transmitting block, which may be used as a transceiver for exchanging an analog signal RS between the first electronic device 10 and the second electronic device 20.

[0044] When a packet is transmitted from the second electronic device 20 to the first electronic device 10, the first electronic device 10 corresponds to a receiving device and the second electronic device 20 corresponds to a transmitting device. Conversely, when a packet is transmitted from the first electronic device 10 to the second electronic device 20, the first electronic device 10 corresponds to a transmitting device and the second electronic device 20 corresponds to a receiving device.

[0045] According to some embodiments, the first electronic device 10 and the second electronic device 20 may be connected via a unidirectional link. In this case, one of the first electronic device 10 and the second electronic device 20 may correspond to a transmitting device and may include only a transmitting block, and the other may correspond to a receiving device and may include only a receiving block.

[0046] Hereinafter, some embodiments will be described focusing on the relationship between a receiving device and a transmitting device. Figure 1 As shown, it should be understood that the description provided herein can be applied in the same manner as the first electronic device 10 and the second electronic device 20 are implemented as a transmitting device and a receiving device configured to perform two-way communication.

[0047] Figure 2 is a flow chart illustrating a method of operating an electronic device according to some embodiments.

[0048] Reference Figure 1 and Figure 2 , the receiving circuit RX1 or RX2 included in the receiving device can generate a plurality of received data bits RB based on the voltage level of the analog signal RS received through the link 30 (S100). In addition, the receiving circuit RX1 or RX2 can generate a plurality of bit reliability values ​​BRV based on the voltage level of the analog signal RS, indicating the error occurrence probability of the plurality of received data bits RB (S200). Figure 6 , Figure 7 , Figure 8 , Fig.26 etc. to describe certain embodiments of the receiving circuits RX1 and RX2.

[0049] The alignment circuit AL1 or AL2 of the receiving device may group the plurality of received data bits RB into a plurality of error correction code (ECC) symbols ESM (S300). In addition, the alignment circuit AL1 or AL2 of the receiving device may generate a plurality of symbol reliability values ​​SRV (S400) indicating the error occurrence probability of the plurality of ECC symbols ESM based on the plurality of bit reliability values ​​BRV. Fig.19 etc. to describe certain embodiments of the alignment circuits AL1 and AL2.

[0050] The decoding circuit DEC1 or DEC2 of the receiving device can correct errors of a plurality of ECC symbols ESM based on a plurality of symbol reliability values ​​SRV (S500). Fig.13 etc. to describe some embodiments of the decoding circuits DEC1 and DEC2.

[0051] The encoding circuit ENC1 or ENC2 of the transmitting device may encode the data and generate a transmission bit TB. The transmitting circuits TX1 and TX2 of the transmitting device may transmit an analog signal RS corresponding to the multi-level signal to the receiving device through the link 30 based on the transmission bit TB.

[0052] When error correction of the decoding circuits DEC1 and DEC2 fails, a plurality of bit reliability values ​​BRV and / or a plurality of symbol reliability values ​​(SRV) may be recalculated based on previous decoding results, etc. In this case, signal delay may increase due to error correction.

[0053] On the other hand, according to some embodiments, regardless of the success or failure of the error correction of the decoding circuit DEC1 or DEC2, a plurality of ECC symbols ESM and a plurality of symbol reliability values ​​SRV aligned with the plurality of ECC symbols ESM may be provided to the decoding circuit DEC1 or DEC2 at the same time. Therefore, the performance of the electronic device may be improved by reducing the error correction time of the decoding circuits DEC1 and DEC2 and increasing the success probability of error correction.

[0054] Figure 3A , Figure 3B , Figure 3C and Figure 3D Is used to describe Figure 1 Diagram of the signal transmission of the system.

[0055] Figure 3A Shows Figure 1 The ideal eye diagram of the analog signal RS, Figure 3B shows an eye diagram obtained by actually simulating the analog signal RS, and Figure 3C Shows Figure 3A Schematic eye diagram of. Figure 3D An exemplary configuration of transmission bits TB represented by a simulation signal RS is shown.

[0056] Reference Figure 3A and Figure 3B , eye diagrams can be used to indicate signal quality in high-speed transmissions. For example, an eye diagram can represent the signal quality of a signal in a system (e.g., Figure 1 An analog signal RS, such as a PAM4 signal, is used to transmit data in a system 50 in FIG. 5A . For example, an eye diagram may represent four symbols of a signal (e.g., "00", "10", "11", "01"), where each of the four symbols represents a different voltage level (or voltage amplitude) VL1, VL2, VL3, and VL4. An eye diagram may be used to provide a visual representation of signal integrity and may indicate the noise margin of a signal.

[0057] To generate an eye diagram, an oscilloscope or other computing device may sample a digital signal according to a sampling period SP (e.g., a unit time interval or a bit period). The sampling period SP may be defined by a clock associated with the signal transmission. The oscilloscope or other computing device may measure the voltage level of the signal during the sampling period SP to form a trace (TRC). By overlapping multiple traces TRC, various characteristics of the measured signal may be determined.

[0058] Eye diagrams can be used to identify many characteristics of communication signals, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), and other characteristics. For example, the eye width W can be used to indicate the timing synchronization of the measured signal or the jitter effect in the measured signal. The eye opening OP can represent the peak-to-peak voltage difference between the various voltage levels VL1, VL2, VL3, and VL4, and can be associated with the voltage margin to distinguish the voltage levels VL1, VL2, VL3, and VL4 of the measured signal.

[0059] Figure 3C A first voltage level VL1, a second voltage level VL2, a third voltage level VL3, and a fourth voltage level VL4 of a PAM4 type analog signal RS and a first hard decision reference value REF1, a second hard decision reference value REF2, and a third hard decision reference value REF3 for detecting or sensing different voltage levels VL1, VL2, VL3, and VL4 are shown. In some exemplary embodiments, the receiving circuit RX1 or RX2 can digitally sample the analog signal RS by converting the voltage level of the analog signal RS into a received digital value using an analog-to-digital converter, and compare the received digital value with the first hard decision reference value REF1, the second hard decision reference value REF2, and the third hard decision reference value REF3. In some exemplary embodiments, the receiving circuit RX1 or RX2 can sample the analog signal RS using an analog method of directly comparing the analog signal RS with the first, second, and third reference voltage levels.

[0060] The first voltage level VL1 is higher than the second voltage level VL2, the second voltage level VL2 is higher than the third voltage level VL3, and the third voltage level VL3 is higher than the fourth voltage level VL4. For example, the first voltage level VL1 may be the same level as the power supply voltage VDDQ, the second voltage level VL2 may be about 2 / 3 of the level of the power supply voltage VDDQ, the third voltage level VL3 may be about 1 / 3 of the level of the power supply voltage VDDQ, and the fourth voltage level VL4 may be the level of the ground voltage GND (i.e., about 0V).

[0061] The first hard decision reference value REF1 may correspond to a voltage level between the first voltage level VL1 and the second voltage level VL2, the second hard decision reference value REF2 may correspond to a voltage level between the second voltage level VL2 and the third voltage level VL3, and the third hard decision reference value REF3 may correspond to a voltage level between the third voltage level VL3 and the fourth voltage level VL4. For example, the first hard decision reference value REF1 may correspond to about ¾ of the level of the power supply voltage VDDQ, the second hard decision reference value REF2 may correspond to about ½ of the level of the power supply voltage VDDQ, and the third hard decision reference value REF3 may correspond to about ¼ of the level of the power supply voltage VDDQ.

[0062] Figure 3D The relationship between the first voltage level VL1, the second voltage level VL2, the third voltage level VL3 and the fourth voltage level VL4 of the PAM4 analog signal RS and the transmission bit TB (ie, the values ​​of the first bit B11 and the second bit B21 corresponding to one PAM4 symbol) is shown.

[0063] When the transmission bit TB corresponding to one PAM4 symbol has a value of '01', that is, the value of the first bit B11 is '0' and the value of the second bit B21 is '1', the analog signal RS generated based on the transmission bit TB may have a first voltage level VL1. Similarly, when the transmission bit TB has a value of "11", the analog signal RS may have a second voltage level VL2, when the transmission bit TB has a value of "10", the analog signal RS may have a third voltage level VL3, and when the transmission bit TB has a value of "00", the analog signal RS may have a fourth voltage level VL4.

[0064] exist Figure 3D In the embodiment of the present invention, the first bit B11 may be the most significant bit MSB of the transmission bit TB corresponding to one PAM4 symbol, and the second bit B21 may be the least significant bit LSB of the transmission bit TB. However, the present disclosure is not limited thereto.

[0065] Furthermore, according to some embodiments, the received digital value may be compared with a plurality of soft decision reference values ​​respectively representing a plurality of error decision ranges centered around a plurality of hard decision reference values ​​to generate a plurality of bit reliability values ​​BRV.

[0066] For example, Figure 3CAs shown, the first error decision range EDR1 can be centered on the first hard decision reference value REF1, and can be represented by the first upper soft decision reference value HREF1 and the first lower soft decision reference value LREF1. The second error decision range EDR2 can be centered on the second hard decision reference value REF2, and can be represented by the second upper soft decision reference value HREF2 and the second lower soft decision reference value LREF2. The third error decision range EDR3 can be centered on the third hard decision reference value REF3, and can be represented by the third upper soft decision reference value HREF3 and the third lower soft decision reference value LREF3.

[0067] The upper soft decision reference value HREFi (i=1, 2, 3) may be greater than the corresponding hard decision reference value REFi by a threshold value Δ, and the lower soft decision reference value LREFi may be less than the corresponding hard decision reference value REFi by a threshold value Δ. In other words, each error decision range EDRi may be twice the threshold value Δ (i.e., 2*Δ).

[0068] Figure 4 is a diagram illustrating an exemplary embodiment of hard decisions and soft decisions of an electronic device according to some embodiments.

[0069] Reference Figure 4 , a hard decision (HD) may be performed to determine the value of the received data bit RB by comparing the received digital value DRS corresponding to the voltage level of the analog signal RS with the hard decision reference values ​​REF1, REF2, and REF3. In addition, a soft decision (SD) may be performed to determine the bit reliability value BRV by comparing the received digital value DRS with the soft decision reference values ​​HREF1, HREF2, HREF3, LREF1, LREF2, and LREF3.

[0070] Results, such as Figure 4 As shown, when the received digital value DRS is included in the multiple error decision ranges EDR1, EDR2, and EDR3, each bit reliability value BRV can be determined as a first value (e.g., "1") indicating a relatively high probability of error occurrence. On the other hand, when the received digital value DRS is not included in the multiple error decision ranges EDR1, EDR2, and EDR3, each bit reliability value BRV can be determined as a second value (e.g., "0") indicating a relatively low probability of error occurrence.

[0071] Figure 5 is a block diagram illustrating an exemplary embodiment of a transmission circuit included in an electronic device according to some exemplary embodiments.

[0072] Reference Figure 5The transmitting circuit 210 may generate an analog signal RS having one of a first voltage level VL1, a second voltage level VL2, a third voltage level VL3, and a fourth voltage level VL4 based on a value of a first bit B11 and a value of a second bit B21 included in a transmission bit TB corresponding to one PAM4 symbol.

[0073] The transmission circuit 210 may include a sampler 250 , a first driver 261 , a second driver 262 , a third driver 263 , and a data input-output pad 270 .

[0074] The sampler 250 may be configured to generate the first drive signal DRV1 , the second drive signal DRV2 , and the third drive signal DRV3 based on the value of the first bit B11 and the value of the second bit B21 .

[0075] The first driver 261 may be configured to generate an analog signal RS having a first voltage level VL1 or a fourth voltage level VL4 based on the first drive signal DRV1. The second driver 262 may generate an analog signal RS having a second voltage level VL2 or a fourth voltage level VL4 based on the second drive signal DRV2. The third driver 263 may generate an analog signal RS having a third voltage level VL3 or a fourth voltage level VL4 based on the third drive signal DRV3.

[0076] In some exemplary embodiments, each of the first driver 261, the second driver 262, and the third driver 263 may include a complementary metal oxide semiconductor (CMOS) gate. For example, the first driver 261 may include a CMOS gate operated based on a first driving voltage VD1 having a first voltage level VL1 and a fourth driving voltage VD4 having a fourth voltage level VL4, the second driver 262 may include a CMOS gate operated based on a second driving voltage VD2 having a second voltage level VL2 and the fourth driving voltage VD4, and the third driver 263 may include a CMOS gate operated based on a third driving voltage VD3 having a third voltage level VL3 and the fourth driving voltage VD4.

[0077] When the transmission bit TB has a value of "01", the first drive signal DRV1 may have a logic high level, and the first driver 261 may be configured to generate an analog signal RS having a first voltage level VL1 based on the first drive signal DRV1, at which time the second driver 262 and the third driver 263 may be deactivated. Similarly, when the transmission bit TB has a value of "11", the second drive signal DRV2 may have a logic high level, and the second driver 262 may be configured to generate an analog signal RS having a second voltage level VL2 based on the second drive signal DRV2, at which time the first driver 261 and the third driver 263 may be deactivated. When the transmission bit TB has a value of "10", the third drive signal DRV3 may have a logic high level, and the third driver 263 may be configured to generate an analog signal RS having a third voltage level VL3 based on the third drive signal DRV3, at which time the first driver 261 and the second driver 262 may be deactivated.

[0078] At the same time, when the transmission bit TB has a value of "00", at least one of the first drive signal DRV1, the second drive signal DRV2, and the third drive signal DRV3 may have a logic low level, and at least one of the first driver 261, the second driver 262, and the third driver 263 may be configured to generate an analog signal RS having a fourth voltage level VL4 based on at least one of the first drive signal DRV1, the second drive signal DRV2, and the third drive signal DRV3.

[0079] The data input-output pad 270 may output the analog signal RS through the link. For example, the pad may indicate a contact pad or a contact pin, but the present disclosure is not limited thereto.

[0080] Figure 6 is a block diagram illustrating an example of a receiving circuit included in an electronic device according to some embodiments.

[0081] Reference Figure 6 , the receiving circuit 400 may include a sampler 410 and a reference value generator (RFC) 420 .

[0082] The reference value generator 420 may be configured to generate the reference value as described above. Figure 3C and Figure 4 The hard decision reference value REF and the soft decision reference values ​​HREF and LREF described above. In some embodiments, the reference value generator 420 can adjust the above-mentioned error decision ranges EDR1, EDR2 and EDR3 based on the threshold Δ. In other words, the reference value generator 420 can adjust the soft decision reference values ​​HREF and LREF based on the threshold Δ. Fig.13 A method for adjusting the width of this error decision range is described below.

[0083] The sampler 410 may include an analog-to-digital converter (ADC) 411 , a hard decision circuit (HDC) 412 , and a soft decision circuit (SDC) 414 .

[0084] The analog-to-digital converter 411 may be configured to convert the voltage level of the analog signal RS into a received digital value DRS. The hard decision circuit 412 may generate a plurality of received data bits RB by comparing the received digital value DRS with a plurality of hard decision reference values ​​REF. The soft decision circuit 414 may generate a plurality of bit reliability values ​​BRV by comparing the received digital value DRS with a plurality of soft decision reference values ​​HREF and LREF indicating a plurality of error decision ranges EDR, each error decision range EDR being centered around a corresponding one of the plurality of hard decision reference values ​​REF.

[0085] Figure 7 It is shown Figure 6 A block diagram of an example of a hard decision circuit included in a receiving circuit of FIG.

[0086] Reference Figure 7 , the hard decision circuit 412 may be configured to generate a plurality of received data bits RB by comparing the received digital value DRS with a plurality of hard decision reference values ​​REF1 , REF2 , and REF3 . Figure 7 An analog-to-digital converter ADC is shown, which is configured to convert an analog signal RS received through the input-output pad 450 into a received digital value DRS. When an analog sampling method is adopted, the analog-to-digital converter ADC can be omitted. In this case, the hard decision circuit 412 can be configured to generate a plurality of received data bits RB by comparing the voltage level of the analog signal RS with a plurality of hard decision reference voltages VREF1, VREF2, and VREF3.

[0087] The hard decision circuit 412 may include a first comparator 461 , a second comparator 462 , a third comparator 463 , and a sampler 470 .

[0088] The first comparator 461 can generate a first comparison signal CS1 based on a comparison of the received digital value DRS with the first hard decision reference value REF1. The second comparator 462 can generate a second comparison signal CS2 based on a comparison of the received digital value DRS with the second hard decision reference value REF2. The third comparator 463 can generate a third comparison signal CS3 based on a comparison of the received digital value DRS with the third hard decision reference value REF3.

[0089] In the case of the analog sampling method, each of the first comparator 461, the second comparator 462, and the third comparator 463 may include an operational amplifier. For example, the first comparator 461 may include an operational amplifier that operates based on the analog signal RS and the first hard decision reference voltage VREF1, the second comparator 462 may include an operational amplifier that operates based on the analog signal RS and the second hard decision reference voltage VREF2, and the third comparator 463 may include an operational amplifier that operates based on the analog signal RS and the third hard decision reference voltage VREF3.

[0090] The sampler 470 may be configured to generate a received data bit RB based on the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3. As a result, the hard decision circuit 412 may perform as described with reference to Figure 4 Describes the hard decision (HD).

[0091] Figure 8 It is shown Figure 6 A block diagram of an example of a soft decision circuit included in a receiving circuit of FIG.

[0092] Reference Figure 8 , the soft decision circuit 414 can be configured to generate a plurality of bit reliability values ​​BRV by comparing the received digital value DRS with a plurality of soft decision reference values ​​HREF1, LREF1, HREF2, LREF2, HREF3, and LREF3. When the analog sampling method is adopted, the above-mentioned analog-to-digital converter ADC can be omitted. In this case, the soft decision unit 414 can be configured to generate a plurality of received data bits RB by comparing the voltage level of the analog signal RS with a plurality of soft decision reference voltages VHREF1, VLREF1, VHREF2, VLREF2, VHREF3, and VLREF3, respectively.

[0093] The soft decision circuit 414 may include a first comparator 481 , a second comparator 482 , a third comparator 483 , a fourth comparator 484 , a fifth comparator 485 , a sixth comparator 486 , and a sampler 490 .

[0094] The first comparator 481 may generate a first upper comparison signal HCS1 based on a comparison of the received digital value DRS with the first upper soft decision reference value HREF1. The second comparator 482 may generate a first lower comparison signal LCS1 based on a comparison of the received digital value DRS with the first lower soft decision reference value LREF1. The third comparator 483 may generate a second upper comparison signal HCS2 based on a comparison of the received digital value DRS with the second upper soft decision reference value HREF2. The fourth comparator 484 may generate a second lower comparison signal LCS2 based on a comparison of the received digital value DRS with the second lower soft decision reference value LREF2. The fifth comparator 485 may generate a third upper comparison signal HCS3 based on a comparison of the received digital value DRS with the third upper soft decision reference value HREF3. The sixth comparator 486 may generate a third lower comparison signal LCS3 based on a comparison of the received digital value DRS with the third lower soft decision reference value LREF3.

[0095] The sampler 490 may be configured to generate a bit reliability value based on the first upper comparison signal HCS1, the second upper comparison signal HCS2, and the third upper comparison signal HCS3 and the first lower comparison signal LCS1, the second lower comparison signal LCS2, and the third lower comparison signal LCS3. As a result, the soft decision circuit 414 may be configured to perform as described with reference to FIG. Figure 4 Described soft decision (SD).

[0096] Fig. 9 is a diagram illustrating an example of received data bits output from a receiving circuit included in an electronic device and corresponding bit reliability values ​​according to some embodiments.

[0097] exist Fig. 9 In the example, the unit interval UI represents the time interval corresponding to one PAM3 symbol received by the receiving device. Fig. 9 As shown, the receiving circuit can output a plurality of received data bits RB in an aligned state and a plurality of corresponding reliability values ​​BRV.

[0098] Some embodiments will be described below based on the Peripheral Component Interconnect Express (PCIe) architecture among multiple interconnect fabric architectures. The main goal of PCIe is to enable components and devices from different vendors to meet multiple market segments; PCIe allows them to interoperate in an open architecture across clients (desktop and mobile), servers (standard and enterprise), and embedded and communication devices. PCIe is a high-performance, general-purpose I / O interconnect defined for a variety of future computing and communication platforms. Some PCIe properties, such as the usage model, load-store architecture, and its software interface, have been retained in its various versions, while the previous parallel bus implementation has been replaced by a fully serial interface with a highly scalable fully serial interface. The latest version of PCIe takes advantage of advances in point-to-point interconnects, switch-based technology, and packet protocols to provide new performance levels and features. Power management, quality of service (QoS), hot-plug (Hot-Plug) / hot-swap (Hot-Swap) support, data integrity, error handling, and credit-based flow control are some of the advanced features supported by PCIe.

[0099] In the past PCI technology, the sending device did not know the status of the receiving device's receive buffer. If a transaction was aborted because the receive buffer was full, the transaction would be retransmitted until completed. As a result, a specific device would occupy the system bus for a long period of time, causing serious degradation of system performance.

[0100] Later, PCIe technology improved efficiency by preventing unnecessary communication by checking the buffer capacity of the receiving port before sending a transaction packet. At this time, endpoint devices such as host devices and storage devices can use a credit-based control mechanism. That is, during system initialization, each receiving port transmits the entire receiving buffer size of the port to the sending port, and thereafter, the receiving port periodically transmits the remaining size (number of credits) of the receiving buffer to the sending port to occupy the receiving buffer to share information about the status of the receiving buffer.

[0101] If the allocated receive buffer size is insufficient, the sending device (e.g., storage device) may not be able to send transaction packets, and the transmission will be delayed while waiting for flow control credit update information from the receiving device (e.g., host device). This can cause performance degradation of the storage device and the entire system.

[0102] In the future, as the speed of interconnect architectures such as PCIe increases, it is expected that the performance degradation of endpoint devices such as storage devices will be further exacerbated due to the limitation of the receiving buffer size of the host device. Exemplary embodiments can improve the error correction capability within the endpoint device and reduce the frequency of retransmission requests, thereby improving the performance degradation of the endpoint device.

[0103] Fig.10 and Fig.11 is a diagram illustrating an example of an interconnect architecture applied to a system according to some embodiments.

[0104] Reference Fig.10 and Fig.11 , an embodiment of a layered protocol stack is shown. The layered protocol stack may include any form of layered communication stack, such as a quick path interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computing interconnect stack, or other layered stacks. Although the present disclosure explains the inventive concept related to the PCIe stack, the same concept can be applied to other interconnect stacks. In some embodiments, the protocol stack may be a PCIe protocol stack including a transaction layer, a data link layer, and a physical layer. Interfaces such as interfaces 317, 318, 321, 322, 326, and 331 may be represented as a communication protocol stack. A representation as a communication protocol stack may also be referred to as a module or interface that implements / includes a protocol stack.

[0105] The PCI Express protocol uses packets to pass information between components. Packets are formed in the transaction layer and the data link layer to carry information from the sending component to the receiving component. As the transmitted packets flow through the other layers, they can be extended with additional information for processing the packets at these layers. On the receiving side, the reverse process occurs, and packets can be converted from their physical layer representation to the data link layer representation and finally (for transaction layer packets) to a form that can be processed by the transaction layer of the receiving device.

[0106] In some embodiments, the transaction layer can be used to provide an interface between the processing core of the device and the interconnect architecture such as the data link layer and the physical layer. In this regard, the primary responsibilities of the transaction layer can include the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). The transaction layer typically manages credit-based flow control of TLPs. PCIe implements split transactions, which can be transactions where requests and responses are separated in time, and can allow the link to carry other traffic while the target device collects data for the response.

[0107] Additionally, the PCIe protocol can utilize credit-based flow control. In this scheme, the device advertises the initial amount of credits for each receive buffer in the transaction layer. The external device at the other end of the link can calculate the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction can be transmitted. When a response is received, the amount of credit is restored. The advantage of the credit scheme is that as long as the credit limit is not reached, the delay in the return of credits does not affect performance.

[0108] In some embodiments, the transaction layer may assemble a packet header / payload. The payload may include data and an error detection code, such as an ECRC. The format of the current packet header / payload may be found in the PCIe specification, which may be obtained at the PCIe specification website or other resources.

[0109] The link layer, also known as the data link layer, can act as an intermediate stage between the transaction layer and the physical layer or PHY layer. In some embodiments, the responsibility of the data link layer can be to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components over a link. One side of the data link layer can accept the TLPs assembled by the transaction layer, can apply a packet sequence identifier, such as a sequence number, an identification number, or a packet number, can calculate and apply an error detection code, such as an LCRC, and can submit the modified TLP to the physical layer for transmission to an external device through the physical layer.

[0110] In some embodiments, the physical layer includes a logical sub-block and an electrical sub-block to physically transmit packets to an external device. Here, the logical sub-block can be responsible for the "digital" functions of the physical layer. In this regard, the logical sub-block can include: a transmitter portion configured to prepare outgoing information for transmission by the physical sub-block; and a receiver portion configured to identify and prepare received information before passing it to the link layer.

[0111] The physical layer may include a transmitter TX and a receiver RX. The logic sub-block may provide symbols to the transmitter TX, and the transmitter may serialize the symbols and transmit them to an external device. The receiver RX may be provided with serialized symbols from an external device, and may convert the received signal into a bit stream. The bit stream may be deserialized and provided to the logic sub-block. In some embodiments, an 8b / 10b transmission code may be used, in which ten-bit symbols are sent / received. Here, special symbols may be used to construct packets with frames. In addition, in some embodiments, the receiver RX may also provide a symbol clock recovered from an incoming serial stream.

[0112] As described above, although the transaction layer, link layer, and physical layer are discussed with reference to a specific implementation or embodiment of the PCIe protocol stack, the present disclosure is not limited thereto. In some embodiments, any layered protocol may be included / implemented.

[0113] Fig.12 is a block diagram illustrating an encoding circuit included in an electronic device according to some embodiments.

[0114] Reference Fig.12, the transmitting circuit 300 may include a CRC encoder 310 and an ECC encoder 320. The CRC encoder 310 may perform CRC encoding on the data and add the CRC to the data. The ECC encoder 320 may perform ECC encoding on the data to which the CRC is added, and may add the ECC to generate a flit. The flit may then be converted into an analog signal RS corresponding to a PAM4 signal by the transmitting circuit and may be sent to a receiving device through a link. In one embodiment, the flit may be a flow control unit in accordance with the PCIe standard.

[0115] Fig.13 is a block diagram illustrating a decoding circuit included in an electronic device according to some embodiments.

[0116] Reference Fig.13 The decoding circuit 500 may include an ECC decoder 510, a CRC decoder 520, and an erasure decoder 530. According to an embodiment or implementation details, the decoding circuit 500 may further include a threshold controller 540.

[0117] The ECC decoder 510 may perform ECC decoding on a micro-slice (eg, according to the PCIe standard), wherein the micro-slice includes a plurality of ECC symbols per ECC group. Each ECC symbol may include a certain number of received data bits RB, and the micro-slice may include a certain number of ECC symbols.

[0118] The CRC decoder 520 may obtain data by performing CRC (Cyclic Redundancy Check) decoding on the decoded flits (D_FLIT).

[0119] When CRC decoding fails, the erasure decoder 530 can be configured to extract an erroneous symbol candidate from a plurality of ECC symbols based on a plurality of symbol reliability values ​​SRV provided from the alignment circuit, and can be configured to replace the erroneous symbol candidate with a symbol generated based on the plurality of symbol reliability values ​​SRV. After processing, ECC decoding can be performed again.

[0120] The ECC decoder 510 may be configured to perform ECC decoding on microchips containing multiple ECC symbols of each ECC group. For example, the ECC decoder 510 may use a Reed-Solomon (RS) signal, which includes row parity and check bits generated by a parity check matrix (PCM) during ECC encoding in a transmitting device. ECC decoding may be performed based on a Reed-Solomon code. In other words, in some embodiments, the above-mentioned ECC symbols may be Reed-Solomon symbols. When error correction for multiple ECC symbols fails, the decoding circuit 500 may be configured to perform RS erasure decoding by extracting error symbol candidates from multiple ECC symbols based on multiple symbol reliability values.

[0121] PCM row parity and check bits can be generated by ECC encoding at the sender. For example, PCM can be defined as follows.

[0122]

[0123] Here, H is PCM, α is an element defined in GF (Galois Field) 28 space, and N is the number of symbols in an ECC group. The rows of PCM can be used to generate row parity and check bits, respectively.

[0124] Row parity can be defined as follows.

[0125]

[0126] Here, P may be a low parity check, and Bi may be a symbol corresponding to TLP, DLP, and CRC in the ECC symbol. That is, the row parity check may be generated by a bitwise exclusive OR (XOR) operation of the Bi symbol.

[0127] The check digit can be defined as follows.

[0128]

[0129] Here, C may be a check bit. That is, similar to CRC generation, a check bit may be generated by a bitwise XOR operation of the Bi symbol multiplied by α.

[0130] For example, generation of row parity and check bits to be used when performing ECC encoding on an ECC group of 86B may be defined as follows.

[0131]

[0132] The transmitting end may be configured to perform ECC encoding based on the row parity and check bits and transmit the ECC encoded signal. The ECC decoder 510 may be configured to perform ECC decoding based on the RS code (i.e., the row parity and check bits) included in the ECC encoded signal, and may be configured to transmit the ECC decoded microchip (D_FLIT) to the CRC decoder 520. If the position of the error is unknown, the RS code can correct one error within one ECC group, and if the position of the error is known, up to two errors can be corrected.

[0133] The CRC decoder 520 may be configured to obtain data by performing CRC decoding on the ECC decoded microchip (D_FLIT). Here, the data may be TLP and DLP. The CRC decoder 520 may be configured to perform CRC decoding on the entire microchip (or more accurately, the remaining ECC symbols except the symbols corresponding to the ECC) without considering the ECC group based on the symbols corresponding to the CRC included in the microchip.

[0134] If CRC decoding fails, CRC decoder 520 may be configured to re-perform CRC decoding after erasure decoder 530 re-performs ECC decoding. If re-performance of CRC decoding fails, CRC decoder 520 may request retransmission (retry) of a flits from the transmitter.

[0135] The erasure decoder 530 may be configured to perform erasure decoding when the CRC decoding of the CRC decoder 520 fails. Erasure decoding may be defined as re-performing the following operations: based on the symbol reliability value SRB, a symbol with a high probability of error occurrence is selected from the ECC symbols included in the micro-chip, at least two symbols of the selected symbols are randomly extracted, erased, and ECC decoding is performed. Here, the erasure process may mean processing the codeword of the corresponding symbol to 0.

[0136] According to some embodiments, when flits are interleaved for three ECC groups and an error occurs in two symbols of at least one ECC group, if the CRC decoder 520 fails in CRC decoding, erasure decoding may be performed.

[0137] As will be referred to below Fig.23As described, the alignment circuit may be configured to determine a symbol reliability value corresponding to each ECC symbol when at least one of the bit reliability values ​​corresponding to each ECC symbol has a first value (e.g., "1"). Each symbol reliability value may be set to a third value (e.g., "1"), indicating that each ECC symbol is an error symbol candidate with a high probability of error occurrence. At the same time, when the bit reliability values ​​corresponding to each ECC symbol have a second value (e.g., "0"), the alignment circuit may assign a fourth value (e.g., "0") to each symbol reliability value corresponding to each ECC symbol, indicating that the symbol is a symbol with a low probability of error occurrence.

[0138] The threshold controller 540 may be configured to adjust a plurality of soft decision reference values ​​representing a plurality of error decision ranges based on the number of error symbol candidates corresponding to the third value obtained in this manner. In other words, the threshold controller 540 may adjust the reference values ​​based on the number of error symbol candidates. Figure 3C Describes the threshold Δ.

[0139] As a result, the receiving circuit can be configured to adjust the multiple soft decision reference values ​​so that when the number of error symbol candidates corresponding to the third value is greater than the reference number, each error decision range is reduced. If the number of error symbol candidates is less than the reference number, the multiple soft decision reference values ​​can be adjusted so that each error decision range increases. In this way, the number of error symbol candidates for error correction can be appropriately adjusted.

[0140] Fig.14 is a diagram for illustrating micro-slice modes supported by a logical sub-block, and Fig.15 is a diagram showing an error correction code (ECC) symbol for each channel.

[0141] Reference Fig.14, a microchip may be a data unit supported in a microchip mode of a standard (e.g., a PCIe standard), and may include TLP, DLP, CRC, and ECC in some embodiments. For example, a microchip may have a size of 256B (bytes), i.e., 2048 bits, and may include, for example, 236B of TLP, 6B of DLP, 8B of CRC, and 6B of ECC. A byte alignment method may be used to interleave microchips for multiple channels. For example, microchips may be interleaved in a 3-way manner. Interleaved microchips may include multiple ECC symbols (or ECC codewords), and multiple ECC symbols may belong to one of multiple ECC groups. For example, when interleaved in a 3-way manner, there may be three ECC groups. Each of the multiple ECC symbols may have a size of 8 bits. The ECC code belonging to each ECC group may correct errors that occur in each ECC group. When the microchip size is 256B and the microchips are interleaved in a 3-way manner, one of the multiple ECC groups may include 86B of ECC symbols, and the remaining ECC groups may each include 85B of ECC symbols.

[0142] As shown in the figure, the ECC symbol can be classified into a symbol corresponding to TLP, a symbol corresponding to DLP, a symbol corresponding to CRC, and a symbol corresponding to ECC. Here, the symbol corresponding to ECC can be a symbol including RS code information in the ECC symbol generated as a result of ECC encoding. In the case of a symbol corresponding to CRC, one ECC group can include three symbols, and the remaining ECC groups can include two symbols.

[0143] Reference Fig.15 , interleaved ECC symbols may be arranged for each channel. Since PAM4 signaling may be applied in micro-slice mode, each ECC symbol may include multiple PAM4 symbols for PAM4 signaling. Therefore, a micro-slice may be understood as including multiple PAM4 symbols. PAM4 symbols may be placed on each 2-bit aligned boundary, and each PAM4 symbol may have a size of 2 bits. For example, as shown in the figure, if the ECC symbol has an 8-bit size, each ECC symbol may include 4 PAM4 symbols.

[0144] Hereinafter, some embodiments of the electronic device 100 having improved correction capability for errors occurring in the above-mentioned microchip will be described. The electronic device may be referred to as a PCIe device or a receiving device, and may correspond to a physical layer included in a PCIe layer.

[0145] Fig.16A , Fig. 16B and Fig. 16C is a diagram used to describe erasure decoding according to some embodiments.

[0146] Reference Fig.16AAccording to some embodiments, when an error occurs in two symbols in one of the multiple ECC groups, erasure decoding may be performed. If CRC decoding fails in CRC decoder 520, erasure decoder 530 may be configured to extract a candidate (numErasure) among the ECC symbols that matches a preset number (numErasure) (in Fig.16A In the case of 3), the corresponding error symbol candidate. The error symbol candidate can be extracted to include the symbol in which the actual error occurs. For example, in Fig.16A In the example of FIG. 5 , if an error actually occurs in Candidate 1 (Cand1) and Candidate 2 (Cand2), the erasure decoder 530 detects an error between Candidate 1 (Cand1) and Candidate 2 (Cand2) and the remaining symbols. Candidate 3 (Cand3) (a symbol with a high probability) may be extracted as an error symbol candidate. Candidates 1 (Cand1) to 3 (Cand3) have indexes corresponding to 45, 48, and 51, respectively. The erasure decoder 530 randomly extracts two candidates from Candidate 1 (Cand1) to Candidate 3 (Cand3), and performs erasure processing and ECC decoding.

[0147] The erasure process may include changing the codeword value of the symbol corresponding to each index to 0. For example, if Candidate 1 (Cand1) and Candidate 3 (Cand3) are extracted from Candidates 1 (Cand1) and 3 (Cand3) in the first attempt, the erasure decoder 530 extracts the codeword value of the candidate, sets it to 0, and re-performs ECC decoding. The first attempt fails because the symbols that actually cause the error are Candidate 1 (Cand1) and Candidate 2 (Cand2).

[0148] If Candidate 1 (Cand1) and Candidate 2 (Cand2) are extracted in the second attempt, the erasure decoder 530 sets the codeword values ​​of the candidates to 0 and then re-performs ECC decoding.

[0149] Since the candidate with the actual error has been extracted, the ECC decoding is successful and the erasure decoding can be terminated.

[0150] Reference Fig. 16B According to some embodiments, when an error occurs in two symbols in two ECC groups among the plurality of ECC groups, erasure decoding may be performed. If CRC decoding fails in CRC decoder 520, erasure decoder 530 may be configured to extract a candidate (numErasure) among the ECC symbols that matches a preset number (numErasure) (in Fig. 16B In the case of 6), the corresponding error symbol candidate. The error symbol candidate can be extracted to include the symbol in which the actual error occurs. For example, in Fig. 16BIn the example, if an error actually occurs in candidate 1 (Cand1) to candidate 4 (Cand4), the erasure decoder 530 detects errors in candidate 1 (Cand1) to candidate 4 (Cand4) and the remaining symbols. Candidate 5 (Cand5) and candidate 6 (Cand6) (symbols with high probability) may be extracted as error symbol candidates. Candidate 1 (Cand1) to candidate 6 (Cand6) have indexes corresponding to 41, 44, 45, 48, 50 and 51, respectively. The erasure decoder 530 can be configured to randomly extract four candidates from candidate 1 (Cand1) to candidate 6 (Cand6), and perform erasure processing and ECC decoding. For example, if candidate 1 (Cand1) to candidate 3 (Cand3) and candidate 5 (Cand5) are extracted from candidate 1 (Cand1) to candidate 6 (Cand6) in the first attempt, after setting the codeword value of the candidate to 0, the erasure decoder 530 can perform ECC decoding again, and the first attempt may fail. If Cand1 to Cand4 are extracted in the second attempt, the erasure decoder 530 may set the codeword value of the candidate to 0 and then re-perform ECC decoding. Since a candidate with an actual error has been extracted, ECC decoding is successful and erasure decoding may be terminated.

[0151] Reference Fig. 16C According to some embodiments, when errors occur in two symbols in each of three ECC groups in the plurality of ECC groups, erasure decoding may be performed. If CRC decoding fails in CRC decoder 520, erasure decoder 530 may be configured to extract a candidate (numErasure) among the ECC symbols that matches a preset number (in Fig. 16C In the case of 8), the corresponding error symbol candidate. The error symbol candidate can be extracted to include the symbol in which the actual error occurs. For example, in Fig. 16C In the embodiment of the present invention, if an error actually occurs in Candidate 1 (Cand1) to Candidate 6 (Cand6), the erasure decoder 530 may detect errors in Candidate 1 (Cand1) to Candidate 6 (Cand6) and the remaining symbols. Candidate 7 (Cand7) and Candidate 8 (Cand8) (symbols with high probability) may be extracted as error symbol candidates. Candidate 1 (Cand1) to Candidate 8 (Cand8) may have indexes corresponding to 41, 43, 44, 45, 46, 48, 50, and 51, respectively.

[0152] The erasure decoder 530 can be configured to randomly extract six candidates from candidate 1 (Cand1) to candidate 8 (Cand8), and perform erasure processing and ECC decoding. For example, if candidate 1 (Cand1) to candidate 5 (Cand5) and candidate 7 (Cand7) are extracted from candidate 1 (Cand1) to candidate 8 (Cand8) in the first attempt, after setting the codeword value of the candidate to 0, the erasure decoder 530 can perform ECC decoding again, and the first attempt may fail. If candidate 1 (Cand1) to candidate 6 (Cand6) are extracted in the second attempt, the erasure decoder 530 can set the codeword value of the candidate to 0 and then re-perform ECC decoding. Since the candidate with an actual error has been extracted, the ECC decoding is successful and the erasure decoding can be terminated.

[0153] Fig.17 is a flow chart illustrating an exemplary embodiment of a method of aligning ECC symbols and symbol reliability values ​​in an electronic device in accordance with some embodiments.

[0154] Reference Figure 1 and Fig.17 , the alignment circuit AL1 or AL2 of the receiving device can generate a synchronization position value SYNC indicating the position of a data block by monitoring a data pattern included in a plurality of received data bits RB, wherein the data block indicates a unit of error correction of the decoding circuit DEC1 or DEC2 (S10). The alignment circuits AL1 and AL2 can group the plurality of received data bits RB into a plurality of ECC symbols ESM based on the synchronization position value SYNC (S20).

[0155] In addition, the alignment circuit AL1 or AL2 may group the plurality of bit reliability values ​​BRV into a plurality of reliability symbols ( ESM ) respectively aligned with the plurality of ECC symbols ESM based on the synchronization position value SYNC. Fig.18 RSM in)(S30).

[0156] A plurality of bit reliability values ​​BRV and / or a plurality of reliability symbols ( Fig.18 The alignment circuit AL1 or AL2 may generate a per-symbol reliability value SRV indicating an error occurrence probability of each ECC symbol ESM by performing a logical OR operation on the bit reliability values ​​included in each reliability symbol (RSM) (S40).

[0157] Fig.18 It is shown by Fig.17 A diagram of examples of method for aligning ECC symbols and symbol reliability values.

[0158] Fig.18The ECC symbols ESMO and ESM1, reliability symbols RSMO and RSM1, and symbol reliability values ​​SRV aligned by alignment circuits AL1 and AL2 are shown. Fig.18 In the embodiment, the unit interval UI can represent a time interval corresponding to one PAM3 symbol received by a receiving device.

[0159] Reference Fig.18 , the ECC symbols ESMO and ESM1 may each include eight bits S0 to S7 included in the received data bits. The reliability symbols RSM0 and RSM1 may each include four bits R0 to R3 included in the bit reliability value BRV. By performing a logical operation on the bits R0 to R3 included in the reliability symbol RSM0 aligned with the ECC symbol ESM0, a symbol reliability value (RSV=RV0) indicating the probability of error occurrence of the ECC symbol ESM0 may be determined. In addition, by performing a logical operation on the bits R0 to R3 included in the reliability symbol RSM aligned with the ECC symbol ESM1, a symbol reliability value (RSV=RV1) indicating the probability of error occurrence in the ECC symbol ESM1 may be determined.

[0160] In the following, reference is made to Figures 19 to 23 , will explain in more detail Fig.17 and Fig.18 method.

[0161] Fig.19 is a block diagram showing an example of an alignment circuit included in an electronic device, and Fig. 20 , Fig.21 and Fig. 22 is a diagram for describing an example of a method of aligning ECC symbols and symbol reliability values ​​in an electronic device according to some embodiments.

[0162] Reference Fig.19 , the alignment circuit 600 may include a buffer unit 610 , a symbol reliability value generator (SRVGN) 620 , a monitor (MON) 630 , and a control unit (CTRL) 640 .

[0163] The buffer unit 610 may include a data buffer (RBBF) configured to store the received data bit RB and a reliability buffer BRVBF configured to store the bit reliability value BRV. The data buffer RBBF and the reliability buffer BRVBF may store the received data bit RB and the reliability value BRV in a receiving unit of a certain number of bits, respectively. For example, Fig.21 As shown, the data buffer RBBF can store the received data bits RB in 64-bit receiving units, and the reliability buffer BRVBF can store the reliability values ​​BRV in 32-bit receiving units. Fig.21As shown, the buffer unit 610 may be provided with two or more storage means or devices to store not only the current reception unit but also the previous reception unit.

[0164] The monitor 630 may monitor a data pattern included in a plurality of received data bits RB, and may generate a synchronization position value SYNC indicating a position of a data block as an error correction unit of a decoding circuit. In some embodiments, the monitor 630 may be a unit for performing error correction on a decoding circuit by monitoring a data pattern corresponding to an electrical idle exit ordered set (EIEOS) according to the PCIe standard included in a plurality of received data bits RB. A synchronization position value SYNC indicating a position of a data block may be generated. The synchronization position value SYNC may correspond to Fig. 20 The starting position of the microchip shown in FIG. 1 and can be expressed as Fig.21 The position value of the data buffer RBBF is shown.

[0165] The control unit 640 may calculate the offset value OFS based on the synchronization position value SYNC. Fig.18 As shown, the receiving circuit can generate a bit reliability value BRV of one bit for every two received data bits RB corresponding to each PAM4 symbol. When each ECC symbol ESM is 8 bits, the control unit 640 can obtain the remainder of the synchronization position value SYNC divided by 8, divide the remainder by 2, and calculate the offset value OFS. Therefore, Fig.21 As shown, the offset value OFS may have a value of 0, 1, 2 or 3. The offset value OFS may indicate the starting position of the ESS symbol ESM in the data buffer RBBF and the starting position (ie, starting point) of the above reliability symbol RSM in the reliability buffer BRVBF.

[0166] The control unit 640 may group the received data bits RB stored in the data buffer RBBF into ECC symbols ESM based on the offset value OFS and output them. In addition, the control unit 640 may group the bit reliability values ​​BRV stored in the reliability buffer BRVBF into reliability symbols RSM aligned with the ECC symbols ESM, respectively, based on the offset value OFS. The symbol reliability value generator 620 may receive the bit reliability values ​​BRV grouped into reliability symbols RSM, and may generate a symbol reliability value SRV corresponding to each ECC symbol ESM.

[0167] Fig.23 It is shown Fig.19 FIG. 1 is a diagram of an exemplary embodiment of a symbol reliability generator included in an alignment circuit.

[0168] Reference Fig.23, the symbol reliability value generator 620 may include a first multiplexer 621, a second multiplexer 622, a third multiplexer 623, a fourth multiplexer 624 and an OR gate 625. Fig.23 In this case, i corresponds to an integer from 0 to 7. If x is a negative integer, BRV[x] means Fig. 22 If x is 0 or a positive integer, it represents the previous bit reliability value (PREVIOUSBRV). If x is 0 or a positive integer, it represents the current bit reliability value (CURRENT BRV). Fig.23 As shown, when i=0, some inputs of the multiplexer may correspond to previous bit reliability values ​​(PREVIOUS BRV).

[0169] The first multiplexer 621 can select and output one of the four bit reliability values ​​BRV[4*i+0], BRV[4*i-1], BRV[4*i-2] and BRV[4*i-3] based on the offset value OFS[1:0]. The second multiplexer 622 can select and output one of the four bit reliability values ​​BRV[4*i+1], BRV[4*i+0], BRV[4*i-1] and BRV[4*i-2] based on the offset value OFS[1:0]. The third multiplexer 623 can select and output one of the four bit reliability values ​​BRV[4*i+2], BRV[4*i+1], BRV[4*i+0] and BRV[4*i-1] based on the offset value OFS[1:0]. The fourth multiplexer 624 may select and output one of the four bit reliability values ​​BRV[4*i+3], BRV[4*i+2], BRV[4*i+1], and BRV[4*i+0] based on the offset value OFS[1:0].

[0170] The OR gate 625 may perform an OR operation on the four-bit reliability values ​​output from the first multiplexer 621 , the second multiplexer 622 , the third multiplexer 623 , and the fourth multiplexer 624 to generate a symbol reliability value SRV[i] corresponding to the i-th ECC symbol ESMi.

[0171] Results, such as Fig. 22As shown, when the offset value OFS is 0, the current bit reliability value (CURRENT BRV) corresponding to positions 0 to 3 becomes the input of the OR operation. When the offset value OFS is 1, the previous bit reliability value (PREVIOUSBRV) corresponding to position 31 and the current bit reliability value (CURRENT BRV) corresponding to positions 0 to 2 become the input of the OR operation. When the offset value OFS is 2, the previous bit reliability value (PREVIOUS BRV) corresponding to positions 30 to 31 and the current bit reliability value (CURRENT BRV) corresponding to positions 0 to 1 become the input of the OR operation. When the offset value OFS is 3, the previous bit reliability value (PREVIOUSBRV) corresponding to positions 29 to 31 and the current bit reliability value (CURRENT BRV) corresponding to position 0 become the input of the OR operation.

[0172] In this way, the offset value OFS can be calculated based on the synchronization position value SYNC, and the received data bits RB and the bit reliability values ​​BRV can be grouped based on the offset value OFS.

[0173] Fig.24 is a diagram illustrating a PAM8 scheme in an electronic device according to some embodiments.

[0174] Fig.24 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 119, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 119, 120, 121, 122, 123, 12

[0175] With reference Figure 3C Similar to the description, a plurality of error determination ranges EDR12 to EDR72 for determining bit reliability values ​​may be set. As described above, a plurality of error determination ranges EDR12 to EDR72 may be determined by setting a plurality of upper soft decision reference values ​​and a plurality of lower soft decision reference values.

[0176] Fig.25 is a diagram illustrating an example of a method of generating a bit reliability value in an electronic device according to some embodiments, and Fig.26 is a diagram showing the implementation according to some embodiments Fig.25 A block diagram of an example of a receiving circuit of the method.

[0177] Reference Fig.25 , a plurality of main error decision ranges HEDR1, HEDR2, and HEDR3 and a plurality of subsidiary error decision ranges LEDR1, LEDR2, and LEDR3, respectively centered around a plurality of hard decision reference values ​​REF1, REF2, and REF3, may be set. Each of the plurality of subsidiary error decision ranges LEDR1, LEDR2, and LEDR3 may be wider than each of the plurality of main error decision ranges HEDR1, HEDR2, and HEDR3, that is, include the plurality of main decision determination ranges HEDR1, HEDR2, and HEDR3.

[0178] Multiple main error decision ranges HEDR1, HEDR2 and HEDR3 can be defined by multiple main soft decision reference values ​​HREF11, LREF11, HREF21, LREF21, HREF31 and LREF31, and multiple secondary error decision ranges LEDR1, LEDR2 and LEDR3 can be defined by multiple secondary soft decision reference values ​​HREF12, LREF12, HREF22, LREF22, HREF32 and LREF32.

[0179] Reference Fig.26 , the receiving circuit 700 may include a hard decision circuit HDC 710, a main soft decision circuit (HSDC) 720 and a sub soft decision circuit (LSDC) 730. Fig.26 In the figure, the analog-to-digital converter that converts the voltage level of the analog signal RS into the received digital value DRS is omitted.

[0180] The hard decision circuit 710 may be configured to generate a plurality of received data bits RB by comparing the received digital value DRS with a plurality of hard decision reference values ​​REF1 , REF2 , and REF3 , respectively.

[0181] The primary soft decision circuit 720 may be configured to generate a primary bit reliability value HBRV by comparing the received digital value DRS with a plurality of primary soft decision reference values ​​HREF11, LREF11, HREF21, LREF21, HREF31 and LREF31 to determine a plurality of bit reliability values ​​BRV among a plurality of bit reliability values ​​BRV.

[0182] The secondary soft decision circuit 730 may be configured to generate a secondary bit reliability value LBRV by comparing the received digital value DRS with a plurality of secondary soft decision reference values ​​HREF12, LREF12, HREF22, LREF22, HREF32, and LREF32 to determine a plurality of bit reliability values ​​BRV among a plurality of bit reliability values ​​BRV.

[0183] The main bit reliability value HBRV and the secondary bit reliability value LBRV represent different degrees of error occurrence probability of the corresponding received data bit RB. The main bit reliability value HBRV and the secondary bit reliability value LBRV can be used to appropriately adjust the number of error symbol candidates. For example, when the number of error symbol candidates is greater than the reference number, only the first value (e.g., "1") indicating a high error occurrence probability is assigned to the received data bits that belong to the main error decision range but not to the secondary error decision range, and the number of error symbol candidates can be reduced.

[0184] Fig. 27 is a diagram illustrating error correction performance of an electronic device according to some embodiments of the inventive concept.

[0185] exist Fig. 27 , the horizontal axis represents RBER (raw bit error rate), and the vertical axis represents retransmission request probability (RETRY PROBABILITY). The first graph CS1 represents the probability of retransmission request when error correction is performed according to the prior art, and the second graph CS2 represents the probability of retransmission request when error correction is performed according to an exemplary embodiment.

[0186] When the RBER is high, the probability of selecting an erroneous ECC symbol decreases, but when the RBER becomes low, the probability of selecting an erroneous ECC symbol greatly increases. The retransmission request probability is the probability of checking an error in an erroneous ECC symbol in PCIe 6.0 by CRC and requesting retransmission from a transmitting device. The lower the retransmission request probability, the lower the retransmission rate, which is beneficial to improving data transmission performance. If the position of a symbol with a high error probability is selected by a method according to an exemplary embodiment, the number of situations that can be corrected in a decoding circuit increases, thereby significantly improving the performance of an electronic device.

[0187] Fig.28 is a diagram illustrating an electronic device according to some embodiments.

[0188] Reference Fig.28 , system 1000 may include an electrical sub-block 1200 and a logical sub-block 1400 .

[0189] The electrical sub-block 1200 according to some embodiments may include an analog-to-digital converter ADC and a feed-forward equalizer EQ_FFE for each of the plurality of channels LANE0 to LANE3. When the electrical sub-block 1200 receives a 4-level PAM4 signal through a link, it may perform analog-to-digital conversion and equalization for each of the plurality of channels LANE0 to LANE3 through the analog-to-digital converter ADC and the feed-forward equalizer EQ_FFE to generate a conversion signal.

[0190] The electrical sub-block 1200 may be connected to the logic sub-block 1400 through a pipe (PIPE) and may be configured to send a conversion signal to the logic sub-block 1400. In some embodiments, the PIPE may be configured to convert signals transmitted between the electrical sub-block 1200 and the logic sub-block 1400 by serialization or parallelization.

[0191] The logic sub-block 1400 may include an ECC decoder 1410, a CRC decoder 1420, and an erasure decoder 1430. Fig.13 As described, the ECC decoder 1410 may be configured to perform ECC decoding on a microchip (FLIT), and the CRC decoder 1420 may be configured to obtain data by performing CRC decoding on the ECC-decoded microchip (D_FLIT). If the CRC decoding fails, the CRC decoder 1420 may be configured to notify the erasure decoder 1430 of the CRC decoding failure.

[0192] When the erasure decoder 1430 finds that the CRC decoding fails, the erasure decoder 1430 may be configured to extract the error symbol candidate based on the symbol reliability value generated by the method according to some embodiments and perform erasure decoding. If the erasure decoding is successful, the erasure decoder 1430 may transmit the decoded signal to the CRC decoder 1420, and the CRC decoder 1420 re-executes the CRC decoding. If the re-execution of the CRC decoding fails, the CRC decoder 1420 may request the transmitter to retransmit the transmission micro-chip.

[0193] As described above, the electronic device and the method of operating the electronic device according to some embodiments can effectively generate the symbol reliability value of the ECC symbol based on the voltage level of the analog signal received through the link, can extract the error symbol candidate and can improve the error correction capability of the electronic device.

[0194] The inventive concept provided herein can be applied to many different types of electronic devices and systems. For example, the inventive concept provided herein can be applied to various systems, examples of which include memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, notebook computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, autonomous driving systems, etc.

[0195] The foregoing is illustrative of some embodiments and should not be construed as limiting them. Although some examples of embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the examples of embodiments described herein without substantially departing from the inventive concept.

Claims

1. An electronic device, comprising: a receiving circuit configured to generate a plurality of received data bits based on a voltage level of an analog signal received over a link, and configured to generate a plurality of bit reliability values ​​indicating probability of error occurrence of the plurality of received data bits based on the voltage level of the analog signal; an alignment circuit configured to group the plurality of received data bits into a plurality of ECC symbols and to generate a plurality of symbol reliability values ​​indicating error occurrence probabilities of the plurality of ECC symbols based on the plurality of bit reliability values, the ECC being an error correction code; as well as A decoding circuit is configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

2. The electronic device according to claim 1, wherein: The receiving circuit comprises: an analog-to-digital converter configured to convert the voltage level of the analog signal into a received digital value; a hard decision circuit configured to generate the plurality of received data bits based on a comparison of the received digital value with a plurality of hard decision reference values; and A soft decision circuit is configured to generate the plurality of bit reliability values ​​based on a comparison of the received digital value with a plurality of soft decision reference values ​​indicating a plurality of error decision ranges, wherein each error decision range is centered around each hard decision reference value.

3. The electronic device according to claim 2, wherein: The soft decision circuit is further configured to: when the received digital value is included in the multiple error decision ranges, determine each bit reliability value as a first value indicating a high error occurrence probability, and when the received digital value is not included in the multiple error decision ranges, determine each bit reliability value as a second value indicating a low error occurrence probability.

4. The electronic device according to claim 3, wherein: The alignment circuit is also configured to: when at least one bit reliability value corresponding to each ECC symbol has the first value, determine each symbol reliability value corresponding to each ECC symbol as a third value indicating that each ECC symbol is an error symbol candidate with a high error occurrence probability, and when all bit reliability values ​​corresponding to each ECC symbol have the second value, determine each symbol reliability value corresponding to each ECC symbol as a fourth value indicating that each ECC symbol is a symbol with a low error occurrence probability.

5. The electronic device according to claim 4, wherein: The receiving circuit is further configured to adjust the plurality of soft decision reference values ​​indicating the error decision range based on the number of error symbol candidates corresponding to the third value.

6. The electronic device according to claim 5, wherein: The receiving circuit is further configured to: when the number of the erroneous symbol candidates corresponding to the third value is greater than the reference number, adjust the multiple soft decision reference values ​​so that each erroneous decision range is reduced, and wherein the receiving circuit is further configured to: when the number of the erroneous symbol candidates corresponding to the third value is less than the reference number, adjust the multiple soft decision reference values ​​so that each erroneous decision range is increased.

7. The electronic device according to claim 2, wherein: Each error decision range corresponds to a range between an upper soft decision reference value and a lower soft decision reference value, wherein the upper soft decision reference value is greater than each hard decision reference value by a threshold value, and the lower soft decision reference value is less than each hard decision reference value by the threshold value.

8. The electronic device according to claim 1, wherein: The alignment circuit is also configured to generate a synchronization position value indicating the position of a data block based on monitoring of a data pattern included in the multiple received data bits, wherein the data block indicates a unit of error correction of the decoding circuit, wherein the alignment circuit is further configured to group the multiple received data bits into the multiple ECC symbols based on the synchronization position value, and wherein the alignment circuit is further configured to group the multiple bit reliability values ​​into multiple reliability symbols aligned with the multiple ECC symbols based on the synchronization position value.

9. The electronic device according to claim 8, wherein: The alignment circuit is further configured to generate a per-symbol reliability value indicating an error occurrence probability of each ECC symbol by performing a logical OR operation on the bit reliability values ​​included in each reliability symbol.

10. The electronic device according to claim 1, wherein: The receiving circuit comprises: a hard decision circuit configured to generate the plurality of received data bits based on a comparison of the voltage level of the analog signal to a plurality of hard decision reference voltages; and A soft decision circuit is configured to generate the plurality of bit reliability values ​​based on a comparison of the voltage level of the analog signal with a plurality of soft decision reference voltages indicating a plurality of error decision ranges, wherein each error decision range is centered around each hard decision reference voltage.

11. The electronic device according to claim 1, wherein: The receiving circuit comprises: an analog-to-digital converter configured to convert the voltage level of the analog signal into a received digital value; a hard decision circuit configured to generate the plurality of received data bits based on a comparison of the received digital value with a plurality of hard decision reference values; a primary soft decision circuit configured to generate a plurality of primary bit reliability values ​​based on a comparison of the received digital value with a plurality of primary soft decision reference values ​​indicating a plurality of primary error decision ranges, wherein each primary error decision range is centered around each hard decision reference value; and A secondary soft decision circuit is configured to generate a plurality of secondary bit reliability values ​​based on comparison of the received digital value with a plurality of secondary soft decision reference values ​​indicating a plurality of secondary error decision ranges, wherein each secondary error decision range is wider than each primary error decision range.

12. The electronic device according to claim 1, wherein: The alignment circuit is further configured to provide the plurality of ECC symbols and the plurality of symbol reliability values ​​aligned with the plurality of ECC symbols to the decoding circuit without considering an error correction failure of the decoding circuit.

13. The electronic device according to claim 1, wherein: The link complies with the Peripheral Component Interconnect Express standard, and the analog signal is a pulse amplitude modulated 4 signal.

14. The electronic device according to claim 13, wherein: The multiple ECC symbols are Reed-Solomon symbols, and the decoding circuit is further configured to: when error correction for the multiple ECC symbols fails, perform Reed-Solomon erasure decoding by extracting error symbol candidates from the multiple ECC symbols based on the multiple symbol reliability values.

15. The electronic device according to claim 13, wherein: The receiving circuit is further configured to generate a bit reliability value of one bit for every two received data bits, and Wherein, the alignment circuit is further configured to: generate a synchronization position value indicating the position of a data block by monitoring a data pattern included in the plurality of received data bits, wherein the data block indicates a unit of error correction of the decoding circuit, and the data pattern corresponds to an electrical idle exit ordered set according to the Peripheral Component Interconnect Express standard; and group the plurality of received data bits into the plurality of ECC symbols based on the synchronization position value.

16. The electronic device according to claim 13, wherein: The decoding circuit comprises: an ECC decoder configured to decode a flits including the plurality of ECC symbols in units of ECC groups, wherein the flits are defined by the Peripheral Component Interconnect Express standard; a cyclic redundancy check decoder configured to perform cyclic redundancy check decoding on the ECC decoded flits; and An erasure decoder is configured to: when the cyclic redundancy check decoding fails, extract at least one error symbol candidate from the multiple ECC symbols based on the multiple symbol reliability values ​​provided from the alignment circuit, and perform ECC decoding by erasing the at least one error symbol candidate.

17. An electronic device, comprising: a receiving circuit configured to generate a plurality of received data bits based on a voltage level of a pulse amplitude modulated 4 signal received through a link, and to generate a plurality of bit reliability values ​​indicating error occurrence probabilities of the plurality of received data bits based on the voltage level of the pulse amplitude modulated 4 signal; an alignment circuit configured to: generate a synchronization position value indicating a position of a data block by monitoring a data pattern included in the plurality of received data bits, wherein the data block indicates a unit of error correction; group the plurality of received data bits into a plurality of ECC symbols based on the synchronization position value; and generate a plurality of symbol reliability values ​​based on the synchronization position value and the plurality of bit reliability values, wherein the plurality of symbol reliability values ​​indicate error occurrence probabilities of the plurality of ECC symbols and are aligned with the plurality of ECC symbols, the ECC being an error correction code; and A decoding circuit is configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

18. The electronic device according to claim 17, wherein: The alignment circuit is also configured to: group the multiple bit reliability values ​​into multiple reliability symbols aligned with the multiple ECC symbols based on the synchronization position value, and generate each symbol reliability value indicating the error occurrence probability of each ECC symbol by performing a logical OR operation on the bit reliability value included in each reliability symbol.

19. The electronic device according to claim 18, wherein: Each ECC symbol corresponds to eight bits and each reliability symbol corresponds to four bits, and The alignment circuit is further configured to: obtain a remainder by dividing the synchronization position value by eight, generate an alignment value by dividing the remainder by two, and determine a starting point of each reliability symbol based on the alignment value.

20. A method of operating an electronic device, the method comprising: generating a plurality of received data bits based on a voltage level of an analog signal received over the link; generating a plurality of bit reliability values ​​indicating probability of error occurrence of the plurality of received data bits based on the voltage level of the analog signal; Grouping the plurality of received data bits into a plurality of ECC symbols, wherein the ECC is an error correction code; generating a plurality of symbol reliability values ​​indicating error occurrence probabilities of the plurality of ECC symbols based on the plurality of bit reliability values; as well as Errors of the plurality of ECC symbols are corrected based on the plurality of symbol reliability values.

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