Memory cell, memory and preparation method thereof

Abstract

The invention relates to the field of semiconductor integrated circuits, and provides a memory cell, a memory and a preparation method thereof. The storage unit comprises a grid electrode, a first isolation layer, a second isolation layer, a third isolation layer, a first electrode, a second electrode, a dielectric layer, a channel layer, a first etching groove and a second etching groove, the bottom end of the first electrode is positioned on the top end surface of the substrate; the bottom end of the first isolation layer is located at the top end of the first electrode; the bottom end of the grid electrode is located at the top end of the first isolation layer; the bottom end of the second isolation layer is located at the top end of the grid electrode; the channel layer is provided with a second part and two first parts; the second part is provided with central recesses positioned in two top end areas, and the two first parts are positioned in the two top end areas of the second part in a one-to-one correspondence manner; the bottom end of the first part is positioned at the top end of the horizontal medium part; the storage unit is used for reducing the physical size of the storage unit, so that the stacking density of the three-dimensional memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a storage unit, a memory and a preparation method thereof. Background Art

[0002] As the size of memory cells continues to shrink, the difficulty of quantum effects and process control increases significantly, resulting in a decrease in the reliability and performance of memory cells. The related art mainly relies on the number of stacked layers to increase storage capacity, but physical limitations limit the possibility of further expansion. When the number of layers continues to increase, the manufacturing process faces process limits. Continuing to reduce the cell size and increase the number of stacked layers, thereby further improving memory performance and density, requires the use of more advanced materials and device technologies. Therefore, there is an urgent need for a memory cell, a memory, and a method for preparing the same to improve the above problems. Summary of the invention

[0003] The object of the present invention is to provide a storage unit, a memory and a method for preparing the same, wherein the storage unit is used to reduce the physical size of the storage unit, thereby increasing the stacking density of the three-dimensional memory.

[0004] In a first aspect, the present invention provides a storage unit, comprising: a gate, a first isolation layer, a second isolation layer, a third isolation layer, a first electrode, a second electrode, a dielectric layer, a channel layer, a first etching groove, and a second etching groove; the bottom end of the first electrode is located at the top surface of the substrate; the bottom end of the first isolation layer is located at the top of the first electrode; the bottom end of the gate is located at the top of the first isolation layer; the bottom end of the second isolation layer is located at the top of the gate; the first isolation layer and the second isolation layer are both used to provide electrical isolation for the gate; the first etching groove penetrates the second isolation layer, the gate, and the first isolation layer in a vertical direction; The first etching groove is used to form the outer contour of the channel layer; the dielectric layer includes two unconnected sub-dielectric regions, each of which has a vertical dielectric portion and a horizontal dielectric portion connected to each other; the bottom end of the vertical dielectric portion is located at the top of the first electrode; the vertical dielectric portion is located in the first etching groove, and the first isolation layer, the gate and the second isolation layer are connected to the vertical dielectric portion on one side facing the first etching groove; the bottom end of the horizontal dielectric portion is located at the top of the second isolation layer; the dielectric layer is used to store charges to control the working state of the channel layer to be a conducting state or a cut-off state; the channel layer has a second portion and two first portions; the second portion has a central concave portion located at two top regions The second electrode is provided with a first electrode and a second electrode respectively. The first electrode has a first electrode and a second electrode respectively. The first electrode has a first electrode and a second electrode respectively. The first electrode has a first electrode and a second electrode respectively. The first electrode has a first electrode and a second electrode respectively. The first electrode has a first electrode and a second electrode respectively. The second electrode has a first electrode and a second electrode respectively. The first electrode has a first electrode and a second electrode respectively.

[0005] Optionally, the gate has a thickness less than 5 nm; and the gate is made of a material with a resistivity less than 30 μΩ·cm.

[0006] Optionally, the memory cell is configured as a floating gate memory cell; the dielectric layer includes a stacked barrier layer, a capture layer and a tunneling layer; the tunneling layer is connected to the channel layer; the barrier layer is connected to the second isolation layer; when reading data, the gate of the floating gate memory cell is used to provide a transfer curve under different read voltages, and the read voltage is lower than the voltage that causes electron tunneling; the transfer curve is used to calculate the threshold voltage of the floating gate memory cell to determine the data storage state; the storage state corresponding to the larger threshold voltage is the programming state, and the storage state corresponding to the smaller threshold voltage is the erasing state.

[0007] Optionally, when a positive voltage pulse is applied to the gate, electrons in the channel layer are injected into the capture layer through the tunneling layer, so that part of the electrons are stored in the capture layer, and the floating gate memory cell is written to a programmed state; when a negative voltage pulse is applied to the gate, electrons in the capture layer are tunneled into the channel layer, the first electrode or the second electrode, so that electrons in the capture layer are lost, and the floating gate memory cell is written to an erased state.

[0008] Optionally, the gate is prepared by an atomic layer deposition (ALD) process; the second portion is configured to be perpendicular to the surface of the substrate; and the thickness of the gate is used to define the overall thickness of the first isolation layer, the gate and the second isolation layer.

[0009] Optionally, the first etching groove is used to form side walls on the horizontal sides of the first isolation layer, the gate and the second isolation layer; the top of the second isolation layer and the side walls and top wall are used to continuously prepare the blocking layer, the capture layer, the tunneling layer and the channel layer using an atomic layer deposition process.

[0010] Optionally, the storage unit is configured as a ferroelectric storage unit; the dielectric layer includes a ferroelectric dielectric; the ferroelectric dielectric has two polarization states with opposite polarization directions; when reading data, the gate of the ferroelectric storage unit is used to provide a transfer curve under different read voltages, and the read voltage is lower than the voltage that changes the polarization direction of the ferroelectric dielectric; the transfer curve is used to calculate the threshold voltage of the ferroelectric storage unit to determine the data storage state; the storage state corresponding to the larger threshold voltage is the programming state, and the storage state corresponding to the smaller threshold voltage is the erasing state.

[0011] Optionally, when a positive voltage pulse is applied to the gate, the polarization direction of the ferroelectric medium is directed toward the opposite direction of the gate, and the ferroelectric memory cell is written to a programming state; when a negative voltage pulse is applied to the gate, the polarization direction of the ferroelectric medium is directed toward the gate direction, and the ferroelectric memory cell is written to an erased state.

[0012] Optionally, the first electrode is set as a source, and the second electrode is set as a drain; or the second electrode is set as a source, and the first electrode is set as a drain.

[0013] In a second aspect, the present invention provides a memory comprising a reading unit, a writing unit and at least one storage unit as described in any one of the first aspects; the reading unit is connected to the storage unit; the reading unit is used to read data in the storage unit; the writing unit is connected to the storage unit; the writing unit is used to write data into the storage unit.

[0014] In a third aspect, the present invention provides a method for preparing a storage unit, which is used in any one of the methods in the first aspect, comprising: providing a substrate; forming a first electrode on the substrate; forming a first isolation layer on the first electrode; forming a gate on the first isolation layer; forming a second isolation layer on the gate; performing a first etching based on the second isolation layer to form a first etching groove, the first etching groove vertically penetrating the second isolation layer, the gate and the first isolation layer; forming a dielectric layer in the first etching groove and on the second isolation layer; performing a second etching based on the dielectric layer to form a second etching groove; the second etching groove vertically penetrating the second isolation layer, the gate, the first isolation layer and the dielectric layer, dividing the dielectric layer into two unconnected sub-dielectric areas; the bottom end of the second etching groove is set as the top of the substrate; a channel layer is formed in the second etching groove and at the top of the dielectric layer; the channel layer has a first portion located at the top of the dielectric layer and a second portion located in the second etching groove; the second portion forms a gap open upward; a filling layer is formed in the gap and at the top of the channel layer; the filling layer at the top of the channel layer is etched, and the filling layer in the gap is retained as a third isolation layer; a second electrode is formed at the top of the third isolation layer and at the top of the channel layer.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: the channel layer provided in the present application adopts oxide semiconductor material, which improves the switching speed of the storage unit, thereby improving the read and write performance of the overall memory; the oxide semiconductor material as the channel layer can reduce the leakage current, reduce the energy consumption of the storage unit in the non-working state, and can maintain good transistor characteristics at a shorter channel length, effectively suppressing the short channel effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of a storage unit provided by the present invention; Figure 2 A structural schematic diagram of a floating gate storage unit provided by the present invention; Figure 3 A schematic structural diagram of a ferroelectric memory cell provided by the present invention; Figure 4 A schematic diagram of the structure of a memory provided by the present invention; Figure 5 A schematic flow chart of a method for preparing a storage unit provided by the present invention.

[0017] Description of reference numerals in the figures: 1. substrate; 2. first electrode; 3. first isolation layer; 4. gate; 5. second isolation layer; 60. dielectric layer; 6. barrier layer; 7. capture layer; 8. tunneling layer; 9. channel layer; 10. third isolation layer; 11. second electrode; 20. Memory; 21. Storage unit; 22. Read unit; 23. Write unit. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0019] In the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0020] In view of the problems existing in the existing technology, such as Figure 1As shown, the first embodiment provides a storage unit, including: a gate 4, a first isolation layer 3, a second isolation layer 5, a third isolation layer 10, a first electrode 2, a second electrode 11, a dielectric layer 60, a channel layer 9, a first etching groove and a second etching groove; the bottom end of the first electrode 2 is located at the top surface of the substrate 1; the bottom end of the first isolation layer 3 is located at the top of the first electrode 2; the bottom end of the gate 4 is located at the top of the first isolation layer 3; the bottom end of the second isolation layer 5 is located at the top of the gate 4; the first isolation layer 3 and the second isolation layer 5 are both used to provide electrical isolation for the gate 4; the first etching groove penetrates the second isolation layer 5, the gate 4 and the first isolation layer 3 in the vertical direction; The first etching groove is used to form the outer contour of the channel layer 9; the dielectric layer 60 includes two unconnected sub-dielectric regions, each of which has a vertical dielectric portion and a horizontal dielectric portion connected to each other; the bottom end of the vertical dielectric portion is located at the top of the first electrode 2; the vertical dielectric portion is located in the first etching groove, and the first isolation layer 3, the gate 4 and the second isolation layer 5 are connected to the vertical dielectric portion on one side of the first etching groove; the bottom end of the horizontal dielectric portion is located at the top of the second isolation layer 5; the dielectric layer 60 is used to store charges to control the working state of the channel layer 9 to be on or off; the channel layer 9 has a second portion and two first portions; the second portion has a central depression located at two top regions, and the two The first parts are located in two top areas of the second part in a one-to-one correspondence; the bottom end of the first part is located at the top of the horizontal dielectric part; the second part is located in the second etching groove; the second part and the first electrode 2 constitute the second etching groove; a third isolation layer 10 is provided between the two first parts; the third isolation layer 10 fills the central recess; the channel is made of oxide semiconductor material; when the gate 4 applies a preset voltage, the channel layer 9 enters a conductive state, allowing current to form between the first electrode 2 and the second electrode 11; the bottom end of the second electrode 11 is located at the top of the two first parts and the top of the third isolation layer 10; the first electrode 2 and the second electrode 11 are used to provide input and output paths for electrical signals.

[0021] In some specific embodiments, the top direction is set to the Z direction. The horizontal direction is set to the X direction or the anti-X direction. The X direction and the Z direction are perpendicular to each other.

[0022] In some other specific embodiments, the memory cell is a gate-all-around 4 transistor (Gate-All-AroundFET, GAA) or a thin film transistor (Thin Film Transistor, TFT). The oxide semiconductor used in the channel includes a monovalent oxide, a binary oxide, or a multivalent oxide semiconductor material. In some examples, the monovalent oxide semiconductor material includes ZnO x 、GaO x 、InO x SnO x 、NiO x , CuO x , WO x , VO x In some other examples, the binary oxide semiconductor material includes a binary oxide composed of two elements of Al, Zn, Ga, In, Sn, Ni, Cu, W, Er, La, V, Ti, Ta, Bi, and Y. In some other examples, the multinary oxide semiconductor material includes a multinary oxide composed of at least three elements of Al, Zn, Ga, In, Sn, Ni, Cu, W, Er, La, V, Ti, Ta, Bi, and Y.

[0023] It is worth mentioning that oxide semiconductor materials have shown broad application prospects in the next generation of electronic devices due to their advantages such as high carrier mobility, low leakage current and suppression of short channel effects. Compared with traditional silicon-based TFTs, oxide TFTs have better performance and manufacturing potential, especially in the preparation of low-power, ultra-short gate length devices. Therefore, the development of oxide thin film transistors provides a new opportunity for building high-density three-dimensional memories. As the size of devices decreases, ultra-short gate length technology becomes the key to improving memory density and speed. Ultra-short gate length TFTs can provide faster switching speeds and lower power consumption. The shortening of the gate length allows the size of the device to be further reduced, thereby achieving higher integration and storage density.

[0024] The channel layer 9 of this embodiment uses oxide semiconductor material to improve the switching speed of the storage unit, thereby improving the read and write performance of the overall memory; oxide semiconductor material as the channel layer 9 can reduce leakage current, reduce the energy consumption of the storage unit in the non-working state, maintain good transistor characteristics at a shorter channel length, and effectively suppress the short channel effect.

[0025] In some embodiments, the thickness of the gate 4 is less than 5 nm; the gate 4 is made of a material with a resistivity less than 30 μΩ•cm.

[0026] Specifically, the gate 4 is configured as a gate 4 thin film, and the material of the gate 4 includes metals Ru, Mo, Ta and Ti. In other specific embodiments, the material of the gate 4 includes an alloy of metals Ru, Mo, Ta and Ti. In some other specific embodiments, the material of the gate 4 includes metal oxides of metals Ru, Mo, Ta and Ti. In some other specific embodiments, the material of the gate 4 includes nitrides of metals Ru, Mo, Ta and Ti.

[0027] In some embodiments, the gate 4 is prepared by an atomic layer deposition process; the second portion is configured to be perpendicular to the surface of the substrate 1; and the thickness of the gate 4 is used to define the overall thickness of the first isolation layer 3, the gate 4 and the second isolation layer 5.

[0028] like Figure 2 As shown, in some embodiments, the memory cell is configured as a floating gate memory cell; the dielectric layer 60 includes a stacked barrier layer 6, a capture layer 7, and a tunneling layer 8; the tunneling layer 8 is connected to the channel layer 9; the barrier layer 6 is connected to the second isolation layer 5; when reading data, the gate 4 of the floating gate memory cell is used to provide a transfer curve under different read voltages, and the read voltage is lower than the voltage that causes electrons to tunnel; the transfer curve is used to calculate the threshold voltage of the floating gate memory cell to determine the data storage state; the storage state corresponding to the larger threshold voltage is the programming state, and the storage state corresponding to the smaller threshold voltage is the erasing state.

[0029] It is worth noting that the barrier layer 6, the capture layer 7 and the tunneling layer 8 together form an oxide-nitride-oxide (ONO) structure. The oxide may be a binary oxide or a multi-element oxide; the nitride may be a binary nitride or a multi-element nitride.

[0030] In some examples, the barrier layer 6 is a stack of at least one material including SiO2, Si3N4, Al2O3, HfO2, ZrO2, Ta2O5, and Y2O3; in other examples, the barrier layer 6 is configured as an oxide or nitride composed of at least two of the elements Si, Al, Hf, Zr, Ba, Ti, Ta, and Y.

[0031] In some embodiments, the charge trapping layer 7 includes a floating gate dielectric, a metal floating gate, a nano-metal, or an oxide floating gate.

[0032] The floating gate dielectric is configured as a stack of one or more of SiO2, Si3N4, Al2O3, HfO2, ZrO2, Ta2O5, Y2O3, or a binary or multi-component oxide or nitride composed of two or more of Si, Al, Hf, Zr, Ba, Ti, Ta, Y. The nanometal is configured as Au or Pt.

[0033] The metal floating gate is set to Mg, Al, Sc, Ti, V, Cr, Mn, Ni, Cu, Zn, Ga, Zr, Nb, Mo, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Ir, Pt, Au, Bi, Co, Ru, or alloys of two or more of these metals, or oxides or nitrides of these metal units or multiples.

[0034] The oxide floating gate is set to ZnOx, GaOx, InOx, SnOx, NiOx, CuOx, WOx, VOx; a binary or multi-element oxide composed of two or more elements of Al, Zn, Ga, In, Sn, Ni, Cu, W, Er, La, V, Ti, Ta, Bi, and Y.

[0035] The tunneling layer 8 includes a stack of one or more of SiO2, Si3N4, Al2O3, HfO2, ZrO2, Ta2O5, and Y2O3, or a binary or multi-component oxide or nitride composed of two or more of the elements Si, Al, Hf, Zr, Ba, Ti, Ta, and Y.

[0036] In some embodiments, when the gate 4 applies a positive voltage pulse, the electrons in the channel layer 9 are injected into the capture layer 7 through the tunneling layer 8, so that part of the electrons are stored in the capture layer 7, and the floating gate memory cell is written to a programmed state; when the gate 4 applies a negative voltage pulse, the electrons in the capture layer 7 are tunneled into the channel layer 9, the first electrode 2 or the second electrode 11, so that the electrons in the capture layer 7 are lost, and the floating gate memory cell is written to an erased state.

[0037] In some examples, when a positive voltage pulse is applied to the gate 4, the positive voltage generates a strong electric field in the channel layer 9, causing the electrons in the channel layer 9 to obtain sufficient energy, pass through the insulating tunneling layer 8 through the tunneling effect, and then be injected into the capture layer 7. As the electrons are continuously injected, some of them will be captured and stored in the capture layer 7. This process is called a programming operation, which puts the floating gate memory cell into a programming state.

[0038] In other examples, when a negative voltage pulse is applied to the gate 4, the direction of the electric field generated by the negative voltage is opposite to that during programming, causing the electrons in the capture layer 7 to regain energy and tunnel back to the channel layer 9, the first electrode 2 or the second electrode 11 through the tunneling effect. As the electrons are lost, the number of electrons in the capture layer 7 decreases, thereby achieving an erase operation and causing the floating gate memory cell to enter an erase state.

[0039] It is worth noting that, in this embodiment, different voltage pulses are applied to control the programming and erasing of the floating gate memory cell, thereby realizing the functions of storing and deleting data.

[0040] In some embodiments, the first etching groove is used to form side walls on the horizontal sides of the first isolation layer 3, the gate 4 and the second isolation layer 5; the top of the second isolation layer 5 and the side walls and top wall are used to continuously prepare the barrier layer 6, the capture layer 7, the tunneling layer 8 and the channel layer 9 using an atomic layer deposition process.

[0041] like Figure 3 As shown, in some embodiments, the storage unit is configured as a ferroelectric storage unit; the dielectric layer 60 includes a ferroelectric dielectric; the ferroelectric dielectric has two polarization states with opposite polarization directions; when reading data, the gate 4 of the ferroelectric storage unit is used to provide a transfer curve under different read voltages, and the read voltage is lower than the voltage that changes the polarization direction of the ferroelectric dielectric; the transfer curve is used to calculate the threshold voltage of the ferroelectric storage unit to determine the data storage state; the storage state corresponding to the larger threshold voltage is the programming state, and the storage state corresponding to the smaller threshold voltage is the erasing state.

[0042] In some specific embodiments, the programming state is set to a data set 1 state, and the erasing state is set to a data set 0 state. In other specific embodiments, the programming state is set to a data set 0 state, and the erasing state is set to a data set 1 state.

[0043] In some other specific embodiments, the ferroelectric dielectric is made of Hf-based ferroelectric materials. In some examples, the Hf-based ferroelectric materials include HfOx, HfZrO, HfAlO, HfSiO and HfTiO.

[0044] In some embodiments, when a positive voltage pulse is applied to the gate 4, the polarization direction of the ferroelectric medium is directed toward the opposite direction of the gate 4, and the ferroelectric memory cell is written to a programming state; when a negative voltage pulse is applied to the gate 4, the polarization direction of the ferroelectric medium is directed toward the direction of the gate 4, and the ferroelectric memory cell is written to an erased state.

[0045] In some specific embodiments, the first electrode 2 is set as a source electrode, and the second electrode 11 is set as a drain electrode; in other specific embodiments, the second electrode 11 is set as a source electrode, and the first electrode 2 is set as a drain electrode.

[0046] In some examples, the source and drain are made of one of the following metals: Mg, Al, Sc, Ti, V, Cr, Mn, Ni, Cu, Zn, Ga, Zr, Nb, Mo, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Ir, Pt, Au, Bi, Co, Ru; or alloys, metal oxides or metal nitrides containing these metals. The alloy is set as a binary or multinary alloy. The metal oxide is set as at least a unit metal oxide, a binary metal oxide or a multinary metal oxide. The metal nitride is set as at least a unit metal nitride, a binary metal nitride or a multinary metal nitride.

[0047] like Figure 4 As shown, the second embodiment provides a memory, comprising a reading unit, a writing unit and at least one storage unit as described in any one of the above embodiments; the reading unit is connected to the storage unit; the reading unit is used to read data in the storage unit; the writing unit is connected to the storage unit; the writing unit is used to write data into the storage unit.

[0048] In some specific embodiments, the reading unit is configured as a data reading circuit. The writing unit is configured as a data writing circuit.

[0049] It is worth noting that at any given time, only one of the data reading circuit and the data writing circuit will establish a connection with the storage unit, while the other will remain disconnected. This design ensures that during the reading or writing process, the two circuits will not operate the storage unit at the same time, thus effectively avoiding potential data conflicts or corruption issues.

[0050] The memory proposed in the above embodiment is highly compatible with existing commercial memory processes and architectures, is suitable for application in high-density three-dimensional integrated chips, and has broad application prospects.

[0051] like Figure 5As shown, the third embodiment provides a method for preparing a memory cell, which is used in any of the methods in the above embodiments, comprising: providing a substrate 1; forming a first electrode 2 on the substrate 1; forming a first isolation layer 3 on the first electrode 2; forming a gate 4 on the first isolation layer 3; forming a second isolation layer 5 on the gate 4; performing a first etching based on the second isolation layer 5 to form a first etching groove, the first etching groove vertically penetrating the second isolation layer 5, the gate 4 and the first isolation layer 3; forming a dielectric layer 60 in the first etching groove and on the second isolation layer 5; performing a second etching based on the dielectric layer 60 to form a second etching groove; the second etching groove vertically penetrating the second isolation layer 5, the gate 4, the first isolation layer 3 and the dielectric layer 60, dividing the dielectric layer 60 into two unconnected sub-dielectric areas; the bottom end of the second etching groove is set as the top of the substrate 1; a channel layer 9 is formed in the second etching groove and at the top of the dielectric layer 60; the channel layer 9 has a first portion located at the top of the dielectric layer 60 and a second portion located in the second etching groove; the second portion forms a gap open upward; a filling layer is formed in the gap and at the top of the channel layer 9; the filling layer at the top of the channel layer 9 is etched, and the filling layer in the gap is retained as a third isolation layer 10; a second electrode 11 is formed at the top of the third isolation layer 10 and at the top of the channel layer 9.

[0052] In some specific embodiments, when the gate 4 is formed on the first isolation layer 3 , the gate 4 is formed on the first isolation layer 3 by using an ALD process.

[0053] In some other specific embodiments, the dielectric layer 60 includes a stacked barrier layer 6, a charge trapping layer 7 and a tunneling layer 8. The barrier layer 6, the charge trapping layer 7, the tunneling layer 8 and the channel layer 9 are continuously prepared using an ALD process. This embodiment itself can obtain a thin film stack with excellent interface quality, ensure the interface quality between the dielectric layer and the channel, and is beneficial to improving the performance of the memory.

[0054] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A storage unit, characterized in that: include: A gate, a first isolation layer, a second isolation layer, a third isolation layer, a first electrode, a second electrode, a dielectric layer, a channel layer, a first etching groove, and a second etching groove; The bottom end of the first electrode is located at the top end of the substrate; the bottom end of the first isolation layer is located at the top end of the first electrode; The bottom end of the gate is located at the top end of the first isolation layer; the bottom end of the second isolation layer is located at the top end of the gate; the first isolation layer and the second isolation layer are both used to provide electrical isolation for the gate; The first etching groove penetrates the second isolation layer, the gate and the first isolation layer in a vertical direction; The first etching groove is used to form an outer contour of the channel layer; The dielectric layer includes two unconnected sub-dielectric regions, each of which has a vertical dielectric portion and a horizontal dielectric portion connected to each other; the bottom end of the vertical dielectric portion is located at the top end of the first electrode; the vertical dielectric portion is located in the first etching groove, and the first isolation layer, the gate and the second isolation layer are connected to the vertical dielectric portion on one side facing the first etching groove; the bottom end of the horizontal dielectric portion is located at the top end of the second isolation layer; the dielectric layer is used to store charges to control the working state of the channel layer to be an on state or an off state; The channel layer comprises a second portion and two first portions; the second portion comprises a central depression located at two top regions, and the two first portions are located in two top regions of the second portion in a one-to-one correspondence; the bottom end of the first portion is located at the top of the horizontal dielectric portion; the second portion is located in the second etching groove; the second portion and the first electrode constitute the second etching groove; a third isolation layer is provided between the two first portions; the third isolation layer is filled in the central depression; the channel is made of an oxide semiconductor material; when a preset voltage is applied to the gate, the channel layer enters a conducting state, allowing a current to be formed between the first electrode and the second electrode; The bottom end of the second electrode is located at the top ends of the two first portions and the top end of the third isolation layer; the first electrode and the second electrode are used to provide an input path and an output path for electrical signals.

2. The storage unit according to claim 1, characterized in that The gate has a thickness of less than 5 nm; the gate is made of a material with a resistivity less than 30 μΩ·cm.

3. The storage unit according to claim 1, characterized in that The memory cell is configured as a floating gate memory cell; the dielectric layer comprises a stacked barrier layer, a capture layer and a tunneling layer; the tunneling layer is connected to the channel layer; the barrier layer is connected to the second isolation layer; When reading data, the gate of the floating gate storage unit is used to provide a transfer curve under different read voltages, and the read voltage is lower than the voltage that causes electron tunneling; the transfer curve is used to calculate the threshold voltage of the floating gate storage unit to determine the data storage state; the storage state corresponding to the larger threshold voltage is the programming state, and the storage state corresponding to the smaller threshold voltage is the erasing state.

4. The storage unit according to claim 3, characterized in that When a positive voltage pulse is applied to the gate, electrons in the channel layer are injected into the capture layer through the tunnel layer, so that part of the electrons are stored in the capture layer, and the floating gate memory cell is written into a programming state; When a negative voltage pulse is applied to the gate, electrons in the capture layer are tunneled into the channel layer, the first electrode or the second electrode, so that electrons in the capture layer are lost and the floating gate memory cell is written into an erased state.

5. The storage unit according to claim 3, characterized in that: The gate is prepared by an atomic layer deposition process; the second portion is configured to be perpendicular to the surface of the substrate; and the thickness of the gate is used to define the overall thickness of the first isolation layer, the gate and the second isolation layer.

6. The storage unit according to claim 3, characterized in that: The first etching groove is used to form sidewalls on horizontal sides of the first isolation layer, the gate and the second isolation layer; The top of the second isolation layer and the sidewalls and top wall are used to continuously prepare the barrier layer, the capture layer, the tunnel layer and the channel layer by an atomic layer deposition process.

7. The storage unit according to claim 1, characterized in that The memory cell is configured as a ferroelectric memory cell; The dielectric layer includes a ferroelectric dielectric; the ferroelectric dielectric has two polarization states with opposite polarization directions; When reading data, the gate of the ferroelectric memory cell is used to provide a transfer curve under different reading voltages, and the reading voltage is lower than the voltage that changes the polarization direction of the ferroelectric medium; the transfer curve is used to calculate the threshold voltage of the ferroelectric memory cell to determine the data storage state; the storage state corresponding to the larger threshold voltage is the programming state, and the storage state corresponding to the smaller threshold voltage is the erasing state.

8. The storage unit according to claim 7, characterized in that When a positive voltage pulse is applied to the gate, the polarization direction of the ferroelectric medium is directed toward the opposite direction of the gate, and the ferroelectric memory cell is written into a programming state; When a negative voltage pulse is applied to the gate, the polarization direction of the ferroelectric medium is directed toward the gate direction, and the ferroelectric memory cell is written into an erased state.

9. The storage unit according to claim 1, characterized in that: The first electrode is configured as a source electrode, and the second electrode is configured as a drain electrode; or the second electrode is configured as a source electrode, and the first electrode is configured as a drain electrode.

10. A memory, characterized in that: comprising a reading unit, a writing unit and at least one storage unit as claimed in any one of claims 1 to 9; The reading unit is connected to the storage unit; the reading unit is used to read the data in the storage unit; the writing unit is connected to the storage unit; the writing unit is used to write data into the storage unit.

11. A method for preparing a memory cell, used for the memory cell according to any one of claims 1 to 9, characterized in that: include: Providing a substrate; forming a first electrode on the substrate; forming a first isolation layer on the first electrode; forming a gate on the first isolation layer; forming a second isolation layer on the gate; Performing a first etching based on the second isolation layer to form a first etching groove, wherein the first etching groove vertically penetrates the second isolation layer, the gate and the first isolation layer; forming a dielectric layer in the first etching groove and on the second isolation layer; A second etching is performed based on the dielectric layer to form a second etching groove; the second etching groove vertically penetrates the second isolation layer, the gate, the first isolation layer and the dielectric layer to divide the dielectric layer into two unconnected sub-dielectric regions; the bottom end of the second etching groove is set as the top end of the substrate; forming a channel layer in the second etching groove and at the top of the dielectric layer; the channel layer has a first portion located at the top of the dielectric layer and a second portion located in the second etching groove; The second portion forms a gap that opens upward; forming a filling layer in the gap and on a top of the channel layer; Etching the filling layer on the top of the channel layer, and retaining the filling layer in the gap as a third isolation layer; A second electrode is formed on a top of the third isolation layer and a top of the channel layer.

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