Detection system and detection method

Abstract

The invention discloses a detection system and a detection method, the detection system is applied to a probe card with a system, and the detection system comprises a test machine, an upper computer and a transfer module; the upper computer is in communication connection with the test machine and the transfer module, the test machine is electrically connected with the transfer module, the transfer module is connected with the probe card with the system, and the upper computer is used for scheduling the test machine and the transfer module; the transfer module comprises a communication main control unit, a channel expansion unit, a system power supply unit and a system-on-card control unit, and the communication main control unit is in communication connection with the upper computer and is in communication connection with the channel expansion unit, the system power supply unit and the system-on-card control unit. The transfer module can directly dispatch the system-on-card of the probe card with the system under the dispatching of the upper computer, and the problem that when an existing probe card analyzer is used for testing the probe card with the system, the card needs to be repeatedly taken down to switch the state is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor equipment testing, and in particular to a detection system with a system probe card and a detection method. Background Art

[0002] The probe card acts as a bridge between the tester and the wafer. As the wafer design capability and complexity increase, the probe card is developing towards a smaller pin pitch and more pins. Since the test capability of the tester is limited and it is difficult to meet the demand for measuring multiple channels at the same time, a control unit is integrated into the probe card to form an on-card system, so that the on-card system can schedule the test channels of multiple probes on the probe card as needed, so that each channel can test more chips. When using a probe card with a system to measure the wafer, it is necessary to first operate the on-card system to connect the test channels of multiple probes to the target channels of the wafer.

[0003] In the prior art, when using a traditional probe card analyzer to detect a probe card with a system, since the traditional probe card analyzer cannot independently control the on-card system on the probe card with a system, it is necessary to set the on-card system on the probe card with a system to a specific state in advance before testing the probe card with a system. This undoubtedly requires frequent card removal and state switching, and the test efficiency is extremely low.

[0004] Currently, no effective solution has been proposed for the problem of low efficiency of testing system probe cards by conventional probe card analyzers in the prior art. Summary of the invention

[0005] In view of this, the embodiments of the present invention provide a detection system and a detection method to at least solve the problem of low efficiency of testing a probe card with a system in a conventional probe card analyzer in the prior art.

[0006] The embodiment of the present invention provides the following technical solutions: An embodiment of the present invention provides a detection system, which is applied to a probe card with a system, and the detection system includes a tester, a host computer and a transfer module; the host computer is respectively connected to the tester and the transfer module for communication, the tester is electrically connected to the transfer module, the transfer module is connected to the probe card with a system, and the host computer is used to schedule the tester and the transfer module; The transfer module includes a communication main control unit, a channel expansion unit, a system power supply unit and an on-card system control unit, wherein the communication main control unit is communicatively connected to the host computer, and is communicatively connected to the channel expansion unit, the system power supply unit and the on-card system control unit respectively; Among them, the communication main control unit obtains and parses the scheduling data sent by the host computer and generates corresponding instruction information, the channel expansion unit matches and connects the resource interface of the test machine with the test channel on the system probe card according to the corresponding instruction information, the system power supply unit supplies power to the system probe card according to the instruction information, and the on-card system control unit operates the on-card system-controlled test channel to switch to the corresponding probe according to the instruction information.

[0007] Further, the channel expansion unit includes a switch circuit, and the switch circuit is respectively connected to the test machine and the probe card with system; The channel expansion unit controls the opening and closing of the switch in the switch circuit so that the resource interface on the test machine matches and connects with the test channel controlled by the system on the card.

[0008] Further, the switch circuit includes a regional short-circuit switch circuit, the regional short-circuit switch circuit includes n regional switch switching arrays, one end of the n regional switch switching arrays is correspondingly connected to the n resource interfaces of the tester, and the other end is correspondingly connected to the n regional test channels controlled by the on-card system on the probe card with system; When the switches on the n regional switch switching arrays are all closed, it is possible to determine whether there is a short circuit between the n regional test channels according to the leakage current between the n regional switch switching arrays.

[0009] Furthermore, the switch circuit includes a SWITCH switch array and / or a Relay switch array.

[0010] Furthermore, the channel extension unit also includes an extended FPGA chip, which is respectively connected to the communication main control unit and the switch circuit, and is used to control the opening and closing of the switch in the switch circuit according to the instructions of the communication main control unit.

[0011] Furthermore, the system power supply unit includes a programmable power supply, and the system power supply unit supplies power to the system probe card via the programmable power supply.

[0012] Furthermore, the system power supply unit also includes a power FPGA chip, and the power FPGA chip supplies power to the system probe card through the programmable power supply.

[0013] Further, the communication main control unit includes a main control FPGA chip and a plurality of interface elements, and the plurality of interface elements are respectively connected to the main control FPGA chip; The communication main control unit is used to parse the scheduling data sent by the host computer into circuit instructions, and send the circuit instructions to the channel expansion unit, the system power supply unit or the on-card system control unit.

[0014] Further, the host computer is connected to the test machine through a first communication interface, and the first communication interface includes at least one of JTAG, IIC, SPI, and Ethernet; The host computer is connected to the transfer module through a second communication interface, wherein the second communication interface includes at least one of an Ethernet and a UART serial port interface; The host computer controls the test machine to start testing, feedback test status and test structure through the first communication interface, and controls the transfer module through the second communication interface with a simple instruction protocol.

[0015] Another aspect of the present invention provides a detection method, which is applied to any of the above detection systems, and the detection method comprises: The host computer obtains a configuration file and initializes the transfer module according to the configuration file, wherein the configuration file includes one or more of the number of resource interfaces of the test machine, the expansion ratio of the channel expansion unit, the address of the channel expansion unit, the address of the system power supply unit, and the address of the system control unit on the card; The host computer preloads the test queue for the communication main control module of the transfer module and obtains the start test instruction; A scheduling transfer module, wherein the scheduling transfer module is used to match and connect the resource interface of the test machine with the test channel of the system control on the card with the system probe card, and switch the test channel of the system control on the card with the system probe card to the corresponding probe; The host computer schedules the test machine to perform testing, and obtains and outputs test results.

[0016] Furthermore, the scheduling transfer module includes obtaining the current test depth, a switch matrix in the scheduling channel expansion module, and a system control unit on the scheduling card.

[0017] Further, the obtaining and outputting the test results includes: The model of the system probe card is obtained, and the test result is output according to the model of the system probe card.

[0018] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects: A detection system of the present invention matches and connects the resource interface of the test machine with the test channel controlled by the on-card system with the system probe card by using the channel expansion unit of the transfer module, and then uses the on-card system control unit of the transfer module to control the on-card system with the system probe card, so as to unbind the test machine and the on-card system with the system probe card, so that the transfer module can directly schedule the on-card system with the system probe card under the scheduling of the host computer, thereby solving the problem that the existing probe card analyzer needs to repeatedly switch the state of the card when testing the system probe card, and avoiding the test machine directly operating the on-card system with the system probe card; Furthermore, the present application uses a channel expansion unit to enable the resource interface of the test machine to be connected only to the test channel with a system probe card, thereby unbinding the test machine from the system probe card and avoiding the test machine from directly operating the system on the scheduling card. Therefore, the DC test machine can be used to detect different models of system probe cards by simply modifying the scheduling program. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A connection diagram of a detection system according to an embodiment of the present invention; Figure 2 A scheduling relationship diagram of a detection system according to an embodiment of the present invention; Figure 3 This is a transfer system architecture diagram of a detection system according to an embodiment of the present invention; Figure 4 A regional short-circuit switch circuit of a switch circuit according to an embodiment of the present invention; Figure 5 A probe card side switch circuit (I) of the switch circuit of an embodiment of the present invention; Figure 6 A probe card side switch circuit (II) of the switch circuit of an embodiment of the present invention; Figure 7 is a flow chart of a detection method according to an embodiment of the present invention; Figure 8 This is a control flow chart of the host computer in an embodiment of the present invention; Fig. 9 A switch matrix control instruction diagram in a detection system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0022] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0023] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0025] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0026] With the improvement of wafer manufacturing capacity and the increase of chip design complexity, probe cards are moving towards a smaller pin pitch and more pins. However, due to the limited testing capacity of the tester, it is difficult to meet the demand for measuring multiple channels at the same time. Therefore, it has become a trend to introduce an on-card system on the probe card to schedule the tester resources so that each channel can test more chips.

[0027] The main difference between a probe card with a system and a probe card without a system is that the channel of a probe card without a system can be measured directly, while the probe card with a system needs to operate its internal system first before measuring the target channel.

[0028] For example, taking a 12-inch wafer as an example, there are more chips in the same area and more probes on the probe card. The tester is not sufficient to support powering on all chips at one time, so the on-card system needs to switch the power supply once to avoid overloading the tester.

[0029] Currently, there is no mature solution for testing probe cards with on-card systems. Existing probe card analyzers cannot effectively detect channels controlled by on-card systems, and using traditional testers to test probe cards is too wasteful. Therefore, a special testing system is urgently needed to solve the problem of testing probe cards with systems.

[0030] In the prior art, there are usually two solutions for testing probe cards with systems: Solution 1: Use a probe card analyzer to test the probe card with the system. Traditional probe card analyzers lack hardware integrated control functions and require the system on the card to be preset to a certain state before testing. This method requires frequent removal and replacement of the state on the card, resulting in extremely low test efficiency.

[0031] Therefore, the existing probe card analyzer can only test the probe card without the system.

[0032] Solution 2: Use a tester to test the probe card directly. On a specific probe card platform, a corresponding tester must be used, and different test programs must be written for the same card system on different platforms to adapt. This method is mainly for mass production testing, but it is too wasteful and costly to use it to test probe cards. In addition, the tester's results are for the wafer, not the probe card itself, and are not directly helpful for identifying probe card problems.

[0033] Therefore, when the probe card serves as a connecting bridge between the tester and the wafer, the tester that can use the system probe card for testing must have the ability to operate the system on the probe card. Therefore, in order to realize the operation of the system on the card, the system probe card needs to rely on a specific tester for testing and verification during factory testing.

[0034] Different probe card platforms have different repetitive structures, which are determined by the tester used. When designing a probe card, the system on the card is expanded according to this structure. The OS (Open Short) test (open circuit test, short circuit test) can be performed on the entire structure of different structures first, and then the OS test can be performed within the structure. Based on this requirement, the test can be performed in time and segment, reducing the number of test source channels required.

[0035] Based on this, this specification embodiment proposes a processing solution: Figures 1 to 3 As shown, a detection system of the present invention utilizes a host computer to first schedule a transfer module, and first utilizes a channel expansion unit of the transfer module to match and connect a resource interface of a test machine with a test channel controlled by a system probe card on a card, and then operates the on-card system on the system probe card through an on-card control system control unit, so that the test channel controlled by the on-card system is switched to a corresponding probe, and finally the host computer schedules the test machine to perform testing, thereby solving the problem that the existing probe card analyzer needs to frequently switch states when testing a system probe card, and the test efficiency is low.

[0036] Furthermore, by matching and connecting the test machine only with the test channel of the system probe card, the test machine and the on-card system on the system probe card are untied, so that the system probe card can be tested using only a commonly used test machine, and only simple modifications to the test program are required to meet the needs of different on-card systems.

[0037] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0038] Example 1 like Figures 1 to 3 As shown, an embodiment of the present invention provides a detection system, which is applied to a system probe card. The detection system includes a tester, a host computer and a transfer module. The host computer is respectively communicated with the tester and the transfer module, the tester is electrically connected to the transfer module, the transfer module is connected to the system probe card, and the host computer is used to schedule the tester and the transfer module.

[0039] The tester of the present application can at least perform OS testing. For example, the tester of the present application can be a DC (Direct Current) tester, which is easy to obtain, low-cost, and can meet the needs of probe card testing.

[0040] Among them, the test machine is mainly used to test the probe card with system through the transfer module.

[0041] Among them, the role of the host computer is to schedule the test machine and transfer module, build the test sequence and integrate the test results.

[0042] The host computer may be a PC host computer or an embedded system host computer, or may be replaced by other devices that can realize the functions of the host computer.

[0043] Among them, the host computer can communicate with the test machine through the first communication interface (interface 1), and the host computer can control the test machine to start testing, feedback test status and test results through the first communication interface. The first communication interface can be a conventional test machine communication interface, such as JTAG, IIC, SPI Ethernet and other communication interfaces.

[0044] The transfer module is used to match the resource interface of the test machine with the test channel with system control on the system probe card, and control the scheduling of the test channel with system control on the system probe card to switch to the corresponding probe.

[0045] Among them, in this application, there is no direct scheduling between the test machine and the transfer module, and the cooperation between the test machine and the transfer module needs to be controlled by the upper computer.

[0046] Among them, the physical connection between the transfer module and the tester is to match the tester and the probe card with the system, and the connection methods include but are not limited to connector connection, cable connection, spring pin connection and other methods.

[0047] The transfer module is connected to the host computer through the second communication interface (interface 2), and the host computer controls the transfer module from the second communication interface through a simple command protocol. The second communication interface can be an Ethernet, UART serial port or other interface.

[0048] Among them, the probe card with system is a probe card with system on card, which includes multiple probes and a control system (system on card) integrated on the probe card. The probe card with system is used to test wafers.

[0049] Specifically, the scheduling method of the present application is that the host computer schedules the test machine and the transfer module, and the transfer module schedules itself and the system on the card with the system probe card and supplies power to the system probe card.

[0050] The present application uses a host computer to schedule a test machine and a transfer module, and the transfer module schedules a system probe card, thereby unbinding the test machine and the system probe card, and uses the transfer module to schedule the system probe card, thereby eliminating the need for the test machine to operate the system probe card, and thus only requires a common test machine such as a DC test machine to test the system probe card.

[0051] Specifically, the transfer module includes a communication main control unit, a channel expansion unit, a system power supply unit and an on-card system control unit. The communication main control unit is communicatively connected to the host computer, and is communicatively connected to the channel expansion unit, the system power supply unit and the on-card system control unit respectively; wherein the communication main control unit obtains and parses the scheduling data sent by the host computer and generates corresponding instruction information, the channel expansion unit matches and connects the resource interface of the test machine with the test channel on the system probe card according to the corresponding instruction information, the system power supply unit supplies power to the system probe card according to the instruction information, and the on-card system control unit operates the on-card system-controlled test channel to switch to the corresponding probe according to the instruction information.

[0052] Among them, the communication main control unit is connected to the host computer through the second communication interface. The communication main control unit is responsible for the external communication of the entire transfer module, is responsible for parsing external protocol instructions, and distributes commands to each specific hardware, such as to the channel expansion unit, system power supply unit and on-card system control unit.

[0053] Specifically, the communication main control unit includes a main control FPGA chip and multiple interface elements, which are respectively connected to the main control FPGA chip; the communication main control unit is used to parse the scheduling data sent by the host computer into circuit instructions, and send the circuit instructions to the channel expansion unit, the system power supply unit or the system control unit on the card.

[0054] Among them, the communication main control unit takes the main control FPGA chip as the core, and builds various interface components based on the main control FPGA chip, and the interface components include the interface type selected by the second communication interface to receive data from the second communication interface.

[0055] Among them, the communication main control unit communicates with the channel expansion unit, the system power supply unit and the system control unit on the card using the TTC protocol.

[0056] Among them, the channel expansion unit is responsible for realizing the one-to-many connection between the resource interface (test channel) of the tester and the channel with the system probe card.

[0057] The number of channel expansion units and system power supply units can be plural, and each unit has its own independent address.

[0058] Among them, the expansion ratio of the channel expansion unit can be set as needed, and it can be expanded in a ratio of 1:2, 1:4, or 1:8.

[0059] Among them, the channel extension unit includes an extended FPGA chip and a switch circuit. The extended FPGA chip is connected to the communication main control unit and the switch circuit respectively, and is used to control the opening and closing of the switch in the switch circuit.

[0060] The extended FPGA chip controls the opening and closing of the switch in the switch circuit so that the resource interface on the test machine matches and connects with the test channel controlled by the system on the card.

[0061] Among them, the system power supply unit is responsible for simulating the test machine to supply power to the system probe card.

[0062] The system power supply unit includes a power FPGA chip and is connected to a power supply interface with a system probe card.

[0063] Optionally, the system power supply unit includes a programmable power supply, and the system power supply unit supplies power to the system probe card through the programmable power supply, that is, the power supply FPGA supplies power to the system probe card through the programmable power supply to form an integrated programmable adjustable DC source to supply power to the system probe card.

[0064] The on-card system control unit is used to dispatch the on-card system with the system probe card, and switches the test channels controlled by the on-card system to different probes in accordance with the test items.

[0065] Among them, the card system control unit uses FPGA master control (card system FPGA), and can realize the conversion of various serial ports and parallel ports to directly operate the card system on the card with system probe card.

[0066] The on-card system control unit is connected to the system control port on the card with the system probe.

[0067] Furthermore, the channel expansion unit includes a switching circuit, which is respectively connected to the test machine and the probe card with the system; wherein the channel expansion unit controls the opening and closing of the switch in the switching circuit so that the resource interface on the test machine matches and connects with the test channel controlled by the system on the card.

[0068] Furthermore, the switch circuit includes a regional short-circuit switch circuit, which includes n regional switch switching arrays, one end of the n regional switch switching arrays correspondingly connected to n resource interfaces of the test machine, and the other end correspondingly connected to n regional test channels controlled by the on-card system on the system probe card; wherein, when the switches on the n regional switch switching arrays are all closed, it can be determined whether there is a short circuit between the n regional test channels based on the leakage current between the n regional switch switching arrays.

[0069] For example, taking a 100-channel test source testing a 400-channel probe card as an example, the transfer module switch matrix is ​​designed with an expansion ratio of 1:4, the test source channels are named CH1-CH100, and the probe card channels are named CHA1-100, CHB1-100, CHC1-100, and CHD1-100. Figure 4 It is a regional short-circuit switch circuit. As can be seen from the figure, CH1, CH2, CH3 and CH4 correspond to the four repeated structural parts of the probe card. The switch of CH1 is closed at CHA1-100, the switch of CH2 is closed at CHB1-100, the switch of CH3 is closed at CHC1-100, and the switch of CH4 is closed at CHD1-100. All signals in the four regions A, B, C and D of the probe card are short-circuited. By measuring the leakage current between CH1, CH2, CH3 and CH4, it can be determined whether there is a short circuit between the regions.

[0070] Among them, the switching circuit includes a SWITCH switch switching array and / or a Relay switch switching array. When the channel resistance accuracy requirement of the system probe card test is low, the SWITCH switch switching array can be used, and when the accuracy requirement of the system probe card test is high, the Relay switch switching array can be used.

[0071] Preferably, the switch circuit includes both a SWITCH switch array and a Relay switch array, and the SWITCH switch array and the Relay switch array are arranged in parallel, so that the relay module can cope with different scenarios.

[0072] like Figures 5 and 6 As shown, the switch circuit also includes a conventional probe card side switch circuit, and the expansion ratio of the conventional probe card side switch circuit can be expanded in ratios of 1:2, 1:4, and 1:8.

[0073] For example, the switching circuit also includes multiple switch groups, each switch group includes multiple switches, one end of the multiple switches in the switch group are respectively connected to the resource port of the test machine, and the other ends of the multiple switches in the switch group are connected in series and connected to the test channel with the system probe card; or the switching circuit includes a switch group, the switch group includes multiple switches, one end of the switch group is connected in series and connected to the resource port of the test machine, and the other end of the switch group is respectively connected to the multiple test channels on the system probe card.

[0074] In the embodiment of the present invention, the connection between the transfer module and the probe card with the system is in the form of a soft board + a gold finger hard board, and different test machine interface boards are replaced according to different test machine platforms.

[0075] A detection system according to an embodiment of the present invention connects a test machine to a test channel with a system probe card through a transfer module, and uses the on-card system control unit of the transfer module to control the on-card system with the system probe card, thereby unbinding the test machine from the system probe card, and then scheduling the transfer module through a host computer to schedule the on-card system, and then completing the matching connection between the resource interface of the test machine and the test channel with the system probe card through a channel expansion unit, and finally scheduling the test machine to complete the detection of the system probe card, thereby realizing the detection of the system probe card by using a DC test machine, and since the test machine and the on-card system are unbinding, different on-card systems can be satisfied only by simply modifying the test program of the transfer module.

[0076] The embodiment of the present invention controls the on-card system through a special module (on-card system control unit), thereby solving the problem that the traditional probe card analyzer does not have hardware control integration, and reduces the requirement for the number of tester channels through the channel expansion module. An easily available DC tester can be used, and a large-scale specific model of a tester is not required, thereby reducing the test cost and test difficulty. The transit module separates the scheduling of the on-card system from the tester itself. The tester is only used for OS testing, and the scheduling of the on-card system is no longer limited by the tester.

[0077] Example 2 like Figure 7-8 As shown, the present application provides a detection method, which is applied to the detection system as described in any one of the embodiments 1, and the detection method comprises: Step S102, the host computer obtains the configuration file and initializes the transfer module according to the configuration file, wherein the configuration file includes one or more of the number of resource interfaces of the test machine, the expansion ratio of the channel expansion unit, the address of the channel expansion unit, the address of the system power supply unit, and the address of the system control unit on the card.

[0078] Before the host computer obtains the configuration file, it first connects the host computer to the test machine and the transfer module respectively, and then initializes the transfer module according to the configuration file.

[0079] Step S104: the host computer preloads the communication main control module of the transfer module into a test queue and obtains a start test instruction.

[0080] After loading the test queue, the host computer obtains the start test instruction to send corresponding instruction information to the transfer module, so that the transfer module executes the scheduling task according to the corresponding instruction information.

[0081] Step S106, the scheduling transfer module, wherein the scheduling transfer module is used to match and connect the resource interface of the test machine with the system-controlled test channel on the card with the system probe card, and switch the system-controlled test channel on the card with the system probe card to the corresponding probe.

[0082] Among them, the scheduling transfer module includes obtaining the current test depth, the switch matrix in the scheduling channel expansion module and the system control unit on the scheduling card.

[0083] The host computer dispatches the transfer module to send command information to the transfer module, so that the transfer module performs switch matrix scheduling and on-card system scheduling according to the command information.

[0084] Take the switch matrix scheduling of the transfer module as an example. Fig. 9As shown in the switch matrix control instruction diagram, the instruction consists of transmission status, instruction type, start channel, end channel, and channel status. The channel range can be specified to batch adjust the instruction status. Multiple instructions can be combined to control each switch in the matrix. The instruction can be adjusted according to the actual situation.

[0085] Step S108: The host computer schedules the test machine to perform the test, obtains the test result, and ends the test.

[0086] Among them, obtaining and outputting test results includes: Get the model with the system probe card, and output the test result according to the model with the system probe card.

[0087] Among them, when the transfer module outputs the test results to the upper level, if there are unfinished test items, the transfer module will be re-scheduled.

[0088] The host computer of the present application starts to detect the test machine interface and the transfer module interface, and starts the test after receiving the connection response. The configuration file of the host computer indicates the current number of test machine channels, the expansion ratio of the transfer module, the number and address of the transfer module channel expansion modules and the system power supply module; after completing the configuration, the host computer pre-loads the test queue for the communication main control module to obtain the test depth; the instruction sequence should follow the schedule of the transfer module first and then operate the test machine; after completing all tests in the test sequence, the test results are output according to the model of the probe card.

[0089] The host computer process of this application can be regarded as the scheduling order of each device in the architecture, and the scheduling ensures that the actual circuit is switched to the part that needs to be tested.

[0090] The embodiment of the present invention can implement on-card system scheduling with a system probe card, so that the test channel with the system probe card is switched to different probes, and the probes before and after the switching are different.

[0091] The test results obtained by the embodiment of the present invention are related to the model of the probe card with the system, which is helpful for troubleshooting the problem of the probe card.

[0092] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A detection system, applied to a probe card with a system, characterized in that: The detection system includes a test machine, a host computer and a transfer module; the host computer is respectively connected to the test machine and the transfer module for communication, the test machine is electrically connected to the transfer module, the transfer module is connected to the probe card with the system, and the host computer is used to schedule the test machine and the transfer module; The transfer module includes a communication main control unit, a channel expansion unit, a system power supply unit and an on-card system control unit, wherein the communication main control unit is communicatively connected to the host computer, and is communicatively connected to the channel expansion unit, the system power supply unit and the on-card system control unit respectively; Among them, the communication main control unit obtains and parses the scheduling data sent by the host computer and generates corresponding instruction information, the channel expansion unit matches and connects the resource interface of the test machine with the test channel on the system probe card according to the corresponding instruction information, the system power supply unit supplies power to the system probe card according to the instruction information, and the on-card system control unit operates the on-card system-controlled test channel to switch to the corresponding probe according to the instruction information.

2. The detection system according to claim 1, characterized in that: The channel expansion unit includes a switch circuit, and the switch circuit is respectively connected to the test machine and the probe card with system; The channel expansion unit controls the opening and closing of the switch in the switch circuit so that the resource interface on the test machine matches and connects with the test channel controlled by the system on the card.

3. The detection system according to claim 2, characterized in that: The switch circuit includes a regional short-circuit switch circuit, and the regional short-circuit switch circuit includes n regional switch switching arrays, one end of the n regional switch switching arrays is correspondingly connected to the n resource interfaces of the tester, and the other end is correspondingly connected to the n regional test channels controlled by the on-card system on the probe card with system; When the switches on the n regional switch switching arrays are all closed, it is possible to determine whether there is a short circuit between the n regional test channels according to the leakage current between the n regional switch switching arrays.

4. The detection system according to claim 3, characterized in that: The switch circuit includes a SWITCH switch array and / or a Relay switch array.

5. The detection system according to any one of claims 2 to 4, characterized in that: The channel extension unit also includes an extended FPGA chip, which is connected to the communication main control unit and the switch circuit respectively, and is used to control the opening and closing of the switch in the switch circuit according to the instructions of the communication main control unit.

6. The detection system according to claim 1, characterized in that: The system power supply unit includes a programmable power supply, and the system power supply unit supplies power to the system probe card through the programmable power supply.

7. The detection system according to claim 6, characterized in that: The system power supply unit further comprises a power FPGA chip, and the power FPGA chip supplies power to the system probe card through the program-controlled power supply.

8. The detection system according to claim 1, characterized in that: The communication main control unit includes a main control FPGA chip and a plurality of interface elements, and the plurality of interface elements are respectively connected to the main control FPGA chip; The communication main control unit is used to parse the scheduling data sent by the host computer into circuit instructions, and send the circuit instructions to the channel expansion unit, the system power supply unit or the on-card system control unit.

9. The detection system according to claim 1, characterized in that: The host computer is connected to the test machine through a first communication interface, wherein the first communication interface includes at least one of JTAG, IIC, SPI, and Ethernet; The host computer is connected to the transfer module through a second communication interface, wherein the second communication interface includes at least one of an Ethernet and a UART serial port interface; The host computer controls the test machine to start testing, feedback test status and test structure through the first communication interface, and controls the transfer module through the second communication interface with a simple instruction protocol.

10. A detection method, characterized in that: Applied to the detection system according to any one of claims 1 to 9, the detection method comprises: The host computer obtains a configuration file and initializes the transfer module according to the configuration file, wherein the configuration file includes one or more of the number of resource interfaces of the test machine, the expansion ratio of the channel expansion unit, the address of the channel expansion unit, the address of the system power supply unit, and the address of the system control unit on the card; The host computer preloads the test queue for the communication main control module of the transfer module and obtains the start test instruction; A scheduling transfer module, wherein the scheduling transfer module is used to match and connect the resource interface of the test machine with the test channel of the system control on the card with the system probe card, and switch the test channel of the system control on the card with the system probe card to the corresponding probe; The host computer schedules the test machine to perform testing, and obtains and outputs test results.

11. The detection method according to claim 10, characterized in that: The scheduling transfer module includes obtaining the current test depth, a switch matrix in the scheduling channel expansion module, and a system control unit on the scheduling card.

12. The detection method according to claim 10, characterized in that: The obtaining and outputting of the test results comprises: The model of the system probe card is obtained, and the test result is output according to the model of the system probe card.

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