Multi-channel data synchronization method based on FPGA

Abstract

The invention belongs to the technical field of radar signal processing, and discloses a multichannel data synchronization method based on an FPGA. The multi-channel data synchronization method comprises the following steps of: analyzing a configuration packet by a configuration parameter analysis module, setting a reference threshold value of a data synchronization control module, and instantiating N data buffers FIFO (First In First Out), judging whether the number of the actually effective data buffers FIFO exceeds a reference threshold value i of the data synchronization control module or not and whether the number of the cached data of each data buffer FIFO exceeds the number M of the fault-tolerant distance gates or not, outputting a read enable signal, reading the data of all the data buffers FIFO, and the like. According to the method, all parameters can be configured, a user can adjust the number of channels and the number of fault-tolerant distance gates by changing the configuration parameters, multi-parameter control and interface standardization and generalization can be achieved, and the requirement for multi-beam calculation of FPGA data processing in the field of signal processing can be met.

Description

Technical Field

[0001] The invention mainly relates to the technical field of radar signal processing, and in particular to a multi-channel data synchronization method based on FPGA. Background Art

[0002] Phased array antennas use a large number of small antenna units to form an antenna array, and synthesize different phase beams by controlling the phase of each antenna unit's transmission. Compared with traditional reflector antennas, they have made a qualitative leap in terms of response speed, multi-target tracking capability, and resolution. With the development of digital phased array technology, the back-end signal processing algorithm processing process has become more and more complex, which has become an inevitable trend in the development of phased array technology.

[0003] In order to achieve high performance of phased array antennas, signal processing needs to use multi-beam data for air situation detection and signal sampling to obtain as much external air situation information as possible. This requires back-end signal processing to perform multi-beam synthesis on the multi-channel data transmitted by the phased array antenna to obtain target information in space. Summary of the invention

[0004] The purpose of the present invention is to provide a multi-channel data synchronization method based on FPGA. The user can adjust the number of channels and the number of fault-tolerant range gates by changing the configuration parameters. The target information carried by the downlink channel data of the phased array antenna can be fully utilized to synchronize and align the multi-channel data of the antenna downlink, thereby improving the fault tolerance of multi-channel data processing, and improving the reliability and correctness of the back-end digital beamforming data processing. It can meet the needs of multi-beam computing of FPGA data processing in the field of signal processing, and can be widely used in radar, 5G communication and other fields.

[0005] To achieve the above object, the present invention provides a multi-channel data synchronization method based on FPGA, comprising the following steps:

[0006] Step 1: The configuration parameter parsing module parses the configuration package to obtain the configuration package parameters that need to be synchronized. The configuration package parameters include the number of channels N, the data bit width P of each channel, the reference threshold i of the data synchronization control module, and the number of fault-tolerant range gates M;

[0007] Step 2: Set the reference threshold i of the data synchronization control module to be less than or equal to the number of channels N;

[0008] Step 3: Instantiate N data buffer FIFOs for caching downlink data of N channels. The data buffer FIFO of each channel transmits the number of cached data and the empty and full signals to the data synchronization control module. The data synchronization control module compares each data buffer FIFO with the data synchronization control module reference threshold i.

[0009] Step 4: If the number of actually valid data buffer FIFOs is greater than or equal to i and the number of data cached in the data buffer FIFO is greater than the number of fault-tolerant range gates, the data synchronization control module outputs a read enable signal to read the data of all data buffer FIFOs;

[0010] When the data end signal is detected, the data synchronization control module outputs a read enable signal to read the last segment of data in the data buffer FIFO until all the data in the data buffer FIFO is read, thereby realizing the data synchronization function;

[0011] If the actual valid data buffer FIFO number is less than i or the number of data cached in the data buffer FIFO is less than or equal to the number of fault-tolerant range gates M, an empty read or full write phenomenon occurs, then the effective value of the corresponding channel effective signal is reduced, the data in the data buffer FIFO is not read, the data is set to invalid, and is not used for back-end signal processing.

[0012] Furthermore, each data buffer FIFO in step 4 uses the same signal.

[0013] Furthermore, in step 3, the language in which the N data buffer FIFOs are instantiated for caching the downstream data of the N channels is Verilog language.

[0014] Furthermore, the number of channels N is 32, the data bit width P of each channel is 32, and the reference threshold i of the data synchronization control module is 4.

[0015] Furthermore, in step 4, while each data buffer FIFO uses the same signal, it also outputs a channel valid signal for back-end data processing.

[0016] Beneficial effects:

[0017] The present invention provides a multi-channel data synchronization method based on FPGA. The present invention can realize multi-parameter control, can support synchronous processing of N (N>0) channel data at the same time, and has downward compatibility and expansion functions. All parameters of the present invention are configurable, and the real-time configuration of the number of channels and the synchronization threshold is realized in the form of configuration parameters. Different signal processing systems can modify the corresponding parameters according to actual needs, so as to realize the data synchronization function of the system. The present invention can realize interface standardization and generalization. The parameter configuration, data reception and transmission of the present invention use a standard AXI interface. The expansion of the number of channels and the synchronization threshold can be realized by modifying the configuration package, thereby improving the compatibility and scalability of the synchronization system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a framework diagram of a multi-channel data synchronization system involved in an embodiment of the present invention;

[0019] Figure 2 is a data synchronization control state flow chart involved in an embodiment of the present invention;

[0020] Reference numerals

[0021] i_sync_th is the reference threshold i of the data synchronization control module; N is the number of channels; P is the data bit width of each channel; and M is the number of fault-tolerant distance gates. DETAILED DESCRIPTION

[0022] The preferred mechanism and implementation method of the present invention are further described below in conjunction with the accompanying drawings and specific implementation methods.

[0023] like Figure 1 to Figure 2 As shown, an embodiment of the present invention discloses a technical solution of a multi-channel data synchronization method based on FPGA, the present invention relates to a configuration parameter parsing module parsing a configuration package, setting a reference threshold i of a data synchronization control module to be less than or equal to the number of channels N, instantiating N data buffer FIFOs, checking whether the number of actually valid data buffer FIFOs exceeds the reference threshold i of the data synchronization control module and whether the number of data cached in each data buffer FIFO exceeds the number of fault-tolerant distance gates M, outputting a read enable signal, reading data of all data buffer FIFOs, etc.

[0024] The reference threshold i of the data synchronization control module means that in the case of multiple channel data transmission, there are N channels in total. If the actual number of valid channels is less than i, then all channel data is in an empty read state and will not participate in the subsequent data processing; if the actual number of valid channels is greater than or equal to i, data synchronization is performed according to the setting of the fault-tolerant distance gate number M. For example, if the number of channels N is 32 and the reference threshold i of the data synchronization control module is 4, it means that the actual number of valid channels is at least 4 or greater than 4, otherwise the data of all channels is in an empty read state and will not participate in the subsequent data processing; only when the actual number of valid channels is greater than or equal to 4, data synchronization will be performed according to the setting of the fault-tolerant distance gate number M.

[0025] The number of fault-tolerant range gates M means that when the maximum clock beats of multiple channel data at the same time are less than or equal to the number of fault-tolerant range gates M, the data synchronization control module outputs the synchronization alignment data of the actual effective number of channels in parallel, and the output channel data are all synchronized and aligned at the same range gate at the same time, and can be directly used for back-end signal processing; when the maximum clock beats of multiple channel data at the same time are greater than the number of fault-tolerant range gates M, the data synchronization control module sets the data of the actual effective number of channels to invalid, and does not use it for back-end signal processing. Taking the value of M as 40 as an example, the total number of channels is N. If the maximum clock beats of the data between the N channels at the same time are less than or equal to 40, it means that within the fault-tolerant interval, the data synchronization control module will output a read enable signal to read the data of all data buffers FIFO; on the contrary, if the maximum clock beats of the data between the N channels at the same time are greater than 40, it means that the error is too large and is not within the fault-tolerant interval, then the channels with the maximum clock beats greater than 40 will be set to invalid and will no longer participate in subsequent operations, and the remaining channels will perform data synchronization normally, and the synchronized data will participate in subsequent data operations.

[0026] There is no necessary relationship between the number of channels N, the data bit width P of each channel, the reference threshold i of the data synchronization control module, and the number of fault-tolerant distance gates M, but the reference threshold i of the data synchronization control module must be less than or equal to the number of channels N.

[0027] Figure 1 This is a multi-channel data synchronization system framework diagram. Figure 2 This is the data synchronization control state flow chart. Figure 1 As shown, a multi-channel data synchronization system based on FPGA can realize the synchronization function of N (N>0) channel data (with expansion capability), and the threshold judgment can set the threshold according to the actual situation of the system to meet the synchronization function requirements of the system.

[0028] Example 1

[0029] The configuration parameter parsing module parses the configuration package to obtain the configuration package parameters that need to be synchronized. The configuration package parameters include the number of channels N, the data bit width P of each channel, the reference threshold i of the data synchronization control module, the number of fault-tolerant distance gates M, etc.

[0030] In order to support data synchronization of up to N channels, N data buffer FIFO modules are first instantiated (generate). Each data buffer FIFO is used to cache the downlink data of the corresponding channel. The depth of the data buffer FIFO setting (that is, the number of data cached by the data buffer FIFO) must not be less than the number of fault-tolerant distance gates M to prevent the data buffer FIFO from overflowing and causing data output errors.

[0031] The data buffer FIFO of each channel transmits the number of cached data and the empty and full signals to the data synchronization control module. The data synchronization control module compares the number of data cached by each data buffer FIFO with the reference threshold i of the data synchronization control module. If the number of data cached by i channel FIFOs is greater than the number of fault-tolerant distance gates M, the data synchronization control module outputs a read enable signal to read all data buffer FIFO data to achieve data synchronization. At the same time, the channel validity is set according to the empty and full signals of the data buffer FIFO. If an empty read or full write occurs, the valid value of the valid signal of the corresponding channel is pulled down and the data is set to invalid.

[0032] This embodiment is described by taking 32 channels (the number of channels N=32), the data bit width P of each channel is 32, and the reference threshold i of the data synchronization control module is set to 4, including:

[0033] Step 1: The configuration parameter parsing module parses the configuration package to obtain the configuration package parameters that need to be synchronized. The configuration package parameters include the number of channels N, the data bit width P of each channel, the reference threshold i of the data synchronization control module, and the number of fault-tolerant distance gates M; N is set to 32, P is set to 32, and i is set to 4;

[0034] Step 2: Set the reference threshold i of the data synchronization control module to be less than or equal to the number of channels N;

[0035] Step 3: Instantiate 32 data buffer FIFOs for caching downlink data of 32 channels. The data buffer FIFO of each channel transmits the number of cached data and the empty and full signals to the data synchronization control module. The data synchronization control module compares each data buffer FIFO with the reference threshold i of the data synchronization control module.

[0036] Step 4: If the number of actually valid data buffer FIFOs is greater than or equal to i and the number of data cached in the data buffer FIFO is greater than the number of fault-tolerant range gates, the data synchronization control module outputs a read enable signal to read the data of all data buffer FIFOs;

[0037] When the data end signal is detected, the data synchronization control module outputs a read enable signal to read the last segment of data in the data buffer FIFO until all the data in the data buffer FIFO is read, thereby realizing the data synchronization function;

[0038] If the actual valid data buffer FIFO number is less than i or the number of data cached in the data buffer FIFO is less than or equal to the number of fault-tolerant range gates M, an empty read or full write phenomenon occurs, then the effective value of the corresponding channel effective signal is reduced, the data in the data buffer FIFO is not read, the data is set to invalid, and is not used for back-end signal processing.

[0039] Furthermore, the language of instantiating N data buffer FIFOs for caching the downlink data of N channels is Verilog language. The data buffer FIFO performs data synchronization output by receiving the read enable signal output by the data synchronization control module. Since the read enable signal of each data buffer FIFO uses the same signal, the data output by each data buffer FIFO is synchronized, and each clock data is aligned. At the same time, a channel valid signal is output for use in data processing at the back end.

[0040] The present invention provides a multi-channel data synchronization method based on FPGA. The user can adjust the number of channels and the number of fault-tolerant range gates by changing the configuration parameters, which can meet the needs of multi-beam computing of FPGA data processing in the field of signal processing.

[0041] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. However, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-channel data synchronization method based on FPGA, characterized in that: The following steps are involved: Step 1: The configuration parameter parsing module parses the configuration package to obtain the configuration package parameters that need to be synchronized. The configuration package parameters include the number of channels N, the data bit width P of each channel, the reference threshold i of the data synchronization control module, and the number of fault-tolerant range gates M; Step 2: Set the reference threshold i of the data synchronization control module to be less than or equal to the number of channels N; Step 3: Instantiate N data buffer FIFOs for caching downlink data of N channels. The data buffer FIFO of each channel transmits the number of cached data and the empty and full signals to the data synchronization control module. The data synchronization control module compares each data buffer FIFO with the data synchronization control module reference threshold i. Step 4: If the number of actually valid data buffer FIFOs is greater than or equal to i and the number of data cached in the data buffer FIFO is greater than the number of fault-tolerant range gates, the data synchronization control module outputs a read enable signal to read the data of all data buffer FIFOs; When the data end signal is detected, the data synchronization control module outputs a read enable signal to read the last segment of data in the data buffer FIFO until all the data in the data buffer FIFO is read, thereby realizing the data synchronization function; If the actual valid data buffer FIFO number is less than i or the number of data cached in the data buffer FIFO is less than or equal to the number of fault-tolerant range gates M, an empty read or full write phenomenon occurs, then the effective value of the corresponding channel effective signal is reduced, the data in the data buffer FIFO is not read, the data is set to invalid, and is not used for back-end signal processing.

2. The FPGA-based multi-channel data synchronization method according to claim 1, characterized in that: Each data buffer FIFO in step 4 uses the same signal.

3. The FPGA-based multi-channel data synchronization method according to claim 1, characterized in that: In step 3, the language of instantiating N data buffer FIFOs for caching the downstream data of N channels is Verilog language.

4. The FPGA-based multi-channel data synchronization method according to claim 1, characterized in that: The number of channels N is 32, the data bit width P of each channel is 32, and the reference threshold i of the data synchronization control module is 4.

5. The FPGA-based multi-channel data synchronization method according to claim 2, characterized in that: In step 4, each data buffer FIFO uses the same signal and simultaneously outputs a channel valid signal for back-end data processing.

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