Time sequence diagram establishment method and device, equipment and storage medium

Abstract

The invention relates to a time sequence diagram establishing method, device and equipment and a storage medium, and is applied to the technical field of integrated circuits, and the time sequence diagram establishing method comprises the steps that a segmentation boundary line is obtained, and the segmentation boundary line is used for dividing a DUT module into different DUT sub-modules; a key path is searched according to the direction of data transmission, and the initial position for searching the key path is the segmentation boundary line; nodes are established at device ports through which the key paths pass, and edges are established inside the devices through which the key paths pass and among the devices; searching a clock path corresponding to the key path at the ending position of the key path, and establishing a corresponding edge according to the clock path; and forming a directed graph by using all the established edges and the nodes correspondingly associated with all the edges, and setting the directed graph as a time sequence diagram. The method has the technical effects that the time sequence diagram is quickly established, the calculation amount in time sequence analysis is reduced, and the analysis efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method, apparatus, device, and storage medium for establishing a timing diagram. Background Art

[0002] In recent years, the scale of integrated circuits has continued to grow, with the application of large-scale digital circuits with billions or even tens of billions of gates increasing. The corresponding demand for auxiliary verification is also becoming increasingly prevalent. Due to the reconfigurability, high speed, and low cost of FPGAs, using FPGAs as hardware simulation accelerators and prototype verification has become a mainstream choice in digital circuit design. The resource capacity of a single FPGA is limited. When the scale of the Design Under Test (DUT) is large, multiple FPGAs need to be interconnected to form a multi-FPGA verification system. Using a multi-FPGA verification system as a hardware implementation to assist in the circuit logic design can achieve speedups of nearly a thousand times compared to software simulation. Automatically partitioning the DUT appropriately and efficiently distributing it across multiple FPGAs is a key issue that needs to be addressed in practical engineering.

[0003] Logic partitioning of large-scale circuits can be modeled as a hypergraph partitioning problem, which is essentially a constrained multi-objective combinatorial optimization problem. Currently, heuristic algorithms are commonly used, using a multi-level partitioning framework consisting of three stages: node coarsening (clustering), initial partitioning, and local refinement. These algorithms primarily focus on minimizing the number of cuts (due to limited interconnect resources between FPGAs), and do not consider the actual performance after partitioning. However, in practice, DUT performance is a crucial metric. Therefore, static timing analysis tools have been introduced. These tools can guide the partitioning algorithm, avoiding cutting critical paths and introducing new ones, resulting in a more optimal partitioning result. Furthermore, after partitioning and completing TDM binding, they can be used to estimate the actual achievable performance of the DUT. Furthermore, if the FPGA Place & Route (Place & Route) outputs an SDF (Standard Delay Format) file, the tool can calculate more accurate DUT performance based on the net / cell delays in the SDF file.

[0004] During static timing analysis, a timing diagram is generally created for the entire DUT design, and then timing analysis is performed to identify the critical path. However, for multi-FPGA systems, due to the introduction of TDM modules (time division multiplexing modules) with relatively large delays, creating a timing diagram for the entire DUT design takes a long time, reducing the efficiency of timing analysis and, in turn, affecting the efficiency of the verification process. Summary of the Invention

[0005] In order to help solve the problem that in multi-FPGA systems, due to the introduction of TDM modules (time division multiplexing modules) with relatively large delays, it takes a long time to establish a timing diagram for the entire DUT design, which reduces the efficiency of timing analysis and thus affects the work efficiency of the verification process, the present application provides a timing diagram establishment method, device, equipment and storage medium.

[0006] In a first aspect, the present application provides a method for establishing a timing diagram, which adopts the following technical solution: the method comprises:

[0007] Obtaining a segmentation boundary line, where the segmentation boundary line is a segmentation boundary line that divides the DUT module into different DUT sub-modules;

[0008] Searching for a critical path according to the direction of data transmission, wherein a starting position of the search for the critical path is the segmentation boundary line;

[0009] Establishing nodes at the ports of the devices through which the critical path passes, and establishing edges inside the devices through which the critical path passes and between the devices;

[0010] Searching for a clock path corresponding to the critical path at an end position of the critical path, and establishing a corresponding edge according to the clock path;

[0011] All established edges and all nodes corresponding to the edges are combined into a directed graph, and the directed graph is set as a time sequence graph.

[0012] In a specific implementation scheme, searching for a critical path according to the direction of data transmission includes:

[0013] The critical path is searched backward and forward according to the direction of data transmission; the critical path is searched backward first and then forward.

[0014] In a specific feasible implementation scheme, the starting position of the backward search critical path is the split boundary line, and the ending position of the backward search critical path is the clock starting position; the starting position of the forward search critical path is the split boundary line, and the ending position of the forward search critical path is the timing checkpoint position, wherein the timing checkpoint position is located inside the output device of data transmission.

[0015] In a specific implementation manner, the critical path includes a data transmission path associated with the partition boundary line.

[0016] In a specific implementation manner, the data transmission path associated with the dividing boundary line is a data transmission path divided and disconnected by the dividing boundary line.

[0017] In a specific implementation scheme, before forming a directed graph with all the edges and the nodes corresponding to the edges and setting the directed graph as a time sequence graph, the method further includes:

[0018] A timing check edge is established inside an output device for data transmission, and a timing check is performed based on the timing check edge.

[0019] In a specific implementation scheme, all the edges include edges within devices and between devices through which the critical path passes, edges corresponding to the clock path, and the timing check edges.

[0020] In a second aspect, the present application provides a timing diagram establishment device, which adopts the following technical solution: the device includes:

[0021] A boundary line acquisition module is used to acquire a segmentation boundary line, where the segmentation boundary line is a segmentation boundary line that divides the DUT module into different DUT sub-modules;

[0022] A path search module, configured to search for a critical path according to a direction of data transmission, wherein a starting position of the search for the critical path is the segmentation boundary line;

[0023] A node and edge establishment module, configured to establish nodes at the device ports through which the critical path passes, and to establish edges within the device through which the critical path passes and between the devices;

[0024] a clock edge establishing module, configured to search for a clock path corresponding to the critical path at the end position of the critical path, and establish a corresponding edge according to the clock path;

[0025] The timing graph establishing module is used to form a directed graph by forming all the established edges and all the nodes corresponding to the edges, and setting the directed graph as a timing graph.

[0026] In a third aspect, the present application provides a computer device that adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute any of the above-mentioned timing diagram establishment methods.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute any of the above-mentioned timing diagram establishment methods.

[0028] In summary, this application has the following beneficial technical effects:

[0029] According to the cutting boundary, forward and backward searches are performed for the critical paths associated with the cutting boundary. After the critical path is found, nodes and edges are established on the critical path to generate the final directed graph, which is the timing graph required by the user. By simplifying the timing graph, the number of nodes and edges is reduced, so that the timing graph can be quickly established. Compared with the existing timing graph establishment method, the time for establishing the timing graph is saved, and the amount of calculation in the later timing analysis can be reduced, the analysis efficiency is improved, and it is convenient for multiple use in engineering iterations. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram for illustrating a timing diagram established by an existing method;

[0031] Figure 2 is a flow chart of a method for establishing a timing diagram in an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of a timing diagram established by the method of an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of a timing diagram establishing device in an embodiment of the present application;

[0034] Figure 5 It is a schematic diagram used to embody a computer device in an embodiment of the present application.

[0035] Reference numerals: 401, boundary line acquisition module; 402, path search module; 403, node and edge establishment module; 404, clock edge establishment module; 405, timing diagram establishment module. DETAILED DESCRIPTION

[0036] The following combination Figure 1-Figure 5 This application is described in further detail.

[0037] The present application discloses a method for establishing a timing diagram, which is applied to a timing diagram establishment system. The method can be used to quickly establish a timing diagram for timing analysis between different DUT submodules. Considering the limited resource capacity of a single FPGA, when the design under test (DUT module) is large, it is difficult for a single FPGA to perform large-scale DUT module verification. Therefore, by dividing the DUT module into different submodules and distributing them to multiple FPGAs for processing, a multi-FPGA verification system is constructed, which can efficiently complete the verification of the design under test.

[0038] The existing timing diagram establishment method usually aims at establishing the timing diagram of the complete DUT module. Figure 1For a complete DUT design, all data transmission paths and timing check paths will be marked with edges, and the directed graph composed of all nodes and all edges will be set as a timing diagram. However, the inventors found that after the large-scale DUT modules were segmented, a time-division multiplexing module with a large delay was introduced, and the critical path of the system appeared on the segmentation boundary. It can also be understood that the critical path of the system is related to the segmentation boundary. Therefore, it is only necessary to establish a timing diagram for the path related to the segmentation boundary. The timing diagram can be established quickly, saving computing time and improving the efficiency of timing analysis. Therefore, the main application scenario of the present application solution is also mainly aimed at the application scenario of DUT module segmentation.

[0039] Considering that the existing timing diagram establishment method often establishes the timing diagram for the entire design under test, which will result in a large amount of computing time and reduced efficiency, therefore, in order to help save computing time and improve work efficiency, the present application provides a timing diagram establishment method.

[0040] Reference Figure 2 , the method comprises the following steps:

[0041] S10, obtaining a partitioning boundary line, where the partitioning boundary line is a partitioning boundary line that divides the DUT module into different DUT sub-modules.

[0042] Specifically, the main application scenario of the present application solution is the scenario of DUT module segmentation. Therefore, before establishing the timing diagram, the user will first use the software tool to segment the DUT module into different DUT sub-modules. The software tool will record the segmentation boundary line. When establishing the timing diagram, the segmentation boundary line information will be transmitted to the timing diagram establishment system. After the system obtains the segmentation boundary line, it will perform subsequent timing diagram establishment operations based on the segmentation boundary line. Figure 3 , the thick solid line in the figure is the dividing boundary line.

[0043] S20 , searching for a critical path according to the direction of data transmission, wherein the starting position of searching for the critical path is the segmentation boundary line.

[0044] Specifically, considering that the time-division multiplexing module introduced after the DUT module is cut has a large delay, the critical path of the system is generally associated with the dividing boundary line. Therefore, the timing diagram establishment method adopted in the present application scheme starts the search for the critical path with the dividing boundary line as the starting position. Specifically, the search method for the critical path includes forward search and backward search, first performing the backward search and then the forward search; the forward and backward directions are determined according to the direction of data transmission, that is, the forward search is performed in the direction of data transmission, and the backward search is performed in the opposite direction of data transmission.

[0045] Among them, the critical path is mainly the data transmission path associated with the dividing boundary line, which can also be understood as the data transmission path that is divided and disconnected by the dividing boundary line. Figure 3 , for a complete DUT module, the DUT module is divided into two parts by the split boundary line. The split boundary line disconnects the connection between the two LUT2s. Then the system will start from the split boundary line and search backward and forward for the critical path associated with the disconnected transmission path. The data transmission path that can be processed in one FPGA and does not exist across the FPGA system does not need to be paid attention to, and does not need to be marked. Figure 3 The data passes through the trigger of the I3 input port, and then passes through LUT1 and LUT2 in sequence, and finally outputs the data through the trigger of the output port. The entire data transmission process can be completed in one FPGA. There is no cross-FPGA system situation, so the data transmission path does not need to be labeled; for the path across the FPGA system, the nodes and edges need to be labeled and a timing diagram that can be used for timing analysis is generated.

[0046] It should be noted that the starting position of the backward search critical path is the split boundary line, and the end position of the backward search critical path is the clock starting position; the starting position of the forward search critical path is the split boundary line, and the end position of the forward search critical path is the timing checkpoint position, wherein the timing checkpoint position is located inside the output device of the data transmission, refer to Figure 3 The output device of data transmission is the trigger at the output end, and the timing checkpoint is also the D end of the trigger.

[0047] S30, establishing nodes at the ports of the devices through which the critical path passes, and establishing edges inside the devices through which the critical path passes and between the devices.

[0048] Specifically, when the searched critical path passes through devices such as flip-flops and LUTs, nodes (vertex) are established at the ports (ports) of the devices that the path passes through, and edges (edges) are drawn between devices and between different ports within the devices, thus forming a complete path graph. Figure 3 , establish nodes (vertex) for the ports I1, I2, I3, CLK connected to the trigger, and the I0 and I1 ports of the LUT respectively; draw directed edges (edges) between devices, and the direction of the edge is also the direction of data transmission; inside the device, you can draw edges (edges) according to the timing relationship file (liberty) inside the device, for example, a directed edge from the CLK end to the Q end inside the trigger.

[0049] S40 , searching for a clock path corresponding to the critical path at the end position of the critical path, and establishing a corresponding edge according to the clock path.

[0050] Specifically, a clock path corresponding to the critical path is searched in reverse at the end position of the critical path, and a corresponding edge is established according to the clock path.

[0051] S50: All the established edges and all the nodes corresponding to the edges are combined into a directed graph, and the directed graph is set as a time sequence graph.

[0052] Specifically, all edges established along the critical path and all nodes associated with them are combined into a directed graph. This directed graph is the timing diagram required by the end user. Creating a timing diagram is a key early step in timing analysis. Simplifying the timing diagram simplifies subsequent steps, thereby improving analysis efficiency.

[0053] In the present application scheme, forward and backward searches are performed on the cutting boundaries for the critical paths associated with the cutting boundaries. After the critical paths are found, nodes and edges are established on the critical paths passed through to generate the final directed graph, which is the timing graph required by the user. By simplifying the timing graph, the number of nodes and edges is reduced, so that the timing graph can be quickly established. Compared with the existing timing graph establishment method, the time for establishing the timing graph is saved, and at the same time, the amount of calculation in the later timing analysis can be reduced, the analysis efficiency can be improved, and it is convenient for multiple use in engineering iterations.

[0054] In one embodiment, considering that a certain time relationship needs to be satisfied between the data path and the clock path, before forming a directed graph with all established edges and nodes corresponding to the edges and setting the directed graph as a timing graph, the following steps may be further performed:

[0055] Timing check edges are established within the output device of data transmission, and timing checks are performed based on these edges. Timing checks are also a crucial part of creating a timing diagram. Therefore, the edges used in the final timing diagram include those within and between devices along which the critical path passes, edges corresponding to the clock path, and timing check edges.

[0056] In the present application, considering that a certain time relationship needs to be satisfied between the data path and the clock path, in order to meet the requirements, when establishing the timing diagram, the timing inside the trigger is checked to ensure the accuracy of the established timing diagram.

[0057] Figure 2 FIG. 1 is a flow chart of a method for establishing a timing diagram in one embodiment. It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be executed in other orders; and Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0058] Based on the above method, an embodiment of the present application also discloses a timing diagram establishment device.

[0059] Reference Figure 4 , the device includes the following modules:

[0060] The boundary line acquisition module 401 is used to acquire a segmentation boundary line, where the segmentation boundary line is a segmentation boundary line that divides the DUT module into different DUT sub-modules;

[0061] A path search module 402 is configured to search for a critical path according to a direction of data transmission, wherein the starting position of the search for the critical path is a segmentation boundary line;

[0062] A node and edge establishment module 403 is used to establish nodes at the device ports through which the critical path passes, and to establish edges within the device and between the devices through which the critical path passes;

[0063] A clock edge establishing module 404 is configured to search for a clock path corresponding to the critical path at the end position of the critical path and establish a corresponding edge according to the clock path;

[0064] The time sequence graph establishing module 405 is used to form a directed graph by combining all the established edges and all the nodes corresponding to the edges, and to set the directed graph as a time sequence graph.

[0065] In one embodiment, the path search module 402 is specifically configured to search for critical paths in a backward and forward direction according to the direction of data transmission; wherein the backward search is performed first, and then the forward search is performed.

[0066] In one embodiment, the starting position of the backward search critical path in the path search module 402 is the split boundary line, and the ending position of the backward search critical path is the clock starting position; the starting position of the forward search critical path is the split boundary line, and the ending position of the forward search critical path is the timing checkpoint position, wherein the timing checkpoint position is located inside the output device of data transmission.

[0067] In one embodiment, the critical path in the path search module 402 includes a data transmission path associated with a partition boundary line.

[0068] In one embodiment, the data transmission path associated with the dividing boundary line in the path search module 402 is the data transmission path divided and disconnected by the dividing boundary line.

[0069] In one embodiment, the timing diagram establishing module 405 is further configured to establish a timing check edge inside the output device for data transmission, and perform a timing check based on the timing check edge.

[0070] In one embodiment, all edges in the timing diagram creation module 405 include edges within and between devices through which critical paths pass, edges corresponding to clock paths, and timing check edges.

[0071] The timing diagram establishment device provided in the embodiment of the present application can be applied to the timing diagram establishment method provided in the above embodiment. For relevant details, please refer to the above method embodiment. Its implementation principles and technical effects are similar and will not be repeated here.

[0072] It should be noted that: the timing diagram establishment device provided in the embodiment of the present application only uses the division of the above-mentioned functional modules / functional units as an example to illustrate when establishing the timing diagram. In actual applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the timing diagram establishment device can be divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the timing diagram establishment method provided in the above-mentioned method embodiment and the implementation method of the timing diagram establishment device provided in this embodiment belong to the same concept. The specific implementation process of the timing diagram establishment device provided in this embodiment is detailed in the above-mentioned method embodiment and will not be repeated here.

[0073] The embodiment of the present application also discloses a computer device.

[0074] Specifically, if Figure 5As shown, the computer device can be a computer device such as a desktop computer, a laptop computer, a handheld computer, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. The processor and the memory may be connected via a bus or other means. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processing units (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gate or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned chips.

[0075] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method embodiment is implemented. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0076] The embodiment of the present application also discloses a computer-readable storage medium.

[0077] Specifically, a computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art will understand that all or part of the processes in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it may include the processes of the implementation methods of the above-mentioned methods. Among them, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium may also include a combination of the above-mentioned types of memories.

[0078] This specific embodiment is merely an explanation of the present invention and is not intended to limit the present invention. After reading this specification, those skilled in the art may make non-creative modifications to this embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A method for establishing a timing diagram, characterized in that: The method comprises: Obtaining a segmentation boundary line, where the segmentation boundary line is a segmentation boundary line that divides the DUT module into different DUT sub-modules; Searching for a critical path according to the direction of data transmission, wherein a starting position of searching for the critical path is the segmentation boundary line; Establishing nodes at the ports of the devices through which the critical path passes, and establishing edges inside the devices through which the critical path passes and between the devices; Searching for a clock path corresponding to the critical path at the end position of the critical path, and establishing a corresponding edge according to the clock path; All the established edges and all the nodes corresponding to the edges are combined into a directed graph, and the directed graph is set as a time sequence graph.

2. The method according to claim 1, characterized in that: The searching of the critical path according to the direction of data transmission includes: The critical path is searched backward and forward according to the direction of data transmission; wherein, the critical path is searched backward first and then forward.

3. The method according to claim 2, characterized in that: The starting position of the backward search critical path is the split boundary line, and the ending position of the backward search critical path is the clock starting position; the starting position of the forward search critical path is the split boundary line, and the ending position of the forward search critical path is the timing checkpoint position, wherein the timing checkpoint position is located inside the output device of data transmission.

4. The method according to claim 1, characterized in that: The critical path includes a data transmission path associated with the partition boundary line.

5. The method according to claim 4, characterized in that: The data transmission path associated with the dividing boundary line is a data transmission path divided and disconnected by the dividing boundary line.

6. The method according to claim 1, characterized in that: Before forming a directed graph with all the established edges and the nodes corresponding to the edges and setting the directed graph as a time sequence graph, the method further includes: A timing check edge is established inside an output device for data transmission, and a timing check is performed based on the timing check edge.

7. The method according to claim 6, characterized in that: All the edges include the edges inside the device and between the devices through which the critical path passes, the edges corresponding to the clock path, and the timing check edges.

8. A timing diagram establishing device, characterized in that: The device comprises: A boundary line acquisition module (401) is used to acquire a segmentation boundary line, wherein the segmentation boundary line is a segmentation boundary line that divides a DUT module into different DUT sub-modules; A path search module (402), used to search for a critical path according to the direction of data transmission, wherein the starting position of the search for the critical path is the segmentation boundary line; A node and edge establishment module (403) is used to establish nodes at the device ports through which the critical path passes, and to establish edges inside the device through which the critical path passes and between the devices; A clock edge establishing module (404), configured to search for a clock path corresponding to the critical path at the end position of the critical path, and establish a corresponding edge according to the clock path; The timing graph establishing module (405) is used to form a directed graph with all the established edges and all the nodes corresponding to the edges, and set the directed graph as a timing graph.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.

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