Channel identification device for live pigs wearing UHF ear tags

Abstract

The invention discloses a channel identification device for a live pig wearing a UHF ear tag, and the device comprises a rectification circuit and a modulation circuit, and also comprises a self-inspection processing circuit which comprises a first processing unit, a second processing unit, and an output unit. The rectification circuit rectifies the RF signal, feeds back an Input signal to the first processing unit for voltage stabilization power supply and fault detection processing, and feeds back a Port1 fault signal and a VDD1 power supply signal to the second processing unit, and feeds back a VDD2 power supply signal to the output unit. The second processing unit generates different Port2 reference carrier signals based on whether the Port1 fails or not, and the different Port2 reference carrier signals are fed back to the modulation circuit through the output unit.

Description

Technical Field

[0001] The invention relates to the technical field of radio frequency signals, and in particular to a channel identification device for pigs wearing UHF ear tags. Background Art

[0002] RFID radio frequency technology shows broad application prospects in the field of biometrics. However, current technology faces a significant challenge: the electromagnetic environment of the device wearing the RFID tag is extremely complex, and the power fluctuation of the input signal may be as high as hundreds or even thousands of times. In order to ensure that the chip can work stably in electromagnetic fields of different intensities, it is particularly important to design a reliable circuit to distinguish and locate the signal. RFID technology can be mainly divided into three modes: passive, semi-active and active. The active mode is known for its long-distance transmission capability, but correspondingly, its cost is also high. The passive mode is known for its low cost, but its use scenario is relatively limited, and because it relies on passive feedback, the transmission distance is short. Once it exceeds the effective range, it is impossible to obtain effective information, which is particularly inconvenient in large-scale applications. The semi-active mode cleverly combines the power supply advantages of the active and the passive self-excited reflection characteristics, and its development potential is huge. In view of this, the present application proposes a detection device that can identify the wearing of UHF ear tags. The device can automatically detect and flexibly switch between active and semi-active modes to meet the needs of different application scenarios. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a channel identification device for pigs wearing UHF ear tags, including a rectifier circuit and a modulation circuit, and also including a self-test processing circuit. The self-test processing circuit includes a first processing unit, a second processing unit, and an output unit. The rectifier circuit rectifies the RF signal and feeds back the Input signal to the first processing unit for voltage stabilization and fault detection processing, and feeds back the Port_1 fault signal and the VDD_1 power supply signal to the second processing unit, and the VDD_2 power supply signal to the output unit. The second processing unit generates different Port_2 reference carrier signals based on whether Port_1 is faulty, and then feeds back to the modulation circuit via the output unit.

[0004] Furthermore, the first processing unit includes a plurality of operational amplifiers, a plurality of resistors, MOS tubes, diodes, voltage stabilizing chips, and capacitors;

[0005] The in-phase end of the operational amplifier U1 among the several operational amplifiers is connected to the in-phase end of the operational amplifier U2, the A pin of the voltage stabilizing chip U3, one end of the resistor R1, one end of the resistor R2, the drain of the MOS tube Q1, and VDD_1, the inverting end is connected to the other end of the resistor R1, one end of the resistor R3, one end of the resistor R4, the other end of the resistor R4, one end of the capacitor C1, and the cathode of the diode D1, and the output end is connected to Port_1; the inverting end of the operational amplifier U2 is connected to one end of the resistor R5 and one end of the resistor R7, and the output end is connected to the gate of the MOS tube Q1; the source of the MOS tube Q1 is connected to the other end of the resistor R5 and VDD_2; the REF pin of the voltage stabilizing chip U3 is connected to the other end of the resistor R2 and one end of the resistor R6; the anode of the diode D1 is connected to the Input; the K pin of the voltage stabilizing chip U3, the other end of the resistor R3, the other end of the resistor R6, the other end of the resistor R7, the other end of the capacitor C1 and the ground are connected.

[0006] Furthermore, the second processing unit includes a plurality of operational amplifiers, a plurality of resistors, an inverter, a plurality of diodes, a plurality of triodes, a MOS tube, a trigger, and a capacitor;

[0007] The input end of the inverter U4 in the several operational amplifiers is connected to the base of the transistor Q4, the 1Q pin of the trigger U7, and Port_2, and the output end is connected to the base of the transistor Q2; the in-phase end of the operational amplifier U5 is connected to one end of the resistor R11 and one end of the resistor R12, the inverting end is connected to the in-phase end of the operational amplifier U6, one end of the resistor R10, one end of the resistor R14, and one end of the capacitor C3, and the output end is connected to the anode of the diode D2; the inverting end of the operational amplifier U6 is connected to one end of the resistor R8, the other end of the resistor R11, and one end of the adjustable resistor R13, and the output end is connected to the anode of the diode D3; the CLR pin and PRE pin of the trigger U7 are connected to the collector of the transistor Q2, the other end of the resistor R8, one end of the resistor R9, and VDD_1, and the 1D pin is connected to the inverting pin of 1Q The 1CLK pin is connected to the source of the MOS tube Q3, one end of the resistor R15, and one end of the resistor R17; the emitter of the transistor Q2 is connected to the other end of the resistor R10; the gate of the MOS tube Q3 is connected to the other end of the resistor R9, one end of the resistor R16, and one end of the capacitor C2; the collector of the transistor Q4 is connected to the other end of the resistor R14; the base of the transistor Q5 is connected to Port_1, and the collector is connected to the other end of the adjustable resistor R13; the cathode of the diode D2, the cathode of the diode D3, and the other end of the resistor R15 are connected; the drain of the MOS tube Q3, the emitter of the transistor Q4, the emitter of the transistor Q5, the other end of the resistor R12, the other end of the resistor R16, the other end of the resistor R17, the other end of the capacitor C1, the other end of the capacitor C2 and the ground are connected.

[0008] Furthermore, the output unit includes a plurality of MOS tubes and inverters;

[0009] The gate of the MOS tube Q6 among the several MOS tubes is connected to the input end of the inverter U8, the gate of the MOS tube Q8, and Port_2, the drain is connected to the drain of the MOS tube Q7 and VDD_2, the source is connected to the source of the MOS tube Q7, the drain of the MOS tube Q8, the drain of the MOS tube Q9, and Coil; the gate of the MOS tube Q7 is connected to the output end of the inverter U8 and the gate of the MOS tube Q9; the source of the MOS tube Q8, the source of the MOS tube Q9 and the grounding end are connected.

[0010] Furthermore, the second processing unit also includes a resistor R18;

[0011] One end of the resistor R18 is connected to Port_2, and the other end is connected to the ground, and is used as a loop when the 1Q pin of the trigger U7 has no external connection.

[0012] Furthermore, the output unit also includes a plurality of resistors;

[0013] One end of the resistor R19 among the plurality of resistors is connected to the gate of the MOS tube Q9; one end of the resistor R20 is connected to the gate of the MOS tube Q8; the other end of the resistor R19 and the other end of the resistor R20 are connected to the ground end, which is used for fast discharge of the internal parasitic capacitance of the MOS to increase the response speed.

[0014] The beneficial effects of the present invention compared with the prior art are:

[0015] When the RFID tag is beyond the reading range of the reader or encounters a fault and cannot be read normally, the present invention can automatically switch to the semi-active mode without changing the original tag data, and issue clear instructions to the staff to ensure the continuity and efficiency of the operation. In the fault-free state, the passive detection mode will be used to increase the battery life. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 The present invention provides an overall structural diagram.

[0018] Figure 2 This is a schematic diagram of the first processing unit of the self-check processing circuit provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the second processing unit of the self-check processing circuit provided by the present invention.

[0020] Figure 4This is a schematic diagram of the output unit of the self-check processing circuit provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0022] The present invention discloses a channel identification device for pigs wearing UHF ear tags, comprising a rectifier circuit and a modulation circuit, and also comprising a self-check processing circuit, wherein the self-check processing circuit comprises a first processing unit, a second processing unit, and an output unit, wherein the rectifier circuit rectifies an RF signal and feeds back an Input signal to the first processing unit for voltage stabilization and fault detection processing, and feeds back a Port_1 fault signal and a VDD_1 power supply signal to the second processing unit, and a VDD_2 power supply signal to the output unit, wherein the second processing unit generates different Port_2s based on Port_1 to the output unit to provide different carrier signals for the modulation circuit.

[0023] Specifically, the first processing unit includes a plurality of operational amplifiers, a plurality of resistors, MOS tubes, diodes, voltage stabilizing chips, and capacitors;

[0024] The in-phase end of the operational amplifier U1 among the several operational amplifiers is connected to the in-phase end of the operational amplifier U2, the A pin of the voltage stabilizing chip U3, one end of the resistor R1, one end of the resistor R2, the drain of the MOS tube Q1, and VDD_1, the inverting end is connected to the other end of the resistor R1, one end of the resistor R3, one end of the resistor R4, the other end of the resistor R4, one end of the capacitor C1, and the cathode of the diode D1, and the output end is connected to Port_1; the inverting end of the operational amplifier U2 is connected to one end of the resistor R5 and one end of the resistor R7, and the output end is connected to the gate of the MOS tube Q1; the source of the MOS tube Q1 is connected to the other end of the resistor R5 and VDD_2; the REF pin of the voltage stabilizing chip U3 is connected to the other end of the resistor R2 and one end of the resistor R6; the anode of the diode D1 is connected to the Input; the K pin of the voltage stabilizing chip U3, the other end of the resistor R3, the other end of the resistor R6, the other end of the resistor R7, the other end of the capacitor C1 and the ground are connected.

[0025] Specifically, the second processing unit includes a plurality of operational amplifiers, a plurality of resistors, an inverter, a plurality of diodes, a plurality of triodes, a MOS tube, a trigger, and a capacitor;

[0026] The input end of the inverter U4 in the several operational amplifiers is connected to the base of the transistor Q4, the 1Q pin of the trigger U7, and Port_2, and the output end is connected to the base of the transistor Q2; the in-phase end of the operational amplifier U5 is connected to one end of the resistor R11 and one end of the resistor R12, the inverting end is connected to the in-phase end of the operational amplifier U6, one end of the resistor R10, one end of the resistor R14, and one end of the capacitor C3, and the output end is connected to the anode of the diode D2; the inverting end of the operational amplifier U6 is connected to one end of the resistor R8, the other end of the resistor R11, and one end of the adjustable resistor R13, and the output end is connected to the anode of the diode D3; the CLR pin and PRE pin of the trigger U7 are connected to the collector of the transistor Q2, the other end of the resistor R8, one end of the resistor R9, and VDD_1, and the 1D pin is connected to the inverting pin of 1Q The 1CLK pin is connected to the source of the MOS tube Q3, one end of the resistor R15, and one end of the resistor R17; the emitter of the transistor Q2 is connected to the other end of the resistor R10; the gate of the MOS tube Q3 is connected to the other end of the resistor R9, one end of the resistor R16, and one end of the capacitor C2; the collector of the transistor Q4 is connected to the other end of the resistor R14; the base of the transistor Q5 is connected to Port_1, and the collector is connected to the other end of the adjustable resistor R13; the cathode of the diode D2, the cathode of the diode D3, and the other end of the resistor R15 are connected; the drain of the MOS tube Q3, the emitter of the transistor Q4, the emitter of the transistor Q5, the other end of the resistor R12, the other end of the resistor R16, the other end of the resistor R17, the other end of the capacitor C1, the other end of the capacitor C2 and the ground are connected.

[0027] Specifically, the output unit includes a plurality of MOS tubes and inverters;

[0028] The gate of the MOS tube Q6 among the several MOS tubes is connected to the input end of the inverter U8, the gate of the MOS tube Q8, and Port_2, the drain is connected to the drain of the MOS tube Q7 and VDD_2, the source is connected to the source of the MOS tube Q7, the drain of the MOS tube Q8, the drain of the MOS tube Q9, and Coil; the gate of the MOS tube Q7 is connected to the output end of the inverter U8 and the gate of the MOS tube Q9; the source of the MOS tube Q8, the source of the MOS tube Q9 and the grounding end are connected.

[0029] Specifically, the second processing unit further includes a resistor R18;

[0030] One end of the resistor R18 is connected to Port_2, and the other end is connected to the ground, and is used as a loop when the 1Q pin of the trigger U7 has no external connection.

[0031] Specifically, the output unit also includes a number of resistors;

[0032] One end of the resistor R19 among the plurality of resistors is connected to the gate of the MOS tube Q9; one end of the resistor R20 is connected to the gate of the MOS tube Q8; the other end of the resistor R19 and the other end of the resistor R20 are connected to the ground end, which is used for fast discharge of the internal parasitic capacitance of the MOS to increase the response speed.

[0033] See also Figure 1 and Figure 2 , in the application, the rectifier circuit is used to rectify the RF signal received by the antenna and output the Input signal to the first processing unit by means of boosting, etc. Due to the complex environment in which the RFID tag is located, the power of the input signal can change by multiples, and the scheme adopts a semi-active design. One path of the Input signal is first stored in capacitor C1 to avoid overcurrent, and the other path is fed back to the voltage regulator chip U3 through resistor R1 for voltage stabilization and power supply to the subsequent circuit and VDD_1 power circuit. The inverting end of the operational amplifier U2 samples the voltage of the resistor R5 and the resistor R7 to control the MOS tube Q1 to turn on, and VDD_2 is used to power the output unit. At the same time, the operational amplifier U1 in the first processing unit also samples the energy storage voltage of the capacitor C1. When the tag is far away from the reading range of the reader or cannot be read due to a fault (the rectifier current cannot receive the RF signal, and there is no Input signal feedback), the operational amplifier U1 outputs the signal Port_1 to the second processing unit;

[0034] See also Figure 2 and Figure 3The second processing unit is used to generate a reference carrier signal used for modulation, and the second processing unit has the function of power-on self-reset and switching reference carrier signals of different frequency bands in case of fault. The purpose of switching is to switch from passive mode to semi-active mode in case of fault. In passive mode, the reference carrier signal and energy storage are provided by the Input signal received by the first processing unit. The reference carrier signal is the carrier waveform of the tag data when it is sent, and in semi-active mode, power is supplied by the energy storage capacitor, and the reference carrier signals of different frequency bands are autonomously stimulated to feedback the tag information; wherein, when there is no fault, the Input signal can be fed back normally, and in the initial stage of power-on, the resistor R9 and the capacitor C2 delay the MOS tube Q3 shutdown signal, and the MOS tube Q3 is in the initial stage of power-on. In the on state, any output of the inverter U4 and the operational amplifier U6 will be pulled down through the MOS tube Q3 loop, the third pin CLK of the trigger U7 is at a low level, the capacitor C2 completes the energy storage and is fed back to the gate of the MOS tube Q3, the MOS tube Q3 is turned off, and the trigger U7 enters the switching state; at the same time, the operational amplifier U6 and the operational amplifier U5 of the second processing unit are at the initial stage of power-on, and the operational amplifier U5 outputs, and the output is used for the trigger U7 to obtain the initial switching signal after the MOS tube Q3 is turned off. The switching signal will be fed back to the inverter U4 and the triode Q4 at the same time. The temporal output of the operational amplifier U6 and the operational amplifier U5 is set by the voltage divider of the resistor R8, the resistor R11, and the resistor R12. The adjustable resistor R13 is used when there is a signal changing the frequency band in Port_1, and there is no fault. When the adjustable resistor R13 is equivalent to an open circuit, the operational amplifier U5 is in the output state because the voltage at the in-phase terminal is higher than the voltage at the inverting terminal capacitor C3 in the initial state. When the MOS tube Q3 is turned on, the third pin CLK of the trigger U7 is in a pull-down state. Therefore, the trigger U7 has no action. At this time, it is in the power-on self-reset stage. The fifth pin 1Q of the trigger U7 is cut off. The inverter U4 inverts and outputs a signal to the base of the transistor Q2. The collector VDD_1 will be fed back to the capacitor C1 through the resistor R10 to keep the voltage at the capacitor C1 terminal at a high potential. When the capacitor C2 stores the voltage through the resistor R9 so that the gate potential of the MOS tube Q3 is not at the negative voltage difference when the MOS tube Q3 is turned on, the MOS tube Q3 will be cut off, and the third pin CLK of the trigger U7 is connected to the After receiving the signal output by the operational amplifier U5, the output state of the fifth pin 1Q will be switched, and the fifth pin 1Q of the trigger U7 will output. At this time, the inverter U4 is cut off, and the transistor Q4 turns on the capacitor C3 through the resistor R14, the transistor Q4, and the ground terminal loop. The voltage of the capacitor C3 drops. The resistance configuration of the resistor R14 and the resistor R10 is the same, and the constant curve is consistent. When the resistors R8, R11, and R12 are consistent, the output frequencies of the operational amplifiers U5 and U6 will be the same due to the same resistance configuration. The UHF ultra-high frequency and LF low frequency are controlled by changing the capacity of the capacitor C3 or synchronously adjusting the resistance values ​​of the resistors R10 and R14. The lower the capacity of the capacitor C3 or the lower the resistance values ​​of the resistors R10 and R14, the faster the output frequencies of the operational amplifiers U5 and U6.When the voltage of the capacitor C3 drops to the voltage of the inverting terminal of the operational amplifier U6, the output signal of the operational amplifier U6 is output through the diode D3. The resistors R15 and R17 are used to match the output signals of the operational amplifiers U5 and U6 to the voltage range of the trigger U7 input. At this time, the trigger U7 is switched to the fifth pin 1Q cut-off again, and the signal is input to the output unit through Port_2. When the tag is far away from the reading range of the reader or cannot be read due to a fault, the voltage at the capacitor C1 end will drop, and the inverting terminal of the operational amplifier U1 samples the capacitor C1 and outputs the signal to Port_1 after the voltage is divided by the resistors R3 and R4 (within the voltage regulation range of the voltage regulator chip U3, there is no input with the input, and the capacitor C1 end is connected to the voltage It will drop but still be within the voltage regulation range of the voltage regulator chip U3. When it is lower than the setting of resistor R3 and resistor R4, it will be detected and output by the operational amplifier U1). At this time, the transistor Q5 is started, and the voltage at the end of resistor R8 will be shunted by the adjustable resistor R13 to cause a voltage drop. The voltage at the connection end of resistor R11 and resistor R12 will drop in proportion. The detection range of the voltage at the end of the switching capacitor C3 is changed, and the signal Port_2 of different frequencies is fed back to the processing unit. In this way of switching the frequency band, the same tag information can be used without increasing the data storage capacity of the tag. At this time, after receiving the same tag information in different frequency bands, the reader can instruct the staff to replace or check whether the corresponding worn tag has problems such as faults.

[0035] See also Figure 4 In the processing unit, MOS transistors Q6 to Q9 are used to produce alternating signals of the Coil coil antenna, and VDD_2 is used to power the MOS transistors. When the Port_2 signal of the second processing unit is input, any group of MOS transistors Q6 and Q8 and MOS transistors Q7 and Q9 are turned on, and Coil provides carrier signals of different frequency bands through MOS transistors Q8 or MOS transistors Q9 and the ground loop respectively. The signals are fed back to the modulation circuit to send the tag data according to the carriers of different frequency bands.

[0036] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A channel identification device for pigs wearing UHF ear tags, comprising a rectifier circuit and a modulation circuit, characterized in that: It also includes a self-test processing circuit, which includes a first processing unit, a second processing unit, and an output unit. The rectifier circuit rectifies the RF signal and feeds back the Input signal to the first processing unit for voltage stabilization and fault detection processing, and feeds back the Port_1 fault signal and the VDD_1 power supply signal to the second processing unit, and the VDD_2 power supply signal to the output unit. The second processing unit generates different Port_2 reference carrier signals based on whether Port_1 is faulty, and then feeds back the signals to the modulation circuit via the output unit.

2. The channel identification device for pigs wearing UHF ear tags according to claim 1, characterized in that: The first processing unit includes a plurality of operational amplifiers, a plurality of resistors, MOS tubes, diodes, voltage stabilizing chips, and capacitors; The in-phase end of the operational amplifier U1 among the several operational amplifiers is connected to the in-phase end of the operational amplifier U2, the A pin of the voltage stabilizing chip U3, one end of the resistor R1, one end of the resistor R2, the drain of the MOS tube Q1, and VDD_1, the inverting end is connected to the other end of the resistor R1, one end of the resistor R3, one end of the resistor R4, the other end of the resistor R4, one end of the capacitor C1, and the cathode of the diode D1, and the output end is connected to Port_1; the inverting end of the operational amplifier U2 is connected to one end of the resistor R5 and one end of the resistor R7, and the output end is connected to the gate of the MOS tube Q1; the source of the MOS tube Q1 is connected to the other end of the resistor R5 and VDD_2; the REF pin of the voltage stabilizing chip U3 is connected to the other end of the resistor R2 and one end of the resistor R6; the anode of the diode D1 is connected to the Input; the K pin of the voltage stabilizing chip U3, the other end of the resistor R3, the other end of the resistor R6, the other end of the resistor R7, the other end of the capacitor C1 and the ground are connected.

3. The channel identification device for pigs wearing UHF ear tags according to claim 1, characterized in that: The second processing unit includes a plurality of operational amplifiers, a plurality of resistors, an inverter, a plurality of diodes, a plurality of triodes, a MOS tube, a trigger, and a capacitor; The input end of the inverter U4 in the several operational amplifiers is connected to the base of the transistor Q4, the 1Q pin of the trigger U7, and Port_2, and the output end is connected to the base of the transistor Q2; the in-phase end of the operational amplifier U5 is connected to one end of the resistor R11 and one end of the resistor R12, the inverting end is connected to the in-phase end of the operational amplifier U6, one end of the resistor R10, one end of the resistor R14, and one end of the capacitor C3, and the output end is connected to the anode of the diode D2; the inverting end of the operational amplifier U6 is connected to one end of the resistor R8, the other end of the resistor R11, and one end of the adjustable resistor R13, and the output end is connected to the anode of the diode D3; the CLR pin and PRE pin of the trigger U7 are connected to the collector of the transistor Q2, the other end of the resistor R8, one end of the resistor R9, and VDD_1, and the 1D pin is connected to the inverting pin of 1Q The 1CLK pin is connected to the source of the MOS tube Q3, one end of the resistor R15, and one end of the resistor R17; the emitter of the transistor Q2 is connected to the other end of the resistor R10; the gate of the MOS tube Q3 is connected to the other end of the resistor R9, one end of the resistor R16, and one end of the capacitor C2; the collector of the transistor Q4 is connected to the other end of the resistor R14; the base of the transistor Q5 is connected to Port_1, and the collector is connected to the other end of the adjustable resistor R13; the cathode of the diode D2, the cathode of the diode D3, and the other end of the resistor R15 are connected; the drain of the MOS tube Q3, the emitter of the transistor Q4, the emitter of the transistor Q5, the other end of the resistor R12, the other end of the resistor R16, the other end of the resistor R17, the other end of the capacitor C1, the other end of the capacitor C2 and the ground are connected.

4. The channel identification device for pigs wearing UHF ear tags according to claim 1, characterized in that: The output unit includes a plurality of MOS tubes and inverters; The gate of the MOS tube Q6 among the several MOS tubes is connected to the input end of the inverter U8, the gate of the MOS tube Q8, and Port_2, the drain is connected to the drain of the MOS tube Q7 and VDD_2, the source is connected to the source of the MOS tube Q7, the drain of the MOS tube Q8, the drain of the MOS tube Q9, and Coil; the gate of the MOS tube Q7 is connected to the output end of the inverter U8 and the gate of the MOS tube Q9; the source of the MOS tube Q8, the source of the MOS tube Q9 and the grounding end are connected.

5. The channel identification device for pigs wearing UHF ear tags according to claim 3, characterized in that: The second processing unit further includes a resistor R18; One end of the resistor R18 is connected to Port_2, and the other end is connected to the ground, and is used as a loop when the 1Q pin of the trigger U7 has no external connection.

6. The channel identification device for pigs wearing UHF ear tags according to claim 4, characterized in that: The output unit also includes a number of resistors; One end of the resistor R19 among the plurality of resistors is connected to the gate of the MOS tube Q9; one end of the resistor R20 is connected to the gate of the MOS tube Q8; the other end of the resistor R19 and the other end of the resistor R20 are connected to the ground end, which is used for fast discharge of the internal parasitic capacitance of the MOS to increase the response speed.

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