Manufacturing method of semi-floating gate device
By performing hydrogen treatment and subsequent ion implantation and annealing activation after deposition of the semi-floating gate polysilicon layer, the problem of insufficient surface flatness of the semi-floating gate polysilicon layer is solved, and the device performance is significantly improved.
Patent Information
- Application Number
- CN202411525046.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-07
AI Technical Summary
In the existing semi-floating gate device manufacturing method, the surface flatness of the semi-floating gate polysilicon layer is poor, resulting in the impact of device performance.
After the deposition of the semi-floating gate polysilicon layer is completed, hydrogen treatment is performed to improve the movement capacity of the silicon atoms. Combined with subsequent ion implantation and annealing activation, the movement control of the silicon atoms is further optimized, thereby improving the semi-floating gate before maskless etching The surface flatness of the polysilicon layer.
Through hydrogen treatment and subsequent ion implantation and annealing activation, the surface flatness of the semi-floating gate polysilicon layer is significantly improved, the depth of butterfly recess is reduced, and the device performance is improved.
Smart Images
Figure CN119400694A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a semi-floating gate transistor device. Background Art
[0002] like Figure 1 FIG. 1 is a flow chart of a conventional method for manufacturing a semi-floating gate device. In the manufacturing process of the semi-floating gate device, a semi-floating gate (SFG) process loop mainly includes the following steps:
[0003] Step S100, incoming. Incoming means entering the SFG loop for the process step, and the process before the SFG loop has been completed. For example, a U-shaped groove has been formed and a semi-floating gate dielectric layer has been formed, a bottom polysilicon layer filling the U-shaped groove has been deposited, and the bottom polysilicon layer has been patterned and etched to form a polysilicon window and a bottom semi-floating gate dielectric layer window.
[0004] Step S101, SFG Poly1 Dep, i.e., forming the deposition of the first polysilicon layer in the SFG loop, Poly1 represents the first polysilicon layer, and Dep represents deposition. The first polysilicon layer needs to fill the polysilicon window and the semi-floating gate dielectric layer window formed by the patterned etching of the bottom polysilicon layer, which easily makes the top surface of the first polysilicon layer uneven. The first polysilicon layer and the bottom polysilicon layer are superimposed to form a semi-floating gate polysilicon layer.
[0005] Step S102, SFG P1 IMP&Ann, i.e., performing ion implantation and annealing activation on the semi-floating gate polysilicon layer, wherein P1 represents Poly1, IMP represents ion implantation, and Ann represents annealing activation.
[0006] Step S103, SFG Poly1 Blanket etch, indicates performing maskless etching on the semi-floating gate polysilicon layer.
[0007] Step S104, SFG Poly2 Gate OX, is to form a control gate oxide layer, wherein Poly2 represents a control gate polysilicon layer formed subsequently, and Gate OX represents a control gate oxide layer.
[0008] Step S105, SFG Poly2 Dep. Poly2 represents the control gate polysilicon layer. Compared with Poly1, Poly2 is formed by the first polysilicon deposition in the SFG loop.
[0009] Step S106, SiN RM. RM is an abbreviation of remove. SiN RM means removing the silicon nitride layer.
[0010] In the existing method, the surface roughness is poor when Poly1 is deposited, and the thickness of different regions is uneven. For example, the depth of the butterfly-shaped depression (dishing) is about
[0011] After SFG Poly1 blanket etch, the depth of the dishing of Poly1 is too large, for example, about The target value should be less than If the depth of the butterfly depression exceeds the target value and is too large, it will affect the charge storage capacity of poly1 and the subsequent Poly2 process, and ultimately affect the device performance. Summary of the invention
[0012] The technical problem to be solved by the present invention is to provide a method for manufacturing a semi-floating gate device, which can improve the surface flatness of the semi-floating gate polysilicon and thus improve the performance of the device.
[0013] In order to solve the above technical problems, the present invention provides a method for manufacturing a semi-floating gate device, comprising the steps of:
[0014] Step 1: depositing a semi-floating gate polysilicon layer on the underlying structure, wherein the top surface of the semi-floating gate polysilicon layer is uneven.
[0015] Step 2: Perform hydrogen treatment on the surface of the semi-floating gate polysilicon layer, and utilize the hydrogen treatment to increase the mobility of silicon atoms and thereby improve the flatness of the top surface of the semi-floating gate polysilicon layer.
[0016] Step three: perform ion implantation and annealing activation on the semi-floating gate polysilicon layer.
[0017] Step 4: performing blanket etching on the semi-floating gate polysilicon layer to reduce the thickness of the semi-floating gate polysilicon layer to a set value.
[0018] A further improvement is that the underlying structure includes a semiconductor substrate, a first active area defined by field oxygen is formed on the semiconductor substrate, a semi-floating gate trench is formed in the first active area, a semi-floating gate dielectric layer is formed on the inner surface of the semi-floating gate trench, the semi-floating gate dielectric layer also extends to the surface of the semiconductor substrate outside the semi-floating gate trench and a semi-floating gate dielectric window is formed outside the semi-floating gate trench, and the semi-floating gate polysilicon layer is directly in contact with the semiconductor substrate in the semi-floating gate dielectric window.
[0019] A further improvement is that in step 1, the deposition thickness of the semi-floating gate polysilicon layer is The deposition temperature is 500°C to 700°C.
[0020] A further improvement is that in step 1, the maximum depth of the butterfly-shaped depression on the top surface of the semi-floating gate polysilicon layer is above.
[0021] A further improvement is that in step 4, after the maskless etching, the thickness of the semi-floating gate polysilicon layer above the top surface of the semi-floating gate dielectric layer outside the semi-floating gate trench is
[0022] A further improvement is that in step 4, after the maskless etching, the maximum depth of the butterfly-shaped depression on the top surface of the semi-floating gate polysilicon layer is the following.
[0023] A further improvement is that in step 2, the hydrogen treatment adopts a low-pressure process and the pressure is 10 Torr to 50 Torr.
[0024] A further improvement is that in step 2, the process temperature of the hydrogen treatment is 500° C. to 900° C., the time is 20 seconds to 10 minutes, and the process gas includes hydrogen and nitrogen.
[0025] A further improvement is that, in the hydrogen treatment, the hydrogen flow rate is 3 liters per minute to 15 liters per minute, and the nitrogen flow rate is 5 liters per minute to 15 liters per minute.
[0026] A further improvement is that in step 3, the implanted impurities of the ion implantation of the semi-floating gate polysilicon layer include boron;
[0027] A further improvement is that in step three, the annealing activation includes thermal annealing or laser annealing, and the thermal annealing includes uniform temperature annealing or spike annealing.
[0028] The thermal annealing temperature is 900°C to 1200°C.
[0029] Further improvements include:
[0030] Step 5: forming a control gate dielectric layer;
[0031] Step 6: forming a control gate polysilicon layer.
[0032] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0033] A further improvement is that the field oxide includes shallow trench isolation.
[0034] A further improvement is that in step 1, the deposition process of the semi-floating gate polysilicon layer includes the following sub-steps:
[0035] After the semi-floating gate dielectric layer is grown and before the semi-floating gate dielectric window is formed, a first polysilicon deposition is performed;
[0036] Performing pattern etching on the first polysilicon layer to form a polysilicon window on the top of the semi-floating gate dielectric window, and then etching the semi-floating gate dielectric layer at the bottom of the polysilicon window to form the semi-floating gate dielectric window;
[0037] A second polysilicon deposition is performed to form a second polysilicon layer, wherein the second polysilicon layer completely fills the semi-floating gate dielectric window and the polysilicon window and extends to the surface of the first polysilicon layer outside the polysilicon window, and the semi-floating gate polysilicon layer is formed by stacking the first polysilicon layer and the second polysilicon layer.
[0038] A further improvement is that the semiconductor substrate includes a logic area and a storage array area, and the semi-floating gate device is located in the storage array area.
[0039] The present invention performs hydrogen treatment after the deposition of the semi-floating gate polysilicon layer is completed and before ion implantation. The hydrogen treatment can increase the mobility of silicon atoms in the semi-floating gate polysilicon layer. Due to the increased mobility of silicon atoms, the mobility of silicon atoms can be further controlled by combining the hydrogen treatment itself with the subsequent ion implantation and annealing activation. Finally, the surface flatness of the semi-floating gate polysilicon layer is improved before the subsequent maskless etching, and then the surface flatness of the semi-floating gate polysilicon layer is improved to meet the process requirements after the maskless etching, so that the thickness uniformity of the semi-floating gate polysilicon layer after the maskless etching is increased and the depth of the butterfly-shaped recess is reduced, so that the control ability of the semi-floating gate polysilicon layer on the channel can be improved, thereby improving the performance of the device. Therefore, the present invention can improve the surface flatness of the semi-floating gate polysilicon and thereby improve the performance of the device.
[0040] In addition, the present invention only needs to insert hydrogen treatment after the semi-floating gate polysilicon layer is deposited and before ion implantation, so it also has the characteristics of simple process and easy implementation, and can improve the surface flatness of the semi-floating gate polysilicon at a relatively low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0042] Figure 1 It is a flow chart of a method for manufacturing a conventional semi-floating gate device;
[0043] Figure 2is a flow chart of a method for manufacturing a semi-floating gate device according to an embodiment of the present invention;
[0044] Figure 3 It is a flow chart of a method for manufacturing a semi-floating gate device according to a preferred embodiment of the present invention;
[0045] Figure 4A-4E It is a three-dimensional structural diagram of the device in each step of the manufacturing method of the semi-floating gate device of the preferred embodiment of the present invention;
[0046] Figure 5A-5F It is a cross-sectional structural diagram of the device in the X direction in each step of the manufacturing method of the semi-floating gate device of the preferred embodiment of the present invention. DETAILED DESCRIPTION
[0047] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semi-floating gate device according to an embodiment of the present invention; Figure 3 As shown in FIG. 1 , it is a flow chart of a method for manufacturing a semi-floating gate device according to a preferred embodiment of the present invention; FIG. 4A to FIG. 4E FIG. 1 is a three-dimensional structural diagram of a device in each step of a method for manufacturing a semi-floating gate device according to a preferred embodiment of the present invention; FIG. 5A to FIG. 5F , which is a cross-sectional structural diagram of the device in the X direction in each step of the method for manufacturing a semi-floating gate device according to a preferred embodiment of the present invention; the method for manufacturing a semi-floating gate device according to an embodiment of the present invention comprises the steps of:
[0048] Step 1: depositing a semi-floating gate polysilicon layer 106 on the underlying structure, wherein the top surface of the semi-floating gate polysilicon layer 106 is uneven.
[0049] like Figure 4A As shown, in the embodiment of the present invention, the bottom layer structure includes a semiconductor substrate 102, a first active region defined by a field oxide 103 is formed on the semiconductor substrate 102, a semi-floating gate trench 105 is formed in the first active region, and a semi-floating gate dielectric layer 201 is formed on the inner surface of the semi-floating gate trench 105. Please refer to Figure 5A The semi-floating gate dielectric layer 201 also extends to the surface of the semiconductor substrate 102 outside the semi-floating gate trench 105 and a semi-floating gate dielectric window is formed outside the semi-floating gate trench 105 , and the semi-floating gate polysilicon layer 106 directly contacts the semiconductor substrate 102 in the semi-floating gate dielectric window.
[0050] In the embodiment of the present invention, the semiconductor substrate 102 includes a silicon substrate.
[0051] The field oxide 103 includes shallow trench isolation.
[0052] The semiconductor substrate 102 includes a logic area 101 b and a memory array area 101 a , and the semi-floating gate device is located in the memory array area 101 a . Figure 4AIn the figure, the logic area 101b is located on the left side of the dotted line AA, and the memory array area 101a is located on the right side of the dotted line AA.
[0053] In the memory array region 101 a , field oxides 103 are arranged in parallel and extend along the X-axis direction, and a hard mask layer 104 is formed on top of the field oxides 103 .
[0054] The hard mask layer 104 includes a silicon nitride layer.
[0055] There is a step between the logic region 101 b and the memory array region 101 a . Before the semi-floating gate polysilicon layer 106 is formed, the surface of the logic region 101 b is covered with a silicon nitride layer.
[0056] In some preferred embodiments, the deposition process of the semi-floating gate polysilicon layer 106 includes the following steps:
[0057] like Figure 4A As shown, after the semi-floating gate dielectric layer 201 is grown and before the semi-floating gate dielectric window is formed, the first polysilicon deposition of the first polysilicon layer 106a is performed. The corresponding cross-sectional structure after the first polysilicon layer 106a is deposited is shown in FIG. Figure 5A shown.
[0058] like Figure 5B As shown, the first polysilicon layer 106a is patterned and etched to form a polysilicon window 107 on the top of the semi-floating gate dielectric window, and then the semi-floating gate dielectric layer 201 at the bottom of the polysilicon window 107 is etched to form a semi-floating gate dielectric window. Figure 3 In the preferred embodiment of the present invention shown, the incoming step corresponding to step S200 represents the starting step of the preferred embodiment of the present invention. The steps before step S200 can be completed using existing methods, which requires the completion of the graphic etching of the first polysilicon layer 106a.
[0059] like Figure 4B As shown, a second polysilicon deposition is performed to form a second polysilicon layer 106b, and the second polysilicon layer 106b completely fills the semi-floating gate dielectric window and the polysilicon window 107 and extends to the surface of the first polysilicon layer 106a outside the polysilicon window 107. The first polysilicon layer 106a and the second polysilicon layer 106b are superimposed to form a semi-floating gate polysilicon layer 106. Please refer to the cross-sectional structure corresponding to the second polysilicon layer 106b after deposition. Figure 5C As shown. Figure 5C As shown, the second polysilicon layer 106b needs to fill the trench formed by the superposition of the semi-floating gate dielectric window and the polysilicon window 107. The filling process is difficult and a deep butterfly-shaped recess 108 is easily formed on the top. Figure 3In the preferred embodiment of the present invention shown, the second polysilicon deposition corresponds to step S201, SFG Poly1 Dep, where SFG represents a semi-floating gate and Poly1 represents a second polysilicon layer 106b.
[0060] In some embodiments, in step 1, the deposition thickness of the semi-floating gate polysilicon layer 106 is The deposition temperature is 500°C to 700°C.
[0061] The maximum depth of the butterfly-shaped recess 108 on the top surface of the semi-floating gate polysilicon layer 106 is above.
[0062] Step 2: Figure 4C As shown, the surface of the semi-floating gate polysilicon layer 106 is subjected to hydrogen treatment, and the hydrogen treatment is used to increase the mobility of silicon atoms and thereby improve the flatness of the top surface of the semi-floating gate polysilicon layer 106 .
[0063] Figure 4C In the diagram, hydrogen treatment is indicated by an arrow line, and H2 is written next to the arrow line. Please refer to the corresponding cross-sectional structure during hydrogen treatment. Figure 5D shown.
[0064] In some embodiments, the hydrogen treatment adopts a low pressure process and the pressure is 10 Torr to 50 Torr.
[0065] The process temperature of the hydrogen treatment is 500° C. to 900° C., the time is 20 seconds to 10 minutes, and the process gas includes hydrogen and nitrogen.
[0066] In the hydrogen treatment, the hydrogen flow rate is 3 liters per minute to 15 liters per minute, and the nitrogen flow rate is 5 liters per minute to 15 liters per minute.
[0067] exist Figure 3 In the preferred embodiment of the present invention shown, the hydrogen treatment corresponds to step S202, H2 treatment. H2 treatment means hydrogen treatment.
[0068] The hydrogen treatment reduces the depth of the butterfly-shaped recess 108 and improves the flatness of the top surface of the semi-floating gate polysilicon layer 106 .
[0069] Step 3: perform ion implantation and annealing activation on the semi-floating gate polysilicon layer 106.
[0070] In the embodiment of the present invention, since the mobility of silicon atoms in the semi-floating gate polysilicon layer 106 is improved after hydrogen treatment, the depth of the butterfly-shaped recess 108 can be further reduced during ion implantation and annealing activation, and the flatness of the top surface of the semi-floating gate polysilicon layer 106 can be further improved.
[0071] In some embodiments, the implanted impurities of the ion implantation of the semi-floating gate polysilicon layer 106 include boron;
[0072] The activation annealing includes thermal annealing or laser annealing, and the thermal annealing includes soak annealing or spike annealing.
[0073] The temperature of thermal annealing is 900°C to 1200°C.
[0074] exist Figure 3 In the preferred embodiment of the present invention shown, ion implantation and annealing activation correspond to step S203, SFGP1IMP&Ann, where P1 represents Poly1, IMP represents ion implantation, and Ann represents annealing activation.
[0075] Step 4: Figure 4D As shown, the semi-floating gate polysilicon layer 106 is etched without a mask so that the thickness of the semi-floating gate polysilicon layer 106 is reduced to a set value. Please refer to the corresponding cross-sectional structure after the maskless etching. Figure 5E shown.
[0076] In some embodiments, after maskless etching, the thickness of the semi-floating gate polysilicon layer 106 on the top surface of the semi-floating gate dielectric layer 201 outside the semi-floating gate trench 105 is
[0077] After maskless etching, the maximum depth of the butterfly-shaped recess 108 on the top surface of the semi-floating gate polysilicon layer 106 is the following.
[0078] exist Figure 3 In the preferred embodiment of the present invention shown, the maskless etching corresponds to step S204, SFGPoly1Blanket etch.
[0079] In the embodiment of the present invention, the following further includes:
[0080] Step 5: Fig. 5F As shown, a control gate dielectric layer 202 is formed.
[0081] In some embodiments, the material of the control gate dielectric layer 202 includes an oxide layer.
[0082] exist Figure 3 In the preferred embodiment of the present invention shown, the step of forming the control gate dielectric layer 202 corresponds to step S205, SFG Poly2 Gate OX, wherein Poly2 represents the control gate polysilicon layer 109 formed subsequently, and Gate OX represents the gate oxide layer, namely the control gate dielectric layer 202.
[0083] Step 6: Fig. 5FAs shown, a control gate polysilicon layer 109 is formed. Please refer to the corresponding stereogram after the control gate polysilicon layer 109 is formed. Figure 4E shown.
[0084] exist Figure 3 In the preferred embodiment of the present invention shown, the step of forming the control gate polysilicon layer 109 corresponds to step S206, SFG Poly2 Dep. Dep means deposition.
[0085] exist Figure 3 In the preferred embodiment of the present invention shown, after the formation of the control gate polysilicon layer 109, the following steps are further included:
[0086] Step S207, SiN RM. RM is an abbreviation for remove. SiN RM means removing the silicon nitride layer, including the silicon nitride layer exposed on the surface of the logic area 101b or the silicon nitride layer exposed in the memory array area 101b.
[0087] In the embodiment of the present invention, hydrogen treatment is performed after the deposition of the semi-floating gate polysilicon layer 106 is completed and before ion implantation. The hydrogen treatment can increase the mobility of silicon atoms in the semi-floating gate polysilicon layer 106. Due to the increased mobility of silicon atoms, combined with the control of the mobility of silicon atoms by the hydrogen treatment itself and the subsequent ion implantation and annealing activation, the mobility of silicon atoms can be further controlled. Finally, the surface flatness of the semi-floating gate polysilicon layer 106 is improved before the subsequent maskless etching, and then after the maskless etching, the surface flatness of the semi-floating gate polysilicon layer 106 is improved to meet the process requirements, so that the thickness uniformity of the semi-floating gate polysilicon layer 106 after the maskless etching is increased and the depth of the butterfly recess 108 is reduced, so that the control ability of the semi-floating gate polysilicon layer 106 on the channel can be improved, thereby improving the performance of the device. Therefore, the embodiment of the present invention can improve the surface flatness of the semi-floating gate polysilicon and thereby improve the performance of the device.
[0088] In addition, the embodiment of the present invention only needs to insert hydrogen treatment after the deposition of the semi-floating gate polysilicon layer 106 is completed and before ion implantation, so it also has the characteristics of simple process and easy implementation, and can improve the surface flatness of the semi-floating gate polysilicon at a relatively low cost.
[0089] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a semi-floating gate device, characterized in that: Includes steps: Step 1: depositing a semi-floating gate polysilicon layer on the underlying structure, wherein the top surface of the semi-floating gate polysilicon layer is uneven; Step 2: performing hydrogen treatment on the surface of the semi-floating gate polysilicon layer, using the hydrogen treatment to increase the mobility of silicon atoms and thereby improve the flatness of the top surface of the semi-floating gate polysilicon layer; Step 3, ion implantation and annealing activation are performed on the semi-floating gate polysilicon layer; Step 4: performing maskless etching on the semi-floating gate polysilicon layer to reduce the thickness of the semi-floating gate polysilicon layer to a set value.
2. The method for manufacturing a semi-floating gate device according to claim 1, wherein: The underlying structure includes a semiconductor substrate, a first active area defined by field oxygen is formed on the semiconductor substrate, a semi-floating gate trench is formed in the first active area, a semi-floating gate dielectric layer is formed on the inner surface of the semi-floating gate trench, the semi-floating gate dielectric layer also extends to the surface of the semiconductor substrate outside the semi-floating gate trench and a semi-floating gate dielectric window is formed outside the semi-floating gate trench, and the semi-floating gate polysilicon layer is directly in contact with the semiconductor substrate in the semi-floating gate dielectric window.
3. The method for manufacturing a semi-floating gate device according to claim 2, wherein: In step 1, the deposition thickness of the semi-floating gate polysilicon layer is The deposition temperature is 500°C to 700°C.
4. The method for manufacturing a semi-floating gate device according to claim 3, wherein: In step 1, the maximum depth of the butterfly-shaped depression on the top surface of the semi-floating gate polysilicon layer is above.
5. The method for manufacturing a semi-floating gate device according to claim 4, wherein: In step 4, after the maskless etching, the thickness of the semi-floating gate polysilicon layer on the top surface of the semi-floating gate dielectric layer outside the semi-floating gate trench is 6. The method for manufacturing a semi-floating gate device according to claim 5, wherein: In step 4, after the maskless etching, the maximum depth of the butterfly-shaped depression on the top surface of the semi-floating gate polysilicon layer is the following.
7. The method for manufacturing a semi-floating gate device according to claim 2, wherein: In step 2, the hydrogen treatment adopts a low-pressure process and the pressure is 10 Torr to 50 Torr.
8. The method for manufacturing a semi-floating gate device according to claim 7, wherein: In step 2, the process temperature of the hydrogen treatment is 500° C. to 900° C., the time is 20 seconds to 10 minutes, and the process gas includes hydrogen and nitrogen.
9. The method for manufacturing a semi-floating gate device according to claim 8, wherein: In the hydrogen treatment, the hydrogen flow rate is 3 liters per minute to 15 liters per minute, and the nitrogen flow rate is 5 liters per minute to 15 liters per minute.
10. The method for manufacturing a semi-floating gate device according to claim 2, wherein: In step three, the implanted impurities of the ion implantation of the semi-floating gate polysilicon layer include boron.
11. The method for manufacturing a semi-floating gate device according to claim 2, wherein: In step 3, the annealing activation includes thermal annealing or laser annealing, and the thermal annealing includes uniform temperature annealing or spike annealing; The thermal annealing temperature is 900°C to 1200°C.
12. The method for manufacturing a semi-floating gate device according to claim 2, wherein the subsequent Also includes: Step 5: forming a control gate dielectric layer; Step 6: forming a control gate polysilicon layer.
13. The method for manufacturing a semi-floating gate device according to claim 2, wherein: The semiconductor substrate includes a silicon substrate.
14. The method for manufacturing a semi-floating gate device according to claim 2, wherein: The field oxide includes shallow trench isolation.
15. The method for manufacturing a semi-floating gate device according to claim 2, wherein: In step 1, the deposition process of the semi-floating gate polysilicon layer includes the following steps: After the semi-floating gate dielectric layer is grown and before the semi-floating gate dielectric window is formed, a first polysilicon deposition is performed; Performing pattern etching on the first polysilicon layer to form a polysilicon window on the top of the semi-floating gate dielectric window, and then etching the semi-floating gate dielectric layer at the bottom of the polysilicon window to form the semi-floating gate dielectric window; A second polysilicon deposition is performed to form a second polysilicon layer, wherein the second polysilicon layer completely fills the semi-floating gate dielectric window and the polysilicon window and extends to the surface of the first polysilicon layer outside the polysilicon window, and the semi-floating gate polysilicon layer is formed by stacking the first polysilicon layer and the second polysilicon layer.