Preparation method of semiconductor structure, semiconductor structure and semiconductor device

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor device. The method comprises the following steps: forming a first transistor on a substrate, wherein the first transistor comprises first source-drain metal and first gate metal; forming a first hard mask on the first source-drain metal, forming a second hard mask on the first gate metal, and forming a first dielectric layer on the first hard mask and the second hard mask; etching the first region of the first dielectric layer and the first hard mask to form a first groove, and forming a first metal interconnection structure on the first source-drain metal based on the first groove; and / or etching a second region of the first dielectric layer and the second hard mask to form a second groove, and forming a second metal interconnection structure on the first gate metal based on the second groove. According to the invention, the preparation difficulty of the semiconductor structure can be reduced, and the product yield can be improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device. Background Art

[0002] As the size of semiconductor structures continues to shrink, the spacing between the source and drain regions and the gate region of the semiconductor structure is also being compressed. In the process of forming source and drain contact holes on the source and drain metal of the semiconductor structure and forming gate contact holes on the gate metal through the back-end process, alignment deviation is prone to occur, resulting in contact between the source and drain contact holes and the gate metal or between the gate contact holes and the source and drain metal, which increases the difficulty of preparing the semiconductor structure and affects the product yield. Summary of the invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a semiconductor device and an electronic device, which can reduce the difficulty of preparing the semiconductor structure and improve the product yield.

[0004] In a first aspect, the present application provides a method for preparing a semiconductor structure, the method comprising: forming a first transistor on a substrate, the first transistor comprising a first source / drain metal and a first gate metal; forming a first hard mask on the first source / drain metal, and forming a second hard mask on the first gate metal, wherein the materials of the first hard mask and the second hard mask are different; forming a first dielectric layer on the first hard mask and the second hard mask; etching a first region of the first dielectric layer and the first hard mask to form a first groove, and forming a first metal interconnection structure on the first source / drain metal based on the first groove; and / or etching a second region of the first dielectric layer and the second hard mask to form a second groove, and forming a second metal interconnection structure on the first gate metal based on the second groove; wherein the first region covers the source / drain region of the first transistor, and the second region covers the gate region of the first transistor.

[0005] In some embodiments, a first hard mask is formed on the first source / drain metal, and a second hard mask is formed on the first gate metal, including: etching the first source / drain metal to a first preset depth, and forming the first hard mask on the first source / drain metal; etching the first gate metal to a second preset depth, and forming a second hard mask on the first gate metal.

[0006] In some embodiments, etching the first region of the first dielectric layer and the first hard mask to form a first groove includes: depositing a hard mask material on the first dielectric layer to form a third hard mask; etching the third hard mask until the first region of the first dielectric layer is exposed; etching the first region of the first dielectric layer and the first hard mask to form a first groove.

[0007] In some embodiments, the first metal interconnect structure includes a first source-drain contact hole; the first region also includes a third region indicating the deployment position of the first source-drain contact hole; wherein etching the first region of the first dielectric layer and the first hard mask includes: after exposing the first region of the first dielectric layer, etching the third region of the first dielectric layer to a third preset depth according to a preset first contact hole deployment scheme, wherein the third preset depth is less than the thickness of the first dielectric layer; etching the area of ​​the first dielectric layer not covered by the third hard mask until the first hard mask is exposed through the third region; etching the first hard mask.

[0008] In some embodiments, a projection area of ​​the third region on the substrate is larger than a projection area of ​​the first source / drain metal on the substrate.

[0009] In some embodiments, the first metal interconnect structure also includes a first source-drain interconnect line; wherein, etching the third hard mask until the first region of the first dielectric layer is exposed includes: forming a first photoresist layer on the third hard mask; etching the first photoresist layer and the third hard mask according to a preset first interconnect line deployment scheme until the first region of the first dielectric layer is exposed.

[0010] In some embodiments, etching the second region of the first dielectric layer and the second hard mask to form a second groove includes: etching the third hard mask until the second region of the first dielectric layer is exposed; etching the second region of the first dielectric layer and the second hard mask to form a second groove.

[0011] In some embodiments, the second metal interconnect structure includes a first gate contact hole; the second region also includes a fourth region indicating the deployment position of the first gate contact hole; wherein, etching the second region of the first dielectric layer and the second hard mask to form a second groove includes: after exposing the first region of the first dielectric layer, etching the fourth region of the first dielectric layer to a fourth preset depth according to a preset contact hole deployment scheme, wherein the fourth preset depth is less than the thickness of the first dielectric layer; etching the area of ​​the first dielectric layer not covered by the third hard mask until the second hard mask is exposed through the fourth region; etching the second hard mask.

[0012] In some embodiments, the first metal interconnect structure includes: a first source-drain interconnection line and a first source-drain contact hole; the first region also includes a third region indicating a deployment position of the first source-drain contact hole; wherein etching the first region of the first dielectric layer and the first hard mask includes: based on a preset first interconnection line deployment scheme, etching the first region on the first dielectric layer for deploying the first source-drain interconnection line to a fifth preset depth to form a third groove on the first dielectric layer, wherein the bottom of the third groove is formed by the first dielectric layer;

[0013] According to a preset contact hole deployment scheme, a third region at the bottom of the third groove for deploying the first source-drain contact hole is etched until the first hard mask is exposed through the third region; and the first hard mask is etched.

[0014] In some embodiments, the method further includes: flipping the wafer and removing the substrate; forming a second transistor stacked with the first transistor on the first transistor, the second transistor including a second source-drain metal and a second gate metal; forming a fourth hard mask on the second source-drain metal, and forming a fifth hard mask on the second gate metal, wherein the fourth hard mask and the fifth hard mask are made of different materials; forming a second dielectric layer on the fourth hard mask and the fifth hard mask; etching the fifth region of the second dielectric layer and the fourth hard mask to form a fourth groove, and forming a third metal interconnection structure on the second source-drain metal based on the fourth groove; and / or etching the sixth region of the second dielectric layer and the fifth hard mask to form a fifth groove, and forming a fourth metal interconnection structure on the second gate metal based on the fifth groove, the fifth region covering the source-drain region of the second transistor, and the sixth region covering the gate region of the second transistor.

[0015] In a second aspect, the present application provides a semiconductor structure, which includes: a first transistor; the first transistor includes: a first source-drain metal, a first metal interconnection structure connected to the first source-drain metal, and a first gate metal adjacent to the first source-drain metal, wherein the first gate metal adjacent to the first source-drain metal is covered with a second hard mask; and / or, the first transistor includes: a first gate metal, a second metal interconnection structure connected to the first gate metal, and a first source-drain metal adjacent to the first gate metal, wherein the first source-drain metal adjacent to the first gate metal is covered with a first hard mask, wherein the materials of the first hard mask and the second hard mask are different.

[0016] In some embodiments, the first metal interconnect structure includes: a first source-drain contact hole and a first source-drain interconnect line integrally formed with the first source-drain contact hole; the second metal interconnect structure includes: a first gate contact hole and a first gate interconnect line integrally formed with the first gate contact hole.

[0017] In some embodiments, a size of at least a portion of the first source-drain contact hole in the horizontal direction is larger than a size of the first source-drain metal in the horizontal direction.

[0018] In a third aspect, the present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment.

[0019] In a fourth aspect, the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0020] The technical solution provided by this application may have the following beneficial effects:

[0021] In the present application, different hard mask materials are used to form a first hard mask on the first source and drain metal of the first transistor, and a second hard mask is formed on the first gate metal of the first transistor. Based on this, when etching the first dielectric layer and the first hard mask to form a first metal interconnection structure in the first groove, since the materials used to form the first hard mask and the second hard mask are different, the second hard mask will not be etched or will not be completely etched during the etching of the first hard mask. Therefore, even if the formation position of the first metal interconnection structure deviates, the second hard mask can isolate the first metal interconnection structure and the adjacent first gate metal, and will not cause the first metal interconnection structure and the first gate metal to be connected, which can reduce the production difficulty of the crystalline semiconductor structure and improve the product yield. Similarly, when etching the first dielectric layer and the second hard mask to form a second metal interconnect structure in the second groove, since the materials used to form the second hard mask and the first hard mask are different, the first hard mask will not be etched or will not be completely etched during the etching of the second hard mask. Therefore, even if the formation position of the second metal interconnect structure deviates, the first hard mask can isolate the second metal interconnect structure and the adjacent first source and drain metal, and will not cause the second metal interconnect structure and the first source and drain metal to be connected, which can also reduce the production difficulty of crystalline semiconductor structures and improve product yield.

[0022] In addition, since the second hard mask located on the first gate metal can achieve electrical isolation between the first metal interconnection structure and the first gate metal, the preparation method provided in the embodiment of the present application can increase the size of the first metal interconnection structure when necessary, and will not cause conduction between the first metal interconnection structure and the adjacent first gate metal. Similarly, since the first hard mask located on the first source and drain metal can achieve electrical isolation between the second metal interconnection structure and the adjacent first source and drain metal. Therefore, through the preparation method provided in the embodiment of the present application, the size of the second metal interconnection structure can be increased when necessary, and will not cause conduction between the second metal interconnection structure and the adjacent first source and drain metal.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application.

[0026] Figure 2 A design layout of a semiconductor structure provided in an embodiment of the present application.

[0027] Figure 3 This is a schematic structural diagram of the first semiconductor structure in an embodiment of the present application.

[0028] Figures 4 to 17 It is a schematic diagram of the preparation process of the first semiconductor structure in the embodiment of the present application.

[0029] Figures 18 to 30 Schematic diagram of the preparation process of the second semiconductor structure in the embodiment of the present application.

[0030] Fig.31 Schematic diagram of the structure of the second semiconductor structure in the embodiment of the present application.

[0031] Figure 32 to Figure 34 It is a schematic diagram of a preparation process of a first transistor in an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 111, first source and drain metal; 112, first gate metal; 113, second hard mask; 114, first hard mask; 115, first dielectric layer; 116, third hard mask; 117, first photoresist layer; 118, first region; 119, second region; 120, second photoresist layer; 121, third region; 122, fourth region; 123, first metal interconnection structure; 124, second metal interconnection structure; 125, insulating layer; 126, carrier wafer; 127, first substrate portion; 128, second substrate portion; 129, active structure; 130, shallow trench Isolation structure; 131, first active structure; 132, first pseudo-gate structure; 133, spacer; 134, first source-drain structure; 135, third dielectric layer; 211, second source-drain metal; 212, second gate metal; 213, fifth hard mask; 214, fourth hard mask; 215, second dielectric layer; 216, sixth hard mask; 217, fourth photoresist layer; 218, fifth region; 219, sixth region; 220, fifth photoresist layer; 221, seventh region; 222, eighth region; 223, third metal interconnection structure; 224, fourth metal interconnection structure. DETAILED DESCRIPTION

[0034] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0035] At present, the following problems exist in the production process of transistors: On the one hand, as the size of transistors continues to shrink, the spacing between the source and drain regions and the gate region of the transistor is also constantly compressed. In the process of forming a source-drain metal interconnection structure on the source and drain metal of the transistor through the back-end process of the transistor, and forming a gate metal interconnection structure on the gate metal, it is easy to have an alignment deviation between the source-drain metal interconnection structure and the source-drain metal and / or an alignment deviation between the gate metal interconnection structure and the gate metal, resulting in conduction between the source-drain metal interconnection structure and the gate metal or between the gate metal interconnection structure and the source-drain metal, which increases the difficulty of semiconductor production and affects the product yield.

[0036] On the other hand, when forming the source-drain metal interconnection structure and the gate metal interconnection structure of the transistor, source-drain contact holes are usually formed on the source-drain metal and gate contact holes are formed on the gate metal first. After that, source-drain interconnection lines are formed on the source-drain contacts and gate interconnection lines are formed on the gate contact holes, which not only complicates the production process of the transistor, but also increases the resistance between the interconnection lines and the contact holes.

[0037] In order to solve the above technical problems, the embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device, which can effectively reduce the conduction between the source-drain metal interconnection structure and the adjacent gate metal caused by the alignment deviation between the source-drain metal interconnection structure and the source-drain metal, thereby effectively reducing the difficulty of semiconductor production and improving product yield.

[0038] Figure 1 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method for preparing the semiconductor structure may include steps S101 to S104.

[0039] In step S101 , a first transistor is formed on a substrate.

[0040] In some embodiments, the first transistor includes a first source-drain metal and a first gate metal.

[0041] In some embodiments, the substrate may be a substrate made of the same semiconductor material, or may be a substrate made by stacking and depositing multiple semiconductor materials.

[0042] Exemplarily, the substrate may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Of course, the substrate may also be a substrate of other semiconductor materials, which is not limited in the embodiments of the present application.

[0043] For example, the above-mentioned substrate can be a substrate made of any one or more materials selected from the group consisting of single crystal silicon, polycrystalline silicon, single crystal germanium, polycrystalline germanium, silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP) and aluminum gallium arsenide (AlGaAs). Of course, the substrate in the embodiment of the present application can also be a substrate made of other semiconductor materials, which is not limited in the embodiment of the present application.

[0044] In some embodiments, the first transistor may include but is not limited to: a fin field effect transistor, a planar transistor, an all-around gate transistor, a vertical field-effect transistor (VFET), a nanosheet field effect transistor, and a complementary field-effect transistor (CFET).

[0045] In some embodiments, the process of forming a first transistor on a substrate can be achieved by at least one of the following processes: a process for preparing a fin-type field effect transistor, a process for preparing a planar transistor, a process for preparing an all-around gate transistor, a process for preparing a vertical field effect transistor, a process for preparing a nanosheet field effect transistor, or a process for preparing a complementary field effect transistor.

[0046] Hereinafter, taking a fin field effect transistor as an example, the implementation process of forming a first transistor on a substrate is introduced.

[0047] The first step is to etch the substrate to form a first active structure on the substrate;

[0048] It can be understood that by etching the substrate, an active structure is formed on the substrate, and an insulating material is deposited on the active structure to form a shallow trench isolation structure (STI). The shallow trench isolation structure wraps the active structure, and the height of the shallow trench isolation structure is greater than the height of the active structure. After the shallow trench isolation structure is formed, a portion of the shallow trench isolation structure is removed by etching to expose the first active structure.

[0049] In the embodiment of the present application, the insulating material forming the shallow trench isolation structure can be any of the following: silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ) or silicon oxycarbide (SiCO), etc.

[0050] In some embodiments, before etching the shallow trench isolation layer, a chemical mechanical planarization process is performed on the shallow trench isolation structure.

[0051] In an embodiment of the present application, chemical mechanical planarization is performed on the shallow trench isolation structure, so that when the shallow trench isolation structure is subsequently etched, the corrosion depths corresponding to the shallow trench isolation structure in different areas are the same, thereby making the heights of the exposed active structures the same.

[0052] The second step is to form a first source-drain structure on the first active structure.

[0053] It can be understood that after etching a portion of the shallow trench isolation structure to expose the first active structure, a semiconductor material can be deposited in the first gate region of the first active structure to form a first dummy gate structure; spacers are formed on both sides of the first dummy gate structure; and a first source-drain structure is formed on the first active structure on both sides of the first dummy gate structure and the spacers.

[0054] In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon, amorphous silicon, etc. The spacer is used to isolate the first source-drain structure from the first gate structure. The structure of the spacer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0055] For example, the spacer may have a single-layer structure and be entirely made of the same material, such as porous silicon carbon oxyhydride (SiCOH).

[0056] In some embodiments, the implementation process of forming the first source-drain structure on the first active structure on both sides of the first dummy gate structure and the spacer may be: etching the first active structure of the first transistor in the source-drain region to form a sixth groove, performing source-drain epitaxial growth at the sixth groove to form the first source-drain structure.

[0057] Exemplarily, a strained material such as silicon germanium or silicon carbide may be formed in the sixth groove by selective epitaxial growth to fill the sixth groove of the first transistor, and then a first source-drain structure is formed on the strained material by a heavy doping process.

[0058] In the third step, a first source-drain metal is formed on the first source-drain structure, and a first gate metal is formed in the first gate region.

[0059] In some embodiments, after forming the first source-drain structure, an interlayer dielectric may be deposited on the first source-drain structure, and the interlayer dielectric may be thinned to a top layer of the first dummy gate structure to form a third dielectric layer.

[0060] Exemplarily, an insulating material (such as silicon dioxide SiO2) may be deposited on the first source-drain structure and the first active structure. 2 ), and planarize the insulating material to form a third dielectric layer. The third dielectric layer can cover the first source-drain structure and the first active structure.

[0061] The planarization process may be, for example, a chemical-mechanical planarization (CMP) process.

[0062] After the first source-drain structure is formed, a gate structure of the first transistor, ie, a first gate structure, may be formed.

[0063] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a seventh groove, an insulating material can be deposited at the seventh groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate metal. The first gate dielectric layer and the first gate metal together constitute a first gate structure.

[0064] Exemplarily, the first gate dielectric layer may include a silicon oxide layer and a hafnium oxide layer having a high K value. It is understood that the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0065] Exemplarily, the first gate metal may be composed of multiple layers of electrode materials, each layer of which includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0066] In some embodiments, after forming the first gate structure, a metal material may be deposited on the first source-drain structure formed above to form a first source-drain metal.

[0067] In some embodiments, when the third dielectric layer is formed after the first source-drain structure is formed, the third dielectric layer on the first source-drain structure may be etched to form a first source-drain metal on the first source-drain structure.

[0068] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the first source-drain metal, the second source-drain structure, the second source-drain metal, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0069] It should be noted that the first source-drain structure, the third dielectric layer, the first gate structure, and the first source-drain metal can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0070] In step 102 , a first hard mask is formed on the first source / drain metal, and a second hard mask is formed on the first gate metal.

[0071] It can be understood that after forming a first transistor including a first source-drain metal and a first gate metal on a substrate based on the above steps, a first hard mask material can be deposited on the first source-drain metal to form a first hard mask on the first source-drain metal, and a second hard mask material can be deposited on the first gate metal to form a second hard mask on the first gate metal. The first hard mask material and the second hard mask material are different.

[0072] In some embodiments, the etching selectivity ratio of the first hard mask material to the second hard mask material may be 12: 1 to 8: 1. For example, the etching selectivity ratio of the first hard mask material to the second hard mask material may be 10:1.

[0073] In some embodiments, the etching selectivity ratio can be understood as the ratio between the etching rate of one material and the etching rate of another material. For example, when etching the first hard mask, the ratio between the etching rate of the first hard mask and the etching rate of the second hard mask is between 12:1 and 8:1.

[0074] In some embodiments, the first hard mask material and the second hard mask material may be different insulating materials.

[0075] For example, the first hard mask material may be silicon nitride, and the second hard mask material may be titanium nitride.

[0076] In some embodiments, after forming a first transistor having a first source-drain metal and a first gate metal on a substrate, a fourth dielectric layer may be deposited on the first source-drain metal and the first gate metal, and the source-drain region and the gate region on the fourth dielectric layer may be etched to expose the first source-drain metal and the first gate metal. After exposing the first source-drain metal through the source-drain region on the fourth dielectric layer and exposing the first gate metal through the gate region of the fourth dielectric layer, a first hard mask material may be deposited on the first source-drain metal to form a first hard mask on the first source-drain metal, and a second hard mask material may be deposited on the first gate metal to form a second hard mask on the first gate metal.

[0077] In some embodiments, the projection of the first hard mask on the substrate may cover the projection of the first source / drain metal on the substrate. Similarly, the projection of the second hard mask on the substrate may cover the projection of the first gate metal on the substrate.

[0078] In some other embodiments, step 102 further includes: etching the first source-drain metal to a first preset depth and forming a first hard mask on the first source-drain metal; etching the first gate metal to a second preset depth and forming a second hard mask on the first gate metal.

[0079] It can be understood that before forming the first hard mask on the first source and drain metal, the first source and drain metal can be etched to a first preset depth to form an eighth groove. Afterwards, the first hard mask material can be filled in the eighth groove to fill the eighth groove to form the first hard mask on the first source and drain metal. Before forming the second hard mask on the first gate metal, the first gate metal can be etched to a second preset depth to form a ninth groove, and then the second hard mask material can be filled in the ninth groove to fill the ninth groove to form the second hard mask on the first gate metal.

[0080] In some embodiments, the first preset depth may be less than or equal to the thickness of the first source / drain metal in the first direction, wherein the first direction is a direction perpendicular to the substrate. Similarly, the second preset depth may be less than or equal to the thickness of the first gate metal in the first direction.

[0081] In an embodiment of the present application, after etching the first source-drain metal to a first preset depth, a first hard mask is formed on the first source-drain metal. In this way, self-alignment of the first hard mask with the first source-drain metal can be achieved. Based on this, in a subsequent step, a metal material is deposited in a first groove formed based on etching the first region of the first dielectric layer and the first hard mask to form a first metal interconnect structure, and self-alignment of the first metal interconnect structure with the first source-drain metal can be achieved. Similarly, by etching the first gate metal to a second preset depth, a second hard mask is formed on the first gate metal, and self-alignment of the second hard mask with the first gate metal can be achieved. Based on this, in a subsequent step, a metal material is deposited in a second groove formed based on etching the second region of the first dielectric layer and the second hard mask to form a second metal interconnect structure, and self-alignment of the second metal interconnect structure with the first gate metal can be achieved.

[0082] In step S103 , a first dielectric layer is formed on the first hard mask and the second hard mask.

[0083] It can be understood that after forming the first hard mask on the first source and drain metal and forming the second hard mask on the first gate metal, a dielectric material can be deposited on the first hard mask and the second hard mask to form a first dielectric layer on the first hard mask and the second hard mask.

[0084] In some embodiments, the dielectric material forming the first dielectric layer includes, but is not limited to, aluminum oxide, zirconium oxide, and silicon nitride.

[0085] It is understandable that the deposition thickness of the first dielectric layer can be set as needed, and the embodiment of the present application does not limit this.

[0086] For example, since the first dielectric layer is used to form a first metal interconnect structure in a subsequent process, the thickness of the first dielectric layer can be determined according to the design requirements of the first metal interconnect structure.

[0087] In some embodiments, after depositing the first dielectric layer on the first hard mask and the second hard mask, the first dielectric layer may be planarized so that the first dielectric layer has a predetermined thickness.

[0088] In some embodiments, the method of planarizing the first dielectric layer includes but is not limited to: mechanical planarization and chemical planarization.

[0089] In step 104, the first region of the first dielectric layer and the first hard mask are etched to form a first groove, and a first metal interconnection structure is formed on the first source and drain metal based on the first groove; and / or, the second region of the first dielectric layer and the second hard mask are etched to form a second groove, and a second metal interconnection structure is formed on the first gate metal based on the second groove.

[0090] It can be understood that after forming the first dielectric layer, the first region on the first dielectric layer and the first hard mask below the first region can be etched to expose the first source-drain metal below the first hard mask. At this time, based on the etched first region on the first dielectric layer and the cavity formed after etching the first hard mask, a first groove is formed, wherein the bottom of the first groove is formed by the first source-drain metal. After forming the first groove, a metal material can be deposited in the first groove to fill the first groove, so as to form a first metal interconnect structure on the first source-drain metal.

[0091] Similarly, after forming the first dielectric layer, the second region on the first dielectric layer and the second hard mask below the second region may be etched to expose the first gate metal below the second hard mask. At this time, based on the etched second region on the first dielectric layer and the cavity formed after etching the second hard mask, a second groove is formed, wherein the bottom of the second groove is formed by the first gate metal. After forming the second groove, a metal material may be deposited in the second groove to fill the second groove, so as to form a second metal interconnection structure on the first gate metal.

[0092] In some embodiments, the first region covers a source / drain region of the first transistor. In some embodiments, the second region covers a gate region of the first transistor.

[0093] It can be understood that the first source and drain metal formed on the first transistor can be one or more; the first gate metal formed on the first transistor can also be one or more, which is not limited in the embodiment of the present application.

[0094] In some embodiments, when a plurality of first source-drain metals are formed on the first transistor, a first metal interconnect structure may be formed on the first source-drain metal by etching a first hard mask on any first source-drain metal among the plurality of first source-drain metals. When a plurality of first gate metals are formed on the first transistor, a second hard mask on a first gate metal not adjacent to the first metal interconnect structure may be etched to form a second metal interconnect structure on the first gate metal.

[0095] For example, when there are multiple first source-drain metals and / or first gate metals formed on the first transistor, the hard masks on the first source-drain metal and the first gate metal that are farthest apart in the horizontal direction can be etched, so that the first metal interconnect structure and the second metal interconnect structure formed on the first transistor are far apart, which can reduce the risk of the first metal interconnect structure and the second metal interconnect structure being turned on. Among them, the hard masks on the first source-drain metal and the first gate metal can be understood as the first hard mask on the first source-drain metal and the second hard mask on the first gate metal.

[0096] In some embodiments, when the first source-drain metal and the first gate metal formed on the first transistor are both one, the first hard mask on the first source-drain metal can be etched to form a first metal interconnection structure on the first source-drain metal; or, the first hard mask on the first gate metal can be etched to form a second metal interconnection structure on the first gate metal.

[0097] In some embodiments, the projected area of ​​the first region of the first dielectric layer on the substrate may be greater than or equal to the projected area of ​​the source region of the first transistor on the substrate. Similarly, the projected area of ​​the second region of the first dielectric layer on the substrate may be greater than or equal to the projected area of ​​the gate region of the first transistor on the substrate.

[0098] It should be noted that, for the first transistor, the upward direction may be understood as a direction away from the substrate, and the downward direction may be understood as a direction close to the substrate.

[0099] In the embodiment of the present application, different hard mask materials are used to form a first hard mask on the first source and drain metal of the first transistor, and a second hard mask is formed on the first gate metal of the first transistor. Based on this, when etching the first dielectric layer and the first hard mask to form the first metal interconnection structure in the first groove, since the materials used to form the first hard mask and the second hard mask are different, the second hard mask will not be etched or will not be completely etched during the etching of the first hard mask. Therefore, even if the formation position of the first metal interconnection structure deviates, the second hard mask can isolate the first metal interconnection structure and the adjacent first gate metal, and will not cause the first metal interconnection structure and the first gate metal to be connected, which can reduce the production difficulty of the crystalline semiconductor structure and improve the product yield. Similarly, when etching the first dielectric layer and the second hard mask to form a second metal interconnect structure in the second groove, since the materials used to form the second hard mask and the first hard mask are different, the first hard mask will not be etched or will not be completely etched during the etching of the second hard mask. Therefore, even if the formation position of the second metal interconnect structure deviates, the first hard mask can isolate the second metal interconnect structure and the adjacent first source and drain metal, and will not cause the second metal interconnect structure and the first source and drain metal to be connected, which can also reduce the production difficulty of crystalline semiconductor structures and improve product yield.

[0100] In addition, since the second hard mask located on the first gate metal can achieve electrical isolation between the first metal interconnection structure and the first gate metal, the preparation method provided in the embodiment of the present application can increase the size of the first metal interconnection structure when necessary, and will not cause conduction between the first metal interconnection structure and the adjacent first gate metal. Similarly, since the first hard mask located on the first source and drain metal can achieve electrical isolation between the second metal interconnection structure and the adjacent first source and drain metal. Therefore, through the preparation method provided in the embodiment of the present application, the size of the second metal interconnection structure can be increased when necessary, and will not cause conduction between the second metal interconnection structure and the adjacent first source and drain metal.

[0101] Hereinafter, a specific embodiment will be used to introduce the process of etching the first region of the first dielectric layer and the first hard mask to form the first groove.

[0102] In some embodiments, etching the first region of the first dielectric layer and the first hard mask to form a first groove includes: depositing a hard mask material on the first dielectric layer to form a third hard mask; etching the third hard mask until the first region of the first dielectric layer is exposed; etching the first region of the first dielectric layer and the first hard mask to form a first groove.

[0103] It can be understood that after forming the first dielectric layer on the first hard mask and the second hard mask, the hard mask material can be further deposited on the first dielectric layer to form a third hard mask on the first dielectric layer. Afterwards, the third hard mask deposited on the first region of the first dielectric layer can be etched to expose the first region of the first dielectric layer. Afterwards, the first region of the first dielectric layer and the first hard mask exposed through the first region of the first dielectric layer can be etched to expose the first source and drain metal. Based on this, a first groove can be formed on the first transistor.

[0104] It can be understood that the hard mask material used to form the third hard mask may be the same as or different from the hard mask material used to form the first hard mask or the second hard mask, and this embodiment of the present application is not limited to this.

[0105] In some embodiments, after the first dielectric layer is planarized, a third hard mask may be formed on the planarized first dielectric layer.

[0106] It is understandable that the deposition thickness of the third hard mask can be set as needed, and the embodiment of the present application is not limited to this.

[0107] In some embodiments, the first metal interconnect structure includes a first source-drain contact hole; the first region also includes a third region indicating the deployment position of the first source-drain contact hole; wherein etching the first region of the first dielectric layer and the first hard mask includes: after exposing the first region of the first dielectric layer, etching the third region of the first dielectric layer to a third preset depth according to a preset first contact hole deployment scheme, wherein the third preset depth is less than the thickness of the first dielectric layer; etching the area of ​​the first dielectric layer not covered by the third hard mask until the first hard mask is exposed through the third region; etching the first hard mask.

[0108] It can be understood that the first metal interconnect structure may also include a first source-drain contact hole. Therefore, the first region of the first dielectric layer also includes a third region for indicating the deployment position of the first source-drain contact hole. Based on this, after the first region on the first dielectric layer is exposed by etching the first photoresist layer and the third hard mask. It is also possible to determine the third region for deploying the first source-drain contact hole from the exposed first region according to the first contact hole deployment scheme indicating the deployment position of the first source-drain contact hole, and etch the third region of the first dielectric layer to a third preset depth, wherein the third preset depth is less than the thickness of the first dielectric layer. Afterwards, the first region on the first dielectric layer that is not covered by the third hard mask may continue to be etched until the first hard mask is exposed through the third region of the first dielectric layer. At this point, the first hard mask may continue to be etched until the first source-drain metal is exposed.

[0109] In some embodiments, the first metal interconnect structure also includes a first source-drain interconnect line; wherein, etching the third hard mask until the first region of the first dielectric layer is exposed includes: forming a first photoresist layer on the third hard mask; etching the first photoresist layer and the third hard mask according to a preset first interconnect line deployment scheme until the first region of the first dielectric layer is exposed.

[0110] It can be understood that the first metal interconnect structure may also include a first source-drain interconnection line on the first transistor. Based on this, before etching the third hard mask, a photoresist may be coated on the third hard mask to form a first photoresist layer. Afterwards, the area for deploying the first source-drain interconnection line on the second photoresist layer may be etched according to the first interconnection line deployment scheme for indicating the deployment position of the first source-drain interconnection line until the third hard mask is exposed. Afterwards, the exposed third hard mask may continue to be etched until the first area of ​​the first dielectric layer is exposed. After the first area is exposed by etching the third hard mask, a second photoresist layer is formed on the first area of ​​the first dielectric layer and the third hard mask, and based on the preset first contact hole deployment scheme, the second photoresist is etched to expose the second area of ​​the first dielectric layer.

[0111] In some embodiments, after the first photoresist layer and the third hard mask are etched to expose the third region on the first dielectric layer, the first photoresist layer can be removed and a second photoresist layer can be formed on the first dielectric layer. Afterwards, the second photoresist layer can be etched according to the first contact hole deployment scheme to expose the third region of the first dielectric layer. At this time, the first region of the first dielectric layer except the third region and the third hard mask are still covered with the second photoresist layer. After the third region of the first dielectric layer is exposed by etching the second photoresist layer, the third region of the first dielectric layer can be etched to a third preset depth. Afterwards, the second photoresist layer can be removed, and at this time, the first region on the first dielectric layer can be exposed (the region on the first dielectric layer except the first region is covered by the third hard mask), until the third region of the first dielectric layer is completely etched to expose the first hard mask through the third region.

[0112] It can be understood that the third preset depth can be any depth that is less than the thickness of the first dielectric layer, and this embodiment of the present application is not limited to this.

[0113] Exemplarily, the third preset depth may be half the thickness of the first dielectric layer in the first direction, wherein the first direction is a direction perpendicular to the substrate.

[0114] In the embodiment of the present application, firstly, according to the first interconnection line deployment scheme, a first region on the first dielectric layer for deploying the first source-drain interconnection line is determined, and then a third region for deploying the first source-drain contact hole is determined from the first region, and the first region, the third region and the first hard mask of the first dielectric layer are etched to form a first groove, and then a first source-drain contact hole and a first source-drain interconnection line are formed on the first source-drain metal based on the first groove. Since the first source-drain contact hole and the first source-drain interconnection line are both formed in the first groove, self-alignment of the first source-drain contact hole and the first source-drain interconnection line can be achieved.

[0115] In addition, since the first source-drain contact hole and the first source-drain interconnection line can be formed at one time by depositing metal material in the first groove, this can not only simplify the formation process of the first source-drain contact hole and the first source-drain interconnection line, but also reduce the resistance between the first source-drain contact hole and the first source-drain interconnection line.

[0116] In some embodiments, a projected area of ​​the third region on the substrate is larger than a projected area of ​​the first source / drain metal on the substrate.

[0117] It can be understood that the projection area of ​​the third region determined on the first dielectric layer on the substrate may be larger than the projection area of ​​the first source-drain metal on the first substrate.

[0118] In some embodiments, the projected area of ​​the third region on the substrate may be greater than the sum of the projected areas of the first source / drain metal and the spacer adjacent to the first source / drain metal on the substrate. That is, by etching the third region of the first dielectric layer, not only the first hard mask but also the spacer adjacent to the first source / drain metal may be exposed.

[0119] In the embodiment of the present application, the projection area of ​​the third region on the substrate is larger than the projection area of ​​the first source-drain metal on the substrate. Since the third region of the first dielectric layer is used to form the first source-drain contact hole, the size of the first source-drain contact hole formed in the third region of the first dielectric layer in the horizontal direction will be larger than the size of the first source-drain metal in the horizontal direction, so that the formation depth of the first source-drain contact hole can be reduced by increasing the size of the first source-drain contact hole in the horizontal direction, thereby reducing the difficulty of forming the first source-drain contact hole.

[0120] In other embodiments, etching the first region of the first dielectric layer and the first hard mask includes: based on a preset first interconnection line deployment scheme, etching the first region on the first dielectric layer for deploying the first source-drain interconnection line to a fifth preset depth to form a third groove on the first dielectric layer, wherein the bottom of the third groove is formed by the first dielectric layer; according to a preset contact hole deployment scheme, etching a third region at the bottom of the third groove for deploying the first source-drain contact hole until the first hard mask is exposed through the third region; etching the first hard mask.

[0121] It can be understood that after forming the first dielectric layer on the first hard mask and the second hard mask, the first region on the first dielectric layer for deploying the first source-drain interconnection can be etched to a fifth preset depth based on the first interconnection deployment scheme to form a third groove on the first dielectric layer. The fifth preset depth is less than the thickness of the first dielectric layer in the first direction. At this time, the region on the first dielectric layer where the third groove is formed is the region for forming the first source-drain interconnection. Afterwards, based on the preset first contact hole deployment scheme, the third region at the bottom of the third groove can be etched to expose the first hard mask through the third region, and the first hard mask can be etched to expose the first source-drain metal.

[0122] In some embodiments, after forming the third groove on the first dielectric layer, a photoresist may be filled in the third groove to form a third photoresist layer at the bottom of the third groove. Thereafter, the third photoresist layer may be removed until a third region at the bottom of the third groove is exposed, and the third region at the bottom of the third groove is etched until the first hard mask is exposed.

[0123] Hereinafter, a specific embodiment will be used to introduce the process of etching the second region of the first dielectric layer and the second hard mask to form the second groove.

[0124] In some embodiments, etching the second region of the first dielectric layer and the second hard mask to form a second groove includes: etching the third hard mask until the second region of the first dielectric layer is exposed; etching the second region of the first dielectric layer and the second hard mask to form a second groove.

[0125] It can be understood that after forming the third hard mask on the first dielectric layer, the third hard mask deposited on the second region of the first dielectric layer can be etched to expose the second region of the first dielectric layer. After that, the second region of the first dielectric layer can be etched, and the second hard mask exposed through the second region of the first dielectric layer can be etched to expose the first gate metal located under the second hard mask. At this time, a second groove can be formed on the first transistor.

[0126] In some embodiments, when there are multiple first gate metals formed on the first transistor, the second hard mask on the first gate metal that is not adjacent to the first metal interconnection structure and the second region of the first dielectric layer on the second hard mask can be etched, so that at least one first source-drain metal or one first gate metal is separated between the formed second groove and the first metal interconnection structure, and the hard mask on the first source-drain metal or the first gate metal between the first metal interconnection structure and the second groove is not etched or not completely etched. Among them, the hard mask on the first source-drain metal or the first gate metal can be understood as the first hard mask on the first source-drain metal and the second hard mask on the first gate metal.

[0127] In some embodiments, the second metal interconnect structure includes a first gate contact hole; the second region also includes a fourth region indicating the deployment position of the first gate contact hole; wherein, etching the second region of the first dielectric layer and the second hard mask to form a second groove includes: after exposing the first region of the first dielectric layer, etching the fourth region of the first dielectric layer to a fourth preset depth according to a preset contact hole deployment scheme, wherein the fourth preset depth is less than the thickness of the first dielectric layer; etching the area of ​​the first dielectric layer not covered by the third hard mask until the second hard mask is exposed through the fourth region; etching the second hard mask.

[0128] It can be understood that the second metal interconnect structure can also include a first gate contact hole. Therefore, the second area also includes a fourth area for indicating the deployment position of the first gate contact hole. Based on this, after the second area on the first dielectric layer where the second metal interconnect structure is to be formed is exposed by etching the first photoresist layer and the third hard mask. It is also possible to determine the fourth area for deploying the first gate contact hole from the exposed second area according to the second contact hole deployment scheme indicating the deployment position of the first gate contact hole, and etch the fourth area of ​​the first dielectric layer to a fourth preset depth. Among them, the fourth preset depth is less than the thickness of the first dielectric layer. Afterwards, the fourth area on the first dielectric layer can be etched continuously until the second hard mask is exposed through the fourth area of ​​the first dielectric layer. At this time, the second hard mask can be etched continuously until the first gate metal is exposed.

[0129] In some embodiments, after forming the second photoresist layer on the first dielectric layer, the second photoresist layer may be etched according to the second contact hole deployment scheme until the fourth region of the first dielectric layer is exposed, and then the fourth region of the first dielectric layer may be etched to a fourth preset depth. Afterwards, the second photoresist layer may be removed, and at this time, the second region on the first dielectric layer may be exposed (the region on the first dielectric layer other than the first region and the second region is covered by the third hard mask), until the fourth region of the first dielectric layer is completely etched to expose the second hard mask through the fourth region.

[0130] In some embodiments, after etching the third hard mask to expose the first region and the second region of the first dielectric layer, a second photoresist layer may be formed on the first dielectric layer and the third hard mask. Thereafter, the second photoresist layer may be etched according to the first contact hole deployment scheme to expose the third region of the first dielectric layer, and the second photoresist layer may be etched according to the second contact hole deployment scheme to expose the fourth region of the first dielectric layer. Thereafter, the third region of the first dielectric layer may be etched to a third preset depth, and the fourth region of the first dielectric layer may be etched to a fourth preset depth. After etching the third region of the first dielectric layer to the third preset depth and etching the fourth region of the first dielectric layer to the fourth preset depth, the second photoresist layer may be removed, and the first region and the second region not covered by the third hard mask may be etched until the first mask is exposed through the third region and the second hard mask is exposed through the fourth region.

[0131] It can be understood that the fourth preset depth can be any depth that is less than the thickness of the first dielectric layer, and this embodiment of the present application is not limited to this.

[0132] Exemplarily, the fourth preset depth may be half the thickness of the first dielectric layer in the first direction.

[0133] In the embodiment of the present application, firstly, according to the second interconnection line deployment scheme, a second region on the first dielectric for deploying the first gate interconnection line is determined, and then a fourth region for deploying the first gate contact hole is determined from the second region, and the second region, the fourth region of the first dielectric layer and the second hard mask exposed by the fourth region are etched to form a second groove, and then a first gate contact hole and a first gate interconnection line are formed on the first gate metal based on the second groove. Since the first gate contact hole and the first gate interconnection line are both formed in the second groove, self-alignment of the first gate contact hole and the first gate interconnection line can be achieved.

[0134] In addition, since the first gate contact hole and the first gate interconnection line can be formed at one time by depositing metal material in the second groove, this can not only simplify the formation process of the first gate contact hole and the first gate interconnection line, but also reduce the resistance between the first gate contact hole and the first gate source-drain interconnection line.

[0135] In some embodiments, a projected area of ​​the fourth region on the substrate is larger than a projected area of ​​the first gate metal on the substrate.

[0136] It can be understood that the projection area of ​​the fourth region determined on the first dielectric layer on the substrate may be larger than the projection area of ​​the first gate metal on the first substrate.

[0137] In some embodiments, the projected area of ​​the fourth region on the substrate may be greater than the sum of the projected areas of the first gate metal and the spacer adjacent to the first gate metal on the substrate. That is, by etching the fourth region of the first dielectric layer, not only the first hard mask but also the spacer adjacent to the first gate metal may be exposed.

[0138] In the embodiment of the present application, the projection area of ​​the fourth region on the substrate is larger than the projection area of ​​the first gate metal on the substrate. Since the fourth region of the first dielectric layer is used to form the first gate contact hole, the size of the first gate contact hole formed in the fourth region of the first dielectric layer in the horizontal direction will be larger than the size of the first gate metal in the horizontal direction, so that the formation depth of the first gate contact hole can be reduced by increasing the size of the first gate contact hole in the horizontal direction, thereby reducing the difficulty of forming the first gate contact hole.

[0139] In some embodiments, the second metal interconnect structure includes a first gate interconnect line; wherein, etching the third hard mask until the second region of the first dielectric layer is exposed includes: etching the first photoresist layer and the third hard mask according to a preset second interconnect line deployment scheme until the second region of the first dielectric layer is exposed.

[0140] It can be understood that the second metal interconnect structure can also include a first gate interconnection line on the first transistor. Based on this, after forming the first photoresist layer on the third hard mask, the area for deploying the first gate interconnection line on the first photoresist layer can be etched according to the second interconnection line deployment scheme for indicating the deployment position of the first gate interconnection line until the third hard mask is exposed. After that, the exposed third hard mask can be further etched until the second area of ​​the first dielectric layer is exposed.

[0141] In other embodiments, etching the second region of the first dielectric layer and the first hard mask includes: based on a preset second interconnection line deployment scheme, etching the second region on the first dielectric layer for deploying the first gate interconnection line to a sixth preset depth to form a tenth groove on the first dielectric layer, wherein the bottom of the tenth groove is formed by the first dielectric layer; according to a preset second contact hole deployment scheme, etching a fourth region at the bottom of the tenth groove for deploying the first gate contact hole until the second hard mask is exposed through the fourth region; etching the second hard mask.

[0142] It can be understood that after the first dielectric layer is formed on the first hard mask and the second hard mask, the fourth region on the first dielectric layer for deploying the first gate interconnection line can be etched to a sixth preset depth based on the second interconnection line deployment scheme to form a tenth groove on the first dielectric layer. The sixth preset depth is less than the thickness of the first dielectric layer in the first direction. At this time, the region on the first dielectric layer where the tenth groove is formed is the region for forming the first gate interconnection line. Afterwards, based on the preset second contact hole deployment scheme, the fourth region at the bottom of the tenth groove can be etched to expose the second hard mask through the fourth region, and the second hard mask can be etched to expose the first gate metal.

[0143] In some embodiments, after forming the tenth groove on the first dielectric layer, a photoresist may be filled in the tenth groove to form a third photoresist layer at the bottom of the tenth groove. Afterwards, the third photoresist layer may be etched to expose the fourth region at the bottom of the tenth groove, and the fourth region at the bottom of the tenth groove may be etched to expose the second hard mask. The exposed second hard mask may be etched to expose the first gate metal. Thus, a second groove may be formed on the first transistor. Depositing a metal material in the second groove may form a second metal interconnect structure on the first gate metal.

[0144] At this point, a first metal interconnection structure and / or a second metal interconnection structure is formed on the first transistor.

[0145] In some embodiments, the first dielectric layer on the first transistor and the first metal interconnection combination and / or the second metal interconnection structure formed in the first dielectric layer constitute a metal interconnection layer of the first transistor.

[0146] In some embodiments, when the semiconductor structure is a stacked transistor, the method also includes: flipping the wafer and removing the substrate; forming a second transistor stacked with the first transistor on the first transistor, the second transistor including a second source-drain metal and a second gate metal; forming a fourth hard mask on the second source-drain metal, and forming a fifth hard mask on the second gate metal, wherein the materials of the fourth hard mask and the fifth hard mask are different; forming a second dielectric layer on the fourth hard mask and the fifth hard mask; etching the fifth region of the second dielectric layer and the fourth hard mask to form a fourth groove, and forming a third metal interconnection structure on the second source-drain metal based on the fourth groove; and / or etching the sixth region of the second dielectric layer and the fifth hard mask to form a fifth groove, and forming a fourth metal interconnection structure on the second gate metal based on the fifth groove, the fifth region covering the source-drain region of the second transistor, and the sixth region covering the gate region of the second transistor.

[0147] It can be understood that in the case where the semiconductor structure provided in the embodiment of the present application is a stacked transistor, after forming the first metal interconnection structure and the second metal interconnection structure on the first transistor, the first transistor can also be flipped to expose the substrate and remove the substrate. Afterwards, a second transistor stacked with the first transistor in the first direction can be formed on the first crystal, wherein the second transistor includes a second source-drain metal and a second gate metal. After forming the second transistor, a third hard mask material can be deposited on the second source-drain metal to form a fourth hard mask on the second source-drain metal, and a fourth hard mask material can be deposited on the second gate metal to form a fifth hard mask on the second gate metal. Afterwards, a second dielectric layer can be formed on the fourth hard mask and the fifth hard mask. After forming the second dielectric layer, the fifth region of the second dielectric layer and the fourth hard mask can be etched to form a fourth groove, and a metal material can be deposited in the fourth groove to form a third metal interconnection structure on the second source-drain metal. The sixth region on the second dielectric layer and the fifth hard mask are etched to form a fifth groove, and a metal material is deposited in the fifth groove to form a fourth interconnection structure on the second gate metal.

[0148] In some embodiments, the implementation process of forming a second transistor having a second source-drain metal and a second gate metal can refer to the above-mentioned process of forming a first transistor having a first source-drain metal and a first gate metal, and this application will not repeat it here.

[0149] In addition, the implementation process of forming the third metal interconnection structure on the second source and drain metal of the second transistor can refer to the formation of the first metal interconnection structure on the first source and drain metal of the first transistor; the formation process of forming the fourth metal interconnection structure on the second gate metal of the second transistor can refer to the formation process of forming the second metal interconnection structure on the first gate metal of the first transistor, and the embodiments of the present application will not be repeated here.

[0150] In some embodiments, before flipping the wafer, an insulating material (such as silicon oxide) is deposited on the metal interconnect layer of the first transistor to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer.

[0151] In the embodiment of the present application, different hard mask materials are used to form a fourth hard mask on the second source and drain metal of the second transistor, and a fifth hard mask is formed on the second gate metal of the second transistor. Based on this, when etching the second dielectric layer and the fourth hard mask to form the first metal interconnection structure in the fourth groove, since the materials used to form the fourth hard mask and the fifth hard mask are different, the fifth hard mask will not be etched or will not be completely etched during the etching of the fourth hard mask. Therefore, even if the deformation and distortion of the wafer cause position deviation when forming the third metal interconnection structure on the second transistor, the fifth hard mask can isolate the third metal interconnection structure and the adjacent first gate metal, and will not cause the third metal interconnection structure and the adjacent second gate metal to be connected, which can reduce the difficulty of transistor production and improve product yield. Similarly, when etching the second dielectric layer and the fifth hard mask to form the fourth metal interconnection structure in the fifth groove, since the materials used to form the fifth hard mask and the fourth hard mask are different, the fourth hard mask will not be etched or will not be completely etched during the etching of the fifth hard mask. Therefore, even if the deformation and twisting of the wafer causes position deviation when forming the fourth metal interconnection structure, the fourth hard mask can also isolate the fourth metal interconnection structure and the adjacent second source and drain metal, and will not cause the fourth metal interconnection structure and the adjacent second source and drain metal to be connected. It can also reduce the production difficulty of transistors and improve product yield.

[0152] In addition, since the fifth hard mask located on the second gate metal can achieve electrical isolation of the third metal interconnection structure and the second gate metal, the preparation method provided in the embodiment of the present application can increase the size of the third metal interconnection structure when necessary, and will not cause conduction between the third metal interconnection structure and the adjacent second gate metal. Similarly, since the fourth hard mask located on the second source-drain metal can achieve electrical isolation of the fourth metal interconnection structure and the adjacent second source-drain metal, the preparation method provided in the embodiment of the present application can increase the size of the fourth metal interconnection structure when necessary, and will not cause conduction between the fourth metal interconnection structure and the adjacent second source-drain metal.

[0153] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first transistor being a fin field effect transistor as an example. Figure 2 This is a design layout of a semiconductor structure in an embodiment of the present application. For ease of understanding, only the fin structure, gate structure, and source-drain structure are shown in the design layout; (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., the AA' direction); (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., the BB' direction). Figure 3A schematic structural diagram of the first semiconductor structure provided in an embodiment of the present application.

[0154] See also Figure 3 As shown, the semiconductor structure includes a first transistor; the first transistor includes: a first source-drain metal, a first metal interconnect structure connected to the first source-drain metal, and a first gate metal adjacent to the first source-drain metal, wherein the first gate metal adjacent to the first source-drain metal is covered with a second hard mask;

[0155] And / or, a first transistor comprises: a first gate metal, a second metal interconnect structure connected to the first gate metal, and a first source-drain metal adjacent to the first gate metal, wherein the first source-drain metal adjacent to the first gate metal is covered with a first hard mask, wherein the materials of the first hard mask and the second hard mask are different.

[0156] In combination with the above preparation method, Figure 3 The preparation process of the semiconductor structure shown is described. Figure 3 The semiconductor structure shown can be Figure 4 and Fig.17 Prepared as shown in the scheme.

[0157] In the first step, a first transistor 11 including a first source-drain metal 111 and a first gate metal 112 is formed on a substrate according to a standard transistor manufacturing process (see Figure 4 ).

[0158] Need to explain, Figure 4 The two first source-drain metals 111 and the three first gate metals 112 shown in the figure do not constitute a limitation on the number of the first source-drain metals 111 and the first gate metals 112 included in the first transistor provided in the embodiment of the application.

[0159] In the second step, the first gate metal 112 on the first transistor is etched to a second preset depth (reference Figure 5 ).

[0160] In the third step, a second hard mask 113 material is deposited on the first gate metal 112 to form a second hard mask 113 on the first gate metal 112 (see Figure 6 ).

[0161] Step 4: Etch the first source / drain metal 111 on the first transistor to a first preset depth (see Figure 7 ).

[0162] Step 5: forming a first hard mask 114 on the first source / drain metal 111 (see Figure 8 ).

[0163] Step 6: forming a first dielectric layer 115 on the first hard mask 114 and the second hard mask 113 (see Fig. 9 ).

[0164] Step 7: forming a third hard mask 116 on the first dielectric layer 115 (see Fig.10 ).

[0165] In the eighth step, photoresist is coated on the third hard mask film 116 to form a first photoresist layer 117 .

[0166] In the ninth step, according to the preset interconnection line deployment scheme, the region on the first photoresist layer 117 for deploying the first source-drain interconnection line and the first gate interconnection line is etched until the third hard mask 116 (see Fig.11 ).

[0167] It should be noted that the interconnection line deployment scheme may include a first interconnection line deployment scheme for indicating the deployment position of the first source-drain interconnection line, and a second interconnection line deployment scheme for indicating the deployment position of the first gate interconnection line.

[0168] In the tenth step, the exposed third hard mask layer 116 is etched to expose the first region 118 for deploying the first source-drain interconnection line and the second region 119 for deploying the first gate interconnection line on the first dielectric layer 115 .

[0169] In the eleventh step, the remaining first photoresist layer is removed.

[0170] In step 12, a second photoresist layer 120 is formed on the exposed first dielectric layer 115 and the third hard mask film 116 .

[0171] In step 13, according to the preset contact hole deployment scheme, the second photoresist layer 120 is etched to expose the third region 121 for deploying the first source and drain contact holes and the fourth region 122 for deploying the first gate contact holes on the first dielectric layer 115 (see Fig.12 ).

[0172] It should be noted that the contact hole deployment scheme may include a first contact hole deployment scheme for indicating the deployment position of the first source and drain contact holes, and a second contact hole deployment scheme for indicating the deployment position of the first gate contact hole.

[0173] Step 14: Etch the third region 121 of the first dielectric layer 115 to a third preset depth, and etch the fourth region 122 to a fourth preset depth (see Fig.13 ).

[0174] In some embodiments, the third preset depth and the fourth preset depth may be the same or different, and this embodiment of the present application is not limited to this.

[0175] In step 15, the remaining second photoresist layer 120 is removed to expose the first region 118 and the second region 119 of the first dielectric layer 115 (see Fig.14 ).

[0176] It should be noted that the area on the first dielectric layer 115 except the first area and the second area is covered by the third hard mask 116 .

[0177] In step 16, the first region 118 and the second region 119 on the first dielectric layer 115 that are not covered by the third hard mask 116 are etched until the first hard mask 114 is exposed through the third region 121 on the first dielectric layer 115, and the second hard mask 113 is exposed through the fourth region 122 on the first dielectric layer 115 (see Fig.15 ).

[0178] Step 17: Etch the exposed first hard mask 114 until the first source / drain metal 111 is exposed (see Fig.16 ).

[0179] In step 18, the exposed second hard mask 113 is etched until the first gate metal 112 is exposed (see Fig.17 ).

[0180] In step 19, a metal material is deposited on the exposed first source-drain metal 111 and the exposed first gate metal 112 to form a first metal interconnect structure 123 on the first source-drain metal 111 and a second metal interconnect structure 124 on the first gate metal 112 (see Figure 3 ).

[0181] In the twentieth step, an insulating material is deposited on the first metal interconnect structure 123 , the second metal interconnect structure 124 and the first dielectric layer 115 to form an insulating layer 125 .

[0182] In the twenty-first step, the insulating layer 125 is bonded to the carrier wafer 126 .

[0183] At this point, the back-end process on the first transistor is completed.

[0184] In some embodiments, when the semiconductor structure further includes a second transistor, the following steps may be referred to to complete the preparation of a third metal interconnect structure and / or a fourth metal interconnect structure on the second transistor.

[0185] In the first step, the semiconductor structure prepared above is flipped over to expose the substrate.

[0186] In the second step, the substrate is removed and a second transistor 12 including a second source-drain metal 211 and a second gate metal 212 is prepared by a standard transistor preparation process (see Fig.18).

[0187] In the second step, the second gate metal 212 on the second transistor is etched to a second preset depth, and a fifth hard mask 213 is formed on the second gate metal 212 (see Fig.19 ).

[0188] In the third step, the second source-drain metal 211 on the second transistor is etched to a first preset depth, and a fourth hard mask 214 is formed on the second source-drain metal (see Fig. 20 ).

[0189] Step 4: forming a second dielectric layer 215 on the fourth hard mask 214 and the fifth hard mask 213 (see Fig.21 ).

[0190] Step 5: forming a sixth hard mask 216 on the second dielectric layer 215 (see Fig. 22 ).

[0191] In a sixth step, photoresist is coated on the sixth hard mask film 216 to form a fourth photoresist layer 217 .

[0192] In the seventh step, according to the preset interconnection line deployment scheme, the region on the fourth photoresist layer 217 for deploying the second source-drain interconnection line and the second gate interconnection line is etched until the sixth hard mask 216 (see Fig.23 ).

[0193] It should be noted that the interconnection line deployment scheme may also include a third interconnection line deployment scheme for indicating the deployment position of the second source-drain interconnection line, and a fourth interconnection line deployment scheme for indicating the deployment position of the second gate interconnection line.

[0194] In the eighth step, the exposed sixth hard mask layer 216 is etched to expose the fifth region 218 for deploying the second source-drain interconnection line and the sixth region 219 for deploying the second gate interconnection line on the second dielectric layer 215 (see Fig.24 ).

[0195] In the ninth step, the remaining fourth photoresist layer 217 is removed.

[0196] In the tenth step, a fifth photoresist layer 220 is formed on the exposed second dielectric layer 215 and the sixth hard mask film 216 .

[0197] In the eleventh step, according to the preset contact hole deployment scheme, the fifth photoresist layer 220 is etched to expose the seventh region 221 for deploying the second source-drain contact hole and the eighth region 222 for deploying the second gate contact hole on the second dielectric layer 215 (see Fig.25 ).

[0198] It should be noted that the contact hole deployment scheme may also include a third contact hole deployment scheme for indicating the deployment position of the second source-drain contact hole, and a fourth contact hole deployment scheme for indicating the deployment position of the second gate contact hole.

[0199] In the twelfth step, the seventh region 221 of the second dielectric layer 215 is etched to the third preset depth, and the eighth region 222 is etched to the fourth preset depth (see Fig.26 ).

[0200] In step 15, the remaining fifth photoresist layer 220 is removed to expose the fifth region 218 and the sixth region 219 of the second dielectric layer 215 (see Fig. 27 ).

[0201] It should be noted that the area on the second dielectric layer 215 except the fifth area 218 and the sixth area 219 is covered by the sixth hard mask 216 .

[0202] In step 16, the fifth region 218 and the sixth region 219 on the second dielectric layer 215 that are not covered by the sixth hard mask 216 are etched until the fourth hard mask 214 is exposed through the seventh region 221 on the second dielectric layer 215, and the fifth hard mask 213 is exposed through the eighth region 222 on the second dielectric layer 215 (see Fig.28 ).

[0203] Step 17: Etch the exposed fifth hard mask 213 until the second source / drain metal 211 is exposed (see Fig.29 ).

[0204] In step 18, the exposed fourth hard mask 214 is etched until the second gate metal 212 is exposed (see Fig.30 ).

[0205] In step 19, a metal material is deposited on the exposed second source-drain metal 211 and the exposed second gate metal 212 to form a third metal interconnect structure 223 on the second source-drain metal 211 and a fourth metal interconnect structure 224 on the second gate metal 212 (see Fig.31 ).

[0206] At this point, the back-end process of forming the semiconductor structure including the first transistor and the second transistor is completed.

[0207] In some embodiments, based on a standard front-end process, a process of forming a first transistor including a first source / drain metal and a first gate metal on a substrate is as follows.

[0208] The first step is to provide a substrate (see Fig.32 (a) in the figure.

[0209] The substrate includes a first substrate portion 127 and a second substrate portion 128 , wherein the second substrate portion 128 is used to form an active structure 129 .

[0210] In the second step, the fin structure is patterned and the second substrate portion 128 is etched to form an active structure 129 (see Fig.32 (b) in the figure.

[0211] The active structure 129 after etching is a fin-shaped structure with a height greater than 100 nm. The first substrate portion 127 retains a certain thickness during the etching process to support the active structure 129 .

[0212] In the third step, an insulating material is deposited on the active structure 129 to form a shallow trench isolation structure 130 . The height of the shallow trench isolation structure 130 is greater than that of the active structure 129 and wraps the active structure 129 .

[0213] In the fourth step, the shallow trench isolation structure 130 of a preset height is removed by etching to expose a portion of the first active structure 131. The bottom of the first active structure 131 is not exposed and is still located in the shallow trench isolation structure 130 (see Fig.32 (c) in the figure.

[0214] In the fifth step, according to the standard steps for preparing transistors, a first dummy gate structure 132 and a spacer 133 in the first transistor are prepared based on the first active structure 131 (see Fig.33 ).

[0215] In the sixth step, a first source-drain structure 134 is formed in the source-drain region of the first active structure 131, and a third dielectric layer 135 is deposited on the first source-drain structure 134 (see Fig.34 ).

[0216] In the seventh step, the first dummy gate structure 132 is etched, and a first gate metal 112 is formed in the gate region of the first active structure 131 .

[0217] In the eighth step, the third dielectric layer on the first source-drain structure 134 is etched, and a first source-drain metal 111 is formed on the first source-drain structure 134 .

[0218] It should be noted that the formation process of the second transistor including the second source-drain structure and the second gate structure may refer to the formation process of the first transistor in the above steps.

[0219] An embodiment of the present application also provides a semiconductor structure, which includes: a first transistor; the first transistor includes: a first source-drain metal, a first metal interconnection structure connected to the first source-drain metal, and a first gate metal adjacent to the first source-drain metal, wherein the first gate metal adjacent to the first source-drain metal is covered with a second hard mask; and / or, the first transistor includes: a first gate metal, a second metal interconnection structure connected to the first gate metal, and a first source-drain metal adjacent to the first gate metal, wherein the first source-drain metal adjacent to the first gate metal is covered with a first hard mask, wherein the materials of the first hard mask and the second hard mask are different.

[0220] In some embodiments, the first metal interconnect structure includes: a first source-drain contact hole and a first source-drain interconnect line integrally formed with the first source-drain contact hole; the second metal interconnect structure includes: a first gate contact hole and a first gate interconnect line integrally formed with the first gate contact hole.

[0221] In some embodiments, a size of at least a portion of the first source-drain contact hole in the horizontal direction is larger than a size of the first source-drain metal in the horizontal direction.

[0222] In some embodiments, a dimension of at least a portion of the first gate contact hole in a horizontal direction is larger than a dimension of the first gate metal in a horizontal direction.

[0223] In some embodiments, the semiconductor structure also includes: a second transistor; a second transistor including: a second source-drain metal, a third metal interconnect structure connected to the second source-drain metal, and a second gate metal adjacent to the second source-drain metal, wherein the second gate metal adjacent to the second source-drain metal is covered with a fifth hard mask; and / or a second transistor including: a second gate metal, a third metal interconnect structure connected to the second gate metal, and a second source-drain metal adjacent to the second gate metal, wherein the second source-drain metal adjacent to the second gate metal is covered with a fourth hard mask, wherein the materials of the fourth hard mask and the fifth hard mask are different.

[0224] In some embodiments, the third metal interconnect structure includes: a second source-drain contact hole and a second source-drain interconnect line integrally formed with the second source-drain contact hole; the fourth metal interconnect structure includes: a second gate contact hole and a second gate interconnect line integrally formed with the second gate contact hole.

[0225] In some embodiments, a size of at least a portion of the second source-drain contact hole in the horizontal direction is larger than a size of the second source-drain metal in the horizontal direction.

[0226] In some embodiments, a size of at least a portion of the second gate contact hole in the horizontal direction is larger than a size of the second gate metal in the horizontal direction.

[0227] An embodiment of the present application also provides a semiconductor device, including: a semiconductor structure provided by any of the above items.

[0228] In some embodiments, the semiconductor device may include at least one or more Figure 2 or Fig.31 The semiconductor structure shown is not described in detail here for the sake of brevity.

[0229] An embodiment of the present application further provides an electronic device, comprising: a circuit board and a semiconductor device provided by any one of the above items, wherein the semiconductor device is arranged on the circuit board.

[0230] In some embodiments, the electronic device may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a head-mounted device, etc. The electronic device may include a circuit board and a semiconductor device disposed on the circuit board.

[0231] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0232] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: forming a first transistor on a substrate, wherein the first transistor comprises a first source-drain metal and a first gate metal; forming a first hard mask on the first source / drain metal, and forming a second hard mask on the first gate metal, wherein the first hard mask and the second hard mask are made of different materials; forming a first dielectric layer on the first hard mask and the second hard mask; The first region of the first dielectric layer and the first hard mask are etched to form a first groove, and a first metal interconnection structure is formed on the first source-drain metal based on the first groove; and / or, the second region of the first dielectric layer and the second hard mask are etched to form a second groove, and a second metal interconnection structure is formed on the first gate metal based on the second groove; wherein the first region covers the source-drain region of the first transistor, and the second region covers the gate region of the first transistor.

2. The method according to claim 1, characterized in that The step of forming a first hard mask on the first source / drain metal and forming a second hard mask on the first gate metal comprises: Etching the first source-drain metal to a first preset depth, and forming a first hard mask on the first source-drain metal; The first gate metal is etched to a second preset depth, and a second hard mask is formed on the first gate metal.

3. The method according to claim 1 or 2, characterized in that: The etching the first region of the first dielectric layer and the first hard mask to form a first groove includes: depositing a hard mask material on the first dielectric layer to form a third hard mask; Etching the third hard mask until the first region of the first dielectric layer is exposed; The first region of the first dielectric layer and the first hard mask are etched to form the first groove.

4. The method according to claim 3, characterized in that The first metal interconnect structure includes a first source-drain contact hole; the first region also includes a third region indicating a deployment position of the first source-drain contact hole; The etching of the first region of the first dielectric layer and the first hard mask includes: After exposing the first region of the first dielectric layer, etching the third region of the first dielectric layer to a third preset depth according to a preset first contact hole deployment scheme, wherein the third preset depth is less than the thickness of the first dielectric layer; Etching an area of ​​the first dielectric layer not covered by the third hard mask until the first hard mask is exposed through the third area; The first hard mask is etched.

5. The method according to claim 4, characterized in that A projection area of ​​the third region on the substrate is larger than a projection area of ​​the first source / drain metal on the substrate.

6. The method according to claim 3, characterized in that The first metal interconnect structure further includes a first source-drain interconnect line; The etching of the third hard mask until the first region of the first dielectric layer is exposed includes: forming a first photoresist layer on the third hard mask; According to a preset first interconnection line deployment scheme, the first photoresist layer and the third hard mask are etched until a first region of the first dielectric layer is exposed.

7. The method according to claim 3, characterized in that The etching the second region of the first dielectric layer and the second hard mask to form a second groove includes: Etching the third hard mask until the second region of the first dielectric layer is exposed; The second region of the first dielectric layer and the second hard mask are etched to form the second groove.

8. The method according to claim 7, characterized in that The second metal interconnect structure includes a first gate contact hole; the second region also includes a fourth region indicating a deployment position of the first gate contact hole; The etching of the second region of the first dielectric layer and the second hard mask to form the second groove includes: After exposing the first region of the first dielectric layer, etching the fourth region of the first dielectric layer to a fourth preset depth according to a preset contact hole deployment scheme, wherein the fourth preset depth is less than the thickness of the first dielectric layer; Etching an area of ​​the first dielectric layer not covered by the third hard mask until the second hard mask is exposed through the fourth area; The second hard mask is etched.

9. The method according to claim 1, characterized in that: The first metal interconnect structure includes: a first source-drain interconnect line and a first source-drain contact hole; the first region also includes a third region indicating the deployment position of the first source-drain contact hole; The etching of the first region of the first dielectric layer and the first hard mask includes: Based on a preset first interconnection line deployment scheme, etching a first region on the first dielectric layer for deploying the first source-drain interconnection line to a fifth preset depth to form a third groove on the first dielectric layer, wherein a bottom of the third groove is formed by the first dielectric layer; According to a preset contact hole deployment scheme, etching a third region at the bottom of the third groove for deploying the first source-drain contact hole, until the first hard mask is exposed through the third region; The first hard mask is etched.

10. The method according to claim 1, characterized in that The method further comprises: flipping the wafer and removing the substrate; forming a second transistor stacked with the first transistor on the first transistor, wherein the second transistor includes a second source-drain metal and a second gate metal; forming a fourth hard mask on the second source / drain metal, and forming a fifth hard mask on the second gate metal, wherein the fourth hard mask and the fifth hard mask are made of different materials; forming a second dielectric layer on the fourth hard mask and the fifth hard mask; The fifth region of the second dielectric layer and the fourth hard mask are etched to form a fourth groove, and a third metal interconnection structure is formed on the second source-drain metal based on the fourth groove; and / or, the sixth region of the second dielectric layer and the fifth hard mask are etched to form a fifth groove, and a fourth metal interconnection structure is formed on the second gate metal based on the fifth groove, the fifth region covers the source-drain region of the second transistor, and the sixth region covers the gate region of the second transistor.

11. A semiconductor structure, characterized in that: The semiconductor structure comprises: a first transistor; The first transistor comprises: a first source-drain metal, a first metal interconnect structure connected to the first source-drain metal, and a first gate metal adjacent to the first source-drain metal, wherein the first gate metal adjacent to the first source-drain metal is covered with a second hard mask; And / or, the first transistor includes: a first gate metal, a second metal interconnect structure connected to the first gate metal, and a first source-drain metal adjacent to the first gate metal, wherein the first source-drain metal adjacent to the first gate metal is covered with a first hard mask, and wherein the materials of the first hard mask and the second hard mask are different.

12. The semiconductor structure according to claim 11, characterized in that: The first metal interconnect structure comprises: a first source-drain contact hole and a first source-drain interconnection line integrally formed with the first source-drain contact hole; The second metal interconnect structure comprises: A first gate contact hole and a first gate interconnection line integrally formed with the first gate contact hole.

13. The semiconductor structure according to claim 12, characterized in that: A size of at least a portion of the first source-drain contact hole in the horizontal direction is larger than a size of the first source-drain metal in the horizontal direction.

14. A semiconductor device, characterized in that: include: A semiconductor structure as claimed in any one of claims 11 to 13.

15. An electronic device, characterized in that: include: Circuit boards; as well as The semiconductor device according to claim 14, wherein the semiconductor device is disposed on the circuit board.

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