Method for improving through hole bottom copper interconnection metal damage
By introducing a buffer layer into the through hole etching process and optimizing the etching process, the problem of poor morphology of copper interconnect metal and grooves in the lower layer is solved by etching through holes, and the effect of reducing the contact resistance of the through holes and improving the grooves is achieved. .
Patent Information
- Application Number
- CN202411547744.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-07
AI Technical Summary
In the prior art, through-hole etching damages the lower copper interconnect metal and the trench bottom morphology formed by the wafer edge region is poor.
The buffer layer is formed under the etch stop layer, and the process steps of buffer layer etching are added after the etch stop layer etching is adjusted. By adjusting the etching time and gas combination, the etching amount of the interlayer dielectric layer and the etch stop layer is reduced, and the copper is reduced to the lower layer of copper Damage to metal wires.
It effectively reduces damage to copper interconnect metal at the bottom of the through hole, reduces the through hole contact resistance, and improves the trench morphology of the wafer edge area, thereby ensuring the performance of semiconductor devices.
Smart Images
Figure CN119400753A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving metal damage of copper interconnection at the bottom of a through hole. Background Art
[0002] The through hole is a channel connecting the upper and lower copper metal wires. Its etching process consists of mask layer etching, through hole main etching, photoresist ashing, trench etching and etching stop layer etching. During the stop layer etching process, a certain amount of overetching is required to ensure the connection between the through hole and the lower copper metal wire, causing damage to the lower copper metal and affecting its contact resistance. The sputtered copper ions and their compounds escape into the etching chamber, which will affect the overall etching rate of the chamber. At the same time, some of the sputtered copper ions and their compounds will accumulate at the edge of the wafer, affecting the bottom morphology of the trench in the trench etching (such as Figure 1D The bottom of the groove shown in Figure 1 gradually narrows). Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving the damage of the copper interconnect metal at the bottom of the through hole, so as to solve the problem in the prior art that the through hole etching damages the underlying copper interconnect metal and the bottom morphology of the groove formed in the edge area of the wafer is poor.
[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving metal damage of copper interconnect at the bottom of a through hole, comprising:
[0005] Step 1, providing a substrate, on which a copper interconnect metal layer is formed, and sequentially forming a buffer layer, an etch stop layer, an interlayer dielectric layer, and a hard mask layer for defining the size of a trench opening on the substrate;
[0006] Step 2, forming a photoresist mask layer to define the size of the through hole;
[0007] Step 3, performing a first etching process using the photoresist mask layer as a mask, and adjusting the duration of the first etching process to reduce the etching amount of the interlayer dielectric layer;
[0008] Step 4, after removing the photoresist mask layer, performing a second etching with the hard mask layer as a mask, and adjusting the duration of the second etching to reduce the etching depth of the groove portion and the etching amount of the etching stop layer;
[0009] Step 5: Perform a third etching to adjust the morphology of the bottom of the through hole until the copper interconnect metal layer is exposed, completing the etching of the groove portion.
[0010] Preferably, the material of the buffer layer is a loosely structured oxide.
[0011] Preferably, the etching process of the third etching adopts a gas combination of C4F8 / O2 / N2, a high-power high-frequency / low-power low-frequency RF power source, and a temperature distribution with low temperature in the center and high temperature at the edge.
[0012] Preferably, the input power of the high-frequency RF power source is 500W-800W, and the input power of the low-frequency RF power source is 50W-200W.
[0013] Preferably, the frequencies of the high-frequency / low-frequency RF power sources are constant, 40.68 MHz and Z / 12.88MH Z .
[0014] Preferably, the thickness of the buffer layer is 200 angstroms to 250 angstroms.
[0015] Preferably, the material of the etch stop layer includes silicon nitride.
[0016] Preferably, the etching amount of the interlayer dielectric layer in step three is reduced by 50% to reduce the over-etching amount in the entire etching process of forming the through hole.
[0017] Preferably, in step 4, the etching depth of the groove portion is reduced by 100 angstroms to 120 angstroms to ensure that the thickness of the film layer below the groove portion does not decrease after step 5 is completed.
[0018] Preferably, in step 4, the etching amount of the etching stop layer is reduced by 20%-25% to reduce consumption of the buffer layer.
[0019] As described above, the method for improving the metal damage of the copper interconnect at the bottom of the through-hole provided in the present application has the following beneficial effects: the through-hole dry etching film layer structure and etching process are optimized, and while ensuring the morphology of the bottom of the through-hole, the damage of the underlying copper metal wire can be effectively reduced, the through-hole contact resistance is reduced, and the groove morphology in the edge area of the wafer is improved, thereby ensuring the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1A-Figure 1D A schematic diagram showing a cross-sectional structure of the invention name provided by an embodiment of the present application;
[0022] Figure 2 A flow chart showing a method for improving metal damage of copper interconnect at the bottom of a through hole provided by an embodiment of the present application;
[0023] Figure 3A-3D It is a schematic diagram of the cross-sectional structure of a device formed after each step is completed in the method for improving metal damage of copper interconnect at the bottom of a through hole provided in an embodiment of the present application. DETAILED DESCRIPTION
[0024] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0029] The existing through hole etching process includes the following steps:
[0030] First, if Figure 1AAs shown, a copper interconnect metal layer 100 is formed on the substrate, and an etching stop layer 101, an interlayer dielectric layer 102 and a hard mask layer 103 defining the size of the trench opening are sequentially formed on the substrate. Then, a photoresist mask layer 105 is formed to define the size of the through hole 106.
[0031] Then, if Figure 1B As shown, the main etching of the through hole is performed using the photoresist mask layer 105 as a mask. After the etching is completed, the bottom of the through hole 106 does not reach the etching stop layer 101.
[0032] Then, if Figure 1C As shown, after the photoresist mask layer 105 is removed by an ashing process, trench etching and etching stop layer etching are sequentially performed using the hard mask layer 103 as a mask to form a trench 107 .
[0033] Then, if Figure 1D As shown, the etching stop layer 101 is overetched to ensure the connection between the through hole 106 and the copper interconnect metal layer 100. Overetching causes damage to the copper interconnect metal layer 100, and the sputtered copper ions and their compounds 108 accumulate in the wafer edge area, which deteriorates the bottom morphology of the trench 107 in the wafer edge area.
[0034] In order to ensure the connection between the through hole 106 and the copper interconnect metal layer 100, the existing through hole etching process cannot directly reduce the over-etching amount of the etch stop layer 101, otherwise it will affect the bottom morphology of the through hole. At the same time, the etching program selection for the etch stop layer 101 is relatively low, which causes more serious damage to the copper interconnect metal layer 100.
[0035] In order to solve the problem in the prior art that through-hole etching damages the underlying copper interconnect metal and the bottom morphology of the groove formed in the edge area of the wafer is poor, the present application provides a method for improving the damage of the copper interconnect metal at the bottom of the through-hole, forming a buffer layer under the etching stop layer, and adding a process step of etching the buffer layer after etching the etching stop layer. Since the buffer layer structure is relatively loose, a program with a higher selectivity can be used during the etching process, which can further reduce the damage to the underlying copper metal wire while correcting the bottom morphology of the through-hole, thereby achieving the purpose of improving the through-hole contact resistance and the uniformity of the characteristic line width of the grooves in different areas of the wafer.
[0036] See also Figure 2 , which shows a flow chart of a method for improving metal damage of copper interconnect at the bottom of a through-hole provided by an embodiment of the present application.
[0037] like Figure 2 As shown, the method for improving the metal damage of copper interconnection at the bottom of the through hole comprises the following steps:
[0038] Step 1, providing a substrate, on which a copper interconnect metal layer is formed, and sequentially forming a buffer layer, an etch stop layer, an interlayer dielectric layer, and a hard mask layer for defining the size of a trench opening on the substrate;
[0039] Step 2, forming a photoresist mask layer to define the size of the through hole;
[0040] Step 3, performing a first etching process using the photoresist mask layer as a mask, and adjusting the duration of the first etching process to reduce the etching amount of the interlayer dielectric layer;
[0041] Step 4, after removing the photoresist mask layer, performing a second etching with the hard mask layer as a mask, and adjusting the duration of the second etching to reduce the etching depth of the groove portion and the etching amount of the etching stop layer;
[0042] Step 5: Perform a third etching to adjust the morphology of the bottom of the through hole until the copper interconnect metal layer is exposed, completing the etching of the groove portion.
[0043] In step 1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of the substrate should not limit the protection scope of the present invention.
[0044] like Figure 3A As shown, a copper interconnect metal layer 300 is formed on the substrate. As an example, a buffer layer 301, an etch stop layer 302, an interlayer dielectric layer 303, and a hard mask layer 305 defining the size of the trench opening are sequentially formed on the substrate through a deposition process. Exemplarily, the hard mask layer 305 includes a TEOS layer 305a and a titanium nitride layer 305b stacked from bottom to top.
[0045] Exemplarily, the material of the buffer layer 301 is a loosely structured oxide, such as BD of Applied Materials; the material of the etch stop layer 302 includes silicon nitride; the material of the interlayer dielectric layer 303 is, for example but not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon oxide (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organic silicates) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ether, or other materials with low dielectric constant (<3.9).
[0046] As an example, the thickness of the buffer layer 301 is 200-250 angstroms. The structure of the buffer layer 301 is loose. If the thickness of the buffer layer 301 is too thin, it is not conducive to the subsequent adjustment of the bottom morphology of the through hole, and it cannot effectively play a buffering role; if the thickness of the buffer layer 301 is too thick, it will cause the film layer to fall off and cause defects.
[0047] In step 2, if Figure 3A As shown, a photoresist mask layer 306 is formed by photolithography and etching processes to define the size of the through hole 307. Exemplarily, the photoresist mask layer 306 includes a spin-on carbon (SOC) layer 306a, a bottom anti-reflective coating (BARC layer) 306b and a photoresist layer 306c stacked from bottom to top.
[0048] In step three, if Figure 3B As shown, the first etching is performed using the photoresist mask layer 306 as a mask, and the duration of the first etching is adjusted to reduce the etching amount of the interlayer dielectric layer 303 .
[0049] As an example, compared with the target value set in the prior art, the etching amount of the interlayer dielectric layer 303 is reduced by 50% ( Figure 3B and Figure 1B Compared with the above, the over-etching amount in the entire etching process of forming the through hole can be reduced (mainly the over-etching amount of the interlayer dielectric layer 303 caused by the subsequent etching of the buffer layer 301).
[0050] In step 4, if Figure 3C As shown, after removing the photoresist mask layer 306 through an ashing process, a second etching is performed using the hard mask layer 305 as a mask, and the duration of the second etching is adjusted to reduce the etching depth of the groove portion 308 and the etching amount of the etching stop layer 302 .
[0051] Since the etching amount of the interlayer dielectric layer 303 in step three is reduced by 50%, correspondingly, the duration of the ashing process is increased by 50%.
[0052] As an example, compared with the target value set in the prior art, the etching depth of the groove portion 308 is reduced by 100 angstroms to 120 angstroms to ensure that the film layer thickness below the groove portion 308 (the sum of the thickness of the interlayer dielectric layer 303, the etching stop layer 302 and the buffer layer 301 compared with the sum of the thickness of the interlayer dielectric layer 303 and the etching stop layer 302 in the prior art) will not decrease after the subsequent etching of the buffer layer 301 is completed.
[0053] As an example, the etching amount of the etching stop layer 302 is reduced by 20%-25% to reduce the consumption of the buffer layer 301, thereby causing the bottom morphology of the through hole 307 to shrink (eg Figure 3C The residual gas (as shown) will be compensated in the subsequent etching of the buffer layer.
[0054] In step five, if Figure 3D As shown, a third etching is performed to adjust the morphology of the bottom of the through hole until the copper interconnect metal layer 300 is exposed, and the etching of the trench portion 308 is completed.
[0055] The buffer layer 301 is etched through the third etching. As an example, the etching procedure uses a gas combination of C4F8 / O2 / N2, a high-power high-frequency / low-power low-frequency RF power source, and a temperature distribution with low center and high edge. The etching amount of the third etching (including the buffer layer 301, the interlayer dielectric layer 303 and the etching stop layer 302) is adjusted by time to reach 300 angstroms-370 angstroms. While fully ensuring the connection between the through hole 307 and the copper interconnect metal layer 300, the thickness of the interlayer dielectric layer 303 under the groove 308 will not decrease.
[0056] The etching process selection of the prior art for etching the etch stop layer 302 using a gas combination mainly composed of CF4 / Ar is relatively low, and it is easy to damage the copper interconnect metal layer 300. The gas combination mainly composed of C4F8 / O2 / N2 can minimize the damage to the copper interconnect metal layer 300 while etching the buffer layer 301. At the same time, the newly added buffer layer 301 ensures the stability of the remaining film thickness at the bottom of the groove 308, and the buffer layer 301 has a loose structure and is more easily etched, which is conducive to increasing the bottom area of the through hole and reducing the through hole contact resistance.
[0057] The gas combination mainly composed of C4F8 / O2 / N2 has a higher etching selectivity ratio. The low-power, low-frequency RF power supply in the center area of the wafer can minimize the damage to the copper interconnect metal layer 300. At the same time, the low center and high edge temperature distribution and the high-power high-frequency RF power supply can further improve the morphology of the groove in the edge area of the wafer, thereby achieving the purpose of improving the uniformity of the through-hole contact resistance and the groove characteristic line width / film thickness.
[0058] As an example, the high-frequency / low-frequency RF power supply frequency of the etching machine is constant, which is 40.68 MH respectively. Z / 12.88MH Z The etching behavior is controlled by adjusting the input power of the high / low frequency RF power supply. The input power of the high frequency RF power supply is 500W-800W, and the input power of the low frequency RF power supply is 50W-200W.
[0059] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0060] In summary, the method for improving the copper interconnect metal damage at the bottom of the through hole provided by the present application optimizes the through hole dry etching film layer structure and etching process, and adds a buffer layer etching step after the stop layer etching, which can minimize the damage to the underlying copper metal wire while ensuring the morphology of the bottom of the through hole, reduce the through hole contact resistance, and improve the groove morphology of the wafer edge area, thereby ensuring the performance of the semiconductor device. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0061] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.
Claims
1. A method for improving copper interconnect metal damage at the bottom of a through hole, characterized in that: The method comprises: Step 1, providing a substrate, on which a copper interconnect metal layer is formed, and sequentially forming a buffer layer, an etch stop layer, an interlayer dielectric layer, and a hard mask layer for defining a size of a trench opening on the substrate; Step 2, forming a photoresist mask layer to define the size of the through hole; Step three, performing a first etching process using the photoresist mask layer as a mask, and adjusting the duration of the first etching process to reduce the etching amount of the interlayer dielectric layer; Step 4, after removing the photoresist mask layer, performing a second etching with the hard mask layer as a mask, and adjusting the duration of the second etching to reduce the etching depth of the groove portion and the etching amount of the etching stop layer; Step five, performing a third etching to adjust the morphology of the bottom of the through hole until the copper interconnect metal layer is exposed, and completing the etching of the groove portion.
2. The method according to claim 1, characterized in that: The material of the buffer layer is an oxide with a loose structure.
3. The method according to claim 1, characterized in that The etching process of the third etching adopts a gas combination of C4F8 / O2 / N2, a high-power high-frequency / low-power low-frequency radio frequency power source, and a temperature distribution with a low temperature in the center and a high temperature at the edge.
4. The method according to claim 3, characterized in that The input power of the high-frequency radio frequency power supply is 500W-800W, and the input power of the low-frequency radio frequency power supply is 50W-200W.
5. The method according to claim 3, characterized in that: The frequencies of the high-frequency / low-frequency RF power sources are constant, and are 40.68 MH Z / 12.88MH Z .
6. The method according to claim 1, characterized in that The thickness of the buffer layer is 200 angstroms to 250 angstroms.
7. The method according to claim 1, characterized in that The material of the etching stop layer includes silicon nitride.
8. The method according to claim 1, characterized in that: In the step three, the etching amount of the interlayer dielectric layer is reduced by 50% to reduce the over-etching amount in the entire etching process of forming the through hole.
9. The method according to claim 1, characterized in that: In the step 4, the etching depth of the groove portion is reduced by 100 angstroms to 120 angstroms to ensure that the thickness of the film layer below the groove portion does not decrease after the step 5 is completed.
10. The method according to claim 1, characterized in that In the step 4, the etching amount of the etching stop layer is reduced by 20%-25% to reduce the consumption of the buffer layer.